Power semiconductor device and preparation method thereof
By setting a specific layout of power pins and signal pins on the substrate of the power semiconductor device, the problem of insufficient device flow capability and tolerance to high power capability is solved, and higher signal transmission efficiency and welding stability are achieved.
Patent Information
- Application Number
- CN202411805400.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-10
- Publication Date
- 2025-03-25
AI Technical Summary
In the prior art, the flow capacity and ability of power semiconductor devices to withstand high power are limited by the package structure, resulting in the device being easily damaged or reduced in service life during use.
Multi-pin design is realized by designing a power semiconductor device, wherein all power pins are arranged on the same side of the substrate, and at least one or more first signal pins are arranged on the side, and the second signal pin and the power pin are arranged on different sides of the substrate.
This design reduces the length of the signal transmission path, reduces signal delay and interference, improves the efficiency and reliability of signal transmission, and improves the soldering stability, flow capacity and high power tolerance of the device through a multi-pin design.
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Figure CN119695015A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor devices, for example, to a power semiconductor device and a method for preparing the same. Background Art
[0002] At present, with the rapid development trend of high quality and high reliability requirements in the power electronics industry, the requirements for highly integrated and high-performance semiconductor devices are becoming higher and higher. There are many external factors in the use environment of the device that can cause the device to fail. The main components of non-hermetic semiconductor packaging devices are frames, solders, chips, plastic packaging materials, DBC (Direct Bonded Copper, direct copper ceramic materials) and other materials. The characteristics of each material are different. When the device is in use, it will generate a certain amount of heat due to itself or external factors. When the power device is in use, accompanied by temperature rise or circuit noise, there will be a certain probability of damage to the device, failure, or reduced service life of the device.
[0003] In the related art, the packaging structure of power devices is mostly a bottom-mount type or a package plug-in structure.
[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:
[0005] Due to the limitation of the packaging structure, the current carrying capacity and high power tolerance capability of the devices in the related art are limited.
[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.
[0008] The embodiments of the present disclosure provide a power semiconductor device and a method for manufacturing the same, so as to improve the current carrying capacity and high power tolerance of the device.
[0009] In some embodiments, a power semiconductor device includes: a substrate, a chip, a power pin, a first signal pin, and a second signal pin; the chip is arranged on the substrate and electrically connected to the power pin, the first signal pin, and the second signal pin; the first signal pin and the power pin are arranged on the same side of the substrate; the second signal pin and the power pin are arranged on different sides of the substrate.
[0010] Optionally, a setting distance between the power pin and the first signal pin is greater than a setting distance between two adjacent second signal pins.
[0011] Optionally, the first signal pin and the power pin are arranged on the first side of the substrate; the second signal pin is arranged on one or more of the second side, the third side, and the fourth side of the substrate; wherein the second side is arranged adjacent to the first side, the third side is arranged opposite to the first side, and the fourth side is arranged opposite to the second side.
[0012] Optionally, the second signal pin includes one or more of a G signal pin, an S signal pin, and a K signal pin; and the first signal pin includes one or more of a G signal pin, an S signal pin, and a K signal pin, wherein the K signal pin is arranged on a side away from the power pin.
[0013] Optionally, there are multiple first signal pins, and the first signal pins are arranged on both sides of the power pin.
[0014] Optionally, there are multiple power pins, and the power pins are arranged on both sides of the first signal pin.
[0015] Optionally, the power pin is a drain potential, and the first signal pin and the second signal pin are a gate potential and a source potential.
[0016] Optionally, the power semiconductor device further includes: an insulating heat sink, which is arranged on the substrate, and the heat dissipation surface of the insulating heat sink is arranged upward.
[0017] In some embodiments, a method for preparing a power semiconductor device includes: fixing a chip on a substrate to form a preliminary electrical connection between the chip and the substrate; configuring a pin layout on the substrate according to requirements of an application circuit; electrically connecting a power pole of the power chip to a power pin; and connecting a signal pole of the power chip to a first signal pin and a second signal pin to form an electrical signal path.
[0018] Optionally, the method for preparing a power semiconductor device further includes: disposing an insulating heat sink with a heat dissipation surface facing upward in the substrate.
[0019] The power semiconductor device and the manufacturing method thereof provided by the embodiments of the present disclosure can achieve the following technical effects:
[0020] In the disclosed embodiment, the power semiconductor device includes a substrate, a chip, a power pin, a first signal pin, and a second signal pin. All the power pins are arranged on the same side of the substrate, and one side of the power pin includes at least one or more first signal pins. The first signal pin and the power pin are arranged on the same side of the substrate, which can reduce the length of the signal transmission path, thereby reducing signal delay and interference, and improving the efficiency and reliability of signal transmission. The second signal pin and the power pin are arranged on different sides of the substrate, which can realize a multi-pin design, improve the welding stability of the power semiconductor device, and improve the current carrying capacity and high power tolerance of the device.
[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:
[0023] Figure 1 is a schematic diagram of a power semiconductor device provided by an embodiment of the present disclosure;
[0024] Figure 2 is a schematic diagram of a pin layout of a power semiconductor device provided by an embodiment of the present disclosure;
[0025] Figure 3 is a schematic diagram of a pin layout of another power semiconductor device provided by an embodiment of the present disclosure;
[0026] Figure 4 is a schematic diagram of a pin layout of another power semiconductor device provided by an embodiment of the present disclosure;
[0027] Figure 5 is a schematic diagram of a pin layout of another power semiconductor device provided by an embodiment of the present disclosure;
[0028] Figure 6 is a schematic diagram of a pin layout of another power semiconductor device provided by an embodiment of the present disclosure;
[0029] Figure 7 is an internal equivalent circuit diagram of a power semiconductor device provided by an embodiment of the present disclosure;
[0030] Figure 8 It is a schematic diagram of a method for preparing a power semiconductor device provided in an embodiment of the present disclosure.
[0031] Reference numerals: 10, substrate; 20, chip; 30, power pin; 41, first signal pin; 42, second signal pin. DETAILED DESCRIPTION
[0032] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.
[0033] The terms "first", "second", etc. in the technical solutions described in this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the disclosed embodiments described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.
[0034] Unless otherwise stated, the term "plurality" means two or more.
[0035] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.
[0036] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.
[0037] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.
[0038] Combination Figure 1 As shown, the embodiment of the present disclosure provides a power semiconductor device, including a substrate 10, a chip 20, a power pin 30, a first signal pin 41, and a second signal pin 42. The chip 20 is disposed on the substrate 10, and is electrically connected to the power pin 30, the first signal pin 41, and the second signal pin 42. The first signal pin 41 and the power pin 30 are disposed on the same side of the substrate 10; the second signal pin 42 and the power pin 30 are disposed on different sides of the substrate 10.
[0039] Combination Figure 1As shown, in this embodiment, all power pins 30 are arranged on the same side of the substrate 10, and one side of the power pin 30 includes at least one or more first signal pins 41. The first signal pin 41 and the power pin 30 are arranged on the same side of the substrate 10, which can reduce the length of the signal transmission path, thereby reducing signal delay and interference, and improving the efficiency and reliability of signal transmission. The second signal pin 42 and the power pin 30 are arranged on different sides of the substrate 10, which can realize a multi-pin design, improve the welding stability of the power semiconductor device, and improve the current carrying capacity and high power tolerance of the device.
[0040] Optionally, a setting distance between the power pin 30 and the first signal pin 41 is greater than a setting distance between two adjacent second signal pins 42 .
[0041] Combination Figure 1 As shown, in this embodiment, the distance H between the power pin 30 and the first signal pin 41 is greater than the distance h between two adjacent second signal pins 42, which can reduce electromagnetic interference and signal crosstalk between the power pin 30 and the first signal pin 41 and improve signal clarity and integrity.
[0042] Optionally, the substrate 10 is made of DBC material. Appropriate layout can be performed on the substrate 10 according to the number of chips 20 and the number of pins.
[0043] Optionally, the first signal pin 41 and the power pin 30 are arranged on the first side of the substrate 10; the second signal pin 42 is arranged on one or more of the second side, the third side, and the fourth side of the substrate 10; wherein the second side is arranged adjacent to the first side, the third side is arranged opposite to the first side, and the fourth side is arranged opposite to the second side.
[0044] In this embodiment, the package layout of the power semiconductor device includes two-sided pins, three-sided pins, and four-sided pins. Suitable for a variety of application circuits, the power semiconductor device can flexibly choose a suitable package layout. The embodiment of the present disclosure does not limit the number and width of the pins, and can be reasonably set according to different actual needs. In addition, in order to have better welding conditions, the shape and structural morphology of the pins are also not limited, such as the pins have a wider patch surface, the pins have through holes in the middle, and the pins have grooves on the sides. Figure 1 As shown, the packaging layout of the power semiconductor device with four-sided pins is shown. For the packaging layout with two-sided pins and three-sided pins, it can be realized by just removing the pin layout on one side or two sides of the substrate 10 accordingly.
[0045] Optionally, combined Figure 2As shown, the design scheme of the two-side pins includes: the first signal pin 41 and the power pin 30 are arranged on the first side of the substrate 10; the second signal pin 42 is arranged on one of the second side, the third side, and the fourth side of the substrate 10.
[0046] Optionally, combined Figure 3 As shown, the design of the three-side pins includes: the first signal pin 41 and the power pin 30 are arranged on the first side of the substrate 10; the second signal pin 42 is arranged on any two sides of the second side, the third side, and the fourth side of the substrate 10.
[0047] Optionally, combined Figure 4 As shown, the design of the four-side pins includes: the first signal pins 41 and the power pins 30 are arranged on the first side of the substrate 10; the second signal pins 42 are arranged on the second side, the third side and the fourth side of the substrate 10.
[0048] In this embodiment, according to the requirements of different application circuits, by selecting a suitable package layout, the power semiconductor device can adapt to various circuit designs. In the design scheme of two-sided pins, pins are provided on two opposite sides or adjacent sides of the device, which is suitable for applications requiring double-sided connection. In the design scheme of three-sided pins, pins are provided on three sides of the device, providing more connection options for circuit design. In the design scheme of four-sided pins, pins are provided on all four sides of the device, which is suitable for applications with compact space and requiring all-round connection. In this way, the power semiconductor device can be flexibly integrated into various circuits, improving the versatility and applicability of the device. By providing different numbers of pin configurations, the most suitable package layout can be selected according to the specific circuit design and space constraints, thereby optimizing the performance and reliability of the entire system.
[0049] Optionally, the second signal pin 42 includes one or more of a G signal pin, an S signal pin, and a K signal pin; and the first signal pin 41 includes one or more of a G signal pin, an S signal pin, and a K signal pin, wherein the K signal pin is arranged on a side away from the power pin 30. The G signal pin represents a gate, and is used to receive a gate signal. The S signal pin represents a source, and is used to receive a source signal. The K signal pin represents a Kelvin pin, and is used for a drive circuit or a measurement circuit.
[0050] In this embodiment, according to different circuit requirements, the first signal pin 41 and the second signal pin 42 can be set to one or more of the G signal pin, the S signal pin, and the K signal pin. Among them, the Kelvin pin is used to monitor and control the power device. In order to reduce the interference of the power pin 30 to the Kelvin pin, the Kelvin pin needs to be placed on a different side from the power pin 30, or as far away from the power pin 30 as possible. Since the power pin 30 will generate a strong electromagnetic field when transmitting a large current, this may cause electromagnetic interference to the nearby signal pins. By physically isolating the Kelvin pin from the power pin 30, the electromagnetic coupling between the two can be reduced, thereby reducing interference. Reducing interference can improve the accuracy and stability of the Kelvin pin, thereby ensuring the correct operation and performance of the power device. In high-speed or high-frequency applications, the accuracy of the signal is particularly important for the response time and reliability of the device. In addition, reducing the interference of the signal pin can also reduce the extra time required for the device to process the signal, thereby increasing the switching speed and thus improving the overall efficiency of the system. Therefore, placing the Kelvin pin on different sides of the power pin 30 or away from the power pin 30 can effectively reduce the interference of the power pin 30 on the signal pin, improve the accuracy and stability of the signal, and thus improve the switching speed and overall performance of the device.
[0051] Optionally, whether the K signal pin needs to be configured is determined based on actual application requirements.
[0052] In this embodiment, the K signal pin is not necessary in the power semiconductor device. When the switching state of the power device needs to be accurately controlled, such as in a complex power electronic converter, the K signal pin needs to be configured to receive the control signal. For simple applications, if no additional control or monitoring functions are required, the K signal pin can be omitted to simplify the design and reduce costs.
[0053] Optionally, combined Figure 5 As shown, there are multiple first signal pins 41 , and the first signal pins 41 are disposed on both sides of the power pin 30 .
[0054] In this embodiment, the first signal pin 41 is isolated by the power pin 30, which can reduce the direct electromagnetic coupling between the two first signal pins 41, thereby reducing the interference between the two first signal pins 41, improving the integrity of the signal, thereby reducing the bit error rate and improving the reliability of data transmission. In addition, Figure 5 The following is a design scheme for four-sided pins. Figure 2 , Figure 3 , Figure 4 The content can be Figure 5 Modify the design scheme in to a suitable two-sided pin or three-sided pin design scheme.
[0055] Optionally, combined Figure 6 As shown, there are multiple power pins 30 , and the power pins 30 are disposed on both sides of the first signal pin 41 .
[0056] The first signal pin 41 is arranged between the power pins 30. The first signal pin 41 can serve as a physical barrier to reduce direct electromagnetic interference between the power pins 30, which helps to reduce the mutual influence between the power pins 30. By placing the first signal pin 41 between two power pins 30, power can be distributed more evenly, avoiding a single power pin 30 from being subjected to excessive current or voltage load, which helps to improve the overall performance and reliability of the device. In addition, Figure 6 The following is a design scheme for four-sided pins. Figure 2 , Figure 3 , Figure 4 The content can be Figure 6 Modify the design scheme in to a suitable two-sided pin or three-sided pin design scheme.
[0057] Optionally, the power pin 30 is a drain potential, and the first signal pin 41 and the second signal pin 42 are a gate potential and a source potential.
[0058] The equivalent circuit diagram inside a power semiconductor device is as follows: Figure 7 As shown, C is the power pole of the device, corresponding to the power pin 30, serving as the drain potential of the device; G, E, and K are the signal poles of the device, corresponding to the first signal pin 41 and the second signal pin 42, serving as the gate potential and source potential of the device, and G corresponds to the G signal pin, E corresponds to the S signal pin, and K corresponds to the K signal pin.
[0059] Optionally, the power semiconductor device further includes: an insulating heat sink, which is arranged on the substrate 10, and the heat dissipation surface of the insulating heat sink is arranged upward.
[0060] In this embodiment, the insulating heat sink can improve the heat dissipation efficiency of the device, thereby enhancing the performance and reliability of the device. The insulating heat sink can provide an effective heat dissipation pathway to conduct away the heat generated when the device is working, so as to reduce the operating temperature of the device. Setting the insulating heat sink upward with the heat dissipation surface facing the top of the device can more directly transfer heat to the surrounding air, or to the heat dissipation structure above the heat sink, which helps to improve the heat transfer efficiency. When designing a power semiconductor device, it is necessary to comprehensively consider the shape, size, material and connection method of the insulating heat sink with the substrate 10 to achieve the best thermal management effect. The design of the heat sink may include fins, grooves or other features that enhance thermal conduction to improve the heat dissipation efficiency.
[0061] Optionally, the power semiconductor device provided by the embodiments of the present disclosure can be applied to different application fields and scenarios, including: automobiles, photovoltaics, charging piles, wind power, energy storage, etc.
[0062] Optionally, the number of chips 20 in the power semiconductor device includes one or more.
[0063] Optionally, the power semiconductor device provided in the embodiment of the present disclosure can be applied to IC (Integrated Circuit) chips, thermistors, IGBT (Insulated Gate Bipolar Transistor), FRD (Fast Recovery Diode), MOS (Metal-Oxide-Semiconductor), BJT (Bipolar Junction Transistor), SCR (Silicon Controlled Rectifier) and other devices. Including single device products, half-bridge circuits, and full-bridge circuit designs.
[0064] The present disclosure also provides a method for preparing a power semiconductor device. Figure 8 As shown, the method includes:
[0065] S101, fixing the chip on the substrate to form a preliminary electrical connection between the chip and the substrate.
[0066] S102, configuring the pin layout on the substrate according to the requirements of the application circuit.
[0067] S103, electrically connecting the power electrode of the power chip to the power pin.
[0068] S104, connecting the signal electrode of the power chip to the first signal pin and the second signal pin to form an electrical signal path.
[0069] Optionally, fixing the chip on the substrate includes: fixing the chip on the substrate by means of solder, conductive glue, silver paste, welding sheet, etc.
[0070] Optionally, the pin layout on the substrate may be configured according to the pin layout in the above-mentioned power semiconductor device.
[0071] Optionally, the pins include a power pin, a first signal pin, and a second signal pin; the pin layout includes: the first signal pin and the power pin are arranged on the same side of the substrate, and the second signal pin and the power pin are arranged on different sides of the substrate.
[0072] Optionally, a setting distance between the power pin and the first signal pin is greater than a setting distance between two adjacent second signal pins.
[0073] Optionally, the first signal pin and the power pin are arranged on the first side of the substrate; the second signal pin is arranged on one or more of the second side, the third side, and the fourth side of the substrate; wherein the second side is arranged adjacent to the first side, the third side is arranged opposite to the first side, and the fourth side is arranged opposite to the second side.
[0074] Optionally, the second signal pin includes one or more of a G signal pin, an S signal pin, and a K signal pin; and the first signal pin includes one or more of a G signal pin, an S signal pin, and a K signal pin, wherein the K signal pin is arranged on a side away from the power pin.
[0075] Optionally, whether the K signal pin needs to be configured is determined based on actual application requirements.
[0076] Optionally, there are multiple first signal pins, and the first signal pins are arranged on both sides of the power pin.
[0077] Optionally, there are multiple power pins, and the power pins are arranged on both sides of the first signal pin.
[0078] Optionally, the power electrode of the power chip is electrically connected to the power pin, including: directly connecting the power electrode of the power chip to the power pin; or interconnecting the power electrode of the power chip to the power pin by wire bonding or sintering.
[0079] Optionally, the signal electrode of the power chip is connected to the first signal pin and the second signal pin, including: the signal electrode of the power chip is connected to the first signal pin and the second signal pin by bonding or sintering; or, the signal electrode of the power chip is connected to the first signal pin and the second signal pin by copper wire bonding.
[0080] Optionally, the method for preparing a power semiconductor device further includes: disposing an insulating heat sink with a heat dissipation surface facing upward in the substrate.
[0081] The above description and accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the technical solutions recorded in this application. As used in the technical solutions recorded in this application, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.
Claims
1. A power semiconductor device, characterized in that: include: A substrate, a chip, a power pin, a first signal pin, and a second signal pin; The chip is arranged on the substrate and is electrically connected to the power pin, the first signal pin, and the second signal pin; The first signal pin and the power pin are arranged on the same side of the substrate; The second signal pin and the power pin are arranged on different sides of the substrate.
2. The power semiconductor device according to claim 1, characterized in that: The arrangement distance between the power pin and the first signal pin is greater than the arrangement distance between two adjacent second signal pins.
3. The power semiconductor device according to claim 1, characterized in that: The first signal pin and the power pin are arranged on the first side surface of the substrate; The second signal pin is disposed on one or more of the second side surface, the third side surface, and the fourth side surface of the substrate; The second side surface is adjacent to the first side surface, the third side surface is opposite to the first side surface, and the fourth side surface is opposite to the second side surface.
4. The power semiconductor device according to claim 1, characterized in that: The second signal pin includes one or more of a G signal pin, an S signal pin, and a K signal pin; and, The first signal pin includes one or more of a G signal pin, an S signal pin, and a K signal pin, wherein the K signal pin is arranged at a side away from the power pin.
5. The power semiconductor device according to claim 4, characterized in that: There are multiple first signal pins, and the first signal pins are arranged on both sides of the power pins.
6. The power semiconductor device according to claim 4, characterized in that: There are multiple power pins, and the power pins are arranged on both sides of the first signal pin.
7. The power semiconductor device according to any one of claims 1 to 6, characterized in that: The power pin is a drain potential, and the first signal pin and the second signal pin are a gate potential and a source potential.
8. The power semiconductor device according to any one of claims 1 to 6, characterized in that: Also includes: The insulating heat sink is arranged on the base plate, and the heat dissipation surface of the insulating heat sink is arranged upward.
9. A method for preparing a power semiconductor device, characterized in that: include: Fixing the chip on the substrate to form a preliminary electrical connection between the chip and the substrate; Configure the pin layout on the substrate according to the requirements of the application circuit; Electrically connect the power electrode of the power chip to the power pin; The signal electrode of the power chip is connected to the first signal pin and the second signal pin to form an electrical signal path.
10. The preparation method according to claim 9, characterized in that: Also includes: An insulating heat sink with a heat dissipation surface facing upward is arranged in the substrate.