Electronic device

Abstract

The invention provides an electronic device. The electronic device includes a semiconductor chip. The semiconductor chip has a first region of a first functional unit proximate a peripheral edge of the semiconductor chip. The semiconductor chip comprises a semiconductor substrate, a first signal bump and a first power bump. The first signal salient point and the first power supply salient point are respectively arranged on opposite surfaces of the semiconductor substrate and are electrically connected with the first function unit. And the first signal salient point and the first power supply salient point are overlapped with the first region.

Description

Technical Field

[0001] The invention relates to an electronic device, in particular to a bump arrangement of a semiconductor chip. Background Art

[0002] In order to ensure the continued miniaturization and multifunctionality of electronic products and communication equipment, integrated circuit (IC) devices are expected to have small size, support multi-pin connection, high-speed operation and high functionality. This will put forward the requirements for semiconductor manufacturers to develop high-density interconnects for signal wiring and power transmission.

[0003] Although existing IC devices are generally adequate for their intended uses, they are not satisfactory in all respects. Therefore, a new type of electronic device is desired to improve the voltage (IR) drop problem in high-density interconnects. Summary of the invention

[0004] An object of the present invention is to provide an improved electronic device having an optimized semiconductor chip layout and configuration to improve its performance and reliability.

[0005] An embodiment of the present invention provides an electronic device. The electronic device includes a semiconductor chip. The semiconductor chip has a first area of ​​a first functional unit near the peripheral edge of the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a first signal bump and a first power bump. The first signal bump and the first power bump are respectively arranged on opposite surfaces of the semiconductor substrate and are electrically connected to the first functional unit. The first signal bump and the first power bump both overlap with the first area.

[0006] An embodiment of the present invention provides an electronic device. The electronic device includes a semiconductor chip. The semiconductor chip has a peripheral edge region. The semiconductor chip includes a first functional unit, a front-side interconnection structure, and a back-side interconnection structure. The front-side interconnection structure is arranged above the first functional unit. The back-side interconnection structure is arranged below the first functional unit. The peripheral edge region includes a first signal bump and a first power bump. The first signal bump is arranged on the front-side interconnection structure and is electrically connected to the first functional unit. The first power bump is arranged on the back-side interconnection structure and is electrically connected to the first functional unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention may be more fully understood by reading the following detailed description and referring to the accompanying drawings, in which:

[0008] Figure 1 is a schematic cross-sectional view of an electronic device according to some embodiments of the present disclosure;

[0009] Figure 2 According to some embodiments of the present disclosure Figure 1 An enlarged top view of an electronic device portion of the device;

[0010] Figure 3 According to some embodiments of the present disclosure Figure 1 an enlarged bottom view of an electronic device portion of the device;

[0011] Figure 4 is a schematic cross-sectional view of an electronic device according to some embodiments of the present disclosure;

[0012] Figure 5 According to some embodiments of the present disclosure Figure 4 An enlarged top view of an electronic device portion of the device;

[0013] Figure 6 According to some embodiments of the present disclosure Figure 4 an enlarged bottom view of an electronic device portion of the device;

[0014] Figure 7 is a schematic cross-sectional view of an electronic device according to some embodiments of the present disclosure;

[0015] Figure 8 According to some embodiments of the present disclosure Figure 7 An enlarged top view of an electronic device portion of the device;

[0016] Fig. 9 According to some embodiments of the present disclosure Figure 7 an enlarged bottom view of an electronic device portion of the device;

[0017] Fig.10 is a schematic cross-sectional view of an electronic device according to some embodiments of the present disclosure;

[0018] Fig.11 According to some embodiments of the present disclosure Fig.10 an enlarged top view of a portion of an electronic device of; and

[0019] Fig.12 According to some embodiments of the present disclosure Fig.10 An enlarged bottom view of the electronic device portion of the . DETAILED DESCRIPTION

[0020] The following description is intended to illustrate the general principles of the invention and should not be taken as a limiting description. The scope of the invention is best determined by the appended claims.

[0021] Advanced integrated circuit (IC) devices are becoming increasingly multifunctional and shrinking in size. Although the shrinking process generally improves production efficiency and reduces associated costs, it also increases the complexity of processing and manufacturing IC devices. For example, fin field effect transistors (FinFETs) have been introduced to replace planar transistors. Among these FinFETs, gate-all-around (GAA) structures such as nanosheet or nanowire metal oxide semiconductor field effect transistors (MOSFETs) have been developed with excellent electrical characteristics, such as better power performance and area scaling than current FinFET technology. In addition, back-side power technology is used in the gate-all-around (GAA) structure to reduce front-side wiring, thereby reducing back-end-of-line (BEOL) capacitance and IR drop, thereby improving the performance of the IC. Although existing integrated circuit (IC) devices are generally adequate, they are not satisfactory in various aspects. For example, since the pitch of the input / output (I / O) cell is much smaller than the pitch of the I / O bumps of the I / O cell, it is a challenge to meet the I / O bump arrangement requirements of the input / output (I / O) cell in the limited peripheral edge of the semiconductor chip. Therefore, there is a need for further improvements in electronic devices to provide improved input / output (I / O) bump designs.

[0022] Figure 1 is a schematic cross-sectional view of an electronic device 500A according to some embodiments of the present disclosure. Figure 2 According to some embodiments of the present disclosure Figure 1 An enlarged top view of a portion 270A of an electronic device 500A. Figure 3 According to some embodiments of the present disclosure Figure 1 An enlarged bottom view of a portion of electronic device 500A. Figure 1 It is also a schematic cross-sectional view along the line AA′ passing through the peripheral edge region and the central region of the semiconductor chip 400A. Figure 2 and Figure 3 Bump arrangements are shown on the top and bottom surfaces of the semiconductor chip 400A near the peripheral edge 400E.

[0023] Electronic device 500A includes semiconductor chip 400A. Semiconductor chip 400A includes top surface 400TS, bottom surface 400BS and peripheral edge (edge ​​surface) 400E. In some embodiments, semiconductor chip 400A is applied to backside power supply technology. In addition, semiconductor chip 400A can be manufactured by full gate (GAA) process. In some embodiments, semiconductor chip 400A can be mounted on a base (not shown), including printed circuit board (PCB), substrate or interposer. In addition, another substrate (or interposer) can be arranged on semiconductor chip 400A and opposite to the base. In some embodiments, semiconductor chip 400A can be electrically connected to base and another substrate by bumps (e.g., micro bumps, controlled collapse chip connection (C4) bumps, or a combination thereof) to form a wafer-level fan-out semiconductor package assembly. Bumps can be arranged on top surface 400TS and bottom surface 400BS of semiconductor chip 400A.

[0024] In some embodiments, the semiconductor chip 400A has a first region R1 and a second region R2. The first region R1 is located near the peripheral edge 400E of the semiconductor chip 400A. The first region R1 is arranged continuously along the peripheral edge 400E. Therefore, the first region R1 is also referred to as the peripheral edge region R1. In addition, the first region R1 can provide space for one or more first functional units C1 disposed therein. The second region R2 corresponds to the central portion of the semiconductor chip 400A, also referred to as the central region R2. The second region R2 is further away from the corresponding peripheral edge 400E than the first region R1. In addition, the first region R1 can surround the second region R2. In some embodiments, the second region R2 provides space for one or more second functional units C2 disposed therein.

[0025] In some embodiments, the second region R2 may also provide space for various functional units, including logic, memory or processor units. The first region R1 provides an electrical interface between the second region R2 and external circuits.

[0026] In some embodiments, the semiconductor chip 400A includes a semiconductor substrate 200 , a first functional unit C1 , a second functional unit C2 , a front-side interconnect structure 210 , a back-side interconnect structure 220 , a signal bump BS1 - 1 , and power bumps BP1 - 1 , BP2 - 1 .

[0027] The semiconductor substrate 200 has a front surface 200F and a back surface 200B. In some embodiments, the material of the semiconductor substrate 200 includes Si, SiP, SiGe, SiC, SiPC, Ge, SOI-Si, SOI-SiGe, III-VI materials, or combinations thereof.

[0028] In the present embodiment, the first functional unit C1 is formed on the front side surface 200F of the semiconductor substrate 200. The first functional unit C1 may include an input / output (I / O) unit. The I / O unit is configured to transmit data and signals to an external environment (e.g., another chip, an active and / or passive element mounted on the same substrate (e.g., a printed circuit board (PCB))). In some embodiments, the second functional unit C2 is formed on the front side surface 200F of the semiconductor substrate 200. The second functional unit C2 may include a central power supply unit. The central power supply unit may provide power to the core functional unit of the semiconductor chip 400A and transmit the power to the peripheral power supply connection. In some embodiments, the first functional unit C1 and the second functional unit C2 may be composed of transistors, diodes, resistors, capacitors and other active / passive devices according to design requirements.

[0029] The front-side interconnect structure 210 is disposed on the front surface 200F of the semiconductor substrate 200. The back-side interconnect structure 220 is disposed on the back surface 200B of the semiconductor substrate 200 and is opposite to the front-side interconnect structure 210. The front-side interconnect structure 210 is separated from the back-side interconnect structure 220 by the semiconductor substrate 200. In the present embodiment, the front-side interconnect structure 210 is formed to cover and electrically connect to the first functional unit C1 and the second functional unit C2. The back-side interconnect structure 220 is electrically connected to the first functional unit C1.

[0030] In some embodiments, the front-side interconnect structure 210 may include multiple dielectric layers and conductive wiring (including signal wiring, power wiring, and ground wiring) formed in the multiple dielectric layers. The conductive wiring including conductive lines and vias (not shown) may be made of copper or copper alloys and may be formed using one or more damascene processes. The dielectric layer may include an interlayer dielectric (ILD) layer and an intermetallic dielectric (IMD) layer.

[0031] In some embodiments, the front-side interconnect structure 210 may include signal wiring (e.g., signal wiring 230S1) and ground wiring (not shown). The signal wiring is configured to transmit data signals, control signals, and other user signals. The ground wiring is used for grounding of the semiconductor chip 400A. In some other embodiments, the front-side interconnect structure 260 may also include power wiring (e.g., power wiring 230P2). The power wiring may include a positive power supply voltage VDD, a ground power supply voltage VSS, an overdrive voltage signal (e.g., a signal greater than VDD), a negative power supply voltage signal, and other power supply voltage signals.

[0032] In some embodiments, the backside interconnect structure 220 may be similar to the frontside interconnect structure 210 and include multiple dielectric layers and conductive wiring (including signal wiring, power wiring, and ground wiring) formed in the multiple dielectric layers. The number of dielectric layers in the frontside interconnect structure 210 and the backside interconnect structure 220 may be the same or different. In some embodiments, the backside interconnect structure 220 may include power wiring (e.g., power wiring 240P1) and ground wiring (not shown). In some other embodiments, the backside interconnect structure 220 may also include signal wiring (e.g., Figure 4 Signal wiring 240S1) shown in.

[0033] In some embodiments, the conductive wiring in the backside interconnect structure 220 is electrically connected to the first functional unit C1 through one or more through-substrate vias (TSVs) passing through the semiconductor substrate 200. For example, the power wiring 240P1 is electrically connected to the first functional unit C1 through the through-substrate via TSV-P1. The through-substrate via TSV-P1 may have a first end that terminates at the front surface 200F and is connected to a corresponding terminal of the first functional unit C1. The through-substrate via TSV-P1 may have a second end that terminates at the back surface 200F of the semiconductor substrate 200 and is connected to the power wiring 240P1.

[0034] In some embodiments, the semiconductor chip 200 includes a signal bump BS1 - 1 , a power bump BP1 - 1 , and ground bumps BG1 - 1 , BG1 - 2 electrically connected to the first functional unit C1 .

[0035] In some embodiments, the number of signal bumps BS1-1, power bumps BP1-1, and ground bumps BG1-1, BG1-2 corresponding to the first functional unit C1 may have a specific signal to power / ground ratio. For example, when the first functional unit C1 is an I / O unit, the signal to power / ground ratio of the first functional unit C1 may be 4:1. For each pair of VDD and VSS power signals, four signal bumps are provided, and the total number of signal, power, and ground bumps is 6.

[0036] For example, the signal bump BS1-1 and the ground bump BG1-1 are disposed at the outermost layer of the front-side interconnect structure 210. In other words, the signal bump BS1-1 and the ground bump BG1-1 are disposed on the top surface 400TS of the semiconductor chip 400A. The signal bump BS1-1 is electrically connected to the signal wiring 230S1 of the front-side interconnect structure 210. The ground bump BG1-1 is electrically connected to the ground wiring (not shown) of the front-side interconnect structure 210. The signal bump BS1-1 and the ground bump BG1-1 are electrically connected to the corresponding bump pads (not shown) of the front-side interconnect structure 210.

[0037] In some embodiments, the power bump BP1-1 and the ground bump BG1-2 are disposed on the outermost layer of the backside interconnect structure 220. In other words, the power bump BP1-1 and the ground bump BG1-2 are disposed on the bottom surface 400BS of the semiconductor chip 400A. The power bump BP1-1 is electrically connected to the power wiring 240P1 of the backside interconnect structure 220. The ground bump BG1-2 is electrically connected to the ground wiring (not shown) of the backside interconnect structure 220. The power bump BP1-1 and the ground bump BG1-2 are electrically connected to corresponding bump pads (not shown) of the backside interconnect structure 220.

[0038] In some embodiments, the signal bump BS1-1 is separated by the semiconductor substrate 200, the front-side interconnect structure 210, and the back-side interconnect structure 220. In addition, the ground bump BG1-1 is separated by the semiconductor substrate 200, the front-side interconnect structure 210, and the back-side interconnect structure 220.

[0039] In some embodiments, the signal bumps BS1-1 and the ground bumps BG1-1 on the front-side interconnect structure 210 may be arranged into a bump array BA1-1 having a single row or multiple rows. The bump array BA1-1 may overlap at least the first region R1.

[0040] The signal bumps BS1-1 and the ground bumps BG1-1 of the bump array BA1-1 have a bump pitch P1 (in the row and column directions). In some embodiments, the pitch P1 is greater than the width W1 of the first region R1. In addition, the width W1 is measured along a direction substantially perpendicular to the corresponding peripheral edge 400E of the semiconductor chip 400A.

[0041] In the bump array BA1-1, the signal bump BS1-1 may be arranged at a position closer to the peripheral edge 400E than the ground bump BG1-1. For example, the signal bump BS1-1 may be arranged in a single row overlapping only the first region R1. Alternatively, the signal bump BS1-1 may be arranged in multiple rows overlapping the first region R1 and the second region R2, depending on the total number of the signal bump BS1-1 and the size of the first region R1. In addition, the ground bump BG1-1 may be arranged to overlap the second region R2.

[0042] In some embodiments, the power bumps BP1-1 and the ground bumps BG1-2 on the backside interconnect structure 220 may be arranged into a bump array BA1-2 overlapping the first region R1. In some embodiments, the bump array BA1-1 and the bump array BA1-2 have the same bump pitch P1.

[0043] Due to the ratio of signal to power / ground, the number of power bumps and ground bumps is less than the number of power bumps corresponding to the same first functional unit C1, and the power bumps BP1-1 and ground bumps BG1-2 on the backside interconnect structure 220 can be arranged into a single row of bump arrays BA1-2 along and overlapping with the first region R1. The bump array BA1-2 may not overlap with the second region R2. In the bump array BA1-2, the power bumps BP1-1 can be arranged alternately with the ground bumps BG1-2. When the first functional unit C1 is an I / O unit, the bump arrays BA1-1 and BA1-2 are also referred to as I / O bump arrays BA1-1 and BA1-2.

[0044] In the first region R1, power bumps BP1-1 and some signal bumps BS1-1 are disposed on opposite surfaces of the semiconductor substrate 200. Ground bumps BG1-2 and some signal bumps BS1-1 are disposed on opposite surfaces of the semiconductor substrate 200. More specifically, the power bumps BP1-1 are disposed on the back surface 200B of the semiconductor substrate 200. Some signal bumps BS1-1 are disposed on the front surface 200F of the semiconductor substrate 200. In addition, ground bumps BG1-2 are disposed on the back surface 200B of the semiconductor substrate 200.

[0045] The semiconductor chip 200 further includes a power bump BP2-1 electrically connected to the second functional unit C2. For example, the power bump BP2-1 is disposed at the outermost layer of the front-side interconnect structure 210. In other words, the power bump BP2-1 is disposed on the top surface 400TS of the semiconductor substrate 200. The power bump BP2-1 is electrically connected to the power wiring 230P2 of the front-side interconnect structure 210. The power bump BP2-1 is electrically connected to a corresponding bump pad (not shown) of the front-side interconnect structure 210.

[0046] In some embodiments, the power bumps BP2-1 on the front-side interconnect structure 210 may be arranged in a bump array BA2 having multiple rows. The bump array BA2 may overlap the second region R2. In addition, the power bumps BP2-1 may be alternately arranged with the ground bumps BG1-1 and / or the signal bumps BS1-1 on the second region R2.

[0047] In some embodiments, the power bumps BP2-1 may be arranged in various shapes, sizes, and spacings in the top view. The shape, size, and spacing of the power bumps BP2-1 arranged alternately with the ground bumps BG1-1 and / or the signal bumps BS1-1 may be the same as the shape, size, and spacing of the ground bumps BG1-1 and / or the signal bumps BS1-1. For example, the power bumps BP2-1 arranged alternately with the ground bumps BG1-1 and / or the signal bumps BS1-1 may have an elliptical shape with a smaller size and spacing (e.g., spacing P1). The power bumps BP2-1 that are not arranged alternately with the ground bumps BG1-1 and / or the signal bumps BS1-1 may have a circular shape with a larger size and spacing (e.g., spacing P2).

[0048] In some embodiments, the power bump BP1-1 and the power bump BP2-1 are disposed on opposite surfaces of the semiconductor substrate 200. For example, the power bump BP1-1 is disposed on the front side surface 200F of the semiconductor substrate 200, and the power bump BP2-1 is disposed on the back side surface 200B of the semiconductor substrate 200. When the second functional unit C2 is a central power unit, the bump array BA2 is also referred to as a central power bump array BA2.

[0049] In some embodiments, the bump array BA1-1, the bump array BA1-2, and the bump array BA2 have the same bump pitch P1.

[0050] In the electronic device 500A, the semiconductor substrate 200 is manufactured using backside power technology to reduce frontside wiring. The power bump BP1-1 electrically connected to the first functional unit C1 arranged in the peripheral edge region R1 can be moved to the back side 200B of the semiconductor substrate 200 accordingly. The bump array BA1-1 (I / O bump array BA1-1) for the first functional unit C1 (e.g., I / O unit) can reduce the number of rows. The conductive wiring of the first functional unit C1 in the front-side interconnect structure 210 can be reduced, thereby improving the IR drop problem. In addition, the area of ​​the front-side interconnect structure 210 originally occupied by the bumps (I / O bumps) electrically connected to the first functional unit C1 in the central region R2 can be released to place more power bumps BP2-1 (and corresponding power wiring and bump pads of the front-side interconnect structure 210) for the second functional unit C2 (e.g., central power unit). The bump array BA2 (central power bump array BA2) can have more rows. The performance of the second functional unit C2 can be improved.

[0051] Figure 4 is a schematic cross-sectional view of an electronic device 500B according to some embodiments of the present disclosure. Figure 5 According to some embodiments of the present disclosure Figure 4 An enlarged top view of portion 270B of electronic device 500B. Figure 6 According to some embodiments of the present disclosure Figure 4 An enlarged bottom view of a portion of electronic device 500B. Figure 4 It is also a schematic cross-sectional view along the line AA′ passing through the peripheral edge region R1 and the central region R2 of the semiconductor chip 400B. Figure 5 and Figure 6 The top surface 400TS, the bottom surface 400BS and the arrangement of the bumps near the peripheral edge 400E of the semiconductor chip 400B are shown. Figure 1 , Figure 2 and Figure 3 The same or similar elements described above will not be repeated for the sake of brevity.

[0052] like Figure 1-Figure 6 As shown, the difference between the electronic device 500A and the electronic device 500B includes at least that the semiconductor chip 400B of the electronic device 500B further includes a signal bump BS1 - 2 and a signal wiring 240S1 disposed on the back side 200B of the semiconductor substrate 200 and electrically connected to the first functional unit C1 .

[0053] In some embodiments, the signal wiring 240S1 is electrically connected to the first functional unit C1 through the through substrate via TSV-S1. Similarly, the through substrate via TSV-S1 may have a first end that terminates at the front surface 200F and is connected to the corresponding terminal of the first functional unit C1. The through substrate via TSV-S1 may have a second end that terminates at the back surface 200F of the semiconductor substrate 200 and is connected to the signal wiring 240S1.

[0054] The signal bumps BS1-2 are disposed at the outermost layer of the backside interconnect structure 220. In other words, the signal bumps BS1-2 are disposed on the bottom surface 400BS of the semiconductor chip 400B. The signal bumps BS1-2 are electrically connected to the signal wiring 240S1 of the backside interconnect structure 220. The signal bumps BS1-2 are electrically connected to corresponding bump pads (not shown) of the backside interconnect structure 220.

[0055] In some embodiments, the signal bump BS1-2 is disposed above the first region R1. The signal bump BS1-1 and the signal bump BS1-2 are disposed on opposite surfaces of the semiconductor substrate 200. More specifically, the signal bump BS1-1 is disposed on the front surface 200F of the semiconductor substrate 200, and the signal bump BS1-2 is disposed on the back surface 200B of the semiconductor substrate 200.

[0056] In the semiconductor chip 400B, since the signal bumps (including the signal bumps BS1-1 and BS1-2) are arranged on the opposite surface of the semiconductor substrate 200, the number of the signal bumps BS1-1 of the bump array BA1-1 may be reduced. For example, the signal bumps BS1-1 of the semiconductor chip 400B may be arranged only in a single row overlapping the first region R1. In addition, the ground bumps BG1-1 of the semiconductor chip 400B may be arranged at a position overlapping the second region R2.

[0057] In some embodiments, the signal bumps BS1-2, the power bumps BP1-1, and the ground bumps BG1-2 on the backside interconnect structure 220 can be arranged in a single row or multiple rows of bump arrays BA1-3. The bump array BA1-3 can overlap at least the first region R1. For example, the bump array BA1-3 can have multiple rows overlapping the first region R1 and occupying a portion of the second region R2. Since there are no bumps electrically connected to the second functional unit C2 on the backside interconnect structure 220 of the second region R2, the occupied portion of the second region R2 on the back side 200B of the substrate 200 will not affect the arrangement of the bumps (e.g., the power bumps BP2-1) and the performance of the second functional unit C2 (e.g., the central power unit).

[0058] In some embodiments, the bump array BA1-1, the bump array BA1-2, the bump array BA2, and the bump array BA1-3 have the same bump pitch P1.

[0059] Compared with the electronic device 500A, the electronic device 500B further moves some signal bumps electrically connected to the first functional unit C1 to the back side 200B of the semiconductor substrate 200. Therefore, the electronic device 500B can further reduce the number of rows of the bump array BA1-1. More areas of the front-side interconnect structure 210 of the central area R2 originally occupied by the bump array BA1-1 can be released to place more power bumps (and the corresponding power wiring and bump pads of the front-side interconnect structure 210) for use by the second functional unit C2. The performance of the second functional unit C2 can be further improved.

[0060] In some embodiments, the first functional unit (e.g., I / O unit) arranged in the peripheral edge region R1 may be formed on the front surface 200F and the back surface 200B of the semiconductor chip 200. For example, some first functional units and the front side interconnection structure 210 may be formed on the front surface 200F of the semiconductor substrate 200 in sequence. Next, the semiconductor substrate 200 may be turned upside down. Some other first functional units and the back side interconnection structure 220 may be formed on the back side 200B of the semiconductor chip 200 in sequence. Therefore, the signal bumps, power bumps, and ground bumps of the first functional unit may be arranged on the opposite surface of the semiconductor substrate 200. The bump array (e.g., I / O bump array) of the first functional unit on each opposite surface may reduce the number of rows. The bumps of the first functional unit on the front surface 200F of the semiconductor substrate 200 may be arranged at a position overlapping only with the peripheral edge region R1 to minimize the occupied area of ​​the front side interconnection structure 210 in the second region R2. Therefore, more bumps (eg, power bumps BP2-1) of the second functional unit C2 (eg, central power unit) may be arranged in the second region R2 on the front surface 200F of the semiconductor substrate 200. The performance of the second functional unit C2 (eg, central power unit) may be improved.

[0061] Figure 7 is a schematic cross-sectional view of an electronic device 500C according to some embodiments of the present disclosure. Figure 8 According to some embodiments of the present disclosure Figure 7 An enlarged top view of a portion of electronic device 500C in FIG. Fig. 9 According to some embodiments of the present disclosure Figure 7 An enlarged bottom view of a portion of electronic device 500C in FIG. Figure 7 It is also a schematic cross-sectional view along the line BB′ along the peripheral edge region (first region R1 ) of the semiconductor chip 400C. Figure 8 and Fig. 9 The top surface 400TS, the bottom surface 400BS and the bump arrangement near the peripheral edge 400E of the semiconductor chip 400C are shown. Figures 1 to 6 The same or similar elements described above will not be repeated for the sake of brevity.

[0062] like Figure 1-Figure 3 and Figure 7-Figure 9 As shown, the difference between the electronic device 500A and the electronic device 500C at least includes that the semiconductor chip 400C of the electronic device 500C further includes a first functional unit C1'. In addition, the semiconductor chip 400C further includes a signal bump BS1-1', a power bump BP1-1' and ground bumps BG1-1', BG1-2' electrically connected to the first functional unit C1'.

[0063] The first functional unit C1' is formed on the back side 200B of the semiconductor substrate 200 and is covered by the backside interconnect structure 220. In some embodiments, the first functional unit C1 and the first functional unit C1' are formed on opposite surfaces of the semiconductor chip 200 in the first region R1.

[0064] In some embodiments, the signal bump BS1-1' and the ground bump BG1-1' are disposed at the outermost layer of the backside interconnect structure 220. In other words, the signal bump BS1-1' and the ground bump BG1-1' are disposed on the bottom surface 400BS of the semiconductor chip 400A. The signal bump BS1-1' is electrically connected to the signal wiring 240S1' of the backside interconnect structure 220. The ground bump BG1-1' is electrically connected to the ground wiring (not shown) of the backside interconnect structure 220. The signal bump BS1-1' and the ground bump BG1-1' are electrically connected to corresponding bump pads (not shown) of the backside interconnect structure 220.

[0065] In some embodiments, the power bump BP1-1' and the ground bump BG1-2' are disposed at the outermost layer of the front-side interconnect structure 210. In other words, the power bump BP1-1' and the ground bump BG1-2' are disposed on the top surface 400TS of the semiconductor chip 400A. The power bump BP1-1' is electrically connected to the first functional unit C1' through the power wiring 230P1' of the front-side interconnect structure 210 and the through-hole TSV-P1' through the substrate. The ground bump BG1-2' is electrically connected to the first functional unit C1' through the ground wiring 230G2' of the front-side interconnect structure 210 and the through-hole TSV-G1' through the substrate. The power bump BP1-1' and the ground bump BG1-2' are electrically connected to the corresponding bump pads (not shown) of the front-side interconnect structure 210.

[0066] In some embodiments, the signal bump BS1-1′ is separated from the power bump BP1-1′ and the ground bump BG1-2′ by the semiconductor substrate 200, the front-side interconnect structure 210, and the back-side interconnect structure 220. In addition, the ground bump BG1-1′ is separated from the power bump BP1-1′ and the ground bump BG1-2′ by the semiconductor substrate 200, the front-side interconnect structure 210, and the back-side interconnect structure 220.

[0067] In some embodiments, the signal bumps BS1-1' and the ground bumps BG1-1' on the backside interconnect structure 220 may be arranged into a bump array BA1-1' having a single row or multiple rows. The bump array BA1-1' may overlap at least the first region R1. The arrangement and bump spacing of the signal bumps BS1-1' and the ground bumps BG1-1' may be the same or similar to the arrangement and bump spacing of the signal bumps BS1-1 and the ground bumps BG1-1 of the bump array BA1-1, and will not be repeated for brevity.

[0068] In some embodiments, the power bumps BP1-1' and the ground bumps BG1-2' on the front-side interconnect structure 210 may be arranged into a bump array BA1-2' overlapping the first region R1. The arrangement and bump spacing of the power bumps BP1-1' and the ground bumps BG1-2' may be the same or similar to the arrangement and bump spacing of the power bumps BP1-1 and the ground bumps BG1-2 of the bump array BA1-2, and will not be repeated for brevity.

[0069] In the first region R1, the power bump BP1-1' and some signal bumps BS1-1' are disposed on opposite surfaces of the semiconductor substrate 200. The ground bump BG1-2' and some signal bumps BS1-1' are disposed on opposite surfaces of the semiconductor substrate 200. More specifically, the power bump BP1-1' is disposed on the front surface 200F of the semiconductor substrate 200. Some signal bumps BS1-1' are disposed on the back surface 200B of the semiconductor substrate 200. In addition, the ground bump BG1-2' is disposed on the front surface 200F of the semiconductor substrate 200.

[0070] In this embodiment, the signal bump BS1-1 and the signal bump BS1-1′ are disposed on opposite surfaces of the semiconductor substrate 200. The power bump BP1-1 and the signal bump BP1-1′ are disposed on opposite surfaces of the semiconductor substrate 200. The ground bump BG1-1 and the ground bump BG1-1′ are disposed on opposite surfaces of the semiconductor substrate 200. The signal bump BS1-1′ and the power bump BP2-1 are disposed on opposite surfaces of the semiconductor substrate 200.

[0071] In this embodiment, the signal bump BS1 - 1 , the ground bump BG1 - 1 , the power bump BP1 - 1 ′, and the ground bump BG1 - 2 ′ are disposed on the same surface (front surface 200F) of the semiconductor substrate 200 .

[0072] In other words, the first functional unit C1' and the corresponding bump arrays BA1-1' and BA1-2' on the back surface 200B of the semiconductor substrate 200 can be vertically inverted (upside down) relative to the first functional unit C1 and the corresponding bump arrays BA1-1 and BA1-2 on the front surface 200F of the semiconductor substrate 200, respectively.

[0073] The semiconductor chip 400C may further include a third functional unit C3 (I / O cross line unit) disposed laterally (along a direction substantially parallel to the front surface 200F (or back surface 200B) of the semiconductor substrate 200) between the first functional unit C1 and the first functional unit C1'. In some embodiments, the third functional unit C3 is adjacent to the first functional unit C1 and the first functional unit C1'. The power bump BP1-1 is electrically connected to the power bump BP1-1' through the third functional unit C3.

[0074] In some embodiments, the third functional unit C3 includes conductive paths 250 composed of power wirings (not shown) formed in the front-side interconnect structure 210 and the back-side interconnect structure 220 and through-substrate vias (not shown) passing through the semiconductor substrate 200. The conductive paths 250 may be electrically connected to the power wirings 240P1 and 240P1′.

[0075] In some embodiments, the conductive path 250 in the third functional unit C3 may also be composed of a ground wiring (not shown) formed in the front-side interconnect structure 210 and the back-side interconnect structure 220 and a through-substrate via (not shown) passing through the semiconductor substrate 200. The conductive path 250 may be electrically connected to the first functional unit C1 and the ground wiring (not shown) in the first functional unit C1. When the first functional units C1 and C1' are I / O units, the third functional unit C3 is also referred to as an I / O cross line unit C3.

[0076] Fig.10 is a schematic cross-sectional view of an electronic device 500D according to some embodiments of the present disclosure. Fig.11 According to some embodiments of the present disclosure Fig.10 A partially enlarged top view of the electronic device 500D. Fig.12 According to some embodiments of the present disclosure Fig.10 A partially enlarged bottom view of the electronic device 500D is shown. Fig.10 and Fig.11 Also shown are the top surface 400TS, the bottom surface 400BS, and the arrangement of bumps near the peripheral edge 400E of the semiconductor chip 400D. Figures 1 to 9 The same or similar elements described above will not be described repeatedly.

[0077] like Figure 7-Figure 12As shown, the difference between the electronic device 500C and the electronic device 500D includes at least that the semiconductor chip 400D of the electronic device 500D further includes a signal bump BS1-2' and a signal wiring 230S1' disposed on the front surface 200F of the semiconductor substrate 200. In addition, the signal bump BS1-2' is electrically connected to the first functional unit C1' through the signal wiring 230S1' and the through substrate via TSV-S1'.

[0078] In the present embodiment, the signal bumps BS1-2', the power bumps BP1-1 and the ground bumps BG1-2' on the front-side interconnect structure 210 may be arranged as a bump array BA1-3' that at least overlaps with the first region R1. The arrangement and bump spacing of the signal bumps BS1-2', the power bumps BP1-1 and the ground bumps BG1-2' may be the same or similar to the arrangement and bump spacing of the signal bumps BS1-2, the power bumps BP1-1 and the ground bumps BG1-2 in the bump array BA1-3, and will not be described again.

[0079] In the present embodiment, the power bump BP1 - 1 , the ground bump BG1 - 1 , the signal bump BS1 - 2 ′, the power bump BP1 - 1 ′, and the ground bump BG1 - 2 ′ are disposed on the same surface (front surface 200F) of the semiconductor substrate 200 .

[0080] In other words, the first functional unit C1 and the corresponding bump arrays BA1-1 and BA1-3 on the front surface 200F of the semiconductor substrate 200 can be vertically inverted (upside down) relative to the first functional unit C1' and the corresponding bump arrays BA1-1' and BA1-3' on the back surface 200B of the semiconductor substrate 200.

[0081] An embodiment provides an electronic device. The electronic device includes a semiconductor chip. The semiconductor chip has a first region of a first functional unit near the peripheral edge of the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a first signal bump and a first power bump. The first signal bump and the first power bump are respectively arranged on opposite surfaces of the semiconductor substrate and are electrically connected to the first functional unit. The first signal bump and the first power bump both overlap with the first region.

[0082] In some embodiments, the semiconductor chip further includes a front-side interconnect structure and a back-side interconnect structure. The front-side interconnect structure is disposed on the front-side surface of the semiconductor substrate. The back-side interconnect structure is disposed on the back-side surface of the semiconductor substrate. The first signal bump is separated by the semiconductor substrate, the front-side interconnect structure, and the back-side interconnect structure.

[0083] In some embodiments, the backside interconnect structure is disposed on the backside surface of the semiconductor substrate, wherein the first signal bump is separated by the semiconductor substrate, the frontside interconnect structure and the backside interconnect structure. The first signal bump is disposed on the frontside interconnect structure and is electrically connected to the first signal wiring of the frontside interconnect structure. The first power bump is disposed on the backside interconnect structure and is electrically connected to the first power wiring of the backside interconnect structure.

[0084] In some embodiments, the first functional unit is formed on the back surface of the semiconductor substrate and is covered by the back interconnect structure. The first power bump is disposed on the front interconnect structure and is electrically connected to the first power wiring of the front interconnect structure. The first signal bump is disposed on the back interconnect structure and is electrically connected to the first signal wiring of the back interconnect structure.

[0085] In some embodiments, the semiconductor chip further includes a second signal bump overlapping the first region and electrically connected to the first functional unit, wherein the first signal bump and the second signal bump are respectively disposed on opposite surfaces of the semiconductor substrate.

[0086] In some embodiments, the semiconductor chip further includes a first ground bump electrically connected to the first functional unit, wherein the first signal bump and the first ground bump are respectively disposed on opposite surfaces of the semiconductor substrate.

[0087] In some embodiments, the first ground bump overlaps the first region.

[0088] In some embodiments, the first ground bump overlaps the second region.

[0089] In some embodiments, the semiconductor chip has a second region corresponding to a second functional unit in a central portion of the semiconductor chip. The semiconductor chip further includes a third power bump overlapping the second region and electrically connected to the second functional unit, wherein the third power bump is disposed on the front-side interconnect structure.

[0090] In some embodiments, the first power bump and the third power bump are respectively disposed on opposite surfaces of the semiconductor substrate.

[0091] In some embodiments, the first signal bump and the third power bump are respectively disposed on opposite surfaces of the semiconductor substrate.

[0092] In some embodiments, the first functional unit includes an input / output unit, and the second functional unit includes a central power supply unit.

[0093] In some embodiments, the semiconductor chip includes another first functional unit disposed in the first region. The semiconductor chip further includes a third signal bump and a fourth power bump, which are respectively disposed on opposite surfaces of the semiconductor substrate and are electrically connected to the another first functional unit. The fourth signal bump and the fourth power bump both overlap the first region.

[0094] In some embodiments, the other first functional unit is formed on the back side surface of the semiconductor substrate and is covered by the back side interconnect structure. The fourth power bump is disposed on and electrically connected to the front side interconnect structure. The third signal bump is disposed on and electrically connected to the back side interconnect structure.

[0095] In some embodiments, the first signal bump and the third signal bump are respectively disposed on opposite surfaces of the semiconductor substrate.

[0096] In some embodiments, the semiconductor chip further includes a third ground bump electrically connected to the another first functional unit. The fourth power bump and the third ground bump are located on the same surface of the semiconductor substrate.

[0097] In some embodiments, the semiconductor chip further includes a third functional unit laterally inserted between the first functional unit and the another first functional unit, wherein the first power bump is electrically connected to the third power bump through the third functional unit.

[0098] The embodiment also provides an electronic device. The electronic device includes a semiconductor chip. The semiconductor chip has a peripheral edge region. The semiconductor chip includes a first functional unit, a first side interconnection structure, and a second side interconnection structure. The first side interconnection structure is located above the first functional unit. The second side interconnection structure is located below the first functional unit. The peripheral edge region includes a first signal bump and a first power bump. The first signal bump is disposed on the first side interconnection structure and is electrically connected to the first functional unit. The first power bump is disposed on the second side interconnection structure and is electrically connected to the first functional unit.

[0099] In some embodiments, the peripheral edge region further includes a first ground bump disposed on the second-side interconnect structure and electrically connected to the first functional unit.

[0100] In some embodiments, the semiconductor chip has a central region. The semiconductor chip further includes a second functional unit disposed in the central region. The front-side interconnect structure is located above the second functional unit. The central region includes a second power bump disposed on the first-side interconnect structure and electrically connected to the second functional unit.

[0101] In some embodiments, the first functional unit includes an input / output unit, and the second functional unit includes a central power supply unit.

[0102] In some embodiments, the semiconductor chip further includes another first functional unit and a third functional unit. The other first functional unit is arranged in the peripheral edge area. The peripheral edge area further includes a third signal bump arranged on the second side interconnect structure and electrically connected to the other first functional unit. The third functional unit is laterally inserted between the first functional unit and the other first functional unit, wherein the first power bump is electrically connected to the third power bump through the third functional unit.

[0103] In the electronic device, the semiconductor chip is manufactured using backside power technology to reduce front-side wiring. The power bump (e.g., input / output power bump) electrically connected to the first functional unit (e.g., input / output unit) arranged in the peripheral edge area can be moved to the back side of the semiconductor substrate accordingly. The electronic device can also move the signal bump electrically connected to the first functional unit to the back side of the semiconductor substrate. The bump array of the first functional unit can reduce the number of rows. The conductive wiring of the first functional unit in the front-side interconnection structure can be reduced, thereby improving the IR voltage drop problem of the front-side interconnection structure.

[0104] In addition, the area of ​​the front-side interconnect structure in the central region originally occupied by the bumps electrically connected to the first functional unit can be released to place more power bumps for the second functional unit (e.g., the central power supply unit). The bump array (central power bump array) can have more rows. The performance of the second functional unit can be improved.

[0105] In addition, the electronic device may include another first functional unit, and the corresponding bump array may be vertically inverted (upside down) relative to the first functional unit and the corresponding bump array on the front side of the semiconductor substrate, respectively. The power supply and ground wiring of the first functional unit on the opposite surface of the semiconductor substrate may be electrically connected together through a third functional unit including the power supply and ground wiring and a through hole penetrating the substrate.

[0106] Although the present invention has been described by way of examples and preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, the present invention is intended to cover various modifications and similar arrangements (as will be apparent to those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. An electronic device, characterized in that: include: A semiconductor chip having a first region of a first functional unit near a peripheral edge of the semiconductor chip, wherein the semiconductor chip comprises: a semiconductor substrate; as well as A first signal bump and a first power bump are respectively arranged on opposite surfaces of the semiconductor substrate and electrically connected to the first functional unit, wherein the first signal bump and the first power bump both overlap with the first area.

2. The electronic device according to claim 1, wherein: The semiconductor chip further comprises: A front-side interconnect structure disposed on the front-side surface of the semiconductor substrate; and A backside interconnect structure is disposed on the backside surface of the semiconductor substrate, wherein the first signal bump is separated by the semiconductor substrate, the frontside interconnect structure and the backside interconnect structure.

3. The electronic device according to claim 2, characterized in that: The first functional unit is formed on the front surface of the semiconductor substrate and is covered by the front interconnect structure. The first signal bump is disposed on the front-side interconnect structure and is electrically connected to the first signal wiring of the front-side interconnect structure, and The first power bump is disposed on the back-side interconnect structure and is electrically connected to a first power wiring of the back-side interconnect structure.

4. The electronic device according to claim 2, characterized in that: The first functional unit is formed on the backside surface of the semiconductor substrate and is covered by the backside interconnect structure. The first power bump is disposed on the front-side interconnect structure and is electrically connected to a first power wiring of the front-side interconnect structure, and The first signal bump is disposed on the backside interconnect structure and is electrically connected to a first signal wiring of the backside interconnect structure.

5. The electronic device according to claim 1, wherein: The semiconductor chip further comprises: A second signal bump overlaps the first region and is electrically connected to the first functional unit, wherein the first signal bump and the second signal bump are respectively disposed on opposite surfaces of the semiconductor substrate.

6. The electronic device according to claim 1, wherein: The semiconductor chip further comprises: A first grounding bump is electrically connected to the first functional unit, wherein the first signal bump and the first grounding bump are respectively disposed on opposite surfaces of the semiconductor substrate.

7. The electronic device according to claim 6, characterized in that: The first ground bump overlaps the first region.

8. The electronic device according to claim 6, characterized in that: The first ground bump overlaps the second region.

9. The electronic device according to claim 2, characterized in that: The semiconductor chip has a second region corresponding to a second functional unit in a central portion of the semiconductor chip, wherein the semiconductor chip further comprises: A third power bump overlaps the second region and is electrically connected to the second functional unit, wherein the third power bump is disposed on the front-side interconnect structure.

10. The electronic device according to claim 9, characterized in that: The first power bump and the third power bump are respectively disposed on opposite surfaces of the semiconductor substrate.

11. The electronic device according to claim 9, characterized in that: The first signal bump and the third power bump are respectively disposed on opposite surfaces of the semiconductor substrate.

12. The electronic device according to claim 9, characterized in that: The first functional unit includes an input / output unit, and the second functional unit includes a central power supply unit.

13. The electronic device according to claim 3, characterized in that: The semiconductor chip includes another first functional unit disposed in the first region, and the semiconductor chip further includes: A third signal bump and a fourth power bump are respectively arranged on opposite surfaces of the semiconductor substrate and electrically connected to the other first functional unit, wherein the fourth signal bump and the fourth power bump both overlap with the first area.

14. The electronic device according to claim 13, characterized in that: The other first functional unit is formed on the backside surface of the semiconductor substrate and is covered by the backside interconnect structure, The fourth power bump is disposed on and electrically connected to the front-side interconnect structure, and The third signal bump is disposed on and electrically connected to the backside interconnect structure.

15. The electronic device according to claim 13, characterized in that: The first signal bump and the third signal bump are respectively disposed on opposite surfaces of the semiconductor substrate.

16. The electronic device according to claim 13, characterized in that: The semiconductor chip further comprises: A third ground bump is electrically connected to the other first functional unit, wherein the fourth power bump and the third ground bump are arranged on the same surface of the semiconductor substrate.

17. The electronic device according to claim 13, characterized in that: The semiconductor chip further comprises: A third functional unit is laterally inserted between the first functional unit and the another first functional unit, wherein the first power bump is electrically connected to the third power bump through the third functional unit.

18. An electronic device, characterized in that: include: A semiconductor chip having a peripheral edge region, wherein the semiconductor chip comprises: a first functional unit disposed in the peripheral edge region; a first-side interconnect structure disposed above the first functional unit; and a second-side interconnect structure disposed below the first functional unit, The peripheral edge area includes: a first signal bump disposed on the first-side interconnect structure and electrically connected to the first functional unit; and A first power bump is disposed on the second-side interconnect structure and electrically connected to the first functional unit.

19. The electronic device according to claim 18, characterized in that: The peripheral edge region further includes: A first ground bump is disposed on the second-side interconnect structure and electrically connected to the first functional unit.

20. The electronic device according to claim 18, characterized in that The semiconductor chip has a central region, and the semiconductor chip further comprises: a second functional unit disposed in the central area, wherein the front-side interconnect structure is located above the second functional unit, and The central area includes: A second power bump is disposed on the first-side interconnect structure and electrically connected to the second functional unit.

21. The electronic device according to claim 20, characterized in that: The first functional unit includes an input / output unit, and the second functional unit includes a central power supply unit.

22. The electronic device according to claim 18, characterized in that The semiconductor chip further comprises: another first functional unit disposed in the peripheral edge region, and The peripheral edge area further includes: a third signal bump disposed on the second-side interconnect structure and electrically connected to another first functional unit; and a fourth power bump disposed on the first-side interconnect structure and electrically connected to the other first functional unit; and A third functional unit is laterally inserted between the first functional unit and the another first functional unit, wherein the first power bump is electrically connected to the third power bump through the third functional unit.

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