A semiconductor test structure and a test method

Abstract

The present invention provides a semiconductor test structure and a test method, the semiconductor test structure includes a substrate, a doped region is formed on it, and the bottom of the doped region is continuous; at least two metal oxide field effect transistors; a contact region formed on the doped region; a conduction voltage terminal, electrically connected to the gate, used to apply a conduction voltage to conduct the metal oxide field effect transistor; a test voltage terminal, electrically connected to the first heavily doped region and / or the second heavily doped region, used to apply a scanning voltage; and a current measurement terminal, electrically connected to the contact region; wherein the test voltage terminal, the metal oxide field effect transistor, the source and drain region, the doped region, the contact region, and the current measurement terminal form a measurement loop. Through the semiconductor test structure and test method provided by the present invention, the reverse bias junction leakage of the source and drain regions with a small Poly spacing can be measured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor testing structure and a testing method. Background Art

[0002] In modern semiconductor device manufacturing, deep submicron CMOS processes are widely used. In these processes, in order to improve the performance of MOS transistors and reduce device size, it is usually necessary to form a metal silicide layer at the source and drain of the MOS tube. The introduction of metal silicide is mainly to reduce contact resistance, thereby improving current conduction efficiency and improving device speed and performance.

[0003] The formation of metal silicide has strict requirements on process accuracy. If there is a process deviation in this process, the silicide layer may excessively invade the silicon layer, forming a silicide spike phenomenon. This phenomenon is particularly obvious in the source and drain regions of the device, which will cause the leakage current to increase when the PN junction is reverse biased, that is, reverse bias junction leakage. This leakage not only affects the normal operation of the device, but may also cause the chip's reliability to decrease and power consumption to increase.

[0004] With the advancement of CMOS process technology nodes, the gate (Poly) spacing of MOS transistors continues to shrink. This spacing reduction makes it easier for silicide spikes to form, especially in the source and drain regions where the Poly spacing is small. In actual operation, the measurement of reverse bias junction leakage is usually completed by applying a reverse bias voltage to the vias (Contact) at the source and drain positions and collecting the leakage current. However, in areas where the Poly spacing is extremely small, due to space limitations, vias cannot be placed for effective measurement and monitoring. Therefore, there is room for improvement. Summary of the invention

[0005] The object of the present invention is to provide a semiconductor test structure and a test method, which can measure the reverse bias junction leakage of the source and drain regions with a small Poly spacing.

[0006] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0007] The present invention provides a semiconductor test structure, characterized in that it comprises:

[0008] A substrate having a doped region formed thereon, wherein the bottom of the doped region is continuous;

[0009] At least two metal oxide field effect transistors, the metal oxide field effect transistors comprising a gate, a first lightly doped drain, a second lightly doped drain, a first heavily doped region, and a second heavily doped region, the gate being formed on the doped region, the first lightly doped drain and the first heavily doped region being formed in sequence on one side of the gate, the second lightly doped drain and the second heavily doped region being formed in sequence on the other side of the gate, and the second heavily doped regions of two adjacent metal oxide field effect transistors being connected to the first heavily doped region to form a source and drain region;

[0010] a contact region formed on the doped region;

[0011] A conduction voltage terminal, electrically connected to the gate, for applying a conduction voltage to conduct the metal oxide field effect transistor;

[0012] a test voltage terminal, electrically connected to the first heavily doped region and / or the second heavily doped region, for applying a scan voltage; and

[0013] a current measuring terminal electrically connected to the contact area;

[0014] The test voltage terminal, the metal oxide field effect transistor, the source and drain regions, the doping region, the contact region, and the current measurement terminal form a measurement loop.

[0015] In an embodiment of the present invention, the test voltage terminal and / or the current measurement terminal is used to measure leakage current in the measurement loop.

[0016] In one embodiment of the present invention, when the current value of the leakage current in the measurement loop is greater than a preset leakage current value, reverse bias junction leakage occurs in the source-drain region.

[0017] In an embodiment of the present invention, the width of the source and drain regions is smaller than the minimum width for placing vias.

[0018] In one embodiment of the present invention, a shallow trench isolation region is further included. The shallow trench isolation region is formed on the doped region, and the shallow trench isolation region is located between the second heavily doped region and the contact region.

[0019] In one embodiment of the present invention, the number of the metal oxide field effect transistors is two, and the two metal oxide field effect transistors are divided into a first field effect transistor and a second field effect transistor;

[0020] When the conduction voltage terminal conducts the first field effect transistor, the test voltage terminal applies a scan voltage to the first heavily doped region of the first field effect transistor, and the test voltage terminal, the first field effect transistor, the source and drain regions, the contact region, and the current measurement terminal form a measurement loop.

[0021] In one embodiment of the present invention, when the turn-on voltage terminal turns on the second field effect transistor, the test voltage terminal applies a scan voltage to the second heavily doped region of the second field effect transistor, and the test voltage terminal, the second field effect transistor, the source and drain regions, the contact region, and the current measurement terminal form a measurement loop.

[0022] In one embodiment of the present invention, the number of the metal oxide field effect transistors is three, and the three metal oxide field effect transistors are divided into a first field effect transistor, a second field effect transistor and a third field effect transistor;

[0023] When the turn-on voltage terminal turns on the first field effect transistor, the test voltage terminal applies a scan voltage to the first heavily doped region of the first field effect transistor, and the test voltage terminal, the source and drain region between the first field effect transistor and the second field effect transistor, the contact region, and the current measurement terminal form a measurement loop.

[0024] In one embodiment of the present invention, when the turn-on voltage terminal turns on the third field effect transistor, the test voltage terminal applies a scanning voltage to the second heavily doped region of the third field effect transistor, and the test voltage terminal, the source and drain region between the second field effect transistor and the third field effect transistor, the contact region, and the current measurement terminal form a measurement loop.

[0025] The present invention also provides a semiconductor testing method, comprising:

[0026] Providing a substrate, forming a doped region on the substrate, wherein the bottom of the doped region is continuous;

[0027] A contact region and at least two metal oxide field effect transistors are formed on the doped region, wherein the metal oxide field effect transistor comprises a gate, a first lightly doped drain, a second lightly doped drain, a first heavily doped region, and a second heavily doped region, the gate is formed on the doped region, the first lightly doped drain and the first heavily doped region are sequentially formed on one side of the gate, the second lightly doped drain and the second heavily doped region are sequentially formed on the other side of the gate, and the second heavily doped regions of two adjacent metal oxide field effect transistors are connected to the first heavily doped region to form a source and drain region;

[0028] electrically connecting the current measuring end to the contact area;

[0029] Applying a conduction voltage to the metal oxide field effect transistor through a conduction voltage terminal to turn on the corresponding metal oxide field effect transistor;

[0030] A scanning voltage is applied to the first heavily doped region or the second heavily doped region through a test voltage terminal, so that the test voltage terminal, the metal oxide field effect transistor, the source and drain region, the doped region, the contact region, and the current measurement terminal form a measurement loop.

[0031] As described above, the present invention provides a semiconductor test structure and test method, which have the unexpected effect of placing closely arranged gate structures and adopting a special design pattern method, so that leakage can be effectively detected even in a space-constrained location. Since silicide spikes are more likely to form in narrow-pitch gate areas, the scheme of the present invention is particularly suitable for monitoring such structures that are prone to defects. By applying voltage and measuring leakage current, abnormal leakage current caused by silicide spikes can be sensitively detected. By using closely arranged gate structures in the design, reverse-biased junction leakage can be measured in areas where vias cannot be directly placed. This innovation allows efficient electrical characteristic monitoring to be maintained in high-density integrated circuit designs.

[0032] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0034] Figure 1 A schematic diagram of a semiconductor test structure according to an embodiment of the present invention;

[0035] Figure 2 is a cross-sectional view of a semiconductor test structure in one embodiment of the present invention;

[0036] Figure 3 A measurement schematic diagram of two field effect transistors in a semiconductor test structure according to an embodiment of the present invention;

[0037] Figure 4 Another measurement schematic diagram of two field effect transistors in a semiconductor test structure according to an embodiment of the present invention;

[0038] Figure 5 A measurement schematic diagram of three field effect transistors in a semiconductor test structure according to an embodiment of the present invention;

[0039] Figure 6 Another measurement schematic diagram of three field effect transistors in a semiconductor test structure according to an embodiment of the present invention;

[0040] Figure 7 The figure is a flow chart of a semiconductor testing method according to an embodiment of the present invention.

[0041] In the figure: 10, substrate; 20, well region; 30, doping region; 40, first field effect transistor; 41, first heavily doped region; 42, first lightly doped drain; 43, gate; 44, second lightly doped drain; 45, second heavily doped region; 46, source and drain region; 47, via; 50, second field effect transistor; 60, third field effect transistor; 70, contact region; 80, shallow trench isolation region; 91, turn-on voltage terminal; 92, test voltage terminal; 93, current measurement terminal. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] See also Figure 1 and Figure 2 The present invention provides a semiconductor test structure, which can be applied to densely arranged gates 43 (Poly) to effectively measure and monitor the reverse-biased junction leakage of the source-drain region 46 between two adjacent gates 43. The semiconductor test structure may include a substrate 10, a well region 20, a doping region 30, a metal oxide field effect transistor, a contact region 70, a shallow trench isolation region 80, a conduction voltage terminal 91, a test voltage terminal 92, and a current measurement terminal 93.

[0044] See also Figure 2 In one embodiment, a substrate 10 (Sub, substrate) serves as a reference surface and a mechanical support, and a well region 20 and a doping region 30 may be sequentially formed on the surface of the substrate 10 .

[0045] In one embodiment, the well region 20 may be a deep N-well (DNW). A deep N-well refers to a highly doped region formed on the substrate 10 by ion implantation (usually using an N-type dopant, such as phosphorus or arsenic). The deep N-well can provide a good N-type basic environment in the subsequent semiconductor structure to isolate or protect the substrate 10 region below.

[0046] In one embodiment, the doped region 30 may be a P-type doped region (P well). The doped region 30 may be formed on the well region 20. The P-type doped region may be formed by injecting a P-type dopant (such as boron) into the N-type well. The P-type doped region may provide a suitable semiconductor environment for the source and drain of the NMOS device, so that it has electrical properties different from the N-type well itself, thereby being able to properly regulate the electrons flowing through the device.

[0047] In one embodiment, a shallow trench isolation region 80 (STI) can be used to isolate different components in a semiconductor structure to prevent current leakage between adjacent components and ensure that each transistor or circuit component can work normally and independently. Specifically, a trench can be etched on the doped region 30 and then filled with an insulating material (such as silicon dioxide) to form an insulating isolation region, namely, the shallow trench isolation region 80.

[0048] See also Figure 2 In one embodiment, after forming the doping region 30, at least two closely arranged metal oxide field effect transistors (MOSFET) and a contact region 70 may be formed on the doping region 30. A closely arranged metal oxide field effect transistor refers to a metal oxide field effect transistor having a spacing between the gates 43 of two adjacent metal oxide field effect transistors that is less than the length / width of the via 47 (Contact). The metal oxide field effect transistor and the contact region 70 may be isolated by a shallow trench isolation region 80, that is, the metal oxide field effect transistor and the contact region 70 may be distributed on both sides of the shallow trench isolation region 80. The contact region 70 may be a P+ heavily doped region, where P+ refers to a heavily doped P-type region, which can form a low-resistance conductive path due to the high concentration of dopants.

[0049] In one embodiment, the number of closely arranged metal oxide field effect transistors may be two or three. When the number of closely arranged metal oxide field effect transistors is two, the two metal oxide field effect transistors may be distinguished as a first field effect transistor 40 and a second field effect transistor 50. When the number of closely arranged metal oxide field effect transistors is three, the three metal oxide field effect transistors may be distinguished as a first field effect transistor 40, a second field effect transistor 50, and a third field effect transistor 60.

[0050] See also Figure 2 In one embodiment, the first field effect transistor 40 may include a first heavily doped region 41, a first lightly doped drain 42, a gate 43, a second lightly doped drain 44, and a second heavily doped region 45. The gate 43 may be formed on the doping region 30, and the first lightly doped drain 42 and the first heavily doped region 41 are sequentially formed on one side of the gate 43, and the second lightly doped drain 44 and the second heavily doped region 45 are sequentially formed on the other side of the gate 43.

[0051] In one embodiment, the first heavily doped region 41 and the second heavily doped region 45 may be N+ heavily doped regions, forming the source and drain of the MOSFET, where N+ represents a high concentration of N-type doping, which is used to reduce the resistance of the source and drain regions. The first lightly doped drain 42 and the second lightly doped drain 44 may be lightly doped drains (LDD), and the lightly doped drain structure is a structure in which a lighter doping is used on the side of the source and drain close to the channel. The lightly doped drain can be used to reduce the hot carrier effect and reduce the drain end electric field, thereby improving the stability and reliability of the MOSFET. The gate 43 may be made of polysilicon (Poly). In the MOSFET, the gate 43 controls the formation of the channel, and the flow of carriers between the source and the drain is controlled by applying a voltage to the gate 43.

[0052] See also Figure 2 In one embodiment, for closely arranged metal oxide field effect transistors, a heavily doped region can be shared to simplify the structure, that is, the drain of the first field effect transistor 40 can share a heavily doped region with the source of the second field effect transistor 50. By sharing, the length of the metal connection between the devices is reduced, thereby reducing the parasitic resistance and parasitic capacitance, which helps to improve the speed of the circuit. In this embodiment, the second heavily doped region 45 of the first field effect transistor 40 and the first heavily doped region of the second field effect transistor 50 can be shared, and the heavily doped regions between the two can be connected to form a source and drain region 46. The second heavily doped region of the second field effect transistor 50 and the first heavily doped region of the third field effect transistor 60 can be shared, and the heavily doped regions between the two can also be connected to form a source and drain region 46. Among them, the width of the source and drain region 46 is less than the minimum width / length that can be placed on the via 47.

[0053] In one embodiment, the source and drain region 46 between the two closely arranged gates 43 may have reverse-biased junction leakage. For example, in the STI etching and subsequent ion implantation processes, the lattice of the source and drain region 46 may be damaged, resulting in increased junction leakage. For another example, if the film layer morphology of the source and drain region 46 is abnormal, residues will be formed in the subsequent etching or cleaning process, thereby affecting the metallization process. After the metallization process is affected, reverse-biased junction leakage will occur. For another example, using metal silicide (such as nickel silicide) in the source and drain region 46 can reduce the contact resistance, but silicide spikes may also be generated in the source and drain region 46, resulting in reverse-biased junction leakage. Since the width of the source and drain region 46 is less than the minimum width / length that can be placed on the via 47, it is impossible to place the via 47 on the source and drain region 46, and thus it is impossible to effectively measure and monitor the reverse-biased junction leakage of the source and drain region 46.

[0054] In one embodiment, when it is necessary to measure and monitor the reverse bias junction leakage of the source and drain region 46, a conduction voltage terminal 91 can be electrically connected to the gate 43. The conduction voltage terminal 91 can be used to apply a conduction voltage to the gate 43, and the gate 43 can control the switching state of the metal oxide field effect tube. By applying a specific conduction voltage to the gate 43 through the conduction voltage terminal 91, the metal oxide field effect tube can enter the conduction state. In this state, a current channel is formed between the source and the drain, and the conduction resistance of the metal oxide field effect tube is reduced. Among them, the magnitude of the conduction voltage can be unlimited, for example, it can be 2.2V. Among them, on the gate of the second field effect tube 50, 0V or a voltage greater than the conduction voltage can be applied.

[0055] In one embodiment, the first heavily doped region 41 and / or the second heavily doped region 45 may be electrically connected to a test voltage terminal 92. The contact region 70 may be electrically connected to a current measuring terminal 93. When the metal oxide field effect transistor is turned on, a scanning voltage is applied to the first heavily doped region 41 or the second heavily doped region 45 through the test voltage terminal 92. At this time, the test voltage terminal 92, the metal oxide field effect transistor, the source and drain regions 46, the doping region 30, the contact region 70, and the current measuring terminal 93 may form a measuring loop.

[0056] In one embodiment, the number of metal oxide field effect transistors is two as an example for description. At this time, one metal oxide field effect transistor can be selected to be turned on to measure the reverse bias junction leakage of the source and drain region 46 between the two metal oxide field effect transistors.

[0057] See also Figure 3 In one embodiment, the on-voltage terminal 91 can apply an on-voltage to the gate 43 of the first field effect transistor 40 to turn on the first field effect transistor 40. Subsequently, the test voltage terminal 92 can apply a scan voltage to the first heavily doped region 41 of the first field effect transistor 40, and the scan voltage can be gradually increased from 0V until it is greater than the on-voltage. At this time, a measurement loop can be formed between the test voltage terminal 92, the first field effect transistor 40, the source and drain regions 46, the contact region 70, and the current measurement terminal 93. The test voltage terminal 92 and / or the current measurement terminal 93 can be used to measure the leakage current in the measurement loop. The magnitude of the scan voltage can be unlimited, for example, it can be 4V. A voltage of 0V or greater than the on-voltage can be applied to the gate of the second field effect transistor 50.

[0058] See also Figure 4In one embodiment, the conduction voltage terminal 91 can apply a conduction voltage to the gate of the second field effect transistor 50 to turn on the second field effect transistor 50. Subsequently, the test voltage terminal 92 can apply a scanning voltage to the second heavily doped region of the second field effect transistor 50. At this time, a measurement loop can be formed between the test voltage terminal 92, the second field effect transistor 50, the source and drain regions 46, the contact region 70, and the current measurement terminal 93. The test voltage terminal 92 and / or the current measurement terminal 93 can be used to measure the leakage current in the measurement loop. Among them, a voltage of 0V or a voltage greater than the conduction voltage can be applied to the gate of the first field effect transistor 40.

[0059] In one embodiment, the number of metal oxide field effect transistors is three as an example for description. At this time, the first or third metal oxide field effect transistor can be selected to be turned on to measure the reverse bias junction leakage of a source and drain region 46 between the two metal oxide field effect transistors.

[0060] See also Figure 5 In one embodiment, the on-voltage terminal 91 can apply an on-voltage to the gate 43 of the first field effect transistor 40 to turn on the first field effect transistor 40. Subsequently, the test voltage terminal 92 can apply a scan voltage to the first heavily doped region 41 of the first field effect transistor 40. At this time, a measurement loop can be formed between the test voltage terminal 92, the first field effect transistor 40, the source and drain regions 46 between the first field effect transistor 40 and the second field effect transistor 50, the contact region 70, and the current measurement terminal 93. The test voltage terminal 92 and / or the current measurement terminal 93 can be used to measure the leakage current in the measurement loop. Among them, a voltage of 0V or greater than the on-voltage can be applied to the gates of the second field effect transistor 50 and the third field effect transistor 60.

[0061] See also Figure 6 In one embodiment, the conduction voltage terminal 91 can apply a conduction voltage to the gate of the third field effect transistor 60 to turn on the third field effect transistor 60. Subsequently, the test voltage terminal 92 can apply a scanning voltage to the second heavily doped region of the third field effect transistor 60. At this time, a measurement loop can be formed between the test voltage terminal 92, the third field effect transistor 60, the source and drain regions 46 between the second field effect transistor 50 and the third field effect transistor 60, the contact region 70, and the current measurement terminal 93. The test voltage terminal 92 and / or the current measurement terminal 93 can be used to measure the leakage current in the measurement loop. Among them, 0V or a voltage greater than the conduction voltage can be applied to the gates of the first field effect transistor 40 and the second field effect transistor 50.

[0062] In one embodiment, during the above test process, even if there is no defect in the source / drain region 46 of the measurement loop, when the measurement loop is turned on, the test voltage terminal 92 and / or the current measurement terminal 93 can also measure the leakage current in the measurement loop. This is a tiny leakage current in normal operation, and the magnitude of the leakage current is about 10e -12 When there is a defect in the source / drain region 46 of the measurement loop, such as a silicide spike defect, the silicide spike defect may cause an unintentional short circuit or other unfavorable current path on the source / drain region 46, causing the leakage current to increase significantly to about 10e -7 The order of magnitude of ampere (0.1μA), this increase in magnitude is obviously abnormal. Therefore, a preset leakage current value can be used. When the current value of the leakage current measured by the test voltage terminal 92 and / or the current measurement terminal 93 is greater than the preset leakage current value, it can be considered that the corresponding source and drain region 46 has reverse junction leakage. When the current value of the leakage current measured by the test voltage terminal 92 and / or the current measurement terminal 93 is less than or equal to the preset leakage current value, it can be considered that the corresponding source and drain region 46 does not have reverse junction leakage. The size of the preset leakage current value can be unlimited, for example, it can be 0.1μA.

[0063] See also Figure 7 The present invention also discloses a semiconductor testing method, which can be applied to the above-mentioned test structure. The testing method may include the following steps:

[0064] Step S10, providing a substrate, forming a doped region on the substrate, wherein the bottom of the doped region is continuous;

[0065] Step S20, forming a contact region and at least two metal oxide field effect transistors on the doped region, wherein the metal oxide field effect transistor includes a gate, a first lightly doped drain, a second lightly doped drain, a first heavily doped region, and a second heavily doped region, the gate is formed on the doped region, the first lightly doped drain and the first heavily doped region are sequentially formed on one side of the gate, the second lightly doped drain and the second heavily doped region are sequentially formed on the other side of the gate, and the second heavily doped regions of two adjacent metal oxide field effect transistors are connected to the first heavily doped region to form a source and drain region;

[0066] Step S30, electrically connecting the current measuring end to the contact area;

[0067] Step S40, applying a conduction voltage to the metal oxide field effect transistor through the conduction voltage terminal to turn on the corresponding metal oxide field effect transistor;

[0068] Step S50, applying a scan voltage to the first heavily doped region or the second heavily doped region through the test voltage terminal, so that the test voltage terminal, the metal oxide field effect transistor, the source and drain regions, the doping region, the contact region, and the current measurement terminal form a measurement loop.

[0069] It can be seen that in the above scheme, the unexpected effect of the present invention is: by placing closely arranged gate structures and adopting a special design pattern method, leakage can be effectively detected even in a space-constrained location. Since silicide spikes are more likely to form in narrow-pitch gate areas, the scheme of the present invention is particularly suitable for monitoring such structures that are prone to defects. By applying voltage and measuring the leakage current, the abnormal leakage current caused by the silicide spikes can be sensitively detected. By using closely arranged gate structures in the design, reverse-biased junction leakage can be measured in areas where vias cannot be directly placed. This innovation allows efficient electrical characteristic monitoring to be maintained in high-density integrated circuit designs.

[0070] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor test structure, characterized in that: include: A substrate having a doped region formed thereon, wherein the bottom of the doped region is continuous; At least two metal oxide field effect transistors, the metal oxide field effect transistors comprising a gate, a first lightly doped drain, a second lightly doped drain, a first heavily doped region, and a second heavily doped region, the gate being formed on the doped region, the first lightly doped drain and the first heavily doped region being formed in sequence on one side of the gate, the second lightly doped drain and the second heavily doped region being formed in sequence on the other side of the gate, and the second heavily doped regions of two adjacent metal oxide field effect transistors being connected to the first heavily doped region to form a source and drain region; a contact region formed on the doped region; A conduction voltage terminal, electrically connected to the gate, for applying a conduction voltage to conduct the metal oxide field effect transistor; a test voltage terminal, electrically connected to the first heavily doped region and / or the second heavily doped region, and used for applying a scan voltage; as well as a current measuring terminal electrically connected to the contact area; Wherein, the test voltage terminal, the metal oxide field effect transistor, the source and drain region, the doping region, the contact region, and the current measurement terminal form a measurement loop; The test voltage terminal and / or the current measurement terminal are used to measure the leakage current in the measurement loop; When the current value of the leakage current in the measurement loop is greater than the preset leakage current value, reverse bias junction leakage occurs in the source-drain region.

2. The semiconductor test structure according to claim 1, characterized in that: The width of the source and drain regions is smaller than the minimum width for placing the via holes.

3. The semiconductor test structure according to claim 1, characterized in that: It also includes a shallow trench isolation region, which is formed on the doped region and is located between the second heavily doped region and the contact region.

4. The semiconductor test structure according to claim 1, characterized in that: The number of the metal oxide field effect transistors is two, and the two metal oxide field effect transistors are divided into a first field effect transistor and a second field effect transistor; When the conduction voltage terminal conducts the first field effect transistor, the test voltage terminal applies a scan voltage to the first heavily doped region of the first field effect transistor, and the test voltage terminal, the first field effect transistor, the source and drain regions, the contact region, and the current measurement terminal form a measurement loop.

5. The semiconductor test structure according to claim 4, characterized in that: When the conduction voltage terminal conducts the second field effect transistor, the test voltage terminal applies a scan voltage to the second heavily doped region of the second field effect transistor, and the test voltage terminal, the second field effect transistor, the source and drain regions, the contact region, and the current measurement terminal form a measurement loop.

6. The semiconductor test structure according to claim 1, characterized in that: The number of the metal oxide field effect transistors is three, and the three metal oxide field effect transistors are divided into a first field effect transistor, a second field effect transistor and a third field effect transistor; When the turn-on voltage terminal turns on the first field effect transistor, the test voltage terminal applies a scan voltage to the first heavily doped region of the first field effect transistor, and the test voltage terminal, the source and drain region between the first field effect transistor and the second field effect transistor, the contact region, and the current measurement terminal form a measurement loop.

7. The semiconductor test structure according to claim 6, characterized in that: When the conduction voltage terminal turns on the third field effect transistor, the test voltage terminal applies a scanning voltage to the second heavily doped region of the third field effect transistor, and the test voltage terminal, the source and drain region between the second field effect transistor and the third field effect transistor, the contact region, and the current measurement terminal form a measurement loop.

8. A semiconductor testing method, characterized in that: include: Providing a substrate, forming a doped region on the substrate, wherein the bottom of the doped region is continuous; A contact region and at least two metal oxide field effect transistors are formed on the doped region, wherein the metal oxide field effect transistor comprises a gate, a first lightly doped drain, a second lightly doped drain, a first heavily doped region, and a second heavily doped region, the gate is formed on the doped region, the first lightly doped drain and the first heavily doped region are sequentially formed on one side of the gate, the second lightly doped drain and the second heavily doped region are sequentially formed on the other side of the gate, and the second heavily doped regions of two adjacent metal oxide field effect transistors are connected to the first heavily doped region to form a source and drain region; electrically connecting the current measuring end to the contact area; Applying a conduction voltage to the metal oxide field effect transistor through a conduction voltage terminal to turn on the corresponding metal oxide field effect transistor; A scanning voltage is applied to the first heavily doped region or the second heavily doped region through a test voltage terminal, so that the test voltage terminal, the metal oxide field effect transistor, the source and drain regions, the doped region, the contact region, and the current measurement terminal form a measurement loop; wherein the test voltage terminal and / or the current measurement terminal are used to measure the leakage current in the measurement loop; when the current value of the leakage current in the measurement loop is greater than a preset leakage current value, reverse bias junction leakage occurs in the source and drain region.

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