Power supply clamp circuit and electronic device including the same

Abstract

The invention relates to a power clamp circuit and an electronic device including the same. The power supply clamp circuit includes an electrostatic discharge (ESD) current discharge circuit including a first MOS transistor, a second MOS transistor, and a third MOS transistor coupled in series between a first power supply rail coupled to a power supply voltage and a second power supply rail coupled to a ground voltage; a first trigger circuit including a first resistor, a first capacitor, and a fourth MOS transistor, and configured to trigger the first MOS transistor; a second trigger circuit including a second resistor, a second capacitor, and a fifth MOS transistor, and configured to trigger the second MOS transistor; and a third trigger circuit configured to turn off the third MOS transistor during normal operation and turn on the third MOS transistor when an ESD event occurs.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0125145 filed in the Korean Intellectual Property Office on September 19, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure generally relate to a power clamp circuit and an electronic device including the power clamp circuit. Background Art

[0004] Power clamp circuits are widely used in the semiconductor industry as an on-chip solution to protect the main circuit or device under test (DUT) from the effects of electrostatic discharge (ESD). Static electricity can accumulate for many reasons, including improper operation of mechanical equipment and the transfer of charge from the human body. When the charge is not transferred, it may cause permanent failure of the core integrated circuit or DUT. The power clamp circuit can include multiple MOS transistors. Since the operating voltage of the MOS transistors that make up the power clamp circuit has a tendency to decrease, measures should be taken to ensure the reliability of the MOS transistors to prevent damage when an ESD event occurs and during normal operation. Summary of the invention

[0005] A power clamp circuit according to an embodiment of the present disclosure may include: an electrostatic discharge (ESD) current discharge circuit, including a first MOS transistor, a second MOS transistor, and a third MOS transistor coupled in series between a first power rail coupled to a power supply voltage and a second power rail coupled to a ground voltage; a first trigger circuit, including a first resistor, a first capacitor, and a fourth MOS transistor, and configured to trigger the first MOS transistor; a second trigger circuit, including a second resistor, a second capacitor, and a fifth MOS transistor, and configured to trigger the second MOS transistor; and a third trigger circuit, configured to turn off the third MOS transistor during normal operation, and to turn on the third MOS transistor when an ESD event occurs.

[0006] An electronic device according to an embodiment of the present disclosure may include a pad, an internal circuit coupled to the pad, a first power rail through which a power supply voltage is provided, a second power rail through which a ground voltage is provided, and a power clamp circuit, which is configured to protect the internal circuit when an electrostatic discharge (ESD) event occurs. The power clamp circuit may include: an ESD current discharge circuit, including a first MOS transistor, a second MOS transistor, and a third MOS transistor coupled in series between the first power rail and the second power rail; a first trigger circuit, including a first resistor, a first capacitor, and a fourth MOS transistor, and configured to trigger the first MOS transistor; a second trigger circuit, including a second resistor, a second capacitor, and a fifth MOS transistor, and configured to trigger the second MOS transistor; and a third trigger circuit, configured to turn off the third MOS transistor during normal operation, and turn on the third MOS transistor when an ESD event occurs. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating an electronic device including a power clamp circuit according to an embodiment of the present disclosure.

[0008] Figure 2 is a circuit diagram showing a power clamp circuit according to an embodiment of the present disclosure.

[0009] Figure 3 The present invention is a diagram showing the Figure 2 A circuit diagram of an example of a voltage branch circuit in which a power clamp circuit includes a first trigger circuit providing a branch voltage.

[0010] Figure 4 The present invention is shown in Figure 2 A circuit diagram of an example of normal operation of the power clamp circuit.

[0011] Figure 5 The present invention is shown in Figure 2 A circuit diagram of an example of the electrostatic discharge protection operation of a power clamp circuit. DETAILED DESCRIPTION

[0012] In the description of the following embodiments, it should be understood that the terms "first" and "second" are intended to identify elements, rather than to define a specific number or sequence of elements. In addition, when an element is referred to as being "on", "above", "above", "below" or "below" another element, it is intended to represent a relative positional relationship, rather than being used to limit certain situations where an element directly contacts another element or there is at least one intermediate element between two elements. Therefore, terms such as "on", "above", "above", "below", "below", "below" used herein are only for the purpose of describing a specific embodiment, rather than for limiting the scope of the present disclosure.

[0013] In addition, when an element is referred to as being "connected" or "coupled" to another element, the element may be directly electrically or mechanically connected or coupled to the other element, or may be indirectly electrically or mechanically connected or coupled to the other element through one or more additional elements between the two elements. In addition, when a parameter is referred to as being "predetermined," it may be intended to mean that the value of the parameter is determined in advance when the parameter is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or may be set during the execution period of the process or algorithm.

[0014] A logic "high" level and a logic "low" level may be used to describe the logic level of an electrical signal. A signal having a logic "high" level may be distinguished from a signal having a logic "low" level. For example, when a signal having a first voltage corresponds to a signal having a logic "high" level, a signal having a second voltage may correspond to a signal having a logic "low" level. In an embodiment, a logic "high" level may be set to a voltage level having a voltage level higher than a logic "low" level. Depending on the embodiment, the logic level of a signal may be set to be different or opposite. For example, a signal having a logic "high" level in one embodiment may be set to have a logic "low" level in another embodiment.

[0015] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the embodiments described herein are only for illustrative purposes and are not intended to limit the scope of the present disclosure.

[0016] Figure 1 is a block diagram illustrating an electronic device including a power clamp circuit according to an embodiment of the present disclosure.

[0017] Reference Figure 1, the electronic device 100 may include a pad 110, an internal circuit 120, an upper ESD protection circuit 131, a lower ESD protection circuit 132, and a power clamp circuit 140. The electronic device 100 may also include a buffer 150. The pad 110 may allow the electronic device 100 to be electrically coupled to an external circuit, such as one or more other integrated circuits. That is, the electronic device 100 may receive a signal from an external circuit through the pad 110 or may send a signal to an external circuit through the pad 110. The pad 110 may be coupled to the upper ESD protection circuit 131, the lower ESD protection circuit 132, and the buffer 150 through the first voltage line 161.

[0018] The internal circuit 120 may perform various types of operations and functions, and may include a plurality of logic devices and circuits, analog devices and circuits, and other types of devices and circuits to perform various types of operations and functions. The internal circuit 120 may include transistors, diodes, preamplifiers, operational amplifiers, buffers, inverters, and / or other circuits. In addition, the internal circuit 120 may include a level shifter adapted to convert a voltage signal within a certain range into a voltage signal within another range, and the internal circuit 120 may include a signal amplification circuit. The internal circuit 120 may include a volatile memory cell such as a DRAM cell or a non-volatile memory cell such as a NAND cell or a NOR cell.

[0019] The internal circuit 120 may be coupled to a second voltage line 162 through which a power supply voltage VDD is applied and a third voltage line 163 through which a ground voltage VSS is applied. The internal circuit 120 may be electrically coupled to the buffer 150. In an embodiment, the buffer 150 may include a pull-up driver and a pull-down driver as input and output circuits. Since the buffer 150 is coupled to the pad 110 through the first voltage line 161, a signal transmitted from the outside through the pad 110 may be transmitted to the internal circuit 120 through the first voltage line 161 and the buffer 150. The signal output from the internal circuit 120 may be transmitted to the outside through the buffer 150, the first voltage line 161 and the pad 110.

[0020] The upper ESD protection circuit 131 may be coupled to the first voltage line 161 and the second voltage line 162. The lower ESD protection circuit 132 may be coupled to the first voltage line 161 and the third voltage line 163. When an ESD event occurs in which an ESD current flows into the pad 110, the ESD current may be discharged to the second voltage line 162 through the upper ESD protection circuit 131, or may be discharged to the third voltage line 163 through the lower ESD protection circuit 132.

[0021] The power clamp circuit 140 may be coupled to the second voltage line 162 and the third voltage line 163. When the electronic device 100 operates normally, the current movement path from the second voltage line 162 to the third voltage line 163 within the power clamp circuit 140 may be blocked. On the other hand, when an ESD event occurs in the electronic device 100, the power clamp circuit 140 may include an ESD current discharge circuit. The current movement path from the second voltage line 162 to the third voltage line 163 may be formed within the power clamp circuit 140. In an embodiment, when an ESD voltage is applied to the pad 110, the ESD current may flow into the power clamp circuit 140 through the upper ESD protection circuit 131 and the second voltage line 162. In this case, the power clamp circuit 140 may allow the ESD current flowing into the power clamp circuit 140 through the second voltage line 162 to be discharged to the third voltage line 163 through the ESD current discharge circuit of the power clamp circuit 140.

[0022] Figure 2 2 is a circuit diagram showing a power clamp circuit according to an embodiment of the present disclosure. The power clamp circuit 200 can be used as described above with reference to Figure 1 The power clamp circuit 140 included in the electronic device 100 is described.

[0023] Reference Figure 2 , the power clamp circuit 200 may include an ESD current discharge circuit 210, a first trigger circuit 221, a second trigger circuit 222, and a third trigger circuit 223. Figure 1 The power clamp circuit ( Figure 1 140), when an ESD event occurs, the power clamp circuit 200 can protect the internal circuit ( Figure 1 120 in the figure) is protected from ESD surge (or ESD current). The power clamp circuit 200 may include a diode 240. The diode 240 may be disposed between the first power rail 231 and the second power rail 232. In an embodiment, the first power rail 231 and the second power rail 232 may be lines through which a power supply voltage VDD and a ground voltage VSS are respectively provided, and may correspond to reference voltages VDD and VSS, respectively. Figure 1 The second voltage line described ( Figure 1 162) and the third voltage line ( Figure 1 163 in the figure). The cathode and anode of the diode 240 may be coupled to the first power rail 231 and the second power rail 232, respectively. When a negative ESD event occurs, the diode 240 may provide an ESD current path from the second power rail 232 to the first power rail 231.

[0024] The ESD current discharge circuit 210 may include a first MOS transistor NM1, a second MOS transistor NM2, and a third MOS transistor NM3 that are serially connected between a first power rail 231 and a second power rail 232. Each of the first MOS transistor NM1, the second MOS transistor NM2, and the third MOS transistor NM3 may be an N-channel MOS (hereinafter referred to as "NMOS") transistor. In the embodiments disclosed herein, the first MOS transistor NM1, the second MOS transistor NM2, and the third MOS transistor NM3 may be referred to as a first NMOS transistor NM1, a second NMOS transistor NM2, and a third NMOS transistor NM3, respectively, and each of the first NMOS transistor NM1, the second NMOS transistor NM2, and the third NMOS transistor NM3 may be implemented using a large MOSFET.

[0025] The gate of the first NMOS transistor NM1 may be coupled to the first gate line 241. Therefore, the first NMOS transistor NM1 may be turned on or off according to the first gate voltage VG1 applied to the first gate line 241. The drain of the first NMOS transistor NM1 may be coupled to the first power rail 231. The source of the first NMOS transistor NM1 may be coupled to the drain of the second NMOS transistor NM2. The gate of the second NMOS transistor NM2 may be coupled to the second gate line 242. Therefore, the second NMOS transistor NM2 may be turned on or off according to the second gate voltage VG2 applied to the second gate line 242. The source of the second NMOS transistor NM2 may be coupled to the drain of the third NMOS transistor NM3. The gate of the third NMOS transistor NM3 may be coupled to the third gate line 243. Therefore, the third NMOS transistor NM3 may be turned on or off according to the third gate voltage VG3 applied to the third gate line 223. The source of the third NMOS transistor NM3 may be coupled to the second power rail 232.

[0026] The first trigger circuit 221 may include a first resistor R1, a first capacitor C1, and a fourth MOS transistor PM1. The first capacitor C1 may be a MOS capacitor. The fourth MOS transistor PM1 may be a P-channel MOS (hereinafter referred to as "PMOS") transistor. In the embodiments disclosed herein, the fourth MOS transistor PM1 may be referred to as a first PMOS transistor PM1. The second trigger circuit 222 may include a second resistor R2, a second capacitor C2, and a fifth MOS transistor PM2. The second capacitor C2 may be a MOS capacitor. The fifth MOS transistor PM2 may be a PMOS transistor. In the embodiments disclosed herein, the fifth MOS transistor PM2 may be referred to as a second PMOS transistor PM2. The resistance of the first resistor R1, the capacitance of the first capacitor C1, the resistance of the second resistor R2, and the capacitance of the second capacitor C2 may be set so that the first RC delay value obtained by multiplying the resistance of the first resistor R1 and the capacitance of the first capacitor C1 is the same as the second RC delay value obtained by multiplying the resistance of the second resistor R2 and the capacitance of the second capacitor C2.

[0027] The first trigger circuit 221 may include a sixth MOS transistor NM4, a seventh MOS transistor NM5, an eighth MOS transistor NM6, and a ninth MOS transistor NM7. Each of the sixth MOS transistor NM4, the seventh MOS transistor NM5, the eighth MOS transistor NM6, and the ninth MOS transistor NM7 may be an NMOS transistor. Hereinafter, the sixth MOS transistor NM4, the seventh MOS transistor NM5, the eighth MOS transistor NM6, and the ninth MOS transistor NM7 may be referred to as a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, and a seventh NMOS transistor NM7, respectively.

[0028] The second trigger circuit 222 may include a tenth MOS transistor NM8, an eleventh MOS transistor NM9, and a twelfth MOS transistor NM10. Each of the tenth MOS transistor NM8, the eleventh MOS transistor NM9, and the twelfth MOS transistor NM10 may be an NMOS transistor. Hereinafter, the tenth MOS transistor NM8, the eleventh MOS transistor NM9, and the twelfth MOS transistor NM10 may be referred to as an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, and a tenth NMOS transistor NM10, respectively.

[0029] The third trigger circuit 223 may include a third resistor R3, a thirteenth MOS transistor PM3, a fourteenth MOS transistor PM4, and a fifteenth MOS transistor NM11. Each of the thirteenth MOS transistor PM3 and the fourteenth MOS transistor PM4 may be a PMOS transistor. The fifteenth MOS transistor NM11 may be an NMOS transistor. Hereinafter, the thirteenth MOS transistor PM3, the fourteenth MOS transistor PM4, and the fifteenth MOS transistor NM11 may be referred to as a third PMOS transistor PM3, a fourth PMOS transistor PM4, and an eleventh NMOS transistor NM11, respectively.

[0030] In more detail, the first resistor R1 of the first trigger circuit 221 may be disposed between the first power rail 231 and the first node N1. The gate of the first PMOS transistor PM1 may be coupled to the first node N1. The source of the first PMOS transistor PM1 may be coupled to the first power rail 231. The drain of the first PMOS transistor PM1 may be coupled to the first gate line 241. The gate of the fourth NMOS transistor NM4 may be coupled to the branch voltage V_DIV. Although Figure 2 Although not shown in FIG. 1 , the branch voltage V_DIV may be generated by a voltage branch circuit. Figure 3 The voltage branch circuit is described in more detail. The drain of the fourth NMOS transistor NM4 can be coupled to the first power rail 231. The source of the fourth NMOS transistor NM4 can be coupled to the gate of the fifth NMOS transistor NM5. The drain of the fifth NMOS transistor NM5 can be coupled to the branch voltage V_DIV. The source of the fifth NMOS transistor NM5 can be coupled to the first gate line 241. In an embodiment, the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 can be transmission transistors that transmit the voltage applied to the gate to the source output.

[0031] The gate of the sixth NMOS transistor NM6 may be coupled to the first gate line 241. The drain of the sixth NMOS transistor NM6 may be coupled to the first node N1. The source of the sixth NMOS transistor NM6 may be coupled to the drain of the seventh NMOS transistor NM7. The gate of the seventh NMOS transistor NM7 may be coupled to the second gate line 242. Therefore, the same second gate voltage VG2 applied to the gate of the second NMOS transistor NM2 may be applied to the gate of the seventh NMOS transistor NM7. The source of the seventh NMOS transistor NM7 may be coupled to the first capacitor C1. When the first capacitor C1 is a MOS capacitor, the source of the seventh NMOS transistor NM7 may be coupled to the gate of the MOS capacitor.

[0032] The second resistor R2 of the second trigger circuit 222 may be disposed between the first gate line 241 and the second node N2. The gate of the second PMOS transistor PM2 may be coupled to the second node N2. The source of the second PMOS transistor PM2 may be coupled to the first gate line 241. The drain of the second PMOS transistor PM2 may be coupled to the second gate line 242. The gate of the eighth NMOS transistor NM8 may be coupled to the voltage at the third node N3, i.e., the third node voltage VN3. The third node N3 may be a node coupled to the drain of the third PMOS transistor PM3 of the third trigger circuit 223. The drain of the eighth NMOS transistor NM8 may be coupled to the first gate line 241. The source of the eighth NMOS transistor NM8 may be coupled to the gate of the ninth NMOS transistor NM9. The drain of the ninth NMOS transistor NM9 may be coupled to the external power supply voltage VCCQ and thus may receive the external power supply voltage VCCQ. The external power supply voltage VCCQ may have an amplitude less than the power supply voltage VDD. The source of the ninth NMOS transistor NM9 may be coupled to the second gate line 242. In an embodiment, the eighth NMOS transistor NM8 and the ninth NMOS transistor NM9 may be transfer transistors that transmit a voltage applied to the gate to a source output. The gate of the tenth NMOS transistor NM10 may be coupled to the second gate line 242. The drain of the tenth NMOS transistor NM10 may be coupled to the second node N2. The source of the tenth NMOS transistor NM10 may be coupled to the second capacitor C2. When the second capacitor C2 is a MOS capacitor, the source of the tenth NMOS transistor NM10 may be coupled to the gate of the MOS capacitor.

[0033] The third resistor R3 of the third trigger circuit 223 can be arranged between the gate of the third PMOS transistor PM3 and the second power rail 232. The source of the third PMOS transistor PM3 can be coupled to the external power supply voltage VCCQ, and thus can receive the external power supply voltage VCCQ. The drain of the third PMOS transistor PM3 can be coupled to the third node N3. The fourth PMOS transistor PM4 and the eleventh NMOS transistor NM11 can constitute an inverter circuit. That is, the gate of the fourth PMOS transistor PM4 and the gate of the eleventh NMOS transistor NM11 can be commonly coupled to the third node N3. The drain of the fourth PMOS transistor PM4 and the drain of the eleventh NMOS transistor NM11 can be commonly coupled to the third gate line 243. The source of the fourth PMOS transistor PM4 can be coupled to the second gate line 242. The source of the eleventh NMOS transistor NM11 can be coupled to the second power rail 232.

[0034] In the present embodiment, the first to fourth PMOS transistors PM1-PM4 and the first to eleventh NMOS transistors NM1-NM11 constituting the power clamp circuit 200 may be transistors for low voltage. For example, each of the first to fourth PMOS transistors PM1-PM4 and the first to eleventh NMOS transistors NM1-NM11 may be manufactured to have an operating voltage of about 1.2V. Figure 1 When the described electronic device 100 is in normal operation, a high voltage, such as a power supply voltage VDD of approximately 3.3V, may be applied through the first power rail 231. In this case, although the first to fourth PMOS transistors PM1-PM4 and the first to eleventh NMOS transistors NM1-NM11 are used for an operating voltage of 1.2V, the gate-drain voltage, gate-source voltage, and drain-source voltage of each of the first to fourth PMOS transistors PM1-PM4 and the first to eleventh NMOS transistors NM1-NM11 may not exceed 110% of the 1.2V operating voltage. Here, the voltage corresponding to 110% of the 1.2V operating voltage may be defined as a reliability guarantee voltage of the transistor, which guarantees the reliability of the transistor. In other words, as long as the gate-drain voltage, gate-source voltage, and drain-source voltage of the transistor are less than the reliability guarantee voltage, the reliability of the transistor can be maintained, which will be referred to below. Figure 4 Describe in more detail.

[0035] Figure 3 The present invention is a diagram showing the Figure 2 A circuit diagram of an example of a voltage branch circuit in which a first trigger circuit included in the power clamp circuit 200 provides a branch voltage V_DIV.

[0036] Reference Figure 3, the voltage branch circuit 300 may include a plurality of (e.g., "L", where "L" is a natural number) NMOS transistors NM(1)-NM(L) coupled to and disposed between the first power rail 231 and the second power rail 232 and a fourth resistor R4. Each of the NMOS transistors NM(1)-NM(L) may have a diode connection structure in which a gate and a drain are directly connected. The diode-connected NMOS transistors NM(1)-NM(L) may all operate only in a saturation region, and thus may perform the same function as a resistor. The drain and gate of the first diode-connected NMOS transistor NM(1) may be coupled to the first power rail 231. The source of the "K-1" ("K" is a natural number less than "L") diode-connected NMOS transistor NM(K-1) may be coupled to the drain and gate of the "K"th diode-connected NMOS transistor NM(K). A source of the “L”th diode-connected NMOS transistor NM(L) may be coupled to the second power rail 232 .

[0037] The output line 301 of the voltage branch circuit 300 can be coupled to the source of the "K-1"th diode-connected NMOS transistor NM(K-1) and the drain and gate of the "K"th diode-connected NMOS transistor NM(K). The fourth resistor R4 can be set on the output line 301 of the voltage branch circuit 300. The branch voltage V_DIV can have an amplitude obtained by subtracting the voltage dropped from the first diode-connected NMOS transistor NM(1) to the "K-1"th diode-connected NMOS transistor NM(K-1) and the voltage dropped due to the fourth resistor R4 from the power supply voltage VDD applied via the first power rail 231. Therefore, the amplitude of the branch voltage V_DIV can be adjusted in a variety of ways by adjusting the position of the output line 301. In an embodiment, the branch voltage V_DIV can have an amplitude of approximately 60% of the power supply voltage VDD. Although Figure 3 Although not shown in FIG. 2 , when an ESD event occurs in which an ESD voltage is applied to the first power rail 231 , the branch voltage V_DIV may have a magnitude of about 60% of the ESD voltage VESD.

[0038] Figure 4 The present invention is shown in Figure 2 200 is a circuit diagram of an example of normal operation of the power clamp circuit. In the example, when an electronic device ( Figure 1100 in FIG. 100) when operating normally, a voltage of 3.3 V is an applied power supply voltage VDD, and a voltage of 1.2 V is an applied external power supply voltage VCCQ. In addition, the first to fourth PMOS transistors PM1-PM4 and the first to eleventh NMOS transistors NM1-NM11 constituting the power supply clamp circuit 200 correspond to transistors each having an operating voltage of 1.2 V. In addition, the voltage branch circuit ( Figure 3 The branch voltage V_DIV (300) in FIG. 3 corresponds to 60% of the power supply voltage VDD of 3.3V, ie, 2.16V.

[0039] Reference Figure 4 , when the power supply voltage VDD of 3.3V is applied to the first power rail 231, the first capacitor C1 of the first trigger circuit 221 may form an open circuit, and no current may flow through the first resistor R1 of the first trigger circuit 221. Therefore, the first node voltage VN1 at the first node N1 is 3.3V, which is the power supply voltage VDD. That is, a voltage of 3.3V may be applied to the gate of the first PMOS transistor PM1 of the first trigger circuit 221. Because the source of the first PMOS transistor PM1 is coupled to the first power rail 231, a voltage of 3.3V (which is the power supply voltage VDD) may also be applied to the source of the first PMOS transistor PM1. Therefore, the first PMOS transistor PM1 may be turned off.

[0040] From the voltage branch circuit ( Figure 3 300 in the output) as a branch voltage V_DIV of 2.16V can be applied to the gate of the fourth NMOS transistor NM4 of the first trigger circuit 221, and therefore, the fourth NMOS transistor NM4 can be turned on. Since the fourth NMOS transistor NM4 acts as a transmission transistor, the voltage obtained by subtracting the threshold voltage of the fourth NMOS transistor NM4 from the 2.16V voltage (i.e., the branch voltage V_DIV) can be applied to the source of the fourth NMOS transistor NM4, which is connected to the gate of the fifth NMOS transistor NM5. In the following, the change in the voltage amplitude caused by the threshold voltage in each MOS transistor will be ignored. As a voltage of 2.16V of the branch voltage V_DIV, it can be applied to the gate of the fifth NMOS transistor NM5, and the fifth NMOS transistor NM5 can be turned on. Because the fifth NMOS transistor NM5 is also used as a transmission transistor, the branch voltage V_DIV of 2.16V can be applied to the first gate line 241 coupled to the source of the fifth NMOS transistor NM5. The 2.16V voltage applied to the first gate line 241 (at Figure 4The first gate voltage VG1 shown in FIG. 2 may be applied to the gate of the first NMOS transistor NM1 of the ESD current discharge circuit 210, so the first NMOS transistor NM1 may be turned on. Since the 2.16V voltage from the first gate line 241 is applied to the gate of the sixth NMOS transistor NM6, the sixth NMOS transistor NM6 may also be turned on.

[0041] When the first gate voltage VG1 of 2.16V is applied to the first gate line 241, the second capacitor C2 of the second trigger circuit 222 may also form an open circuit like the first capacitor C1. Therefore, no current may flow through the second resistor R2 of the second trigger circuit 222, and a voltage of 2.16V as the first gate voltage VG1 may be applied to the second node N2, as shown in FIG. Figure 4 2 is a second node voltage VN2. That is, a voltage of 2.16V may be applied to the gate of the second PMOS transistor PM2 of the second trigger circuit 222. Since the source of the second PMOS transistor PM2 is coupled to the first gate line 241, a voltage of 2.16V as the first gate voltage VG1 may also be applied to the source of the second PMOS transistor PM2. Therefore, the second PMOS transistor PM2 may be turned off.

[0042] The voltage at the third node N3 of the third trigger circuit 223 (at Figure 4 2 (shown as the third node voltage VN3) can be applied to the gate of the eighth NMOS transistor NM8 of the second trigger circuit 222. Because the gate of the third PMOS transistor PM3 of the third trigger circuit 223 is coupled to the second power rail 232 via the third resistor R3, the ground voltage VSS (i.e., 0V) is applied through the second power rail 232, so the third PMOS transistor PM3 can remain turned on. Therefore, the third node voltage VN3 (i.e., 1.2V) can become the external power supply voltage VCCQ applied to the source of the third PMOS transistor PM3. With the third node voltage VN3 of 1.2V applied to the gate of the eighth NMOS transistor NM8 of the second trigger circuit 222, the eighth NMOS transistor NM8 can be turned on. Since the eighth NMOS transistor NM8 acts as a transmission transistor, the voltage of 1.2V as the third node voltage VN3 can be applied to the source of the eighth NMOS transistor NM8, i.e., the gate of the ninth NMOS transistor NM9, and the ninth NMOS transistor NM9 can be turned on. Since the ninth NMOS transistor NM9 also functions as a pass transistor, the third node voltage VN3 of 1.2V may be applied to the second gate line 242 coupled to the source of the ninth NMOS transistor NM9. The voltage of 1.2V applied to the second gate line 242 (at Figure 4The second gate voltage VG2 shown in FIG. 2 may be applied to the gate of the second NMOS transistor NM2 of the ESD current discharge circuit 210, and thus, the second NMOS transistor NM2 may be turned on. Since the 1.2V voltage from the second gate line 242 is also applied to the gate of the tenth NMOS transistor NM10, the tenth NMOS transistor NM10 may also be turned on. As the second gate voltage VG2 of 1.2V is applied to the gate of the seventh NMOS transistor NM7 of the first trigger circuit 221, the seventh NMOS transistor NM7 may also be turned on.

[0043] When a voltage of 0V is applied to the gate of the third PMOS transistor PM3 of the third trigger circuit 223, the third PMOS transistor PM3 may be turned on, and the third node voltage VN3 may become 1.2V, which is the external power supply voltage VCCQ. The third node voltage VN3 of 1.2V may become an input voltage of an inverter composed of the fourth PMOS transistor PM4 and the eleventh NMOS transistor NM11. As the fourth PMOS transistor PM4 is turned off and the eleventh NMOS transistor NM11 is turned on, a voltage of 0V may be applied to the third gate line 243. Therefore, a voltage of 0V may be applied to the gate of the third NMOS transistor NM3 of the ESD current discharge circuit 210 as the third gate voltage VG3, and the third NMOS transistor NM3 may be turned off. Therefore, even when the first and second NMOS transistors NM1 and NM2 of the ESD current discharge circuit 210 are turned on, in the case where the third NMOS transistor NM3 of the ESD current discharge circuit 210 is turned off, a current moving path in the ESD current discharge circuit 210 may not be formed as a result.

[0044] As reference Figure 4 As described above, when a voltage of 3.3V as a normal input / output voltage is applied to the pad 110 (not shown), all current moving paths between the first power rail 231 and the second power rail 232 can be blocked within the power clamp circuit 200. In normal operation, the 3.3V power supply voltage VDD applied to the first power rail 231 can be blocked by the buffer ( Figure 1 150) is applied to the internal circuit ( Figure 1 As a result, a voltage of less than 1.32 V as a reliability guarantee voltage is applied between the gate and the drain (gate-drain), between the gate and the source (gate-source), and between the drain and the source (drain-source). Therefore, the first to fourth PMOS transistors PM1-PM4 and the first to eleventh NMOS transistors NM1-NM11 constituting the power clamp circuit 200 can be more reliable.

[0045] For example, for the first NMOS transistor NM1 of the ESD current discharge circuit 210, voltages of 2.16 V, 3.3 V, and 2.16 V may be applied to the gate, drain, and source, respectively, and the gate-source voltage, the gate-drain voltage, and the drain-source voltage may become 0 V, 1.14 V, and 1.14 V, respectively, so that a voltage less than 1.32 V may be applied in all cases. For the second NMOS transistor NM2, voltages of 1.2 V, 2.16 V, and 1.2 V may be applied to the gate, drain, and source, respectively, and the gate-source voltage, the gate-drain voltage, and the drain-source voltage may become 0 V, 0.96 V, and 0.96 V, respectively, so that a voltage less than 1.32 V may be applied in all cases. For the third NMOS transistor NM3, voltages of 0V, 1.2V and 0V can be applied to the gate, drain and source, respectively, and the gate-source voltage, gate-drain voltage and drain-source voltage become 0V, 1.2V and 1.2V, respectively, so that a voltage less than 1.32V can be applied in all cases.

[0046] For the first PMOS transistor PM1 of the first trigger circuit 221, voltages of 3.3 V, 3.3 V, and 2.16 V may be applied to the gate, source, and drain, respectively, and the gate-source voltage, the gate-drain voltage, and the drain-source voltage may be changed to 0 V, 1.14 V, and 1.14 V, respectively, so that a voltage less than 1.32 V may be applied in all cases. For the fourth NMOS transistor NM4, voltages of 2.16 V, 3.3 V, and 2.16 V may be applied to the gate, source, and drain, respectively, and the gate-source voltage, the gate-drain voltage, and the drain-source voltage may be changed to 0 V, 1.14 V, and 1.14 V, respectively, so that a voltage less than 1.32 V may be applied in all cases. For the fifth NMOS transistor NM5, voltages of 2.16V, 2.16V, and 2.16V may be applied to the gate, drain, and source, respectively, and the gate-source voltage, the gate-drain voltage, and the gate-drain voltage may all become 0V. For the sixth NMOS transistor NM6, voltages of 2.16V, 3.3V, and 2.16V may be applied to the gate, drain, and source, respectively, and the gate-source voltage, the gate-drain voltage, and the drain-source voltage may all become 0V, 1.14V, and 1.14V, so that a voltage less than 1.32V may be applied in all cases. For the seventh NMOS transistor NM7, voltages of 1.2V, 2.16V, and 1.2V may be applied to the gate, drain, and source, respectively, and the gate-source voltage, the gate-drain voltage, and the drain-source voltage may all become 0V, 0.96V, and 0.96V, so that a voltage less than 1.32V may be applied in all cases.

[0047] For the second PMOS transistor PM2 of the second trigger circuit 222, voltages of 2.16V, 2.16V and 1.2V may be applied to the gate, source and drain, respectively, and the gate-source voltage, the gate-drain voltage and the drain-source voltage may be changed to 0V, 0.96V and 0.96V, respectively, so that a voltage less than 1.32V may be applied in all cases. For the eighth NMOS transistor NM8, voltages of 1.2V, 2.16V and 1.2V may be applied to the gate, source and drain, respectively, and the gate-source voltage, the gate-drain voltage and the drain-source voltage may be changed to 0V, 0.96V and 0.96V, respectively, so that a voltage less than 1.32V may be applied in all cases. For the ninth NMOS transistor NM9, voltages of 1.2V, 1.2V and 1.2V may be applied to the gate, source and drain, respectively, and the gate-source voltage, the gate-drain voltage and the drain-source voltage may all be changed to 0V. For the tenth NMOS transistor NM10, voltages of 1.2V, 2.16V and 1.2V can be applied to the gate, source and drain, respectively, and the gate-source voltage, gate-drain voltage and drain-source voltage can be changed to 0V, 0.96V and 0.96V, respectively, so that a voltage less than 1.32V can be applied in all cases.

[0048] For the third PMOS transistor PM3 of the third trigger circuit 223, voltages of 0 V, 1.2 V, and 1.2 V may be applied to the gate, source, and drain, respectively, and the gate-source voltage, the gate-drain voltage, and the drain-source voltage may be changed to 1.2 V, 1.2 V, and 0 V, respectively, so that a voltage less than 1.32 V may be applied in all cases. For the fourth PMOS transistor PM4, voltages of 1.2 V, 1.2 V, and 0 V may be applied to the gate, source, and drain, respectively, and the gate-source voltage, the gate-drain voltage, and the drain-source voltage may be changed to 0 V, 1.2 V, and 1.2 V, respectively, so that a voltage less than 1.32 V may be applied in all cases. For the eleventh NMOS transistor NM11, voltages of 1.2V, 0V and 0V can be applied to the gate, source and drain, respectively, and the gate-source voltage, gate-drain voltage and drain-source voltage can be changed to 1.2V, 1.2V and 0V, respectively, so that a voltage less than 1.32V can be applied in all cases.

[0049] Figure 5 The present invention is shown in Figure 2 A circuit diagram of an example of the electrostatic discharge (ESD) protection operation of the power clamp circuit. In the example, when an ESD surge voltage is applied to the pad ( Figure 1 110), an ESD event may occur in an electronic device ( Figure 1100). As mentioned above Figure 1 As described, applied to the pad ( Figure 1 The ESD voltage of 110) in the first power rail 231 is applied to the first power rail 231 through the upper ESD protection circuit 131. In addition, all terminals to which the external power supply voltage VCCQ is applied can be in a floating state. Figure 4 As in the case of FIG. 2 , the first to fourth PMOS transistors PM1 - PM4 and the first to eleventh NMOS transistors NM1 - NM11 constituting the power clamp circuit 200 are described, each having an operating voltage of 1.2V. Voltage branch circuit ( Figure 3 The output amplitude of 300) corresponds to a branch voltage V_DIV of 60% of the ESD voltage VESD.

[0050] Reference Figure 5 , when the ESD voltage VESD is applied to the pad 110, the first capacitor C1 of the first trigger circuit 221 may form a closed circuit due to the alternating characteristics of the ESD voltage VESD. A first node voltage VN1 less than the ESD voltage VESD may be applied to the first node N1 of the first trigger circuit 221. The first node voltage VN1 may be applied to the gate of the first PMOS transistor PM1 of the first trigger circuit 221. Because the source of the first PMOS transistor PM1 is coupled to the first power rail 231, the ESD voltage VESD may be applied to the source of the first PMOS transistor PM1. When the difference between the ESD voltage VESD and the first node voltage VN1 becomes greater than the threshold voltage of the first PMOS transistor PM1, the first PMOS transistor PM1 may be turned on. In this case, the first PMOS transistor PM1 may not be fully turned on, but may be slightly turned on. As the first PMOS transistor PM1 is turned on, the ESD voltage VESD may be applied to the first gate line 241.

[0051] From the voltage branch circuit ( Figure 3The branch voltage V_DIV outputted by the first trigger circuit 221 (300) may be applied to the gate of the fourth NMOS transistor NM4 of the first trigger circuit 221. As described above, the branch voltage V_DIV may have an amplitude corresponding to 60% (i.e., 0.6×VESD) of the ESD voltage VESD. When the branch voltage V_DIV is applied to the gate of the fourth NMOS transistor NM4, the fourth NMOS transistor NM4 may be turned on. Since the fourth NMOS transistor NM4 acts as a transmission transistor, the voltage obtained by subtracting the threshold voltage of the fourth NMOS transistor NM4 from the branch voltage V_DIV may be applied to the source of the fourth NMOS transistor NM4, i.e., the gate of the fifth NMOS transistor NM5. In the following, the change in the voltage amplitude due to the threshold voltage in each MOS transistor will be ignored. The branch voltage V_DIV may be applied to the gate of the fifth NMOS transistor NM5, but when the ESD voltage VESD is applied to the source of the fifth NMOS transistor NM5, the fifth NMOS transistor NM5 may be turned on. When the first PMOS transistor PM1 is turned on, the ESD voltage VESD applied to the first gate line 241 may be applied to the gate of the first NMOS transistor NM1 of the ESD current discharge circuit 210 as the first gate voltage VG1, and thus the first NMOS transistor NM1 may be turned on. In addition, the ESD voltage VESD applied to the first gate line 241 may also be applied to the gate of the sixth NMOS transistor NM6, and thus the sixth NMOS transistor NM6 may also be turned on.

[0052] When the ESD voltage VESD is applied to the first gate line 241, the second capacitor C2 of the second trigger circuit 222 may also form a closed circuit like the first capacitor C1. A second node voltage VN2 less than the ESD voltage VESD applied to the first gate line 241 may be applied to the second node N2 of the second trigger circuit 222. The second node voltage VN2 may be applied to the gate of the second PMOS transistor PM2 of the second trigger circuit 222. Since the source of the second PMOS transistor PM2 is coupled to the first gate line 241, the ESD voltage VESD may be applied to the source of the second PMOS transistor PM2. When the difference between the ESD voltage VESD and the second node voltage VN2 becomes greater than the threshold voltage of the second PMOS transistor PM2, the second PMOS transistor PM2 may be turned on. In this case, the second PMOS transistor PM2 may be in a slightly turned-on state like the first PMOS transistor PM1. As the second PMOS transistor PM2 is turned on, the ESD voltage VESD may be applied to the second gate line 242.

[0053] The voltage at the third node N3 of the third trigger circuit 223 (i.e., the third node voltage VN3) can be applied to the gate of the eighth NMOS transistor NM8 of the second trigger circuit 222. Because the gate of the third PMOS transistor PM3 of the third trigger circuit 223 is coupled to the second power rail 232 through the third resistor R3, the second power rail 232 is applied with the ground voltage VSS, i.e., 0V, so the third PMOS transistor PM3 can remain turned on. During the ESD event, the source of the third PMOS transistor PM3 to which the external power supply voltage VCCQ is provided can float, and therefore, the third node voltage VN3 can become about 0V (strictly, the threshold voltage of the PMOS transistor). With the third node voltage VN3 (0V) applied to the gate of the eighth NMOS transistor NM8 of the second trigger circuit 222, the eighth NMOS transistor NM8 can be turned off. With the eighth NMOS transistor NM8 turned off, the ninth NMOS transistor NM9 can also be turned off.

[0054] The ESD voltage VESD applied to the second gate line 242 may be applied as the second gate voltage VG2 to the gate of the second NMOS transistor NM2 of the ESD current discharge circuit 210, and thus, the second NMOS transistor NM2 may be turned on. Since the ESD voltage VESD applied to the second gate line 242 is also applied to the gate of the tenth NMOS transistor NM10, the tenth NMOS transistor NM10 may also be turned on. As the tenth NMOS transistor NM10 is turned on, the state of the second PMOS transistor PM2 may be changed from a slightly turned-on state to a fully turned-on state. The ESD voltage VESD applied to the second gate line 242 may also be applied to the gate of the seventh NMOS transistor NM7 of the first trigger circuit 221, and thus, the seventh NMOS transistor NM7 may be turned on. As the seventh NMOS transistor NM7 is turned on, the state of the first PMOS transistor PM1 may also be changed from a slightly turned-on state to a fully turned-on state.

[0055] When a 0V voltage is applied to the gate of the third PMOS transistor PM3 of the third trigger circuit 223, the third PMOS transistor PM3 may be turned on. However, because the source of the third PMOS transistor PM3 floats, the third node voltage VN3 may become about 0V. The 0V voltage as the third node voltage VN3 may be an input voltage of an inverter composed of the fourth PMOS transistor PM4 and the eleventh NMOS transistor NM11. As the fourth PMOS transistor PM4 is turned on and the eleventh NMOS transistor NM11 is turned off, the ESD voltage VESD may be applied to the third gate line 243. Therefore, the ESD voltage VESD may be applied to the gate of the third NMOS transistor NM3 of the ESD current discharge circuit 210 as the third gate voltage VG3, and the third NMOS transistor NM3 may be turned on. When the first NMOS transistor NM1, the second NMOS transistor NM2, and the third NMOS transistor NM3 of the ESD current discharge circuit 210 are all turned on, the ESD current can be discharged from the first power rail 231 to the second power rail 232 through the first NMOS transistor NM1, the second NMOS transistor NM2, and the third NMOS transistor NM3. The turned-on state of the first NMOS transistor NM1, the second NMOS transistor NM2, and the third NMOS transistor NM3 of the ESD current discharge circuit 210 can maintain a time interval corresponding to the first RC delay time of the first resistor R1 and the first capacitor C1 from the first trigger circuit 221 (the same as the second RC delay time of the second resistor R2 and the second capacitor C2 from the second trigger circuit 222).

[0056] For illustrative purposes, a limited number of possible embodiments of this teaching have been given above. It will be appreciated by those skilled in the art that multiple modifications, additions, and substitutions are possible. Although this patent document contains many details, these details should not be interpreted as limitations on the scope of this teaching or the scope that may be claimed, but rather as descriptions of features that may be specific to a particular embodiment. Certain features described in the context of a separate embodiment in this patent document may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. In addition, although the features may be described as working in certain combinations, even initially claimed as such, in some cases, one or more features in the claimed combination may be deleted from the combination, and the claimed combination may be directed to a variant of a sub-combination or a sub-combination.

Claims

1. A power clamp circuit, comprising: An ESD current discharge circuit includes a first MOS transistor, a second MOS transistor and a third MOS transistor coupled in series between a first power rail and a second power rail, wherein the first power rail is coupled to a power supply voltage, the second power rail is coupled to a ground voltage, and ESD refers to electrostatic discharge; A first trigger circuit includes a first resistor, a first capacitor and a fourth MOS transistor, and triggers the first MOS transistor; A second trigger circuit includes a second resistor, a second capacitor and a fifth MOS transistor, and triggers the second MOS transistor; as well as A third trigger circuit turns off the third MOS transistor during normal operation and turns on the third MOS transistor when an ESD event occurs.

2. The power clamp circuit according to claim 1, in, The first MOS transistor, the second MOS transistor and the third MOS transistor are respectively a first NMOS transistor, a second NMOS transistor and a third NMOS transistor, where NMOS refers to an N-channel MOS. wherein a gate of the first NMOS transistor is coupled to a first gate line, a drain of the first NMOS transistor is coupled to the first power rail, and a source of the first NMOS transistor is coupled to a drain of the second NMOS transistor, wherein the gate of the second NMOS transistor is coupled to the second gate line, and the source of the second NMOS transistor is coupled to the drain of the third NMOS transistor, and The gate of the third NMOS transistor is coupled to a third gate line, and the source of the third NMOS transistor is coupled to the second power rail.

3. The power clamp circuit according to claim 2, wherein: The first trigger circuit: providing a branch voltage generated by dividing the power supply voltage to the first gate line, and When the ESD event occurs, an ESD voltage is provided to the first gate line.

4. The power clamp circuit according to claim 2, in, The first resistor is provided between the first power rail and a first node, the first capacitor is provided between the first node and the second power rail, and the fourth MOS transistor is a first PMOS transistor, where PMOS refers to a P-channel type MOS, and The gate of the first PMOS transistor is coupled to the first node, the source of the first PMOS transistor is coupled to the first power rail, and the drain of the first PMOS transistor is coupled to the first gate line.

5. The power clamp circuit according to claim 4, in, The first trigger circuit further includes a sixth MOS transistor and a seventh MOS transistor arranged between the first power rail and the first gate line, the sixth MOS transistor and the seventh MOS transistor are respectively a fourth NMOS transistor and a fifth NMOS transistor, wherein a gate of the fourth NMOS transistor is coupled to a branch voltage generated by decomposing the power supply voltage, a drain of the fourth NMOS transistor is coupled to the first power rail, and a source of the fourth NMOS transistor is coupled to a gate of the fifth NMOS transistor, and The drain of the fifth NMOS transistor is coupled to the branch voltage, and the source of the fifth NMOS transistor is coupled to the first gate line.

6. The power clamp circuit according to claim 5, further comprising a voltage branch circuit, wherein the voltage branch circuit provides the branch voltage. in, The voltage branch circuit includes a plurality of diode-connected MOS transistors coupled in series between the first power rail and the second power rail.

7. The power clamp circuit according to claim 6, wherein: The voltage branch circuit provides a branch voltage of at least 60% of a voltage applied to the first power rail.

8. The power clamp circuit according to claim 4, in, The first trigger circuit further includes an eighth MOS transistor and a ninth MOS transistor arranged between the first node and the first capacitor, the eighth MOS transistor and the ninth MOS transistor being a sixth NMOS transistor and a seventh NMOS transistor, respectively. wherein the gate of the sixth NMOS transistor is coupled to the first gate line, the drain of the sixth NMOS transistor is coupled to the first node, the source of the sixth NMOS transistor is coupled to the drain of the seventh NMOS transistor, and The gate of the seventh NMOS transistor is coupled to the second gate line, and the source of the seventh NMOS transistor is coupled to the first capacitor.

9. The power clamp circuit according to claim 2, wherein: The second trigger circuit: providing an external power supply voltage lower than the power supply voltage to the second gate line, and When the ESD event occurs, the ESD voltage is provided to the second gate line.

10. The power clamp circuit according to claim 2, in, The second resistor is provided between the first gate line and the second node, the second capacitor is provided between the second node and the second power rail, the fifth MOS transistor is a second PMOS transistor, PMOS refers to a P-channel type MOS, and The gate of the second PMOS transistor is coupled to the second node, the source of the second PMOS transistor is coupled to the first gate line, and the drain of the second PMOS transistor is coupled to the second gate line.

11. The power clamp circuit according to claim 10, in, The second trigger circuit further includes a tenth MOS transistor and an eleventh MOS transistor disposed between the first gate line and the second gate line, the tenth MOS transistor and the eleventh MOS transistor are an eighth NMOS transistor and a ninth NMOS transistor, respectively. wherein the gate of the eighth NMOS transistor is coupled to the third node voltage, the drain of the eighth NMOS transistor is coupled to the first gate line, the source of the eighth NMOS transistor is coupled to the gate of the ninth NMOS transistor, and The drain of the ninth NMOS transistor is coupled to an external power supply voltage which is lower than the power supply voltage, and the source of the ninth NMOS transistor is coupled to the second gate line.

12. The power clamp circuit according to claim 11, in, The second trigger circuit further includes a twelfth MOS transistor disposed between the second node and the second capacitor, the twelfth MOS transistor being a tenth NMOS transistor, and The gate of the tenth NMOS transistor is coupled to the second gate line, the drain of the tenth NMOS transistor is coupled to the second node, and the source of the tenth NMOS transistor is coupled to the second capacitor.

13. The power clamp circuit according to claim 2, wherein: The third trigger circuit: providing the ground voltage to the third gate line, and When the ESD event occurs, the ESD voltage is provided to the third gate line.

14. The power clamp circuit according to claim 2, in, The third trigger circuit includes a third resistor, a thirteenth MOS transistor, a fourteenth MOS transistor and a fifteenth MOS transistor, wherein the thirteenth MOS transistor, the fourteenth MOS transistor and the fifteenth MOS transistor are respectively a third PMOS transistor, a fourth PMOS transistor and an eleventh NMOS transistor, wherein PMOS refers to a P-channel MOS. wherein the third resistor is coupled to the second power rail and the gate of the third PMOS transistor, the drain of the third PMOS transistor is coupled to an external power voltage less than the power voltage, and the source of the third PMOS transistor is coupled to a third node, wherein the gate of the fourth PMOS transistor and the gate of the eleventh NMOS transistor are commonly coupled to the third node, the source of the fourth PMOS transistor is coupled to the second gate line, the drain of the fourth PMOS transistor and the drain of the eleventh NMOS transistor are commonly coupled to the third gate line, and Wherein, a source of the eleventh NMOS transistor is coupled to the second power rail.

15. The power clamp circuit according to claim 1, wherein: A product of the resistance of the first resistor and the capacitance of the first capacitor is equal to a product of the resistance of the second resistor and the capacitance of the second capacitor.

16. An electronic device comprising: Solder pads; an internal circuit coupled to the pad, a first power rail through which a power supply voltage is provided, and a second power rail through which a ground voltage is provided; as well as A power clamp circuit that protects the internal circuit when an ESD event occurs. ESD refers to electrostatic discharge. Wherein, the power clamp circuit comprises: An ESD current discharge circuit comprising a first MOS transistor, a second MOS transistor and a third MOS transistor coupled in series between the first power rail and the second power rail; A first trigger circuit includes a first resistor, a first capacitor and a fourth MOS transistor, and triggers the first MOS transistor; a second trigger circuit, comprising a second resistor, a second capacitor, and a fifth MOS transistor, and triggering the second MOS transistor; and A third trigger circuit is configured to turn off the third MOS transistor during normal operation and turn on the third MOS transistor when the ESD event occurs.

17. The electronic device according to claim 16, in, The first MOS transistor, the second MOS transistor and the third MOS transistor are respectively a first NMOS transistor, a second NMOS transistor and a third NMOS transistor, where NMOS refers to an N-channel MOS. wherein a gate of the first NMOS transistor is coupled to a first gate line, a drain of the first NMOS transistor is coupled to the first power rail, and a source of the first NMOS transistor is coupled to a drain of the second NMOS transistor, wherein the gate of the second NMOS transistor is coupled to the second gate line, and the source of the second NMOS transistor is coupled to the drain of the third NMOS transistor, and The gate of the third NMOS transistor is coupled to a third gate line, and the source of the third NMOS transistor is coupled to the second power rail.

18. The electronic device according to claim 17, in, The first trigger circuit further includes a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor and a ninth MOS transistor, The fourth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor and the ninth MOS transistor are respectively a first PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and a seventh NMOS transistor, and PMOS refers to a P-channel MOS. wherein the first resistor is coupled to the first power rail and a first node, The gate, source and drain of the first PMOS transistor are respectively coupled to the first node, the first power rail and the first gate line, wherein the gate, drain and source of the fourth NMOS transistor are respectively coupled to a branch voltage generated by decomposing the power supply voltage, the first power rail and the gate of the fifth NMOS transistor, The drain and source of the fifth NMOS transistor are respectively coupled to the branch voltage and the first gate line, The gate, drain and source of the sixth NMOS transistor are respectively coupled to the first gate line, the first node and the drain of the seventh NMOS transistor, and The gate and the source of the seventh NMOS transistor are respectively coupled to the second node voltage at the second node and the first capacitor.

19. The electronic device according to claim 18, in, The second trigger circuit further includes a tenth MOS transistor, an eleventh MOS transistor and a twelfth MOS transistor, The fifth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor and the twelfth MOS transistor are respectively a second PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor and a tenth NMOS transistor, wherein the second resistor is coupled to the first gate line and a second node, The gate, source and drain of the second PMOS transistor are respectively coupled to the second node, the first gate line and the second gate line. The gate, drain and source of the eighth NMOS transistor are respectively coupled to the third node voltage at the third node, the first gate line and the gate of the ninth NMOS transistor. wherein the drain and source of the ninth NMOS transistor are respectively coupled to an external power supply voltage less than the power supply voltage and the second gate line, and The gate, drain and source of the tenth NMOS transistor are respectively coupled to the second gate line, the second node and the second capacitor.

20. The electronic device according to claim 19, in, The third trigger circuit includes a third resistor, a thirteenth MOS transistor, a fourteenth MOS transistor and a fifteenth MOS transistor, The thirteenth MOS transistor, the fourteenth MOS transistor and the fifteenth MOS transistor are respectively a third PMOS transistor, a fourth PMOS transistor and an eleventh NMOS transistor, wherein the third resistor is coupled to the second power rail and the gate of the third PMOS transistor, wherein the drain of the third PMOS transistor is coupled to an external power supply voltage that is less than the power supply voltage, and the source of the third PMOS transistor is coupled to the third node, wherein the gate of the fourth PMOS transistor and the gate of the eleventh NMOS transistor are commonly coupled to the third node, the source of the fourth PMOS transistor is coupled to the second gate line, and the drain of the fourth PMOS transistor and the drain of the eleventh NMOS transistor are commonly coupled to the third gate line, and Wherein, a source of the eleventh NMOS transistor is coupled to the second power rail.

Images