USB PD protocol high-accuracy decoding method

Abstract

The invention discloses a USB PD protocol high-accuracy chip decoding communication method, and belongs to the technical field of chip decoding communication. The problem of decoding failure caused by overlarge duty ratio distortion in the prior art is solved, by detecting the flipping interval time of the BMC signal, when the detected BMC signal is flipped, the count value of the counter is stored to cnt1, meanwhile, the value of the original cnt1 is stored to cnt2, and the decoding efficiency is improved. Therefore, whether the current BMC signal is 0 or 1 is judged according to the value of the current counter and the stored counting value characteristics of the value of the last counter, so that decoding can still be successful through the characteristics of two adjacent periods when the duty ratio deformation is relatively large.

Description

Technical Field

[0001] The present invention relates to the technical field of chip decoding communication, in particular to a high-accuracy decoding method for a USB PD protocol. Background Art

[0002] As the battery capacity of electronic devices becomes larger and larger, the USB PD protocol comes out to solve the communication problem between the charger and the charged device, and is compatible with both "high voltage and low current" and "low voltage and high current" modes.

[0003] USB PD communication uses BMC encoding. One of the difficulties in communication is to restore the clock and data information from the BMC signal. Since communication occurs in the power transmission stage, interference is relatively serious at this time, and the waveform is easily distorted, causing communication failure and interrupting the ongoing charging.

[0004] The BMC encoding rule is that after each bit of data is sent, the level signal is inverted. If it is a 1 sent, it is flipped again in the middle of 1UI. This encoding method can ensure that the number of 0s and 1s on the CC line is basically the same, making it easier to recover the clock information.

[0005] However, in the actual decoding process, due to the uneven quality of the charging device and the charged device, as well as the impedance of the charging cable, the ideal BMC encoding signal will be severely distorted, causing the waveform period and duty cycle to deviate seriously from the requirements of the PD specification, resulting in decoding failure; therefore, it does not meet the existing needs. In this regard, we propose a high-accuracy decoding method for the USB PD protocol. Summary of the invention

[0006] The purpose of the present invention is to provide a high-accuracy decoding method for the USB PD protocol, which detects the flip signal of the BMC signal and saves the counter count value to cnt1, and saves the original cnt1 value to cnt2, so as to judge whether the current BMC signal is 0 or 1 according to the count value characteristics of the current counter value and the previous counter value saved, so that when the duty cycle is greatly deformed, decoding can still be successful through the characteristics of two adjacent cycles, thereby solving the problems raised in the above-mentioned background technology.

[0007] To achieve the above object, the present invention provides the following technical solution: a USB PD protocol high-accuracy decoding method, comprising the following steps: Detect the flip interval of the BMC signal. When the detected BMC signal flips, save the counter value to cnt1 and save the original cnt1 value to cnt2. The currently saved cnt1 value is judged and processed. If the interval between two BMC signal flips is within 53±10%, the BMC signal does not flip within 1UI time, and the corresponding decoding is 0; Add the values ​​of cnt1 and cnt2. If the sum of cnt1 and cnt2 is within 53±10%, the BMC signal flips within 1UI time, the corresponding decoding is 1, and cnt2 is cleared. Add the values ​​of cnt1 and cnt2. If the sum of cnt1 and cnt2 is greater than 70, it means that half a UI cycle is currently received and the previous complete code is in the 0 state. Do not decode at this time and continue to wait for the next half cycle.

[0008] Furthermore, when decoding starts, the counter is cleared, and when the BMC signal is turned on and starts to receive data, the counter starts counting.

[0009] Further, detecting the flip interval time of the BMC signal includes the following steps: When the BMC signal flips for the first time, the internal counter is started; When the counter is flipped for the second time, the counter value is saved as cnt1, and the counter is cleared and counted again; At the third rollover, the previously saved cnt1 is saved as cnt2, and the new counter value is saved as cnt1. At the same time, the counter is cleared and counted again; The value of cnt1 is judged to see whether it is within 53±10%.

[0010] Furthermore, the value of cnt1 is judged and processed, including: If the value of cnt1 is between 53±10%, the interval between two BMC signal flips is 1UI, that is, the decoded data is 0; If the value of cnt1 is not within 53±10%, the values ​​of cnt1 and cnt2 are added and the calculation result is divided into: If the sum of cnt1 and cnt2 is between 53±10%, the decoded data is 1; If the sum of cnt1 and cnt2 is not between 53±10%, then three consecutive flips are the previous 1UI plus half UI, and data reception is not completed yet, so no decoding is performed.

[0011] Furthermore, the flip interval of the BMC signal is detected, and when a flip is detected, it is determined whether the current BMC signal is 0 or 1 according to the count value characteristics of the current counter value and the last saved counter value.

[0012] Furthermore, detecting the flip interval time of the BMC signal includes: Filter the original BMC signal; Perform beat synchronization on BMC signal; Detect the rising and falling edges of the BMC signal.

[0013] Furthermore, the original BMC signal is filtered using a low-pass filter and a high-pass filter. The low-pass filter is used to remove high-frequency noise and interference in the original BMC signal, and the high-pass filter is used to increase the frequency response range of the original BMC signal.

[0014] Furthermore, at the rising edge or falling edge of the BMC signal, the counter is cleared to restart counting, and a count value backup is saved at the same time.

[0015] Furthermore, according to the BMC signal flipping interval, if the time represented by the current count value satisfies 330us and is within ±20%, the BMC signal of the current cycle is decoded as 0; According to the two count values ​​generated by three consecutive BMC signal flips, if the sum of the two count values ​​and the time represented meets 330us and is within the range of ±20%, the BMC signal of the current cycle is decoded as 1.

[0016] Furthermore, the time represented by the count value is obtained by multiplying the count value by the clock period according to the frequency of the count clock, and finally obtaining the time interval of the BMC signal flipping, wherein the count clock frequency is 16 MHz.

[0017] Compared with the prior art, the present invention has the following beneficial effects: When the present invention detects that the BMC signal is flipped, it is necessary to save the counter count value to cnt1 and save the original cnt1 value to cnt2 for subsequent calculation of the number of flips. The currently saved cnt1 value is judged to determine whether the interval between two BMC flips is within 53±10%. If it is within the range, it means that the signal has not flipped within 1UI time, and the corresponding decoding should be 0. The values ​​of cnt1 and cnt2 are added. If the sum of the two numbers is within 53±10%, it means that the signal has flipped within 1UI time, and the corresponding decoding should be 1. At the same time, cnt2 is cleared, and the values ​​of cnt1 and cnt2 are added. If the sum of the two numbers is greater than 70, it means that half a UI is received and the previous complete code is in the 0 state. At this time, no decoding is performed, and the next half cycle is continued to wait. Based on the above decoding steps, according to the count value characteristics of the current counter value and the saved previous counter value, it is determined whether the current BMC signal is 0 or 1, so that when the duty cycle is greatly deformed, the characteristics of the two adjacent cycles can still be used for decoding. Successful. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a BMC signal decoding sampling data diagram of the present invention; Figure 2 The present invention is a flowchart of a USB PD protocol high-accuracy decoding method. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] In order to solve the technical problem that the quality of existing charging devices and charged devices is uneven, and the impedance of the charging cable will cause the ideal BMC encoding signal to be seriously distorted, causing the waveform period and duty cycle to seriously deviate from the requirements of the PD specification, resulting in decoding failure, please refer to Figure 1-Figure 2 , this embodiment provides the following technical solutions: A high-accuracy decoding method for USB PD protocol, comprising the following steps: Detect the flip interval of the BMC signal. When the detected BMC signal flips, save the counter value to cnt1 and save the original cnt1 value to cnt2. The currently saved cnt1 value is judged and processed. If the interval between two BMC signal flips is within 53±10% (i.e., between 48 and 58), the BMC signal does not flip within 1UI time, and the corresponding decoding is 0; Add the values ​​of cnt1 and cnt2. If the sum of cnt1 and cnt2 is within 53±10% (i.e., between 48 and 58), the BMC signal flips within 1UI time, the corresponding decoding is 1, and cnt2 is cleared. Add the values ​​of cnt1 and cnt2. If the sum of cnt1 and cnt2 is greater than 7 0, it means that half a UI cycle is currently received and the previous complete code is in the 0 state. Do not decode at this time and continue to wait for the next half cycle.

[0021] The technical effect of the above content is: accurate decoding by detecting the flip signal of the BMC signal. First, when the BMC signal is detected to be flipped, the value of the counter cnt1 is saved to cnt2 to ensure the continuity of the signal. Then, the value of cnt1 is processed. If the interval between two BMC signal flips is within the range of 53±10%, it is considered that the BMC signal has not flipped within 1UI time, and the corresponding decoding should be 0 (such as Figure 1 Then, add the values ​​of cnt1 and cnt2. If they are within the range of 53±10%, it means that the BMC signal has flipped within 1UI time, and the corresponding decoding should be 1 (such as Figure 1 T3 in the figure), and clear cnt2 after receiving the complete 1UI data. Finally, if the sum of cnt1 and cnt2 exceeds 70, but the previous complete code is 0 (such as Figure 1 ), which means that half a UI cycle is received, but no decoding is performed, and the next half cycle is continued to be waited.

[0022] In this embodiment, the coding information is obtained by detecting the BMC signal transition edge, counting between the transition edges, and processing the two count values ​​of adjacent edges. This method supports receiving a frequency offset of ±20%, and also supports BMC coding duty cycle distortion of 30% to 70%, and can also be correctly decoded. Therefore, when the duty cycle deformation is large, decoding can still be successful through the characteristics of two adjacent cycles.

[0023] When decoding starts, the counter is cleared and waits for the BMC signal to flip and start receiving data, at which time the counter starts counting.

[0024] The technical effect of the above content is: when starting decoding, the counter should be cleared and start counting only after waiting for the BMC signal to flip. Only when the BMC signal flips, the counter will start counting and judge the state of the current BMC cycle according to the number of flips, and then decode the data, thereby ensuring the accuracy of decoding and avoiding errors caused by misjudgment.

[0025] Detecting the flip interval of the BMC signal includes the following steps: When the BMC signal flips for the first time, the internal counter is started; When the counter is flipped for the second time, the counter value is saved as cnt1, and the counter is cleared and counted again; At the third rollover, the previously saved cnt1 is saved as cnt2, and the new counter value is saved as cnt1. At the same time, the counter is cleared and counted again; The value of cnt1 is judged to see whether it is within 53±10%.

[0026] The technical effects of the above content are as follows: first, when the BMC signal flips for the first time, the internal counter is started to ensure that the flip of the BMC signal is detected in time and the counter value is updated in time. Secondly, when the BMC signal flips for the second time, the counter value is saved as cnt1 and the counter is cleared to distinguish the previous counting result from the current counting result to avoid confusion, which is also to ensure the consistency of subsequent counting. Then, when the BMC signal flips for the third time, the previously saved cnt1 is saved as cnt2, and the new counter value is saved as cnt1 again, and the counter is cleared and counted again, which is also to ensure the consistency of subsequent counting. Finally, the value of cnt1 is judged to determine whether it meets the condition within 53±10%. This step is the core part of the entire decoding process and determines whether a decoding operation is required. If the condition is met, the corresponding decoding operation is performed. Otherwise, the decoding operation is not performed and the next round of counting is directly entered. Through multiple flips and the use of counters, high-precision recognition and decoding of BMC signals are achieved with a high accuracy rate, thereby improving the decoding accuracy and stability of the USB PD protocol.

[0027] The value of cnt1 is judged and processed, including: If the value of cnt1 is between 53±10%, the interval between two BMC signal flips is 1UI, that is, the decoded data is 0; If the value of cnt1 is not within 53±10%, the values ​​of cnt1 and cnt2 are added and the calculation result is divided into: If the sum of cnt1 and cnt2 is between 53±10%, the decoded data is 1; If the sum of cnt1 and cnt2 is not between 53±10%, then three consecutive flips are the previous 1UI plus half UI, and data reception is not completed yet, so no decoding is performed.

[0028] The technical effect of the above content is: the value of cnt1 is judged and processed, and corresponding decoding operations can be taken according to different judgment results. If the value of cnt1 is within the range of 53±10%, it means that the flip interval between two BMC signals is 1UI, so the decoded data is 0. If the value of cnt1 is not within the range of 53±10%, then we need to add cnt1 and cnt2 to obtain a more accurate flip number, which is divided into the following cases: If the sum of cnt1 and cnt2 is within the range of 53±10%, the decoded data is 1; If the sum of cnt1 and cnt2 is not within the range of 53±10%, it means that there are three consecutive rollovers, and data reception has not been completed after the previous 1UI plus half UI. Therefore, it can be considered that data reception is still in progress and does not need to be decoded immediately, but continues to wait for the next half cycle; Through the above method, the information provided by cnt1 and cnt2 can be fully utilized, and the two count values ​​of adjacent edges can be processed to obtain the encoded information. When the duty cycle is greatly deformed, decoding can still be successful through the characteristics of the two adjacent cycles, thereby improving the accuracy and stability of decoding.

[0029] The flip interval of the BMC signal is detected. When a flip is detected, it is determined whether the current BMC signal is 0 or 1 according to the count value characteristics of the current counter value and the last saved counter value.

[0030] The technical effect of the above content is: when two consecutive flip signals are detected, proceed to the next step, and judge the value of the counter. If it is found that the interval between the two flips is within 53±10%, it is considered that it does not exceed a complete clock cycle, so the decoded data is 0. Otherwise, the value of the counter is added, and it is judged whether three consecutive flips have occurred based on the calculation result. If so, it is necessary to temporarily stop decoding and continue to wait for the next complete clock cycle. Regardless of whether three consecutive flips have occurred, it is necessary to add the values ​​of cnt1 and cnt2 to obtain the final decoding result. When the flip of the BMC signal is detected, the current BMC signal is judged to be 0 or 1 by comparing the value of the current counter with the value of the counter saved last time, so as to perform the corresponding decoding operation.

[0031] Detect the flip interval of the BMC signal, including: Filter the original BMC signal; Perform beat synchronization on BMC signal; Detect the rising and falling edges of the BMC signal.

[0032] The technical effect of the above content is: after detecting the flip signal of the BMC signal, the original BMC signal is filtered to eliminate the influence of noise, which can make the decoding process more accurate. During the decoding process, it is necessary to ensure that all BMC signals are correctly detected. To this end, the BMC signal is processed by the beat synchronization method to ensure that all BMC signals are processed synchronously, which helps to improve the precision and accuracy of the BMC signal. Detection is performed at the rising and falling edges of each BMC signal to ensure that our decoding process is accurate. Through the above operations, the flip of the BMC signal can be detected more accurately, thereby improving the decoding accuracy.

[0033] The original BMC signal is filtered using a low-pass filter and a high-pass filter. The low-pass filter is used to remove high-frequency noise and interference in the original BMC signal, and the high-pass filter is used to increase the frequency response range of the original BMC signal.

[0034] The technical effect of the above content is: for the filtering processing of the original BMC signal, two types of filters, a low-pass filter and a high-voltage filter, are used to process the original BMC signal respectively, so as to achieve the purpose of eliminating high-frequency noise and interference and improving the frequency response range of the original BMC signal. The function of the low-pass filter is to remove the high-frequency noise and interference in the original BMC signal, and the function of the high-pass filter is to improve the frequency response range of the original BMC signal. In actual operation, the original BMC signal is first filtered using a low-pass filter to remove the high-frequency noise and interference therein, and then a high-pass filter is used to further improve the frequency response range of the original BMC signal. Through the above filtering processing, a cleaner original BMC signal with a wider frequency response range can be obtained, which is beneficial to subsequent decoding work.

[0035] At the rising or falling edge of the BMC signal, the counter is cleared to zero, restarts counting, and saves a count value backup at the same time.

[0036] The technical effect of the above content is: in the BMC signal, the rising edge and the falling edge are very important characteristic points. When the BMC signal rises or falls, the counter will be cleared and the counting will start again, so as to ensure the accuracy of the counting. If the counter is not in the correct position, it may cause counting errors, which will affect the final decoding result. In addition, it is also very necessary to save a count value backup at the same time. During the counting process, the counter may be affected by some external factors, such as electromagnetic interference, unstable power supply voltage, etc. These factors may cause the value of the counter to change. If there is no backup, it may affect the subsequent decoding work. The backup count value can help find the correct count value when the counter changes, thereby ensuring the accuracy of the decoding.

[0037] According to the BMC signal flip interval, if the time represented by the current count value meets 330us and is within ±20%, the BMC signal decoding of the current cycle is 0; According to the two count values ​​generated by three consecutive BMC signal flips, if the sum of the two count values ​​and the time represented meets 330us and is within the range of ±20%, the BMC signal of the current cycle is decoded as 1.

[0038] The technical effect of the above content is: according to the BMC signal flip interval, if the time represented by the current count value meets 330us and is within ±20%, the BMC signal of the current cycle is decoded as 0; if three consecutive BMC signal flips are received, check whether the two count values ​​generated by the three flips are within the specified range; if they are within the range, the BMC signal of the current cycle is decoded as 1. The characteristics of the BMC signal are utilized, and a higher decoding accuracy is achieved by accumulating the counter value and setting the decoding rules.

[0039] The time represented by the count value is obtained by multiplying the count value by the clock cycle according to the frequency of the count clock, and finally obtaining the time interval of the BMC signal flipping. It should be noted that the BMC communication frequency is 300k, and a deviation of ±10% is allowed. Ideally, the time count value of a BMC cycle is the count clock frequency / 300kHz. In this embodiment, the count value is 53, and the count clock frequency is 16MHz, but the count clock frequency is not limited to a fixed 16MHz, and other frequencies can be used, and should be regarded as the same method.

[0040] The technical effect of the above content is that the time interval represented by the count value is obtained according to the count clock frequency, rather than according to a specific physical time interval. This method has greater flexibility and accuracy. In addition, the count clock frequency is not limited to 16MHz. It can be any frequency that can obtain the corresponding count value time. As long as the count value time interval obtained by counting is consistent with the actual physical time interval, the same method can be used for decoding, so as to better understand and analyze the flipping of the BMC signal, thereby improving the accuracy of decoding.

[0041] Working principle: When the BMC signal is detected to be flipped, the counter count value needs to be saved to cnt1, and the original cnt1 value needs to be saved to cnt2 for subsequent calculation of the number of flips. The currently saved cnt1 value is judged to determine whether the interval between the two BMC flips is within 53±10%. If it is within the range, it means that the signal has not flipped within 1UI time, and the corresponding decoding should be 0. The values ​​of cnt1 and cnt2 are added. If the sum of the two numbers is within 53±10%, it means that the signal has flipped within 1UI time, and the corresponding decoding should be 1. At the same time, cnt2 is cleared, and the values ​​of cnt1 and cnt2 are added. If the sum of the two numbers is greater than 70, it means that half a UI is received, and the previous complete code is in the 0 state. At this time, no decoding is performed, and the next half cycle is continued to wait. Based on the above decoding steps, according to the current counter value and the count value characteristics of the last saved counter value, it is determined whether the current BMC signal is 0 or 1, so that when the duty cycle is greatly deformed, the characteristics of the two adjacent cycles can still be used for decoding.

[0042] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0043] While the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that many changes, modifications, substitutions and variations can be made to the embodiments without departing from the principles and spirit of the invention.

Claims

1. A high-accuracy decoding method for USB PD protocol, characterized in that: The following steps are involved: Detect the flip interval of the BMC signal. When the detected BMC signal flips, save the counter value to cnt1 and save the original cnt1 value to cnt2. The currently saved cnt1 value is judged and processed. If the interval between two BMC signal flips is within 53±10%, the BMC signal does not flip within 1UI time, and the corresponding decoding is 0; Add the values ​​of cnt1 and cnt2. If the sum of cnt1 and cnt2 is within 53±10%, the BMC signal flips within 1UI time, the corresponding decoding is 1, and cnt2 is cleared. Add the values ​​of cnt1 and cnt2. If the sum of cnt1 and cnt2 is greater than 70, it means that half a UI cycle is currently received and the previous complete code is in the 0 state. Do not decode at this time and continue to wait for the next half cycle.

2. A USB PD protocol high accuracy decoding method according to claim 1, characterized in that: When decoding starts, the counter is cleared and waits for the BMC signal to flip and start receiving data, at which time the counter starts counting.

3. A USB PD protocol high accuracy decoding method according to claim 1, characterized in that: Detecting the flip interval of the BMC signal includes the following steps: When the BMC signal flips for the first time, the internal counter is started; When the counter is flipped for the second time, the counter value is saved as cnt1, and the counter is cleared and counted again; At the third rollover, the previously saved cnt1 is saved as cnt2, and the new counter value is saved as cnt1. At the same time, the counter is cleared and counted again; The value of cnt1 is judged to see whether it is within 53±10%.

4. A USB PD protocol high accuracy decoding method according to claim 3, characterized in that: The value of cnt1 is judged and processed, including: If the value of cnt1 is between 53±10%, the interval between two BMC signal flips is 1UI, that is, the decoded data is 0; If the value of cnt1 is not within 53±10%, the values ​​of cnt1 and cnt2 are added and the calculation result is divided into: If the sum of cnt1 and cnt2 is between 53±10%, the decoded data is 1; If the sum of cnt1 and cnt2 is not between 53±10%, then three consecutive flips are the previous 1UI plus half UI, and data reception is not completed yet, so no decoding is performed.

5. A USB PD protocol high accuracy decoding method according to claim 3, characterized in that: The flip interval of the BMC signal is detected. When a flip is detected, it is determined whether the current BMC signal is 0 or 1 according to the count value characteristics of the current counter value and the last saved counter value.

6. A USB PD protocol high accuracy decoding method according to claim 1, characterized in that: Detect the flip interval of the BMC signal, including: Filter the original BMC signal; Synchronize the BMC signal with the beat; Detect the rising and falling edges of the BMC signal.

7. A USB PD protocol high accuracy decoding method according to claim 6, characterized in that: The original BMC signal is filtered using a low-pass filter and a high-pass filter. The low-pass filter is used to remove high-frequency noise and interference in the original BMC signal, and the high-pass filter is used to increase the frequency response range of the original BMC signal.

8. A USB PD protocol high accuracy decoding method according to claim 6, characterized in that: At the rising or falling edge of the BMC signal, the counter is cleared to zero, restarts counting, and saves a count value backup at the same time.

9. A USB PD protocol high accuracy decoding method according to claim 3, characterized in that: According to the BMC signal flip interval, if the time represented by the current count value meets 330us and is within ±20%, the BMC signal decoding of the current cycle is 0; According to the two count values ​​generated by three consecutive BMC signal flips, if the sum of the two count values ​​and the time represented meets 330us and is within the range of ±20%, the BMC signal of the current cycle is decoded as 1.

10. A USB PD protocol high accuracy decoding method according to claim 9, characterized in that: The time represented by the count value is obtained by multiplying the count value by the clock cycle according to the frequency of the count clock, and finally obtaining the time interval of the BMC signal flipping, wherein 16 MHz is the count clock frequency.

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