Circuit determination method and device, nonvolatile storage medium and electronic equipment

Abstract

The invention discloses a circuit determination method and device, a nonvolatile storage medium and electronic equipment. The circuit determination method comprises the following steps: acquiring respective gate-source voltage of a plurality of chips; an initial circuit model is established, and the initial circuit model comprises a plurality of branches connected in parallel; determining a reference branch in the plurality of branches connected in parallel; determining a reference chip matched with the reference branch in the plurality of chips; respectively determining gate-source voltage differences between the reference branch and the plurality of other branches to obtain a plurality of gate-source voltage differences in one-to-one correspondence with the plurality of other branches; and according to the plurality of gate-source electrode voltage differences and the reference chip, chips are matched for the plurality of other branches to obtain a target circuit model, so that currents in the plurality of parallel branches included in the target circuit model are uniform. According to the invention, the technical problem of unbalanced current in a multi-chip parallel circuit under asymmetric layout is solved.

Description

Technical Field

[0001] The present invention relates to the field of parallel circuit current balancing, and in particular to a circuit determination method, device, non-volatile storage medium and electronic equipment. Background Art

[0002] With the rapid development of power electronics technology, the requirements for the switching frequency, power density and operating temperature of power converters are getting higher and higher. Power semiconductor devices are the core of power converters and the main factor driving the upgrade of power converters. As a new generation of semiconductor devices, silicon carbide (SiC) metal oxide semiconductor transistors (MOSFETs) have the advantages of high switching frequency, low power consumption and high temperature resistance. It is an ideal device to replace silicon (Si) insulated gate bipolar transistors (IGBTs). In order to improve the wafer yield, the active area of ​​SiC chips is designed to be smaller, resulting in a lower current for a single chip, which cannot meet the needs of high current applications. In order to increase the rated current of the chip, multiple chips or multiple discrete devices in parallel are usually used in power modules. However, the current imbalance between parallel units (chips or devices) will lead to uneven power loss and junction temperature, thereby reducing the reliability and life of the entire system.

[0003] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0004] Embodiments of the present invention provide a circuit determination method, device, non-volatile storage medium and electronic device to at least solve the technical problem of current imbalance in a multi-chip parallel circuit under an asymmetric layout.

[0005] According to one aspect of an embodiment of the present invention, a circuit determination method is provided, comprising: obtaining gate-source voltages of respective chips; establishing an initial circuit model, wherein the initial circuit model includes multiple parallel branches; determining a reference branch among the multiple parallel branches; determining a reference chip that matches the reference branch among the multiple chips; respectively determining the gate-source voltage difference between the reference branch and multiple other branches to obtain multiple gate-source voltage differences corresponding one-to-one to the multiple other branches; matching chips for the multiple other branches according to the multiple gate-source voltage differences and the reference chip to obtain a target circuit model, so that the currents in the multiple parallel branches included in the target circuit model are uniform.

[0006] Optionally, the gate-source voltage of each of the multiple chips is obtained, including: when the drain-source voltage is a fixed value, gradually increasing the voltage between the gate and the source on the multiple chips according to a fixed step size until the drain current of each of the multiple chips is a predetermined current value, thereby obtaining the gate-source voltage of each of the multiple chips, wherein the predetermined current value is the minimum drain current value after the gate-source voltages of each of the multiple chips are fixed in order.

[0007] Optionally, determining a reference branch among multiple parallel branches includes: determining the parasitic inductance of each of the multiple parallel branches; sorting the parasitic inductances of each of the multiple parallel branches, and determining the branch with the largest parasitic inductance as the reference branch.

[0008] Optionally, determining a reference chip matching the reference branch among a plurality of chips includes: sorting the gate-source voltages of the plurality of chips; and determining a chip having the smallest gate-source voltage as the reference chip.

[0009] Optionally, the gate-source voltage difference between the reference branch and multiple other branches is determined respectively to obtain multiple gate-source voltage differences corresponding one-to-one to the multiple other branches, including: determining the equivalent circuits of the reference branch and multiple other branches respectively to obtain multiple equivalent circuits corresponding one-to-one to the multiple other branches; determining the unbalanced current between the reference branch and multiple other branches according to the multiple equivalent circuits to obtain multiple unbalanced currents corresponding one-to-one to the multiple other branches; determining the gate-source voltage difference between the reference branch and multiple other branches according to the multiple unbalanced currents to obtain multiple gate-source voltage differences.

[0010] Optionally, based on multiple gate-source voltage differences and a reference chip, chips are matched for other branches to obtain a target circuit model so that the currents in multiple parallel branches included in the target circuit model are uniform, including: summing the multiple gate-source voltage differences with the gate-source voltage of the reference chip respectively to obtain a current-sharing voltage corresponding one-to-one to multiple other branches; matching chips for multiple other branches based on the current-sharing voltages corresponding one-to-one to multiple other branches to obtain the target circuit model.

[0011] According to another aspect of an embodiment of the present invention, a circuit determination device is provided, comprising: a first acquisition module, used to acquire gate-source voltages of respective multiple chips; a first establishment module, used to establish an initial circuit model, wherein the initial circuit model includes multiple parallel branches; a first determination module, used to determine a reference branch among the multiple parallel branches; a second determination module, used to determine a reference chip matching the reference branch among the multiple chips; a third determination module, used to respectively determine the gate-source voltage difference between the reference branch and multiple other branches, and obtain multiple gate-source voltage differences corresponding to the multiple other branches one by one;

[0012] According to another aspect of an embodiment of the present invention, a non-volatile storage medium is provided. The non-volatile storage medium stores a plurality of instructions, and the instructions are suitable for being loaded by a processor and executing any one of the circuit determination methods.

[0013] According to another aspect of an embodiment of the present invention, there is provided an electronic device, comprising: one or more processors and a memory, the memory being used to store one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement any one of the circuit determination methods.

[0014] According to yet another aspect of an embodiment of the present invention, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the circuit determination method described above is implemented.

[0015] In an embodiment of the present invention, by obtaining the gate-source voltages of each of the multiple chips; establishing an initial circuit model, wherein the initial circuit model includes multiple parallel branches; determining a reference branch among the multiple parallel branches; determining a reference chip that matches the reference branch among the multiple chips; respectively determining the gate-source voltage difference between the reference branch and multiple other branches, and obtaining multiple gate-source voltage differences corresponding to the multiple other branches one by one; matching chips for the multiple other branches according to the multiple gate-source voltage differences and the reference chip, and obtaining a target circuit model, so that the currents in the multiple parallel branches included in the target circuit model are uniform, thereby solving the technical problem of current imbalance in a multi-chip parallel circuit under an asymmetric layout, achieving the purpose of current balance in a multi-chip parallel circuit under an asymmetric layout, and further realizing the technical effect of improving the current utilization rate and overall reliability of the parallel unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0017] Figure 1 is a flow chart of a circuit determination method provided according to an embodiment of the present invention;

[0018] Figure 2 is a schematic diagram of an optional gate-source voltage of a power semiconductor chip for testing provided in an embodiment of the present invention;

[0019] Figure 3 is a schematic diagram of an optional initial circuit model provided according to an embodiment of the present invention;

[0020] Figure 4 is a schematic diagram of an optional equivalent circuit of two parallel-connected power semiconductor chips provided according to an embodiment of the present invention;

[0021] Figure 5 is a schematic diagram of a circuit determination device provided according to an embodiment of the present invention;

[0022] Figure 6 is a schematic diagram of an electronic device provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0025] According to an embodiment of the present invention, a circuit determination method embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0026] Figure 1 is a flow chart of a circuit determination method according to an embodiment of the present invention. Figure 1 As shown, the method comprises the following steps:

[0027] Step S102, obtaining gate-source voltages of the respective chips.

[0028] In this step, a certain test method or equipment is used to measure and record the gate-source voltage values ​​(V gs ), that is, testing the voltage between the gate and source in the power semiconductor device (MOSFET).

[0029] In an optional embodiment, the gate-source voltage of each of the multiple chips is obtained, including: when the drain-source voltage is a fixed value, gradually increasing the voltage between the gate and the source on the multiple chips according to a fixed step size until the drain current of each of the multiple chips is a predetermined current value, and obtaining the gate-source voltage of each of the multiple chips, wherein the predetermined current value is the minimum drain current value after the gate-source voltages of each of the multiple chips are fixed in order.

[0030] Optionally, the gate-source voltage of each chip refers to the gate-source voltage of each chip corresponding to the smallest drain current when the drain current continues to increase and the order of the gate-source voltage of each chip no longer changes. The gate-source voltage of each chip at this time is the current-sharing voltage of each chip. For example, when the drain current is 5A, the gate-source voltages of the parallel chips are sorted, and when the drain current continues to increase, the order of the gate-source voltages of the parallel chips no longer changes. The smallest drain current is selected because the drain current increases from 0, and the larger the drain current, the longer the test time required, so selecting the smallest drain current can reduce the test time.

[0031] The specific test steps are as follows: record the total number of power semiconductor chip samples n, where the total number of samples n is the total number of power semiconductor chips to be applied; number the power semiconductor chip samples from 1 to n; start the power analyzer, select the gate-source voltage and drain current test module, and set the parameter values ​​of the test data points. The drain current of the data point can be 5A, and the drain-source voltage can be 10V. Figure 2 As shown, the gate-source voltage of the power semiconductor chip is tested. The test process of the gate-source voltage is that the drain-source voltage is fixed at 10V, and the gate-source voltage increases from 0V, with a step size of 0.1V, until the drain current of the power semiconductor chip is 5A, the test is stopped, and the gate-source voltage corresponding to the drain current of 5A is recorded. According to the above gate-source voltage test process, the gate-source voltage test of power semiconductor chips No. 1 to No. n is performed in sequence, and the gate-source voltage of each chip obtained by the test is the current-sharing voltage of each chip. The expression of the current-sharing voltage is:

[0032]

[0033] In the formula, i d The drain current is 5A, g fs is the transconductance corresponding to a drain current of 5A, V th is the threshold voltage of the power semiconductor chip.

[0034] Step S104, establishing an initial circuit model, wherein the initial circuit model includes a plurality of parallel branches.

[0035] In this step, before designing or analyzing the circuit, a theoretical model of the circuit must be constructed. This model will contain multiple parallel branches. The initial circuit model is usually established based on the basic physical and electrical characteristics of the circuit. It includes the main components in the circuit, such as power supply, load, and wires or paths connecting these components. The initial circuit model does not include power semiconductor chips. Figure 3 As shown, this is the initial circuit model. Figure 3 O1 is the drain junction of the parallel chips, O2 is the power source junction of the parallel chips, Q1~Q m There are m power semiconductor chips connected in parallel, i d1 ~i dm Q1~Q m The drain current, i d is the sum of the drain currents of m power semiconductor chips connected in parallel, G1~G m Q1~Q m The gate of S1~S m Q1~Q m The power source, L d is the drain parasitic inductance of the power semiconductor chip, L s1 ~L sm Q1~Q m The power source parasitic inductance.

[0036] Step S106, determining a reference branch among the multiple parallel branches.

[0037] In this step, the purpose of determining the reference branch is to solve the problem of uneven current distribution in the parallel circuit. The selection of the reference branch can be based on the characteristics of its parasitic parameters, such as selecting the branch with the largest or smallest parasitic inductance. After determining the reference branch, the gate-source voltage will be adjusted according to the difference in parasitic parameters between the reference branch and other branches to ensure that the current distribution of the chips in all parallel branches is as uniform as possible.

[0038] In an optional embodiment, determining a reference branch among multiple parallel branches includes: determining the parasitic inductance of each of the multiple parallel branches; sorting the parasitic inductances of each of the multiple parallel branches, and determining the branch with the largest parasitic inductance as the reference branch.

[0039] Optionally, the branch number is determined by the power source parasitic inductance. The branch with the largest power source parasitic inductance is numbered 1, which is the reference branch. The power source parasitic inductance is represented by L s1 Indicates that the branch with the second largest parasitic inductance of the power source is numbered 2, and the parasitic inductance of the power source is L s2 Indicates that they are numbered in turn according to the parasitic inductance of the power source. The branch with the smallest parasitic inductance of the power source is numbered m, and the parasitic inductance of the power source is numbered L.sm express.

[0040] Step S108, respectively determining the gate-source voltage difference between the reference branch and the other branches, and obtaining a plurality of gate-source voltage differences corresponding to the other branches one by one;

[0041] In this step, the current distribution of each branch in the parallel circuit and the degree of current imbalance caused by differences in parasitic parameters can be evaluated through the calculated gate-source voltage difference. Then, using these voltage differences as a basis, the chip's current sharing voltage is adjusted to compensate for the inconsistency of parasitic parameters, thereby reducing the unbalanced parallel current and improving the performance and reliability of the entire parallel circuit.

[0042] In an optional embodiment, determining a reference chip matching the reference branch among a plurality of chips includes: sorting the gate-source voltages of the plurality of chips; and determining the chip with the smallest gate-source voltage as the reference chip.

[0043] Optionally, the gate-source voltages of the n chips are sorted in descending order, wherein the power semiconductor chip with the smallest current sharing voltage is numbered x1, which is the reference chip. The power semiconductor chip with the second smallest current sharing voltage is numbered x2, and the order is continued in sequence, and finally the power semiconductor chip with the largest current sharing voltage is numbered x1. n .

[0044] Step S110, respectively determining the gate-source voltage difference between the reference branch and the other branches, and obtaining a plurality of gate-source voltage differences corresponding to the other branches one by one;

[0045] In this step, the current distribution of each branch in the parallel circuit and the degree of current imbalance caused by differences in parasitic parameters can be evaluated through the calculated gate-source voltage difference. Then, using these voltage differences as a basis, the chip's current sharing voltage is adjusted to compensate for the inconsistency of parasitic parameters, thereby reducing the unbalanced parallel current and improving the performance and reliability of the entire parallel circuit.

[0046] In an optional embodiment, the gate-source voltage difference between the reference branch and multiple other branches is determined respectively to obtain multiple gate-source voltage differences corresponding one-to-one to the multiple other branches, including: determining the equivalent circuits of the reference branch and multiple other branches respectively to obtain multiple equivalent circuits corresponding one-to-one to the multiple other branches; determining the unbalanced current between the reference branch and multiple other branches according to the multiple equivalent circuits to obtain multiple unbalanced currents corresponding one-to-one to the multiple other branches; determining the gate-source voltage difference between the reference branch and multiple other branches according to the multiple unbalanced currents to obtain multiple gate-source voltage differences.

[0047] Optionally, take any two branches with different parasitic inductance of power source as an example to analyze the parallel current distribution. The equivalent circuit of two parallel power semiconductor chips is as follows: Figure 4 As shown. DC is the DC bus voltage, C bus is the busbar capacitor, R1 is the parasitic resistance of the line between the busbar capacitor and the freewheeling diode D, D is the freewheeling diode, V D is the voltage across the freewheeling diode, L load is the load inductance, L1 is the parasitic inductance of the connection between the busbar capacitor and the freewheeling diode D. Q a , Q b For two power semiconductor chips connected in parallel, L da , L db Q a , Q b The drain parasitic inductance, L sa , L sb Q a , Q b The power source parasitic inductance, L asa , L asb Q a , Q b Kelvin source parasitic inductance, C gda , C gdb Q a , Q b The parasitic capacitance between the gate and drain, C gsa , C gsb Q a , Q b The parasitic capacitance between the gate and the power source, C dsa , C dsb Q a , Q b The parasitic capacitance between the drain and the power source, R ga , R gb Q a , Q b The gate drive resistor, R g is the driving resistor, V gs is the driving voltage.

[0048] Power semiconductor chip Q a , Q b The drain current during the turn-on process can be expressed as:

[0049] i da (t) = g fs (V gsa (t)-V th )

[0050] idb (t) = g fs (V gsb (t)-V th )

[0051] In the formula, i da (t), i db (t) are the drain currents of two parallel-connected power semiconductor chips, V gsa (t), V gsb (t) are the gate-source voltages of two parallel-connected power semiconductor chips, g fs is the transconductance of the power semiconductor chip, V th is the threshold voltage of the power semiconductor chip.

[0052] The unbalanced current of two parallel power semiconductor chips is:

[0053] Δi d (t) = g fs (V gsa (t)-V gsb (t))

[0054] Q a , Q b The gate-source voltage can be expressed as:

[0055]

[0056] In the formula, i G (t) is the total driving current of two parallel power semiconductor chips, i ga (t), i gb (t) are Q a , Q b The driving current, R g is the driving resistor, V gs is the driving voltage.

[0057] Let i g (t) = i ga (t) = i gb (t)=0.5i G (t),Q a , Q b The gate-source voltage can be expressed as:

[0058]

[0059] Among them, i ga (t), i gb (t) are respectively expressed as:

[0060]

[0061] Where V gda (t), V gdb (t) are Q a , Q b The voltage difference between the gate and drain.

[0062] V gda (t) = V gsa (t)-V dsa (t)

[0063] V gdb (t) = V gsb (t)-V dsb (t)

[0064] Where V dsa (t), V dsb (t) are Q a , Q b The voltage difference between the drain and the power source.

[0065]

[0066] Combining the above equations, we can get V gsa (t), V gsb The expression of (t) is:

[0067]

[0068] a1=g fs (2R g +R ga )C gda (L da +L sa ),b1=(2R g +R ga )(C gsa +C gda )+g fs L sa ,

[0069] a2=g fs (2R g +R gb )C gdb (L db +L sb ),b2=(2R g +R gb )(C gsb +C gdb )+g fs L sb .

[0070] Since a1< <b1,a2<<b2,V gsa(t), V gsb (t) can be simplified as:

[0071]

[0072] Q a , Q b The gate-source voltage difference can be expressed as:

[0073]

[0074] The unbalanced current of two parallel power semiconductor chips is:

[0075]

[0076] From the above formula, we can know that when Δi d =0, ΔV gs = 0. During the entire current rise process, the gate-source voltage difference of the parallel devices can be solved by integration, that is:

[0077]

[0078] Where t1 is V gs Reach V th At the moment t2 is i d The moment when steady-state current is reached.

[0079] Therefore, when the current-sharing voltage difference of the parallel power semiconductor chips is -ΔV gs When Δi d = 0 to eliminate the unbalanced parallel current. According to the above method, the gate-source voltage difference between each branch and the reference branch is calculated in turn.

[0080] Step S112, matching chips for multiple other branches according to multiple gate-source voltage differences and reference chips, to obtain a target circuit model, so that the currents in the multiple parallel branches included in the target circuit model are uniform.

[0081] In this step, after determining the reference branch and its matching reference chip, and calculating the gate-source voltage difference between the reference branch and other branches, based on this information, the chips of other branches in the parallel circuit are screened and matched to obtain the target circuit model. The current in the target circuit model can be evenly distributed in all branches, and there is no significant parallel unbalanced current phenomenon.

[0082] In an optional embodiment, based on multiple gate-source voltage differences and a reference chip, chips are matched for other branches to obtain a target circuit model so that the currents in multiple parallel branches included in the target circuit model are uniform, including: summing the multiple gate-source voltage differences with the gate-source voltage of the reference chip respectively to obtain a current-sharing voltage corresponding one-to-one to multiple other branches; matching chips for multiple other branches based on the current-sharing voltages corresponding one-to-one to multiple other branches to obtain the target circuit model.

[0083] Optionally, the gate-source voltage differences between the reference branch and branch 2, branch 3, and branch m are calculated and recorded as ΔV ct12 , ΔV ct1 , ΔV ct1m . Apply the power semiconductor chip with serial number x1 to branch 1, and record the current sharing voltage of x1 as V ct1 , the matching current sharing voltage of branch 2 is V ct1 +ΔV ct12 The power semiconductor chip, branch 3 matching current sharing voltage is V ct1 +ΔV ct13 The power semiconductor chip, the m branch matching current sharing voltage is V ct1 +ΔV ct1m power semiconductor chips.

[0084] The gate-source voltages of the respective chips are obtained through the above method; an initial circuit model is established, wherein the initial circuit model includes a plurality of parallel branches; a reference branch is determined among the plurality of parallel branches; a reference chip matching the reference branch is determined among the plurality of chips; the gate-source voltage difference between the reference branch and a plurality of other branches is determined respectively, and a plurality of gate-source voltage differences corresponding to the plurality of other branches are obtained; according to the plurality of gate-source voltage differences and the reference chip, chips are matched for the plurality of other branches to obtain a target circuit model, so that the currents in the plurality of parallel branches included in the target circuit model are uniform, thereby solving the technical problem of current imbalance in a multi-chip parallel circuit under an asymmetric layout, achieving the purpose of current balance in a multi-chip parallel circuit under an asymmetric layout, and further realizing the technical effect of improving the current utilization rate and overall reliability of the parallel unit.

[0085] Based on the above embodiments and optional embodiments, the present invention proposes an optional implementation mode:

[0086] Step S1, obtaining the gate-source voltage of each of the multiple chips, including: when the drain-source voltage is a fixed value, gradually increasing the voltage between the gate and the source on the multiple chips according to a fixed step size until the drain current of each of the multiple chips is a predetermined current value, and obtaining the gate-source voltage of each of the multiple chips, wherein the predetermined current value is the minimum drain current value after the gate-source voltages of each of the multiple chips are fixed in order.

[0087] Optionally, the gate-source voltage of each chip refers to the gate-source voltage of each chip corresponding to the smallest drain current when the drain current continues to increase and the order of the gate-source voltage of each chip no longer changes. The gate-source voltage of each chip at this time is the current-sharing voltage of each chip. For example, when the drain current is 5A, the gate-source voltages of the parallel chips are sorted, and when the drain current continues to increase, the order of the gate-source voltages of the parallel chips no longer changes. The smallest drain current is selected because the drain current increases from 0, and the larger the drain current, the longer the test time required, so selecting the smallest drain current can reduce the test time.

[0088] The specific test steps are as follows: record the total number of power semiconductor chip samples n, where the sample capacity n is the total number of power semiconductor chips to be applied; number the power semiconductor chip samples from 1 to n; start the power analyzer, select the gate-source voltage and drain current test module, and set the parameter values ​​of the test data points. The drain current of the data point can be 5A, and the drain-source voltage can be 10V. Figure 2 As shown, the gate-source voltage of the power semiconductor chip is tested. The test process of the gate-source voltage is as follows: the drain-source voltage is fixed at 10V, and the gate-source voltage increases from 0V with a step size of 0.1V until the drain current of the power semiconductor chip is 5A, then the test is stopped, and the gate-source voltage corresponding to the drain current of 5A is recorded. According to the above-mentioned gate-source voltage test process, the gate-source voltage tests of power semiconductor chips No. 1 to No. n are performed in sequence, and the gate-source voltage of each chip obtained by the test is the current-sharing voltage of each chip.

[0089] The expression of the current sharing voltage is:

[0090]

[0091] In the formula, i d The drain current is 5A, g fs is the transconductance corresponding to a drain current of 5A, V th is the threshold voltage of the power semiconductor chip.

[0092] Step S2, determining a reference chip matching the reference branch from among the multiple chips, including: sorting the gate-source voltages of the multiple chips; and determining the chip with the smallest gate-source voltage as the reference chip.

[0093] Optionally, the gate-source voltages of the n chips are sorted in descending order, wherein the power semiconductor chip with the smallest current sharing voltage is numbered x1, which is the reference chip. The power semiconductor chip with the second smallest current sharing voltage is numbered x2, and the order is continued in sequence, and finally the power semiconductor chip with the largest current sharing voltage is numbered x1. n .

[0094] Step S3, establishing an initial circuit model, wherein the initial circuit model includes a plurality of parallel branches;

[0095] In this step, before designing or analyzing the circuit, a theoretical model of the circuit must be constructed. This model will contain multiple parallel branches. The initial circuit model is usually established based on the basic physical and electrical characteristics of the circuit. It includes the main components in the circuit, such as power supply, load, and wires or paths connecting these components. The initial circuit model does not include power semiconductor chips. Figure 3 As shown, this is the initial circuit model. Figure 3 O1 is the drain junction of the parallel chips, O2 is the power source junction of the parallel chips, Q1~Q m There are m power semiconductor chips connected in parallel, i d1 ~i dm Q1~Q m The drain current, i d is the sum of the drain currents of m power semiconductor chips connected in parallel, G1~G m Q1~Q m The gate of S1~S m Q1~Q m The power source, L d is the drain parasitic inductance of the power semiconductor chip, L s1 ~L sm Q1~Q m The power source parasitic inductance.

[0096] Step S4, determining a reference branch among the multiple parallel branches, includes: determining the parasitic inductance of each of the multiple parallel branches; sorting the parasitic inductances of each of the multiple parallel branches, and determining the branch with the largest parasitic inductance as the reference branch.

[0097] Optionally, the branch number is determined by the power source parasitic inductance. The branch with the largest power source parasitic inductance is numbered 1, which is the reference branch. The power source parasitic inductance is represented by L s1 Indicates that the branch with the second largest parasitic inductance of the power source is numbered 2, and the parasitic inductance of the power source is L s2 Indicates that they are numbered in turn according to the parasitic inductance of the power source. The branch with the smallest parasitic inductance of the power source is numbered m, and the parasitic inductance of the power source is numbered L. sm express.

[0098] Step S5, respectively determining the gate-source voltage difference between the reference branch and multiple other branches, and obtaining multiple gate-source voltage differences corresponding one-to-one to the multiple other branches, including: respectively determining the equivalent circuits of the reference branch and multiple other branches, and obtaining multiple equivalent circuits corresponding one-to-one to the multiple other branches; respectively determining the unbalanced current between the reference branch and multiple other branches based on the multiple equivalent circuits, and obtaining multiple unbalanced currents corresponding one-to-one to the multiple other branches; respectively determining the gate-source voltage difference between the reference branch and multiple other branches based on the multiple unbalanced currents, and obtaining multiple gate-source voltage differences.

[0099] Optionally, take any two branches with different parasitic inductance of power source as an example to analyze the parallel current distribution. The equivalent circuit of two parallel power semiconductor chips is as follows: Figure 4 As shown. DC is the DC bus voltage, C bus is the busbar capacitor, R1 is the parasitic resistance of the line between the busbar capacitor and the freewheeling diode D, D is the freewheeling diode, V D is the voltage across the freewheeling diode, L load is the load inductance, L1 is the parasitic inductance of the connection between the busbar capacitor and the freewheeling diode D. Q a , Q b For two power semiconductor chips connected in parallel, L da , L db Q a , Q b The drain parasitic inductance, L sa , L sb Q a , Q b The power source parasitic inductance, L asa , L asb Q a , Q b Kelvin source parasitic inductance, C gda , C gdb Q a , Q b The parasitic capacitance between the gate and drain, C gsa , C gsb Q a , Q b The parasitic capacitance between the gate and the power source, C dsa , C dsb Q a , Q b The parasitic capacitance between the drain and the power source, R ga , R gb Q a , Q b The gate drive resistor, R g is the driving resistor, Vgs is the driving voltage.

[0100] Power semiconductor chip Q a , Q b The drain current during the turn-on process can be expressed as:

[0101] i da (t) = g fs (V gsa (t)-V th )

[0102] i db (t) = g fs (V gsb (t)-V th )

[0103] In the formula, i da (t), i db (t) are the drain currents of two parallel-connected power semiconductor chips, V gsa (t), V gsb (t) are the gate-source voltages of two parallel-connected power semiconductor chips, g fs is the transconductance of the power semiconductor chip, V th is the threshold voltage of the power semiconductor chip.

[0104] The unbalanced current of two parallel power semiconductor chips is:

[0105] Δi d (t) = g fs (V gsa (t)-V gsb (t))

[0106] Q a , Q b The gate-source voltage can be expressed as:

[0107]

[0108] In the formula, i G (t) is the total driving current of two parallel power semiconductor chips, i ga (t), i gb (t) are Q a , Q b The driving current, R g is the driving resistor, V gs is the driving voltage.

[0109] Let i g (t) = i ga (t) = i gb (t)=0.5i G (t),Qa , Q b The gate-source voltage can be expressed as:

[0110]

[0111] Among them, i ga (t), i gb (t) are respectively expressed as:

[0112]

[0113] Where V gda (t), V gdb (t) are Q a , Q b The voltage difference between the gate and drain.

[0114] V gda (t) = V gsa (t)-V dsa (t)

[0115] V gdb (t) = V gsb (t)-V dsb (t)

[0116] Where V dsa (t), V dsb (t) are Q a , Q b The voltage difference between the drain and the power source.

[0117]

[0118] Combining the above equations, we can get V gsa (t), V gsb The expression of (t) is:

[0119]

[0120] a1=g fs (2R g +R ga )C gda (L da +L sa ),b1=(2R g +R ga )(C gsa +C gda )+g fs L sa ,

[0121] a2=g fs (2R g +Rgb )C gdb (L db +L sb ),b2=(2R g +R gb )(C gsb +C gdb )+g fs L sb .

[0122] Since a1< <b1,a2<<b2,V gsa (t), V gsb (t) can be simplified as:

[0123]

[0124] Q a , Q b The gate-source voltage difference can be expressed as:

[0125]

[0126] The unbalanced current of two parallel power semiconductor chips is:

[0127]

[0128] From the above formula, we can know that when Δi d =0, ΔV gs = 0. During the entire current rise process, the gate-source voltage difference of the parallel devices can be solved by integration, that is:

[0129]

[0130] Where t1 is V gs Reach V th At the moment t2 is i d The moment when steady-state current is reached.

[0131] Therefore, when the current-sharing voltage difference of the parallel power semiconductor chips is -ΔV gs When Δi d = 0 to eliminate the unbalanced parallel current. According to the above method, the gate-source voltage difference between each branch and the reference branch is calculated in turn.

[0132] Step S6, matching chips for other branches according to multiple gate-source voltage differences and reference chips to obtain a target circuit model so that the currents in multiple parallel branches included in the target circuit model are uniform, including: summing up the multiple gate-source voltage differences with the gate-source voltage of the reference chip respectively to obtain a current-sharing voltage corresponding one-to-one to multiple other branches; matching chips for multiple other branches according to the current-sharing voltage corresponding one-to-one to multiple other branches to obtain the target circuit model.

[0133] Optionally, the gate-source voltage differences between the reference branch and branch 2, branch 3, and branch m are calculated and recorded as ΔV ct12 , ΔV ct13 , ΔV ct1m . Apply the power semiconductor chip with serial number x1 to branch 1, and record the current sharing voltage of x1 as V ct1 , the matching current sharing voltage of branch 2 is V ct1 +ΔV ct12 The power semiconductor chip, branch 3 matching current sharing voltage is V ct1 +ΔV ct13 The power semiconductor chip, the m branch matching current sharing voltage is V ct1 +ΔV ct1m power semiconductor chips.

[0134] The above optional implementation achieves at least the following effects: solves the technical problem of current imbalance in multi-chip parallel circuits under an asymmetric layout, achieves the purpose of current balance in multi-chip parallel circuits under an asymmetric layout, and then achieves the technical effect of improving the current utilization and overall reliability of the parallel unit.

[0135] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0136] In this embodiment, a circuit determination device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the terms "module" and "device" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0137] According to an embodiment of the present invention, a device embodiment for implementing the circuit determination method is also provided. Figure 5 A schematic diagram of a circuit determination device according to an embodiment of the present invention is shown in FIG. Figure 5As shown, the circuit determination device includes a first acquisition module 51, a first establishment module 52, a first determination module 53, a second determination module 54, a third determination module 55, and a first matching module 56. The device is described below.

[0138] A first acquisition module 51 is used to acquire the gate-source voltage of each of the multiple chips;

[0139] A first establishing module 52, connected to the first acquiring module 51, for establishing an initial circuit model, wherein the initial circuit model includes a plurality of parallel branches;

[0140] A first determining module 53, connected to the first establishing module 52, for determining a reference branch among a plurality of parallel branches;

[0141] A second determination module 54, connected to the first determination module 53, for determining a reference chip matching the reference branch among the plurality of chips;

[0142] A third determination module 55, connected to the second determination module 54, is used to determine the gate-source voltage difference between the reference branch and the other branches respectively, and obtain a plurality of gate-source voltage differences corresponding to the other branches one by one;

[0143] The first matching module 56 is connected to the third determining module 55, and is used to match chips for multiple other branches according to multiple gate-source voltage differences and reference chips to obtain a target circuit model so that the currents in multiple parallel branches included in the target circuit model are uniform.

[0144] In a circuit determination device provided by an embodiment of the present invention, a first acquisition module is set to obtain the gate-source voltage of each of a plurality of chips; a first establishment module is used to establish an initial circuit model, wherein the initial circuit model includes a plurality of parallel branches; a first determination module is used to determine a reference branch among the plurality of parallel branches; a second determination module is used to determine a reference chip that matches the reference branch among the plurality of chips; a third determination module is used to respectively determine the gate-source voltage difference between the reference branch and a plurality of other branches to obtain a plurality of gate-source voltage differences corresponding one to one to the plurality of other branches; a first matching module is used to match chips for the plurality of other branches according to the plurality of gate-source voltage differences and the reference chip to obtain a target circuit model, so that the currents in the plurality of parallel branches included in the target circuit model are uniform, thereby solving the technical problem of current imbalance in a multi-chip parallel circuit under an asymmetric layout, achieving the purpose of current balance in a multi-chip parallel circuit under an asymmetric layout, and further realizing the technical effect of improving the current utilization rate and overall reliability of the parallel unit.

[0145] It should be noted that the above modules can be implemented by software or hardware. For example, for the latter, it can be implemented in the following ways: the above modules can be located in the same processor; or the above modules can be located in different processors in any combination.

[0146] It should be noted that the first acquisition module 51, the first establishment module 52, the first determination module 53, the second determination module 54, the third determination module 55, and the first matching module 56 correspond to steps S102 to S112 in the embodiment, and the examples and application scenarios implemented by the above modules and the corresponding steps are the same, but are not limited to the contents disclosed in the above embodiments. It should be noted that the above modules can be run in a computer terminal as part of the device.

[0147] It should be noted that the optional or preferred implementation of this embodiment can refer to the relevant description in the embodiment, which will not be repeated here.

[0148] The above-mentioned circuit determination device may also include a processor and a memory. The first acquisition module 51, the first establishment module 52, the first determination module 53, the second determination module 54, the third determination module 55, the first matching module 56, etc. are all stored in the memory as program units, and the processor executes the above-mentioned program units stored in the memory to realize the corresponding functions.

[0149] The processor includes a kernel, which retrieves the corresponding program unit from the memory. There can be one or more kernels. The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one storage chip.

[0150] An embodiment of the present invention provides a non-volatile storage medium on which a program is stored. When the program is executed by a processor, a circuit determination method is implemented.

[0151] like Figure 6 It is shown that an embodiment of the present invention provides an electronic device, the electronic device 10 includes a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, the following steps are implemented: the memory is used to store a computer program, wherein when the computer program is executed by the processor, the processor implements the above-mentioned circuit determination method. The device in this article may be a server, a PC, etc.

[0152] The present invention also provides a computer program product, which, when executed on a data processing device, is suitable for executing a program initialized with the following method steps: computer instructions are executed by a processor to perform the above-mentioned circuit determination method.

[0153] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0154] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0155] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0156] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0157] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0158] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0159] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0160] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0161] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0162] The above are only embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A circuit determination method, characterized in that: include: Obtaining gate-source voltages of multiple chips; Establishing an initial circuit model, wherein the initial circuit model includes a plurality of parallel branches; Determining a reference branch among the plurality of parallel branches; determining a reference chip matching the reference branch among the plurality of chips; Determining the gate-source voltage difference between the reference branch and a plurality of other branches respectively, and obtaining a plurality of gate-source voltage differences corresponding to the plurality of other branches one by one; According to the multiple gate-source voltage differences and the reference chip, matching chips are provided for the multiple other branches to obtain a target circuit model so that the currents in the multiple parallel branches included in the target circuit model are uniform.

2. The method according to claim 1, characterized in that The obtaining of gate-source voltages of the plurality of chips includes: When the drain-source voltage is a fixed value, the voltage between the gate and the source on the multiple chips is gradually increased according to a fixed step size until the drain current of each of the multiple chips is a predetermined current value, thereby obtaining the gate-source voltage of each of the multiple chips, wherein the predetermined current value is the minimum drain current after the gate-source voltages of each of the multiple chips are fixed in order.

3. The method according to claim 1, characterized in that The step of determining a reference branch among the plurality of parallel branches comprises: Determining the parasitic inductance of each of the plurality of parallel branches; The parasitic inductances of the plurality of parallel branches are sorted, and the branch with the largest parasitic inductance is determined as the reference branch.

4. The method according to claim 1, characterized in that The step of determining a reference chip matching the reference branch among the plurality of chips comprises: sorting the gate-source voltages of the plurality of chips; The chip with the smallest gate-source voltage is determined as the reference chip.

5. The method according to claim 1, characterized in that The respectively determining the gate-source voltage difference between the reference branch and a plurality of other branches to obtain a plurality of gate-source voltage differences corresponding to the plurality of other branches one by one, comprises: Determine the equivalent circuits of the reference branch and the other branches respectively, and obtain a plurality of equivalent circuits corresponding to the other branches one by one; According to the multiple equivalent circuits, respectively determine the unbalanced current between the reference branch and the multiple other branches to obtain multiple unbalanced currents corresponding to the multiple other branches one by one; According to the multiple unbalanced currents, gate-source voltage differences between the reference branch and the multiple other branches are respectively determined to obtain the multiple gate-source voltage differences.

6. The method according to claim 1, characterized in that The step of matching the chips for the other branches according to the plurality of gate-source voltage differences and the reference chip to obtain a target circuit model so that the currents in the plurality of parallel branches included in the target circuit model are uniform comprises: respectively summing the plurality of gate-source voltage differences with the gate-source voltage of the reference chip to obtain current-sharing voltages corresponding one-to-one to the plurality of other branches; According to the one-to-one corresponding current sharing voltages of the multiple other branches, chips are matched for the multiple other branches to obtain the target circuit model.

7. A circuit determination device, characterized in that: include: A first acquisition module is used to acquire the gate-source voltage of each of the multiple chips; A first establishing module, used to establish an initial circuit model, wherein the initial circuit model includes a plurality of parallel branches; A first determining module, configured to determine a reference branch among the plurality of parallel branches; A second determination module, configured to determine a reference chip matching the reference branch among the plurality of chips; A third determination module is used to determine the gate-source voltage difference between the reference branch and a plurality of other branches respectively, and obtain a plurality of gate-source voltage differences corresponding to the plurality of other branches one by one; The first matching module is used to match the chips for the multiple other branches according to the multiple gate-source voltage differences and the reference chip to obtain a target circuit model so that the currents in the multiple parallel branches included in the target circuit model are uniform.

8. A non-volatile storage medium, characterized in that: The non-volatile storage medium stores a plurality of instructions, wherein the instructions are suitable for being loaded by a processor and executing the circuit determination method according to any one of claims 1 to 6.

9. An electronic device, characterized in that: include: One or more processors and a memory, wherein the memory is used to store one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the circuit determination method described in any one of claims 1 to 6.

10. A computer program product comprising computer instructions, characterized in that: The computer instructions are executed by a processor to execute the circuit determination method according to any one of claims 1 to 6.

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