Common-mode voltage suppression and neutral-point voltage self-balancing control method for parallel NPC type three-level inverter system
Through the zero common mode modulation and mid-point voltage self-balancing control method of parallel NPC three-level inverter, the problem of common mode voltage and mid-point potential imbalance in parallel three-level inverter is solved, and the stability and efficiency of the system are improved.
Patent Information
- Application Number
- CN202411963384.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-03-25
AI Technical Summary
The parallel three-level inverter will generate a large common mode voltage under the pulse width modulation method, resulting in electromagnetic interference and common mode noise in the system, increasing system losses, and affecting service life. In addition, the imbalance of the midpoint potential increases the low-frequency harmonic content of the output voltage, causing the power switching device to withstand uneven voltage stress.
By connecting the zero common mode modulation of the parallel NPC three-level inverter, the circulation between the two inverters is suppressed, and the midpoint voltage self-balancing is achieved. The specific methods include constructing a parallel NPC-type inverter system structural model based on an NPC-type three-level inverter, determining the three-phase reference voltage vector, selecting the corresponding zero common mode basic vector combination, calculating the acting time of the basic vector, and allocating the basic vector action sequence according to the principle of volt-second equilibrium to achieve midpoint potential equilibrium.
It effectively suppresses common mode voltage, reduces electromagnetic interference and common mode noise, improves the quality of grid-connected current, improves the stability and efficiency of the entire parallel three-level inverter system, and realizes self-balancing of the midpoint voltage, reducing the voltage stress inhomogeneity of the power switching device.
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Figure CN119696335A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of power electronics, and in particular to a common-mode voltage suppression and midpoint voltage self-balancing control method for a parallel NPC type three-level inverter system. Background Art
[0002] In high-power applications, three-level inverters are widely used due to their low harmonic content and low voltage stress on the switch tube. However, the capacity of a single three-level inverter is limited and it is difficult to meet the needs of high-power applications. Therefore, inverter paralleling has become an important option to increase the power capacity of the system. In industries such as photovoltaics, wind power, and motor drives, parallel three-level inverters have been widely used.
[0003] Although inverter parallel connection can improve system capacity and reliability, under the current pulse width modulation method, a large common mode voltage will be generated, and excessive common mode voltage may cause electromagnetic interference (EMI) and common mode noise in the system, and may damage other components in the circuit or interfere with other electronic equipment. The circulating current channel in the parallel structure will cause serious zero-sequence circulating current problems, which will increase system losses, cause grid current distortion, and make the power switch tube bear uneven current stress, seriously affecting the service life. In addition, the imbalance of the midpoint potential will increase the low-frequency harmonic content of the output voltage, and at the same time cause inconsistent voltage stress on the power switch device.
[0004] Therefore, it is of great significance to study the common-mode voltage suppression and midpoint voltage self-balancing control methods of parallel three-level inverters. The basic idea of the common-mode voltage suppression methods of parallel three-level inverters currently studied is to select the switch state with low common-mode voltage amplitude to participate in the modulation, so as to achieve the purpose of reducing the common-mode voltage amplitude. However, the reduction in the number of available switch states will cause a series of problems such as increased current THD and unbalanced midpoint voltage, and the common-mode voltage is only reduced to Vdc / 6 (V dc The voltage on the DC side) cannot be completely eliminated. The coordinated control between the neutral point balance and the zero-sequence circulating current is achieved by adjusting the redundant vector action time, introducing the neutral point balance adjustment factor, injecting the zero-sequence component, etc. These methods require accurate calculation and adjustment of the neutral point balance allocation factor, which increases the complexity of the control algorithm. Summary of the invention
[0005] Purpose of the invention: The purpose of the present invention is to provide a common-mode voltage suppression and mid-point voltage self-balancing control method for a parallel NPC three-level inverter system. By means of zero common-mode modulation of the parallel NPC three-level inverter, the circulating current between the two inverters is suppressed, and the mid-point voltage self-balancing is achieved, thereby solving the problems of common-mode current and common-mode interference generated in the process of electric energy conversion, improving the quality of the grid-connected current, and improving the stability and efficiency of the entire parallel three-level inverter system.
[0006] Technical solution: The common-mode voltage suppression and midpoint voltage self-balancing control method of a parallel NPC type three-level inverter system described in the present invention comprises the following steps:
[0007] (1) Construct a parallel NPC inverter system structure model based on an NPC three-level inverter;
[0008] (2) determining a three-phase reference voltage vector in a three-phase stationary coordinate system according to the three-phase sine wave to be output, and converting the reference voltage vector in the three-phase stationary coordinate system into an αβ coordinate system;
[0009] (3) According to the reference voltage vector amplitude in the αβ coordinate system and its angle with the α axis, determine the sector where the vector is located and the area where the vector is located in the sector;
[0010] (4) According to the large sector and the small sector where the reference voltage vector is located, combined with the basic output voltage vector, a corresponding zero common mode basic vector combination is selected;
[0011] (5) Calculate the action time of the basic vector in each sector;
[0012] (6) According to the volt-second balance principle, the basic vector action sequence is assigned to achieve midpoint potential balance.
[0013] Furthermore, step (1) is specifically as follows: a parallel NPC inverter system structure model is formed by connecting two NPC three-level inverters in parallel through a shared DC bus; wherein the NPC three-level inverter is composed of three parallel three-level bridge arms, each bridge arm includes four power switch tubes and two reverse series diodes; wherein the four power switch tubes are connected in series in a forward direction to the positive and negative poles of the DC bus, and the two reverse series diodes are connected in parallel to the two power switch tubes in the middle of the bridge arm, and the midpoints of the two diodes are connected to the neutral point of the filter capacitor on the DC bus side.
[0014] Furthermore, step (2) is specifically as follows: The standard three-phase reference voltage vector formula in the three-phase stationary coordinate system is as follows:
[0015] V a =V m cos(ωt)
[0016]
[0017]
[0018] Where V m is the phase voltage peak value, ω is the angular velocity; convert the reference voltage vector to equal amplitude:
[0019]
[0020] Furthermore, step (3) is as follows: On the αβ plane, according to the reference voltage vector V ref The angle and amplitude determine the sector and region where the reference voltage vector is located. The six sectors are divided as follows: Sector 1: -30°≤θ<30°, Sector 2: 30°≤θ<90°, Sector 3: 90°≤θ<150°, Sector 4: 150°≤θ<180° and -180°≤θ<-150°, Sector 5: -150°≤θ<-90°, Sector 6: -90°≤θ<-30°; The zero common mode point is formed by the zero common mode vector combination synthesized by the 27 basic voltage vectors of the standard three-level, and the modulation plane is divided into 6 sectors and 24 regions according to the zero common mode point.
[0021] Furthermore, step (4) is specifically as follows: each phase bridge arm of the NPC three-level converter outputs three different voltage levels including a positive level P, a zero level O and a negative level N; based on the three possible switching states P, O, N (2, 1, 0) of each phase bridge arm, 27 basic voltage vectors of the NPC three-level converter are defined; the spatial voltage vector diagram of the NPC three-level converter is drawn according to the basic output voltage vector; and a switching state combination that can generate a zero common-mode voltage is selected to draw a zero common-mode spatial voltage vector diagram of the parallel NPC inverter system.
[0022] Furthermore, step (5) is specifically as follows: Assuming that the reference voltage vector is in any sector area, three adjacent zero common mode vectors are used to synthesize, and according to the volt-second balance principle, the action time of the zero vector combination in each sector area is calculated:
[0023] V ref ·T S =V1T1+V2T2+V0T0
[0024] T S =T1+T2+T0
[0025] Among them, V ref represents the space vector, T is the switching period, V1, V2 and V0 represent three adjacent zero common mode vectors, and T1, T2 and T0 are the action times of the three zero vectors.
[0026] Furthermore, step (5) is specifically as follows: the zero common mode vector includes a plurality of distribution combinations. According to the 7-segment symmetrical vector distribution principle, the zero common mode vector of the combination is split to determine the switching sequence with the constraint of reducing the number of switching actions; by reasonably distributing the zero vector combination state, the average value of the charge flowing into and out of the midpoint of the DC side is made zero at any time; according to the volt-second balance principle, after each carrier cycle, the switching sequences of the two parallel inverters are exchanged.
[0027] The common mode voltage suppression and midpoint voltage self-balancing control system of a parallel NPC type three-level inverter system described in the present invention comprises:
[0028] Parallel NPC inverter system structure module: used to build a parallel NPC inverter system structure model based on NPC three-level inverter;
[0029] Coordinate system module: used to determine the three-phase reference voltage vector in the three-phase stationary coordinate system according to the three-phase sine wave output as needed, and convert the reference voltage vector in the three-phase stationary coordinate system into the αβ coordinate system;
[0030] Sector module: used to determine the sector where the vector is located and the area where the vector is located in the sector according to the reference voltage vector amplitude in the αβ coordinate system and its angle with the α axis;
[0031] Vector combination module: used to select the corresponding zero common mode basic vector combination according to the large sector and small sector where the reference voltage vector is located, combined with the basic output voltage vector;
[0032] Time module: used to calculate the action time of the basic vector in each sector;
[0033] Balance module: used to distribute the basic vector action sequence according to the volt-second balance principle to achieve midpoint potential balance.
[0034] An electronic device described in the present invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that when the computer program is loaded into the processor, the common-mode voltage suppression and midpoint voltage self-balancing control method of a parallel NPC type three-level inverter system described in any one of the items is implemented.
[0035] A storage medium described in the present invention stores a computer program, characterized in that when the computer program is executed by a processor, any one of the common-mode voltage suppression and mid-point voltage self-balancing control methods for a parallel NPC type three-level inverter system is implemented.
[0036] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: All 27 basic output vectors are used to synthesize the reference voltage vector, which makes full use of the modulation freedom of the three-level inverter and has good output harmonic performance. The common-mode voltage of the parallel three-level inverter is suppressed to near zero, and zero common-mode modulation is theoretically achieved. The parallel three-level converter SVPWM method provided by the present invention adopts multi-vector integrated modulation to synthesize the space vector. It only needs to divide the modulation plane into 6 sectors and 24 regions, and calculate the time for the four regional vectors of the first sector to act respectively, which significantly reduces the amount of calculation and the implementation process is simple. Avoid the complex plane division and duty cycle calculation of traditional 5-level modulation. In the switch sequence setting of the present invention, while reducing the number of switch switching times and suppressing the circulating current, it ensures that the midpoint currents generated by each vector in the sector offset each other, and the sum of the midpoint currents generated by all output voltage vectors is zero, so as to achieve self-balancing of the midpoint voltage. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] Figure 1 It is a schematic diagram of the topological structure of the present invention;
[0038] Figure 2 It is the parallel NPC zero common mode vector diagram of the present invention;
[0039] Figure 3 It is a schematic diagram of sector area division proposed by the present invention;
[0040] Figure 4 It is a flow chart of the implementation of the zero common mode voltage output method proposed by the present invention;
[0041] Figure 5 It is a schematic diagram of the action sequence of the switch state of sector 1 region 2 provided by the present invention;
[0042] Figure 6 is a common mode voltage comparison diagram of the present invention;
[0043] Figure 7 is the ab phase voltage waveform of the parallel converter system of the present invention;
[0044] Figure 8 is the three-phase current output waveform of the present invention;
[0045] Fig. 9 is the voltage waveform of the upper and lower capacitors on the DC side of the present invention;
[0046] Fig.10 It is the circulating current waveform diagram of the A-phase bridge arm of the two converters of the present invention. DETAILED DESCRIPTION
[0047] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.
[0048] like Figure 1 As shown, an embodiment of the present invention provides a common-mode voltage suppression and midpoint voltage self-balancing control method for a parallel NPC type three-level inverter system, comprising the following steps:
[0049] Figure 1 The parallel NPC three-level converter shown in FIG. 1 is composed of two NPC three-level converter submodules. Each submodule of this topology has three phase units, each of which is composed of four switching devices and two diodes. Each phase unit can output three levels, namely V dc / 2, 0, -V dc / 2(V dc The midpoints of the two diodes are connected to the neutral points of the two filter capacitors on the DC side, and the two inverters share the same DC side.
[0050] The present invention adopts SVPWM mode, aims at eliminating common mode voltage, realizing self-balancing of midpoint voltage, and suppressing circulating current, and proposes a control method for common mode voltage suppression and self-balancing of midpoint voltage of parallel three-level inverter system. The specific implementation steps include the following processes:
[0051] The given three-phase reference voltage (V a ,V b ,V c ) is transformed into the αβ coordinate system to obtain the reference voltage vector; the reference voltage vector is transformed into the dq coordinate system to obtain the amplitude and phase angle of the reference voltage vector. The sector and region where the reference voltage is located are determined based on its amplitude and phase angle. The coordinate transformation method is as follows:
[0052]
[0053]
[0054] The common mode voltage (CMV) in the inverter is the average output voltage between the neutral point O and the three terminals. In a parallel inverter system, the common mode voltage should be the average output voltage between the neutral point O and the six terminals.
[0055] The common-mode voltage of a single inverter can be expressed as:
[0056]
[0057] The common-mode voltage of parallel inverters can be expressed as:
[0058]
[0059] Where Vcmv is the common mode voltage, V XO is the voltage of the output terminal to the center point O, X=A, B, C.
[0060] Figure 2 It is the space vector diagram of the parallel three-level converter. The vector synthesis takes the output common mode voltage as zero as the constraint condition. Based on the 27 basic space vectors of the three-level, there are 19 synthetic vectors that can make the output common mode voltage zero. And each synthetic zero vector has 1 or 2 vector combinations. For example, zero vector 420 is composed of basic vectors 210 and 210, and zero vector 321 is composed of basic vectors 221 and 100, or 110 and 211.
[0061] like Figure 3 As shown, the present invention divides the modulation plane into 6 sectors and 24 regions according to 19 zero common mode synthetic vectors, and uses the nearest three vectors to synthesize the rotating reference vector. According to the volt-second balance principle, the action time of the zero vector combination in each sector region is calculated:
[0062] V ref ·T S =V1T1+V2T2+V0T0
[0063] T S =T1+T2+T0
[0064] Where V ref represents the space vector, T S is the switching period, V1, V2 and V0 represent three adjacent zero common-mode vectors, and T1, T2 and T0 are the action times of the three zero vectors.
[0065] Depend on Figure 3 , Figure 4 It can be seen that according to the volt-second balance principle, a reference voltage vector can be synthesized through three zero common-mode vectors in any triangular area, and the output common-mode voltage value is zero.
[0066] In the switching sequence setting, it is necessary to use a zero common mode vector to control the fluctuation of the midpoint voltage, suppress the circulating current, and have a smaller number of switching times. Figure 5 This is a schematic diagram of the switching sequence of the reference voltage in the four regions of the first sector. Taking region 2 of sector I as an example, vector 312 has two combinations (211+101) or (100+212), vector 402 has two combinations (201+201) or (202+200), and vector 411 has two combinations (211+200) or (201+210). The sequence selection is based on reducing the number of switching actions, and the combinations are shown in Table 1.
[0067] Table 1 Voltage vector arrangement
[0068]
[0069] As shown in Table 1, 312, 402, and 411 are a combination vector that treats the two parallel inverters as an integrated modulation. In one carrier cycle, each switch tube only operates twice. And at any time, the average output voltage is zero. Taking Zone 1 as an example, the voltage output by inverter 1 is V dc / 2, 0, V dc / 2, the voltage output by inverter 2 is 0, -V dc / 2, -V dc / 2, when operating in parallel, the system common mode voltage value is zero.
[0070] In order to balance the output between the two inverters, the switching sequences of the two inverters are exchanged after each switching cycle so that the volt-seconds of the two inverters are balanced within two cycles, thereby suppressing the circulating current between the inverters.
[0071] When the inverter circuit outputs different basic voltage vectors, different paths will be formed. The load current flows through the midpoint of the DC side capacitor to charge and discharge the capacitor. The imbalance of charge flowing into and out of the midpoint in a cycle will cause the midpoint voltage to shift. To ensure the precise stability of the midpoint potential, it is necessary to control the inflow charge to be equal to the outflow charge in a cycle. Only when the switch state of the phase arm is 1, there will be a midpoint current i NP As shown in Table 1, at any time, the number of phase arms of the two inverters in state 1 is the same, and the time of vector action is exactly the same. The charge flowing into the neutral point is equal to the charge flowing out. Therefore, the set switching sequence achieves self-balancing of the midpoint voltage.
[0072] This example is verified by MATLAB / Simulink simulation. In the simulation, the DC power supply uses 200V DC, the DC side capacitance is 500μF, the load resistance is 9.7Ω, the load inductance is 0.5mH, the coupling inductance is 1.1mH, and the modulation index is 0.9.
[0073] Figure 6 This is a comparison chart of the common mode voltage between the modulation method proposed by the present invention and the conventional SVPWM. The common mode voltage is basically reduced to near 0V, thereby suppressing the common mode current from harming the motor bearings of the motor system and the photovoltaic panels of the photovoltaic system. At the same time, the suppression of the common mode voltage also reduces the possibility of electromagnetic interference, thereby ensuring the safe and reliable operation of the system.
[0074] Figure 7-10 The waveforms of the output phase voltage, three-phase current, upper and lower capacitor voltages on the DC side, and zero-sequence circulating current of the parallel NPC inverter of this embodiment when the modulation index is 0.9.
Claims
1. A method for common mode voltage suppression and midpoint voltage self-balancing control of a parallel NPC type three-level inverter system, characterized in that: The following steps are involved: (1) Construct a parallel NPC inverter system structure model based on an NPC three-level inverter; (2) determining a three-phase reference voltage vector in a three-phase stationary coordinate system according to the three-phase sine wave to be output, and converting the reference voltage vector in the three-phase stationary coordinate system into an αβ coordinate system; (3) According to the reference voltage vector amplitude in the αβ coordinate system and its angle with the α axis, determine the sector where the vector is located and the area where the vector is located in the sector; (4) According to the large sector and the small sector where the reference voltage vector is located, combined with the basic output voltage vector, a corresponding zero common mode basic vector combination is selected; (5) Calculate the action time of the basic vector in each sector; (6) According to the volt-second balance principle, the basic vector action sequence is assigned to achieve midpoint potential balance.
2. The common mode voltage suppression and midpoint voltage self-balancing control method of a parallel NPC type three-level inverter system according to claim 1, characterized in that: Step (1) is as follows: Parallel NPC inverter system structure model: two NPC three-level inverters are connected in parallel through a shared DC bus; wherein the NPC three-level inverter is composed of three parallel three-level bridge arms, each bridge arm includes four power switch tubes and two reverse series diodes; wherein the four power switch tubes are connected in series in a forward direction to the positive and negative poles of the DC bus, and the two reverse series diodes are connected in parallel to the two power switch tubes in the middle of the bridge arm, and the midpoints of the two diodes are connected to the neutral point of the filter capacitor on the DC bus side.
3. The common mode voltage suppression and midpoint voltage self-balancing control method of a parallel NPC type three-level inverter system according to claim 1, characterized in that: Step (2) is as follows: The standard three-phase reference voltage vector formula in the three-phase stationary coordinate system is as follows: V a =V m cos(ωt) Where V m is the phase voltage peak value, ω is the angular velocity; convert the reference voltage vector to equal amplitude:
4. The common mode voltage suppression and midpoint voltage self-balancing control method of a parallel NPC type three-level inverter system according to claim 1, characterized in that: Step (3) is as follows: On the αβ plane, according to the reference voltage vector V ref The angle and amplitude determine the sector and region where the reference voltage vector is located. The six sectors are divided as follows: Sector 1: -30°≤θ<30°, Sector 2: 30°≤θ<90°, Sector 3: 90°≤θ<150°, Sector 4: 150°≤θ<180° and -180°≤θ<-150°, Sector 5: -150°≤θ<-90°, Sector 6: -90°≤θ<-30°; The zero common mode point is formed by the zero common mode vector combination synthesized by the 27 basic voltage vectors of the standard three-level, and the modulation plane is divided into 6 sectors and 24 regions according to the zero common mode point.
5. The common mode voltage suppression and midpoint voltage self-balancing control method of a parallel NPC type three-level inverter system according to claim 1, characterized in that: Step (4) is as follows: each phase bridge arm of the NPC three-level converter outputs three different voltage levels including a positive level P, a zero level O and a negative level N; based on the three possible switching states P, O, N (2, 1, 0) of each phase bridge arm, 27 basic voltage vectors of the NPC three-level converter are defined; the spatial voltage vector diagram of the NPC three-level converter is drawn according to the basic output voltage vector; and a switching state combination that can generate a zero common-mode voltage is selected to draw a zero common-mode spatial voltage vector diagram of the parallel NPC inverter system.
6. The common mode voltage suppression and midpoint voltage self-balancing control method of a parallel NPC type three-level inverter system according to claim 1, characterized in that: Step (5) is as follows: Assume that the reference voltage vector is in any sector area, and use three adjacent zero common mode vectors to synthesize them. According to the volt-second balance principle, calculate the action time of the zero vector combination in each sector area: In ref ·T S =V1T1+V2R2+V0T0 T S =T1+T2+T0 Among them, V ref represents the space vector, T is the switching period, V1, V2 and V0 represent three adjacent zero common mode vectors, and T1, T2 and T0 are the action times of the three zero vectors.
7. The method for common mode voltage suppression and midpoint voltage self-balancing control of a parallel NPC type three-level inverter system according to claim 1, characterized in that: Step (5) is as follows: the zero common mode vector includes a plurality of distribution combinations. According to the 7-segment symmetrical vector distribution principle, the zero common mode vector of the combination is split to reduce the number of switching actions as a constraint, and the switching sequence is determined; by reasonably distributing the zero vector combination state, the average value of the charge flowing into and out of the midpoint of the DC side is made zero at any time; according to the volt-second balance principle, after each carrier cycle, the switching sequences of the two parallel inverters are exchanged.
8. A common mode voltage suppression and midpoint voltage self-balancing control system for a parallel NPC type three-level inverter system, characterized in that: include: Parallel NPC inverter system structure module: used to build a parallel NPC inverter system structure model based on NPC three-level inverter; Coordinate system module: used to determine the three-phase reference voltage vector in the three-phase stationary coordinate system according to the three-phase sine wave output as needed, and convert the reference voltage vector in the three-phase stationary coordinate system into the αβ coordinate system; Sector module: used to determine the sector where the vector is located and the area where the vector is located in the sector according to the reference voltage vector amplitude in the αβ coordinate system and its angle with the α axis; Vector combination module: used to select the corresponding zero common mode basic vector combination according to the large sector and small sector where the reference voltage vector is located, combined with the basic output voltage vector; Time module: used to calculate the action time of the basic vector in each sector; Balance module: used to distribute the basic vector action sequence according to the volt-second balance principle to achieve midpoint potential balance.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the computer program is loaded into a processor, the method for common-mode voltage suppression and midpoint voltage self-balancing control of a parallel NPC type three-level inverter system according to any one of claims 1 to 7 is implemented.
10. A storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method for common-mode voltage suppression and midpoint voltage self-balancing control of a parallel NPC type three-level inverter system according to any one of claims 1 to 7 is implemented.
Citation Information
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