DC-DC module control method and device, medium and product

Abstract

The embodiment of the invention relates to the technical field of digital signal processing, and discloses a DC-DC module control method and device, a medium and a product. Comprising the following steps: performing electrical parameter sampling on a DC-DC module, and judging whether a current working mode is a Buck mode or a Boost mode through a comparator circuit; calculating the deviation between the output voltage and the target voltage in the real-time electrical parameters, generating a PWM duty ratio adjusting signal, and generating a plurality of paths of staggered PWM driving signals through a phase shift circuit; performing power distribution on the multiple paths of staggered PWM driving signals, and adjusting the conduction time of each path of switch tube to obtain a current-sharing control signal; and analyzing the real-time electrical parameters, the current working mode, the PWM duty ratio adjustment signal, the multi-path staggered PWM driving signal and the current-sharing control signal to obtain a dynamic adjustment strategy. The technical problem that the control accuracy and efficiency of the DC-DC module are low can be at least solved.

Description

Technical Field

[0001] The present application relates to the field of digital signal processing technology, and in particular to a control method, device, medium and product of a DC-DC module. Background Art

[0002] As a key component in power electronic systems, DC-DC converters are widely used in new energy power generation, electric vehicles, aerospace and other fields. Traditional DC-DC converter control methods mainly use fixed frequency PWM control, sliding mode control or predictive control. These methods achieve output voltage stability by adjusting the on-time of the switch tube. With the development of power electronic technology, multi-phase parallel DC-DC converters have gradually become the mainstream choice for high-power applications because of their advantages such as current stress dispersion, uniform heat loss and small output ripple. In multi-phase parallel systems, master-slave control, circulating current control or distributed control strategies are often used to achieve current sharing between phases.

[0003] However, the existing DC-DC converter control methods still have some shortcomings. First, in scenarios where the working mode is frequently switched, traditional control strategies are difficult to respond quickly, which can easily lead to output voltage fluctuations or system instability. Secondly, current sharing control in multi-phase parallel systems often relies on precise current sampling, which not only increases system costs but also may introduce additional noise. In addition, in the face of complex and changeable load conditions and input voltage fluctuations, fixed-parameter controllers are difficult to maintain optimal performance. Finally, most of the existing control methods are designed for specific working modes and lack a unified control strategy for Buck mode and Boost mode, which limits the application of DC-DC converters under a wide range of input and output conditions. Summary of the invention

[0004] One object of the present application is to provide a control method, device, medium and product for a DC-DC module, at least to solve the technical problem of low accuracy and efficiency of control of the DC-DC module.

[0005] To achieve the above objectives, some embodiments of the present application provide the following aspects:

[0006] In the first aspect, some embodiments of the present application also provide a control method for a DC-DC module, including: sampling electrical parameters of the DC-DC module to obtain real-time electrical parameters; analyzing the real-time electrical parameters, and judging whether the current working mode is Buck mode or Boost mode through a comparator circuit; calculating the deviation between the output voltage and the target voltage in the real-time electrical parameters, and generating a PWM duty cycle adjustment signal through a PI controller; processing the PWM duty cycle adjustment signal, and generating a multi-channel interleaved PWM drive signal through a phase shift circuit; performing power distribution on the multi-channel interleaved PWM drive signal, and adjusting the conduction time of each switch tube through a parallel current sharing controller to obtain a current sharing control signal; comprehensively analyzing the real-time electrical parameters, the current working mode, the PWM duty cycle adjustment signal, the multi-channel interleaved PWM drive signal and the current sharing control signal through an adaptive control algorithm to obtain a dynamic adjustment strategy.

[0007] In a second aspect, some embodiments of the present application further provide an electronic device, comprising: one or more processors; and a memory storing computer program instructions, wherein the computer program instructions, when executed, cause the processor to perform the steps of the method described above.

[0008] In a third aspect, some embodiments of the present application further provide a computer-readable medium having computer program instructions stored thereon, wherein the computer program instructions can be executed by a processor to implement the method as described above.

[0009] In a fourth aspect, some embodiments of the present application further provide a computer program product, comprising a computer program / instruction, which implements the steps of the method described above when executed by a processor.

[0010] Compared with the related art, in the scheme provided by the embodiment of the present application, the electrical parameters of the DC-DC module are sampled to obtain real-time electrical parameters, which provides an accurate data basis for subsequent control. Then, by analyzing these real-time electrical parameters and judging the comparator circuit, it is possible to accurately identify whether the current working mode is Buck mode or Boost mode, which lays the foundation for the subsequent control strategy selection. After determining the working mode, the method calculates the deviation between the output voltage and the target voltage, and generates a PWM duty cycle adjustment signal through a PI controller to ensure the stability and rapid responsiveness of the output voltage. Subsequently, the PWM duty cycle adjustment signal is processed, and a multi-channel interlaced PWM drive signal is generated through a phase shift circuit. This interlaced control technology effectively reduces the output ripple and improves the overall performance of the system. In a multi-phase parallel system, the method distributes power to the multi-channel interlaced PWM drive signal, and uses a parallel current sharing controller to adjust the conduction time of each switch tube, thereby obtaining a current sharing control signal, ensuring the balanced operation of the multi-phase system and reducing the stress of a single switch tube. Finally, an adaptive control algorithm is introduced to comprehensively analyze the real-time electrical parameters, current working mode, PWM duty cycle adjustment signal, multi-channel interleaved PWM drive signal and current sharing control signal to obtain a dynamic adjustment strategy. This adaptive control mechanism enables the system to adjust the control parameters in real time according to the changes in working conditions, ensuring the best performance of the DC-DC module under various working conditions. Comprehensive, accurate and flexible control of the DC-DC module is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0012] Figure 1 An exemplary flow chart of a control method of a DC-DC module provided according to some embodiments of the present application;

[0013] Figure 2 This is a schematic diagram of the structure of an electronic device provided according to some embodiments of the present application. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0015] First embodiment

[0016] The first embodiment of the present application relates to a control method of a DC-DC module. Figure 1 As shown, the method may include the following steps:

[0017] S101, sampling electrical parameters of the DC-DC module to obtain real-time electrical parameters;

[0018] S102, analyzing the real-time electrical parameters, and determining whether the current working mode is Buck mode or Boost mode through a comparator circuit;

[0019] S103, calculating the deviation between the output voltage and the target voltage in the real-time electrical parameters, and generating a PWM duty cycle adjustment signal through a PI controller;

[0020] S104, processing the PWM duty cycle adjustment signal, and generating a multi-path interleaved PWM drive signal through a phase shift circuit;

[0021] S105, performing power distribution on the multiple interleaved PWM drive signals, adjusting the on-time of each switch tube through a parallel current sharing controller, and obtaining a current sharing control signal;

[0022] S106, comprehensively analyzing the real-time electrical parameters, the current working mode, the PWM duty cycle adjustment signal, the multi-channel interleaved PWM drive signal and the current sharing control signal through an adaptive control algorithm to obtain a dynamic adjustment strategy.

[0023] Specifically, high-precision sampling of input voltage, output voltage, input current and output current is performed. The sampling circuit uses a high-speed analog-to-digital converter to convert analog signals into digital signals. Subsequently, the sampled digital signals are low-pass filtered to eliminate high-frequency noise interference. Next, the filtered data is smoothed by a moving average algorithm to improve the stability of the data. Finally, the smoothed data is calibrated and compensated to eliminate the error of the sampling circuit and obtain accurate real-time electrical parameters. After obtaining the real-time electrical parameters, the control method analyzes these parameters and determines the current working mode through a comparator circuit. Specifically, the ratio of the input voltage to the output voltage is compared. If the input voltage is greater than the output voltage, it is judged to be a Buck mode; otherwise, it is judged to be a Boost mode. In order to improve the accuracy of the judgment and the anti-interference ability, the comparison of the input current and the output current is also introduced as an auxiliary judgment basis. The results of the voltage comparison and the current comparison are combined through logical operations to obtain the final working mode judgment result. In order to prevent frequent switching of the working mode, time delay and filtering processing are introduced to ensure the stability of the working mode.

[0024] After determining the working mode, the control method calculates the deviation between the output voltage and the target voltage, and generates a PWM duty cycle adjustment signal through a PI controller. The PI controller consists of a proportional link and an integral link, wherein the proportional link is used to quickly respond to the voltage deviation, and the integral link is used to eliminate the steady-state error. The output of the PI controller is subjected to linear transformation and dead zone compensation to obtain the initial value of the PWM duty cycle. Finally, the duty cycle value is limited and quantized to obtain the final PWM duty cycle adjustment signal. Next, the control method processes the PWM duty cycle adjustment signal and generates multiple interleaved PWM drive signals through a phase shift circuit. First, the PWM signal is frequency-multiplied to obtain a high-frequency PWM reference signal. Then, the high-frequency reference signal is phase-decomposed and offset to generate multiple interleaved phase signals. These signals are subjected to waveform shaping, rising edge detection and delay processing to form multiple interleaved PWM drive signals. Interleaved PWM technology can effectively reduce output voltage ripple and improve the overall performance of the system.

[0025] In a multi-phase parallel system, the control method distributes power to multiple interleaved PWM drive signals, and adjusts the on-time of each switch tube through a parallel current sharing controller to obtain a current sharing control signal. First, each PWM signal is demodulated to obtain the on-time data of each switch tube. Then, the average on-time is calculated and compared with the on-time of each channel to obtain the on-time deviation. The deviation is adjusted through proportional integral operation to generate a current sharing adjustment amount. Finally, the current sharing adjustment amount is superimposed on each PWM reference voltage to achieve accurate adjustment of the on-time of each switch tube. Finally, the control method uses an adaptive control algorithm to comprehensively analyze real-time electrical parameters, current working mode, PWM duty cycle adjustment signal, multiple interleaved PWM drive signals and current sharing control signal to obtain a dynamic adjustment strategy. The adaptive control algorithm first normalizes and extracts features of various parameters, and then obtains preliminary adjustment parameters through data fusion and fuzzy reasoning. These parameters are adaptively adjusted and constrained to form a continuous adjustment curve. Finally, the adjustment curve is piecewise linearized and quantized to obtain the final dynamic adjustment strategy.

[0026] For example, assume a four-phase parallel DC-DC converter system with an input voltage of 48V and a target output voltage of 12V. At a certain moment, the sampled output voltage is 11.8V. The control method first determines that the working mode is Buck mode. Then, the voltage deviation is calculated to be 0.2V, and a PWM duty cycle adjustment signal is generated through the PI controller. Assuming that the adjusted duty cycle is 25%, the phase shift circuit decomposes this signal into four PWM drive signals with a phase difference of 90 degrees. In the current sharing control, it is found that the current of the first channel is slightly higher, and the current sharing is achieved by adjusting its duty cycle to 24.8%. Finally, the adaptive control algorithm fine-tunes the PI controller parameters according to the current working state to optimize the system response speed and stability. Through this series of fine control steps, the DC-DC module can maintain stable and efficient operation under various working conditions.

[0027] In this embodiment, the electrical parameters of the DC-DC module are sampled to obtain real-time electrical parameters, providing an accurate data basis for subsequent control. Then, by analyzing these real-time electrical parameters and judging the comparator circuit, it is possible to accurately identify whether the current working mode is Buck mode or Boost mode, which lays the foundation for the subsequent control strategy selection. After determining the working mode, the method calculates the deviation between the output voltage and the target voltage, and generates a PWM duty cycle adjustment signal through a PI controller to ensure the stability and rapid responsiveness of the output voltage. Subsequently, the PWM duty cycle adjustment signal is processed, and a multi-channel interleaved PWM drive signal is generated through a phase shift circuit. This interleaved control technology effectively reduces the output ripple and improves the overall performance of the system. In a multi-phase parallel system, the method distributes power to the multi-channel interleaved PWM drive signal, and uses a parallel current sharing controller to adjust the conduction time of each switch tube, thereby obtaining a current sharing control signal, ensuring the balanced operation of the multi-phase system and reducing the stress of a single switch tube. Finally, an adaptive control algorithm is introduced to comprehensively analyze the real-time electrical parameters, current working mode, PWM duty cycle adjustment signal, multi-channel interleaved PWM drive signal and current sharing control signal to obtain a dynamic adjustment strategy. This adaptive control mechanism enables the system to adjust the control parameters in real time according to the changes in working conditions, ensuring the best performance of the DC-DC module under various working conditions. Comprehensive, accurate and flexible control of the DC-DC module is achieved.

[0028] Second embodiment

[0029] The second embodiment of the present application relates to a control method for a DC-DC module. The second implementation is an improvement on the first embodiment, and the specific improvement is: sampling electrical parameters of the DC-DC module to obtain real-time electrical parameters, including:

[0030] (1) Connecting the input and output ends of the DC-DC module to a voltage sampling circuit and a current sampling circuit respectively to obtain an original sampling signal;

[0031] (2) performing analog-to-digital conversion on the original sampling signal to obtain digital sampling data, and performing low-pass filtering on the digital sampling data to obtain a filtered digital signal;

[0032] (3) performing moving average processing on the filtered digital signal to obtain smoothed voltage and current data, and performing calibration compensation on the smoothed voltage and current data to obtain calibrated voltage and current values;

[0033] (4) performing effective value calculation on the calibrated voltage and current values ​​to obtain effective voltage and current values ​​of input and output, and performing mutation detection on the effective voltage and current values ​​to obtain voltage and current mutation marks;

[0034] (5) The effective voltage and current values ​​and the voltage and current mutation signs are combined to obtain real-time electrical parameters.

[0035] In the embodiment of the present application, multiple precise data collection and processing steps are involved. First, a voltage sampling circuit and a current sampling circuit are connected to the input and output ends of the DC-DC module respectively to obtain the original sampling signal. The voltage sampling circuit usually adopts a resistor divider network, while the current sampling circuit usually uses a Hall sensor or a sampling resistor. The design of these sampling circuits needs to consider high common-mode voltage suppression and wide bandwidth characteristics to ensure that accurate sampling signals can be obtained under various working conditions. After obtaining the original sampling signal, analog-to-digital conversion is performed to convert the continuous analog signal into a discrete digital signal. The selection of analog-to-digital converter (ADC) is crucial, and factors such as sampling rate, resolution and conversion speed need to be considered. For DC-DC modules, a 12-bit or 16-bit ADC is usually used, and the sampling rate is between 100kHz and 1MHz to take into account sampling accuracy and system response speed. The converted digital sampling data is then low-pass filtered to remove high-frequency noise and interference. Commonly used low-pass filters include Butterworth filters or Chebyshev filters, and the cut-off frequency of the filter is usually set to 1 / 10 to 1 / 5 of the switching frequency to effectively suppress switching noise without affecting useful signals. The low-pass filtered digital signal is then processed by moving average to obtain smoothed voltage and current data. Moving average is a simple and effective digital smoothing technique that reduces random fluctuations by calculating the average value of the most recent N sampling points. The selection of N requires a balance between smoothing effect and system response speed. For DC-DC modules, N is usually between 8 and 32. The smoothed data is then calibrated and compensated to obtain calibrated voltage and current values. The calibration and compensation process takes into account the gain error, offset error, and nonlinear error of the sampling circuit, and corrects the data through the pre-measured calibration coefficient to ensure the accuracy of the measurement results.

[0036] The calibrated voltage and current values ​​are then subjected to effective value calculation to obtain the effective voltage and current values ​​of the input and output. The effective value calculation adopts the root mean square (RMS) method. For DC signals, the effective value is equal to the average value; for signals containing ripple, the effective value calculation can reflect the energy level of the signal. At the same time, the effective voltage and current values ​​are subjected to mutation detection to obtain voltage and current mutation signs. The mutation detection algorithm identifies rapid changes in voltage or current by comparing the difference between adjacent sampling points with the preset threshold, which is very important for detecting load mutations or input voltage fluctuations. Finally, the effective voltage and current values ​​and the voltage and current mutation signs are combined to obtain complete real-time electrical parameters. These parameters include the effective values ​​of input voltage, output voltage, input current, output current, and the corresponding mutation signs. This comprehensive information provides a comprehensive and accurate data basis for subsequent control algorithms.

[0037] For example, assume a DC-DC module working in Buck mode, with a rated input voltage of 48V, an output voltage of 12V, and a rated power of 500W. At a certain moment, the original input voltage signal collected by the voltage sampling circuit is 47.8V, and after 16-bit ADC conversion, the digital value is 31130. This digital value is processed by low-pass filtering to remove high-frequency noise components. Then, it is smoothed by a 32-point moving average algorithm to obtain a more stable value of 31128. After compensation by a pre-calibrated calibration coefficient of 1.0006, the calibrated digital value is 31147. Finally, the input voltage effective value is calculated to be 47.95V. At the same time, the mutation detection algorithm compares the current value with the value of the previous sampling cycle and finds that the voltage change does not exceed the preset threshold of 0.5V, so the mutation flag is not triggered. This process is also applied to the processing of output voltage, input current, and output current.

[0038] Third embodiment

[0039] The third embodiment of the present application relates to a control method for a DC-DC module. The third implementation is an improvement on the first embodiment, and the specific improvement is: analyzing the real-time electrical parameters, and judging whether the current working mode is Buck mode or Boost mode through a comparator circuit, including:

[0040] (1) comparing the input voltage and the output voltage in the real-time electrical parameters to obtain a voltage ratio, and comparing the voltage ratio with a preset threshold to obtain a preliminary working mode judgment result;

[0041] (2) comparing the input current and the output current in the real-time electrical parameters to obtain a current ratio, and comparing the current ratio with a preset threshold to obtain a result of determining the auxiliary working mode;

[0042] (3) performing a logical AND operation on the preliminary working mode judgment result and the auxiliary working mode judgment result to obtain a comprehensive working mode judgment result;

[0043] (4) performing time delay processing on the comprehensive working mode judgment result to obtain a delayed working mode judgment result, and performing filtering processing on the delayed working mode judgment result to obtain a smoothed working mode judgment result;

[0044] (5) performing threshold comparison on the smoothed working mode judgment result to obtain a candidate working mode, and comparing the candidate working mode with the working mode of the previous cycle to obtain a working mode switching flag;

[0045] (6) Perform edge detection on the working mode switching flag to obtain a switching trigger signal, and latch the candidate working modes according to the switching trigger signal to obtain the current working mode, which is Buck mode or Boost mode.

[0046] In the embodiment of the present application, the input voltage and the output voltage in the real-time electrical parameters are compared to calculate the voltage ratio. This ratio is the main basis for judging the working mode, because in Buck mode, the output voltage is lower than the input voltage; while in Boost mode, the output voltage is higher than the input voltage. The calculated voltage ratio is then compared with a preset threshold value, which is usually slightly greater than 1 to take into account the error and fluctuation of the voltage measurement. The comparison result is used as a preliminary working mode judgment result to provide a basis for subsequent judgment. In order to improve the accuracy and robustness of the judgment, the control method also introduces current comparison as an auxiliary judgment basis. The input current and the output current in the real-time electrical parameters are compared to obtain a current ratio. Ideally, the current ratio of the Buck mode is less than 1, while the current ratio of the Boost mode is greater than 1. This current ratio is also compared with the preset threshold value to obtain an auxiliary working mode judgment result. Current comparison can provide additional judgment basis when the voltage comparison result is unclear, especially under light load or heavy load conditions.

[0047] The preliminary working mode judgment result and the auxiliary working mode judgment result are logically ANDed to obtain the comprehensive working mode judgment result. The logical AND operation requires that the results of the voltage comparison and the current comparison are consistent in order to obtain a definite working mode judgment. This dual judgment mechanism greatly improves the reliability of the judgment and reduces the probability of misjudgment. Considering the voltage and current fluctuations that may exist in actual work, the control method performs time delay processing on the comprehensive working mode judgment result to obtain the delayed working mode judgment result. The time delay processing is usually implemented by a shift register to store the judgment results of multiple consecutive sampling cycles. The result after delay processing is then filtered to obtain a smoothed working mode judgment result. The filtering process can adopt a simple majority voting method, that is, within a certain time window, which mode judgment result appears the most times, and the mode is used as the final result. This processing method effectively suppresses the influence of instantaneous fluctuations on the judgment result.

[0048] The smoothed working mode judgment result is then subjected to threshold comparison to obtain the candidate working mode. This threshold comparison process is actually a hysteresis comparator, which sets different thresholds for switching from Buck mode to Boost mode and from Boost mode to Buck mode to avoid frequent switching at the mode boundary. The candidate working mode is compared with the working mode of the previous cycle. If they are different, a working mode switching flag is generated. Finally, the working mode switching flag is edge detected to obtain a switching trigger signal. Edge detection can capture the moment of change of the working mode and provide timely response for subsequent control. According to the switching trigger signal, the candidate working mode is latched to obtain the current working mode, which is determined to be Buck mode or Boost mode. The latching process ensures that the working mode remains unchanged within a complete control cycle, providing stable working mode information for other control links.

[0049] For example, suppose that the input voltage of a DC-DC module is 48V, the output voltage is 24V, the input current is 10A, and the output current is 19A at a certain moment. First, the voltage ratio is calculated to be 0.5, which is less than the preset threshold value of 1.05, and the preliminary judgment is Buck mode. The current ratio is 1.9, which is greater than the preset threshold value of 0.95, and the auxiliary judgment is also Buck mode. The two are logically ANDed, and the comprehensive judgment result is Buck mode. This result is processed by a 10ms time delay and 5-point average filtering to obtain a smoothed judgment result. Assuming that in the past 100ms, 80% of the time is judged as Buck mode and 20% is judged as Boost mode, the final candidate working mode is determined to be Buck mode. Compared with the Boost mode of the previous cycle, a mode switching flag is generated. The edge detection captures this switching flag, triggers the mode latch, and finally determines that the current working mode is Buck mode.

[0050] Fourth embodiment

[0051] The fourth embodiment of the present application relates to a control method for a DC-DC module. The fourth implementation is an improvement on the second embodiment, and the specific improvement is: calculating the deviation between the output voltage and the target voltage in the real-time electrical parameters, and generating a PWM duty cycle adjustment signal through a PI controller, including:

[0052] (1) performing low-pass filtering on the output voltage in the real-time electrical parameters to obtain a filtered output voltage value, and performing a difference calculation between the filtered output voltage value and the target voltage to obtain a voltage deviation value;

[0053] (2) amplifying the voltage deviation value to obtain an amplified voltage deviation signal, and limiting the amplified voltage deviation signal to obtain a limited voltage deviation signal;

[0054] (3) performing a proportional operation on the voltage deviation signal after the amplitude limitation to obtain a proportional term output, and performing an integral operation on the voltage deviation signal after the amplitude limitation to obtain an integral term output;

[0055] (4) performing weighted summation processing on the proportional term output and the integral term output to obtain a PI controller output signal, and performing feedback compensation processing on the PI controller output signal to obtain a compensated control signal;

[0056] (5) performing linear transformation on the compensated control signal to obtain an initial value of the PWM duty cycle, and performing dead zone compensation processing on the initial value of the PWM duty cycle to obtain a compensated PWM duty cycle value;

[0057] (6) The compensated PWM duty cycle value is limited to obtain a limited PWM duty cycle value, and the limited PWM duty cycle value is quantized to obtain a PWM duty cycle adjustment signal.

[0058] In the embodiment of the present application, the output voltage in the real-time electrical parameter is subjected to low-pass filtering to obtain the output voltage value after filtering. The transfer function H(s) of the low-pass filter can be expressed as:

[0059]

[0060] Among them, ω c is the cutoff angular frequency, and s is the complex frequency variable. This filtering process can effectively remove high-frequency noise and improve the stability of subsequent control. The difference between the output voltage value after filtering and the target voltage is calculated to obtain the voltage deviation value e(t):

[0061] e(t)=V ref -V o (t)

[0062] Among them, V ref is the target voltage, V o (t) is the output voltage after filtering.

[0063] The voltage deviation value is amplified to obtain an amplified voltage deviation signal. The selection of the amplification factor K_a requires a balance between control accuracy and system stability. The amplified signal is limited to obtain a limited voltage deviation signal to prevent excessive deviation from causing controller saturation. The limiting function can be expressed as:

[0064]

[0065] Among them, e lim (t) is the deviation signal after limiting, e max is the maximum allowable deviation, K a is the amplification factor, which is used to adjust the amplitude of the original deviation signal.

[0066] The voltage deviation signal after limiting is subjected to proportional operation and integral operation respectively to obtain proportional output and integral output. The output signal of the PI controller is subjected to feedback compensation to obtain a compensated control signal. The output of the PI controller can be expressed as:

[0067]

[0068] Among them, K p is the proportionality coefficient, K i is the integral coefficient, u(t) is the output signal of the PI controller, and τ is the integral variable, which represents all the moments from 0 to t. It is a dummy variable used to represent time in the integration process. Feedback compensation can improve the dynamic response characteristics of the system. The compensated control signal is linearly transformed to obtain the initial value of the PWM duty cycle. The linear transformation can be expressed as:

[0069] D init =K d u(t)+D0

[0070] Among them, D init is the initial value of PWM duty cycle, K d is the conversion coefficient, and D0 is the reference duty cycle.

[0071] The initial value of the PWM duty cycle also needs to be processed with dead zone compensation to obtain the compensated PWM duty cycle value. Dead zone compensation can eliminate the influence of nonlinear characteristics during the opening and closing of the power switch tube. Finally, the compensated PWM duty cycle value is limited and quantized to obtain the final PWM duty cycle adjustment signal.

[0072] For example, assume a Buck DC-DC module, the target output voltage is 12V, and the actual sampled output voltage is 11.8V. After low-pass filtering with a cutoff frequency of 1kHz, the filtered output voltage value is 11.85V. The calculated voltage deviation value is e(t) = 12-11.85 = 0.15V. Assuming the amplification factor K a =10, the amplified deviation signal is 1.5V. After the ±2V limiting process, the limited deviation signal remains at 1.5V.

[0073] Set the PI controller parameter K p =0.5, K i =10, the proportional term output is 0.5*1.5=0.75, and the integral term output is assumed to be 0.5 (depending on the accumulated deviation in the past). The PI controller outputs u(t)=0.75+0.5=1.25. After feedback compensation and linear transformation (assuming Kd=0.1, D0=0.5), the initial value of the PWM duty cycle Dinit=0.1*1.25+0.5=0.625 is obtained. Considering that the dead time is 100ns and the switching period is 10μs, the duty cycle value after dead zone compensation is 0.635. Finally, after a limit processing of 0.1~0.9 and 8-bit quantization (256 levels), the final PWM duty cycle adjustment signal is 163.

[0074] Fifth embodiment

[0075] The fifth embodiment of the present application relates to a control method for a DC-DC module. The fifth embodiment is an improvement on the fourth embodiment, and the specific improvement is: processing the PWM duty cycle adjustment signal, generating a multi-path interleaved PWM drive signal through a phase shift circuit, including:

[0076] (1) digitally processing the PWM duty cycle adjustment signal to obtain a digital PWM signal, and performing frequency multiplication processing on the digital PWM signal to obtain a high-frequency PWM reference signal;

[0077] (2) performing phase decomposition on the high-frequency PWM reference signal to obtain multiple reference phase signals, and performing phase shift processing on the multiple reference phase signals to obtain multiple interleaved phase signals;

[0078] (3) performing waveform shaping on the multi-channel interlaced phase signals to obtain a square wave signal, and performing rising edge detection on the square wave signal to obtain a trigger time signal;

[0079] (4) delaying the trigger time signal to obtain a delayed trigger signal, and performing pulse width modulation on the delayed trigger signal to obtain a modulated PWM signal;

[0080] (5) performing dead zone insertion processing on the modulated PWM signal to obtain a PWM signal with a dead zone, and performing level conversion on the PWM signal with the dead zone to obtain a driving level signal;

[0081] (6) Buffering the driving level signal to obtain a buffered driving signal, and output isolating the buffered driving signal to obtain a multi-channel interleaved PWM driving signal.

[0082] In an embodiment of the present application, the PWM duty cycle adjustment signal is digitized to obtain a digital PWM signal. Digital processing includes converting an analog signal into a digital signal, which is usually completed using a high-speed analog-to-digital converter (ADC). The digital PWM signal is then subjected to frequency multiplication processing to obtain a high-frequency PWM reference signal. Frequency multiplication is usually achieved through a digital phase-locked loop (DPLL), which increases the frequency of the original PWM signal by several times to increase control accuracy and reduce output ripple. The high-frequency PWM reference signal is then phase-decomposed to obtain a multi-channel reference phase signal. Phase decomposition is the decomposition of a high-frequency signal into multiple signals with a fixed phase difference, which is usually implemented using a shift register or a counter. For N-phase interleaved PWM, the phase difference is usually 360° / N. The multi-channel reference phase signals are then phase-shifted to obtain a multi-channel interleaved phase signal. Phase shift processing can further optimize the phase relationship between the signals to minimize output ripple.

[0083] The multiple interleaved phase signals are processed by waveform shaping to obtain a square wave signal. Wave shaping usually includes the adjustment of the rising and falling edges to ensure fast signal conversion and low jitter. The square wave signal is then detected by the rising edge to obtain the trigger time signal. The rising edge detection is usually implemented by a comparator or an edge trigger to accurately locate the start time of the PWM signal. The trigger time signal is processed by delay to obtain a delayed trigger signal. The purpose of the delay processing is to compensate for the turn-on delay of the drive circuit and the power switch device, which is usually implemented by a programmable delay line. The delayed trigger signal is then pulse-width modulated to obtain a modulated PWM signal. Pulse width modulation is the process of adjusting the high level duration according to the duty cycle calculated by the control algorithm.

[0084] The modulated PWM signal is processed with dead zone insertion to obtain a PWM signal with dead zone. The dead zone is a short off time introduced to prevent the upper and lower bridge arm switches from being turned on at the same time, usually in the range of tens to hundreds of nanoseconds. The PWM signal with dead zone is level-converted to obtain a drive level signal. Level conversion converts the logic level signal into the drive level required by the power switching device, usually implemented by a level shifting circuit. The drive level signal is buffered to obtain a buffered drive signal. The buffering process can provide sufficient drive capability to ensure the rapid opening and closing of the power switching device. Finally, the buffered drive signal is output isolated to obtain a multi-channel interleaved PWM drive signal. Output isolation is usually implemented by optocouplers or digital isolators to isolate the control circuit and the power circuit to improve the anti-interference ability and safety of the system.

[0085] For example, assume a four-phase interleaved Buck DC-DC module with a base PWM frequency of 100kHz and a duty cycle of 40%. First, a high-frequency PWM reference signal of 400kHz is obtained by 4 times frequency multiplication. Then, phase decomposition is performed to obtain four reference phase signals with a phase difference of 90°. Assuming that an additional 5° phase shift is required, the phases of the four interleaved phase signals are 0°, 95°, 190°, and 285° respectively. After waveform shaping, these signals are square wave signals with steep rising edges and slow falling edges. The trigger moment signal interval obtained by rising edge detection is 2.5μs (1 / 400kHz). Considering that the turn-on delay of the MOSFET is 50ns, the trigger moment signal is delayed by 50ns. The delayed trigger signal is pulse-width modulated to obtain a PWM signal with a duty cycle of 40% and a duration of 1μs.

[0086] After inserting a 200ns dead zone, a PWM signal with dead zone is obtained. The level conversion converts the 0-3.3V logic level signal into a 0-12V drive level signal. After buffering, the rise time and fall time of the drive signal are optimized to 20ns and 30ns respectively. Finally, through optocoupler isolation, four electrically isolated interleaved PWM drive signals are obtained, which can directly drive the four power MOSFETs of the Buck converter.

[0087] Sixth embodiment

[0088] The sixth embodiment of the present application relates to a control method for a DC-DC module. The sixth embodiment is an improvement on the first embodiment, and the specific improvement is: power distribution is performed on multiple interleaved PWM drive signals, and the conduction time of each switch tube is adjusted by a parallel current sharing controller to obtain a current sharing control signal, including:

[0089] (1) Demodulating the multiple interleaved PWM drive signals to obtain the on-time data of each switch tube, and normalizing the on-time data of each switch tube to obtain a normalized on-time value;

[0090] (2) performing weighted average calculation on the normalized on-time values ​​to obtain an average on-time reference value, and performing difference calculation on the average on-time reference value and the normalized on-time value of each channel to obtain an on-time deviation value;

[0091] (3) performing proportional integral operation on the conduction time deviation value to obtain an initial current sharing adjustment value, and performing a limiting process on the initial current sharing adjustment value to obtain a current sharing adjustment value after limiting;

[0092] (4) quantizing the current sharing regulation amount after limiting to obtain a quantized current sharing regulation signal, and performing digital-to-analog conversion on the quantized current sharing regulation signal to obtain an analog current sharing regulation voltage;

[0093] (5) amplifying the analog current sharing regulation voltage to obtain an amplified current sharing regulation voltage, and superimposing the amplified current sharing regulation voltage to obtain a PWM reference voltage after each regulation;

[0094] (6) Compare and process the adjusted PWM reference voltages of each channel with the triangular wave carrier to obtain an adjusted PWM signal, and drive the adjusted PWM signal to obtain a current sharing control signal.

[0095] In the embodiment of the present application, the multi-channel interleaved PWM drive signal is demodulated to obtain the on-time data of each switch tube. The demodulation process uses a counter technology to record the high level duration of each PWM signal. Subsequently, the on-time data of each switch tube is normalized to obtain a normalized on-time value. The normalization process can be expressed as:

[0096]

[0097] Among them, T n,i is the normalized on-time value of the i-th channel, T i is the actual conduction time of the i-th path, T max is the maximum on-time of all paths. The normalized on-time values ​​are weighted averaged to obtain the average on-time reference value. The weighted average calculation formula is:

[0098]

[0099] Among them, T avg is the average on-time reference value, Q is the number of parallel paths, and w i is the weight coefficient of the i-th path, satisfying

[0100] Next, the difference between the average on-time reference value and the normalized on-time value of each channel is calculated to obtain the on-time deviation value:

[0101] ΔT i =T avg -T n,i

[0102] Where, ΔT i is the conduction time deviation value of the i-th path.

[0103] Perform proportional-integral operation on the conduction time deviation value to obtain the initial current sharing adjustment value. The proportional-integral operation can be expressed as:

[0104]

[0105] Among them, U i (k) is the initial current equalization adjustment value of the i-th channel at the k-th sampling, K x and K c are proportional coefficient and integral coefficient respectively. The initial current sharing adjustment amount is processed by limiting to obtain the current sharing adjustment amount after limiting to prevent over-regulation. The limiting process can be expressed as:

[0106]

[0107] Among them, U i,lim (k) is the current sharing adjustment after limiting, U max is the maximum allowable adjustment.

[0108] The current sharing regulation amount after limiting is quantized to obtain a quantized current sharing regulation signal. The quantization process converts the continuous regulation amount into a discrete digital signal. The quantized current sharing regulation signal is converted into an analog current sharing regulation voltage through a digital-to-analog converter (DAC). The analog current sharing regulation voltage is amplified to obtain an amplified current sharing regulation voltage. The amplification process is usually implemented using an operational amplifier to match the voltage range of the subsequent circuit.

[0109] The amplified current-sharing regulated voltage is superimposed with the original PWM reference voltage to obtain the regulated PWM reference voltage of each channel. The superposition process can be expressed as:

[0110] V pwm,i =V pwm,0 +K l U i,lim

[0111] Among them, V pwm,i is the PWM reference voltage after adjustment for the i-th channel, V pwm,0 is the original PWM reference voltage, K lis the superposition coefficient. The regulated PWM reference voltages of each channel are compared with the triangular wave carrier to obtain the regulated PWM signal. The comparison process is implemented by a high-speed comparator. When the reference voltage is higher than the triangular wave, a high level is output, otherwise a low level is output. Finally, the regulated PWM signal is driven and processed to obtain a current sharing control signal, which is used to directly control the power switch tube.

[0112] For example, assume a four-phase parallel Buck DC-DC module with a switching frequency of 100kHz. At a certain moment, the on-times of the four switches are 4.5μs, 4.8μs, 4.6μs, and 4.7μs, respectively. First, normalization is performed, and the normalized on-time values ​​are 0.9375, 1.0000, 0.9583, and 0.9792, respectively. Assuming that the four weights are equal, the average on-time reference value is 0.9688. The on-time deviation values ​​of the four are calculated to be 0.0313, -0.0312, 0.0105, and -0.0104, respectively.

[0113] Assume the proportionality factor K x =0.5, integral coefficient K c =0.1, assuming that the previous integral value is 0, the initial current sharing adjustment values ​​are 0.0157, -0.0156, 0.0053 and -0.0052 respectively. After the limiting process of ±0.02, the current sharing adjustment value after limiting remains unchanged. These adjustment values ​​are converted into analog voltages by 12-bit DAC, with a range of 0-3.3V. Assuming the amplification factor is 2, the current sharing adjustment voltage range after amplification is 0-6.6V. The original PWM reference voltage is 5V, and the superposition coefficient K l =1, the four regulated PWM reference voltages are 5.1047V, 4.8953V, 5.0353V and 4.9647V respectively. These voltages are compared with the triangle wave carrier with a peak value of 10V to generate four PWM signals with slightly different duty cycles. After these PWM signals are processed by the drive circuit, the current sharing control signals that can achieve current balance are obtained.

[0114] Seventh embodiment

[0115] The seventh embodiment of the present application relates to a control method for a DC-DC module. The seventh implementation is an improvement on the sixth embodiment, and the specific improvement is: a dynamic adjustment strategy is obtained by comprehensively analyzing the real-time electrical parameters, the current working mode, the PWM duty cycle adjustment signal, the multi-channel staggered PWM drive signal and the current sharing control signal through an adaptive control algorithm, including:

[0116] (1) performing data normalization processing on real-time electrical parameters, current working mode, PWM duty cycle adjustment signal, multi-channel interleaved PWM drive signal and current sharing control signal to obtain a normalized input vector, and performing feature extraction on the normalized input vector to obtain a feature vector;

[0117] (2) Performing data fusion processing on the feature vectors to obtain fusion features, and performing fuzzification processing on the fusion features to obtain a fuzzy input set;

[0118] (3) Perform fuzzy reasoning on the fuzzy input set to obtain a fuzzy output set, and defuzzify the fuzzy output set to obtain preliminary adjustment parameters;

[0119] (4) Adaptively adjusting the preliminary adjustment parameters to obtain adjusted parameters, and constraining the adjusted parameters to obtain constrained adjustment parameters;

[0120] (5) interpolating the constrained adjustment parameters to obtain a continuous adjustment curve, and performing piecewise linearization on the continuous adjustment curve to obtain a piecewise linear adjustment strategy;

[0121] (6) The piecewise linear regulation strategy is quantized to obtain discrete regulation instructions, and the discrete regulation instructions are encoded to obtain a dynamic regulation strategy.

[0122] In an embodiment of the present application, data normalization processing is performed on real-time electrical parameters, current working mode, PWM duty cycle adjustment signal, multi-channel interleaved PWM drive signal and current sharing control signal to obtain a normalized input vector. Normalization processing unifies data of different dimensions into the interval [0,1], which is helpful for subsequent processing. The normalized input vector is subjected to feature extraction to obtain a feature vector. Feature extraction uses the principal component analysis (PCA) method to extract the most representative low-dimensional features from high-dimensional data to reduce data complexity. The feature vector is then subjected to data fusion processing to obtain a fused feature. Data fusion uses the Dempster-Shafer evidence theory to comprehensively consider the reliability and conflict degree of multi-source information to form a more comprehensive description of the system state. The fused features are fuzzified to obtain a fuzzy input set. The fuzzification process converts precise numerical values ​​into fuzzy sets and uses membership functions to describe the uncertainty of the data.

[0123] The fuzzy input set enters the fuzzy reasoning link, and reasoning is performed based on the preset fuzzy rule base to obtain the fuzzy output set. Fuzzy reasoning uses the Mamdani reasoning method to map input to output through IF-THEN rules. The fuzzy output set is defuzzified to obtain preliminary adjustment parameters. Defuzzification uses the centroid method to convert the fuzzy set into an accurate numerical output. The preliminary adjustment parameters are then adaptively adjusted to obtain the adjusted parameters. The adaptive adjustment uses the recursive least squares method (RLS) to update the parameter estimate in real time according to the system response. The adjusted parameters are constrained to obtain the constrained adjustment parameters. Constraint processing ensures that the parameters are within a reasonable range to avoid over-adjustment that causes system instability.

[0124] The constrained adjustment parameters are interpolated to obtain a continuous adjustment curve. The interpolation uses the cubic spline interpolation method to generate a smooth continuous curve between discrete points. The continuous adjustment curve is then piecewise linearized to obtain a piecewise linear adjustment strategy. Piecewise linearization simplifies complex nonlinear curves into multi-segment linear functions, which is convenient for actual controller implementation. Finally, the piecewise linear adjustment strategy is quantized to obtain discrete adjustment instructions. The quantization process converts the continuous adjustment strategy into a finite number of discrete levels to adapt to the digital control system. The discrete adjustment instructions are encoded to obtain the final dynamic adjustment strategy. The encoding process converts the adjustment instructions into an instruction format that can be directly executed by the controller.

[0125] For example, assume a four-phase parallel Buck type DC-DC module with an input voltage of 48V, a target output voltage of 12V, and a rated power of 1kW. At a certain moment, the real-time electrical parameters show that the output voltage is 11.8V, the total output current is 80A, and the four-phase currents are 19.5A, 20.2A, 20.5A, and 19.8A respectively. The current working mode is Buck mode, the PWM duty cycle is 25%, and the phase difference of the four-way interleaved PWM drive signal is 90°. First, data normalization is performed to map parameters such as voltage, current, and duty cycle to the [0,1] interval. For example, the normalized output voltage is 0.983 (11.8 / 12) and the total current is 0.8 (80 / 100). After feature extraction, a 5-dimensional feature vector is obtained, which contains output voltage deviation, total current percentage, phase current imbalance, PWM duty cycle, and working mode indication.

[0126] Data fusion takes these five features into consideration and obtains a system status indicator. Fuzzification converts this indicator into the membership of three fuzzy sets: "light load", "normal" and "heavy load". Assume that the obtained memberships are 0.1, 0.7 and 0.2 respectively. Fuzzy reasoning is based on preset rules, such as "IF the load is normal AND the voltage is low THEN increase the duty cycle slightly", to obtain the fuzzy set of adjustment suggestions. After defuzzification, preliminary adjustment parameters are obtained, such as a 1.2% increase in the duty cycle. Adaptive adjustment considers the current response speed and stability of the system and may adjust the duty cycle increase to 1.5%. Constraint processing ensures that the adjusted duty cycle does not exceed the upper limit of 30%. Interpolation and piecewise linearization convert this adjustment amount into a piecewise function with different adjustment slopes in different load ranges.

[0127] Finally, the quantization process discretizes the continuous adjustment curve into 256 levels, and after encoding, generates the final dynamic adjustment strategy, including PWM duty cycle adjustment instructions and current sharing control parameter update instructions. This dynamic adjustment strategy guides the controller to fine-tune the PWM signal and current sharing control in the next control cycle, so that the output voltage gradually approaches the target value, while optimizing the current distribution of each phase. Through this series of complex data processing and decision-making processes, the DC-DC module control method achieves intelligent adaptation and precise control of complex working conditions.

[0128] The step division of the above methods is only for the purpose of clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent; adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the scope of protection of this patent.

[0129] In addition, some embodiments of the present application also provide an electronic device. The electronic device may be a digital computer in various forms, such as a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, etc. The electronic device may also be a mobile device in various forms, such as a personal digital processing, a cellular phone, a smart phone, a wearable device, and other similar computing devices.

[0130] The electronic device includes: one or more processors; and a memory storing computer program instructions, wherein when the computer program instructions are executed, the processor executes the steps of the method provided in any one or more of the above embodiments. Figure 2 An exemplary structural diagram of the electronic device is disclosed. Figure 2As shown, the electronic device includes: one or more processors 1101, memory 1102, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the electronic device, including instructions stored in or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some other embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple electronic devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Among them, the components shown in this article, their connections and relationships, and their functions are only used as examples, and are not intended to limit the implementation of the present application described and / or required herein.

[0131] The electronic device may further include: an input device 1103 and an output device 1104. The processor 1101, the memory 1102, the input device 1103 and the output device 1104 may be connected via a bus or other means. Figure 2 The example of connecting through bus is taken in the following.

[0132] The input device 1103 can receive input digital or character information, and generate key signal input related to the user settings and function control of the electronic device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick and other input devices. The output device 1104 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The display device may include, but is not limited to, a liquid crystal display (LCD), a light emitting diode (LED) display and a plasma display. In some embodiments, the display device may be a touch screen.

[0133] To provide interaction with a user, the electronic device may be a computer. The computer has: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball), through which the user can provide input to the computer. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0134] In the embodiments of the present application, a computer program / instruction is stored on a computer-readable medium, and when the computer program / instruction is executed by a processor, the steps of the method provided by any one or more of the above embodiments are implemented. The computer-readable medium may be included in the electronic device described in the above embodiments; or it may exist independently without being assembled into the device. The above computer-readable medium carries one or more computer-readable instructions.

[0135] The memory 1102 can be used as a non-transient computer-readable storage medium, which can be used to store non-transient software programs, non-transient computer executable programs and modules. The processor 1101 executes various functional applications and data processing of the server by running the non-transient software programs, instructions and modules stored in the memory 1102, so as to implement the program instructions / modules corresponding to the method provided by any one or more embodiments in the embodiments of the present application.

[0136] The memory 1102 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the electronic device, etc. In addition, the memory 1102 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory 1102 may optionally include a memory remotely arranged relative to the processor 1101, and these remote memories may be connected to the electronic device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0137] It should be noted that the computer-readable medium described in the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device.

[0138] Computer readable media include permanent and non-permanent, removable and non-removable media, and can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, modules of programs or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

[0139] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0140] In the above-described embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. For example, it can be implemented by using an application specific integrated circuit (ASIC), a general-purpose computer or any other similar hardware device. In certain embodiments, the software program of the present application can be executed by a processor to implement the above steps or functions. Similarly, the software program of the present application (including relevant data structures) can be stored in a computer-readable recording medium, for example, a RAM memory, a magnetic or optical drive or a floppy disk and similar devices. In addition, some steps or functions of the present application can be implemented by hardware, for example, as a circuit that cooperates with a processor to perform each step or function.

[0141] The computer program product provided in the embodiment of the present application includes one or more computer programs / instructions, and when the computer program / instructions are executed by the processor, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from a computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrations. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc.

[0142] The flow chart or block diagram in the accompanying drawings shows the possible architecture, function and operation of the equipment, method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated system for hardware that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0143] The scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes that fall within the meaning and scope of the equivalent elements of the claims are included in the present application. Any figure mark in the claims should not be regarded as limiting the claims involved. In addition, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices stated in the device claim may also be implemented by one unit or device through software or hardware. The words "first", "second", etc. are only used to distinguish the description, and do not indicate any particular order, nor can they be understood as indicating or implying relative importance.

[0144] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily mention changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims, and the above embodiments should be regarded as exemplary and non-restrictive.

Claims

1. A control method for a DC-DC module, characterized in that: include: Sampling electrical parameters of the DC-DC module to obtain real-time electrical parameters; Analyze the real-time electrical parameters and determine whether the current working mode is Buck mode or Boost mode through a comparator circuit; Calculating the deviation between the output voltage and the target voltage in the real-time electrical parameter, and generating a PWM duty cycle adjustment signal through a PI controller; Processing the PWM duty cycle adjustment signal to generate multiple interleaved PWM drive signals through a phase shift circuit; Power distribution is performed on the multiple interleaved PWM drive signals, and the conduction time of each switch tube is adjusted by a parallel current sharing controller to obtain a current sharing control signal; The real-time electrical parameters, the current working mode, the PWM duty cycle adjustment signal, the multi-channel interleaved PWM drive signal and the current sharing control signal are comprehensively analyzed through an adaptive control algorithm to obtain a dynamic adjustment strategy.

2. The method according to claim 1, characterized in that Sampling electrical parameters of the DC-DC module to obtain real-time electrical parameters, including: The input end and the output end of the DC-DC module are connected to a voltage sampling circuit and a current sampling circuit respectively to obtain an original sampling signal; Performing analog-to-digital conversion on the original sampling signal to obtain digital sampling data, and performing low-pass filtering on the digital sampling data to obtain a filtered digital signal; Performing moving average processing on the filtered digital signal to obtain smoothed voltage and current data, and performing calibration compensation on the smoothed voltage and current data to obtain calibrated voltage and current values; Performing effective value calculation on the calibrated voltage and current values ​​to obtain effective voltage and current values ​​of input and output, and performing mutation detection on the effective voltage and current values ​​to obtain voltage and current mutation marks; The effective voltage and current values ​​and the voltage and current mutation flags are combined to obtain the real-time electrical parameters.

3. The method according to claim 1, characterized in that Analyzing the real-time electrical parameters and determining whether the current working mode is Buck mode or Boost mode through a comparator circuit includes: Comparing the input voltage and the output voltage in the real-time electrical parameters to obtain a voltage ratio, and comparing the voltage ratio with a preset threshold to obtain a preliminary working mode determination result; Comparing the input current and the output current in the real-time electrical parameters to obtain a current ratio, and comparing the current ratio with a preset threshold to obtain an auxiliary working mode judgment result; Performing a logical AND operation on the preliminary working mode determination result and the auxiliary working mode determination result to obtain a comprehensive working mode determination result; Performing time delay processing on the comprehensive working mode judgment result to obtain a delayed working mode judgment result, and performing filtering processing on the delayed working mode judgment result to obtain a smoothed working mode judgment result; Performing threshold comparison on the smoothed working mode judgment result to obtain a candidate working mode, and comparing the candidate working mode with the working mode of the previous cycle to obtain a working mode switching flag; The working mode switching flag is edge detected to obtain a switching trigger signal, and the candidate working mode is latched according to the switching trigger signal to obtain the current working mode, which is Buck mode or Boost mode.

4. The method according to claim 2, characterized in that: Calculating the deviation between the output voltage and the target voltage in the real-time electrical parameter, and generating a PWM duty cycle adjustment signal through a PI controller, including: Performing low-pass filtering on the output voltage in the real-time electrical parameter to obtain a filtered output voltage value, and performing difference calculation between the filtered output voltage value and a target voltage to obtain a voltage deviation value; amplifying the voltage deviation value to obtain an amplified voltage deviation signal, and limiting the amplified voltage deviation signal to obtain a limited voltage deviation signal; Performing a proportional operation on the voltage deviation signal after the amplitude limitation to obtain a proportional term output, and performing an integral operation on the voltage deviation signal after the amplitude limitation to obtain an integral term output; Performing weighted sum processing on the proportional term output and the integral term output to obtain a PI controller output signal, and performing feedback compensation processing on the PI controller output signal to obtain a compensated control signal; Performing linear transformation on the compensated control signal to obtain an initial value of the PWM duty cycle, and performing dead zone compensation processing on the initial value of the PWM duty cycle to obtain a compensated PWM duty cycle value; The compensated PWM duty cycle value is subjected to a limiting process to obtain a limited PWM duty cycle value, and the limited PWM duty cycle value is subjected to a quantization process to obtain the PWM duty cycle adjustment signal.

5. The method according to claim 4, characterized in that The PWM duty cycle adjustment signal is processed to generate a multi-path interleaved PWM drive signal through a phase shift circuit, including: Digitally process the PWM duty cycle adjustment signal to obtain a digital PWM signal, and perform frequency multiplication processing on the digital PWM signal to obtain a high-frequency PWM reference signal; Performing phase decomposition on the high-frequency PWM reference signal to obtain multiple reference phase signals, and performing phase shift processing on the multiple reference phase signals to obtain multiple interlaced phase signals; Performing waveform shaping on the multi-path interlaced phase signals to obtain square wave signals, and performing rising edge detection on the square wave signals to obtain trigger timing signals; Performing delay processing on the trigger time signal to obtain a delayed trigger signal, and performing pulse width modulation on the delayed trigger signal to obtain a modulated PWM signal; Performing dead zone insertion processing on the modulated PWM signal to obtain a PWM signal with a dead zone, and performing level conversion on the PWM signal with the dead zone to obtain a driving level signal; The driving level signal is buffered to obtain a buffered driving signal, and the buffered driving signal is output isolated to obtain the multi-path interleaved PWM driving signal.

6. The method according to claim 1, characterized in that The power distribution is performed on the multiple interleaved PWM drive signals, and the conduction time of each switch tube is adjusted by a parallel current sharing controller to obtain a current sharing control signal, including: Demodulating the multiple interleaved PWM drive signals to obtain on-time data of each switch tube, and normalizing the on-time data of each switch tube to obtain a normalized on-time value; Performing weighted average calculation on the normalized on-time values ​​to obtain an average on-time reference value, and performing difference calculation on the average on-time reference value and the normalized on-time values ​​of each channel to obtain an on-time deviation value; Performing proportional integral operation on the conduction time deviation value to obtain an initial current sharing adjustment amount, and performing amplitude limiting processing on the initial current sharing adjustment amount to obtain an amplitude limited current sharing adjustment amount; Quantizing the current sharing adjustment amount after the limiting to obtain a quantized current sharing adjustment signal, and performing digital-to-analog conversion on the quantized current sharing adjustment signal to obtain an analog current sharing adjustment voltage; Amplifying the analog current sharing regulation voltage to obtain an amplified current sharing regulation voltage, and superimposing the amplified current sharing regulation voltage to obtain a PWM reference voltage after each regulation; The regulated PWM reference voltages of each channel are compared with the triangular wave carrier to obtain the regulated PWM signal, and the regulated PWM signal is driven to obtain the current sharing control signal.

7. The method according to claim 6, characterized in that The real-time electrical parameters, the current working mode, the PWM duty cycle adjustment signal, the multi-channel interleaved PWM drive signal and the current sharing control signal are comprehensively analyzed by an adaptive control algorithm to obtain a dynamic adjustment strategy, including: Performing data normalization processing on the real-time electrical parameters, the current working mode, the PWM duty cycle adjustment signal, the multi-channel interleaved PWM drive signal and the current sharing control signal to obtain a normalized input vector, and performing feature extraction on the normalized input vector to obtain a feature vector; Performing data fusion processing on the feature vector to obtain fusion features, and performing fuzzification processing on the fusion features to obtain a fuzzy input set; Performing fuzzy reasoning on the fuzzy input set to obtain a fuzzy output set, and performing defuzzification processing on the fuzzy output set to obtain preliminary adjustment parameters; Adaptively adjusting the preliminary adjustment parameters to obtain adjusted parameters, and constraining the adjusted parameters to obtain constrained adjustment parameters; Performing interpolation processing on the constrained adjustment parameters to obtain a continuous adjustment curve, and performing piecewise linearization processing on the continuous adjustment curve to obtain a piecewise linear adjustment strategy; The piecewise linear regulation strategy is quantized to obtain discrete regulation instructions, and the discrete regulation instructions are encoded to obtain the dynamic regulation strategy.

8. An electronic device, characterized in that: The electronic device comprises: one or more processors; and A memory storing computer program instructions, which, when executed, cause the processor to perform the steps of the method as claimed in any one of claims 1 to 7.

9. A computer readable medium having a computer program / instructions stored thereon, characterized in that: When the computer program / instructions are executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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