Multi-output full-wave rectification single-stage voltage-adjustable rectification system

Abstract

The invention provides a single-stage voltage-adjustable rectification system for multi-output full-wave rectification. The single-stage voltage-adjustable rectification system comprises a rectifier and a control module, the rectifier comprises a generation module, an idle switch assembly, a first transistor assembly, a second transistor assembly, a load and a third transistor assembly which are electrically connected. The generation module is used for generating alternating-current input voltage; the first transistor component and the second transistor component are configured to generate a direct current output voltage based on an alternating current input voltage; the load is configured to: obtain a DC output voltage; the control module is configured to control the idle switch assembly, the first transistor assembly, the second transistor assembly and the third transistor assembly to be turned on or turned off according to the direct current output voltage and a direct current output voltage reference level if the direct current output voltage is not in a target voltage interval, so that the direct current output voltage is in the target voltage interval; therefore, the output voltage values of a plurality of output ports can be simultaneously adjusted in the multi-output rectification circuit.

Description

Technical Field

[0001] The present application relates to the technical field of rectifier circuits, and in particular to a single-stage adjustable voltage rectifier system with multiple output full-wave rectification. Background Art

[0002] Wireless energy transfer technology has been widely used in current implantable biomedical devices, including cochlear, retinal and neural prostheses. In wireless energy transfer systems, power receivers with tens of milliwatts are usually preferred to provide power for multiple regulated power rails that support various functions. In order to achieve efficient power transfer in implanted devices, wireless charging systems are generally used to achieve the above purpose.

[0003] At present, the wireless charging system adopts a single-input multi-output rectifier circuit, which uses time-division multiplexing to supply power to different power output ports. When the supply voltage of the power output port reaches the required voltage of the load, the load connected to the power output port is charged, which realizes efficient power supply and can supply power to multiple power output ports.

[0004] However, during the application process, when the power supply voltage of some loads in multiple power output ports does not reach the required voltage, while the power supply voltage of some loads reaches the required voltage, the PMOS transistors corresponding to some output DC voltages in the rectifier circuit will not be turned on. If the subsequent rectifier circuit is still in the charging mode, the input voltage of the rectifier circuit will exceed the output voltage and the gate voltage of the PMOS transistor, causing the body diode of the PMOS transistor to be turned on, thereby causing the voltage regulation function of the rectifier circuit to fail or even be damaged; if the rectifier circuit is switched to the idling mode, it will not be able to normally supply power to the power output ports corresponding to the loads whose power supply voltage does not reach the required voltage, thereby limiting the output power and voltage regulation freedom of the rectifier circuit. Summary of the invention

[0005] The present application provides a single-stage adjustable voltage rectifier system with multi-output full-wave rectification to solve the technical problem that the output power of each power output port cannot be adjusted in the existing multi-output rectifier circuit.

[0006] The present application provides a single-stage adjustable voltage rectification system with multiple output full-wave rectification, comprising:

[0007] A rectifier and a control module, wherein the rectifier is communicatively connected with the control module;

[0008] The rectifier comprises: a generating module, an idling switch component, a first transistor component, a second transistor component, a load, and a third transistor component that are electrically connected; the generating module is connected in parallel with the idling switch component, the idling switch component and the load are connected in parallel with the first transistor component, the second transistor component, and the third transistor component, and the first transistor component, the second transistor component, and the third transistor component are connected in parallel;

[0009] The generating module is used to generate an AC input voltage;

[0010] The first transistor component, the second transistor component and the third transistor component are configured as follows:

[0011] Based on the AC input voltage, generating a DC output voltage;

[0012] The load is configured as:

[0013] Get the DC output voltage;

[0014] The control module is configured to:

[0015] Determine the DC output voltage reference level;

[0016] According to the DC output voltage reference level, obtaining a target voltage range;

[0017] If the DC output voltage is not within the target voltage range, the idle switch component, the first transistor component, the second transistor component, and the third transistor component are controlled to be turned on or off according to the DC output voltage and the DC output voltage reference level, so that the DC output voltage is within the target voltage range;

[0018] The third transistor component (7) is configured with at least one PMOS transistor or NMOS transistor; the number of the PMOS transistor or the NMOS transistor is determined by the number of the loads (6).

[0019] In some embodiments, the generating module comprises:

[0020] An electrically connected tapped coil, a first resonant capacitor, and a second resonant capacitor, wherein the tapped coil is connected in series with the first resonant capacitor and the second resonant capacitor, and the first resonant capacitor and the second resonant capacitor are connected in parallel with the tapped coil;

[0021] The idling switch assembly comprises:

[0022] A first idling switch and a second idling switch are electrically connected, wherein the first idling switch and the second idling switch are connected in series, the first idling switch and the first resonant capacitor are connected in parallel, and the second idling switch and the second resonant capacitor are connected in parallel.

[0023] In some embodiments, the first transistor component comprises:

[0024] a first PMOS transistor and a second PMOS transistor electrically connected;

[0025] The first PMOS transistor and the second PMOS transistor are in a cross-connection structure.

[0026] In some embodiments, the second transistor component comprises:

[0027] A first NMOS transistor, a second NMOS transistor, a first comparator, and a second comparator are electrically connected, wherein the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected in parallel, the first NMOS transistor is connected in series with the first comparator, and the second NMOS transistor is connected in series with the second comparator;

[0028] The first NMOS transistor and the second NMOS transistor are active diode structures.

[0029] In some embodiments, the load includes:

[0030] An electrically connected load voltage-stabilizing capacitor, a load resistor, and a load component, wherein the load voltage-stabilizing capacitor, the load resistor, and the load component are connected in parallel, and the load component is configured with a plurality of load voltage-stabilizing capacitors and load resistors;

[0031] The first load stabilizing capacitor is configured as:

[0032] Obtaining a first DC output voltage;

[0033] The load assembly is configured as:

[0034] A second DC output voltage is obtained.

[0035] In some embodiments, the control module is further configured to:

[0036] Obtaining a load current according to the second DC output voltage;

[0037] Based on the load current, obtaining a load state of the load current; the load state includes: a light load state and a heavy load state;

[0038] If the load current is in a light load state, controlling the idle switch component, the first transistor component, the second transistor component, and the third transistor component to be turned on or off, so that the first DC output voltage is within a first target voltage range, and the second DC output voltage is within a second target voltage range;

[0039] If the load current is in a heavy load state, the first PMOS transistor and the third transistor component are controlled to be turned on, so that the first DC output voltage is within a first target voltage range and the second DC output voltage is within a second target voltage range.

[0040] In some embodiments, the control module is further configured to:

[0041] When the load current is in a light load state, if the first DC output voltage is less than a first DC output voltage reference level, and the second DC output voltage is less than a second DC output voltage reference level, the first PMOS transistor, the second NMOS transistor, and the third transistor component are controlled to be turned on, so that the first DC output voltage is within a first target voltage range, and the second DC output voltage is within a second target voltage range;

[0042] If the first DC output voltage is less than a first DC output voltage reference level and the second DC output voltage is greater than a second DC output voltage reference level, controlling the first PMOS transistor and the second NMOS transistor to be turned on so that the first DC output voltage is within a first target voltage range and the second DC output voltage is within a second target voltage range;

[0043] If the first DC output voltage is greater than a first DC output voltage reference level and the second DC output voltage is greater than a second DC output voltage reference level, the idling switch component is controlled to open so that the first DC output voltage is within a first target voltage range and the second DC output voltage is within a second target voltage range.

[0044] In some embodiments, the control module includes:

[0045] An electrically connected first hysteresis comparator, a second hysteresis comparator, a third hysteresis comparator, a D flip-flop component, a logic gate component, an inverter chain delay circuit, and an inverter component;

[0046] The first hysteresis comparator is used to obtain a first comparison result according to the first DC output voltage and the first DC output voltage reference level;

[0047] The second hysteresis comparator is used for obtaining a second comparison result according to the second DC output voltage and the second DC output voltage reference level;

[0048] The third hysteresis comparator is configured as:

[0049] Based on the second DC output voltage reference level, obtaining a reference voltage;

[0050] Obtaining a third comparison result according to the second DC output voltage and the reference voltage;

[0051] The logic gate component is used to generate a trigger signal according to the first comparison result, the second comparison result, and the third comparison result; the trigger signal is used to control the idling switch component, the first transistor component, the second transistor component, and the third transistor component to be turned on or off, so that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the second target voltage range.

[0052] In some embodiments, the control module is further configured to:

[0053] If the load current is in a heavy load state, the first PMOS transistor and the third transistor component are controlled to be turned on, so that the first DC output voltage is within a first target voltage range and the second DC output voltage is within a third target voltage range; the third target voltage range is obtained by the reference voltage and the second DC output voltage reference level.

[0054] In some embodiments, the first comparator and the second comparator include:

[0055] Electrically connected PMOS transistor components and NMOS transistor components;

[0056] Among them, when the value of the signal to be compared input by the first comparator or the second comparator is greater than the positive value of the power supply voltage of the first comparator or the second comparator, the first comparator or the second comparator outputs a low level; when the value of the signal to be compared input by the first comparator or the second comparator is less than or equal to the positive value of the power supply voltage of the first comparator or the second comparator, the first comparator or the second comparator outputs a high level.

[0057] The present application provides a single-stage adjustable voltage rectifier system with multi-output full-wave rectification, comprising: a rectifier and a control module, wherein the rectifier is communicatively connected to the control module; the rectifier comprises: an electrically connected generating module, an idle switch component, a first transistor component, a second transistor component, a load, and a third transistor component; the generating module is connected in parallel with the idle switch component, the idle switch component and the load are connected in parallel with the first transistor component and the second transistor component, and the first transistor component and the second transistor component are connected in parallel; the generating module is used to generate an AC input voltage; the first transistor component and the second transistor component are configured as : Based on the AC input voltage, a DC output voltage is generated; the load is configured to: obtain the DC output voltage; the control module is configured to: obtain a DC output voltage reference level; according to the DC output voltage reference level, a target voltage range is obtained; if the DC output voltage is not within the target voltage range, then according to the DC output voltage and the DC output voltage reference level, the free-wheeling switch component, the first transistor component, the second transistor component, and the third transistor component are controlled to be turned on or off, so that the DC output voltage is within the target voltage range, so as to realize that the output voltage values ​​of multiple output ports can be adjusted simultaneously in the multi-output rectifier circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0059] Figure 1 This is a first schematic diagram of the structure of a single-stage adjustable voltage rectifier system with multiple output full-wave rectification in the present application;

[0060] Figure 2 A second schematic diagram of the structure of a single-stage adjustable voltage rectifier system with multiple output full-wave rectification in the present application;

[0061] Figure 3 It is a structural diagram of the control module in this application;

[0062] Figure 4 is a schematic diagram of the structure of the first comparator and the second comparator in this application;

[0063] Figure 5 It is a structural diagram of the current wireless charging system;

[0064] Figure 6 It is a structural diagram of the current single-input multiple-output rectifier circuit;

[0065] Figure 7This is a schematic diagram of the structure of the rectifier circuit in the present application when it is in a double-side charging mode;

[0066] Figure 8 This is a schematic diagram of the structure when the rectifier circuit in this application is in high-side charging mode;

[0067] Fig. 9 This is a schematic diagram of the structure of the rectifier circuit in the present application when it is in an idling mode;

[0068] Fig.10 It is a structural schematic diagram of the rectifier circuit in the present application when it is in the charge distribution mode;

[0069] Fig.11 It is a schematic diagram of the transient switching performance of the rectifier circuit when there is no charge distribution mode in this application;

[0070] Fig.12 It is a schematic diagram of transient switching performance of the rectifier circuit when there is a charge distribution mode in this application;

[0071] Fig.13 Schematic waveform of input and output voltage when the rectifier circuit in this application is in double-side charging mode;

[0072] Fig.14 The input and output voltages and NMOS gate voltage test waveforms of the rectifier circuit under the first load condition in this application;

[0073] Fig.15 The input and output voltages and NMOS gate voltage test waveforms of the rectifier circuit under the second load condition in the present application;

[0074] Fig.16 The input and output voltages and NMOS gate voltage test waveforms of the rectifier circuit under the third load condition in this application;

[0075] Fig.17 The input and output voltages and NMOS gate voltage test waveforms of the rectifier circuit under the fourth load condition in the present application;

[0076] Fig.18 This is a first schematic diagram of two-way output voltage waveforms and load switching signals of the rectifier circuit in the present application when a load current suddenly changes;

[0077] Fig.19 A second schematic diagram of two-way output voltage waveforms and load switching signals of the rectifier circuit in the present application when a load current suddenly changes;

[0078] Fig. 20 This is a test diagram of the efficiency of the rectifier circuit in this application under different load sizes.

[0079] Description of reference numerals:

[0080] 1-control module; 11-first hysteresis comparator; 12-second hysteresis comparator; 13-third hysteresis comparator; 14-D flip-flop component; 15-logic gate component; 16-inverter chain delay circuit; 17-inverter component; 2-generation module; 21-tap coil; 22-first resonant capacitor; 23-second resonant capacitor; 3-idle switch component; 31-first idling switch; 32-second idling switch; 4-first transistor component; 41-first PMOS transistor; 42-second PMOS transistor; 5-second transistor component; 51-first NMOS transistor; 52-second NMOS transistor; 53-first comparator; 54-second comparator; 541-PMOS transistor component; 542-NMOS transistor component; 6-load; 61-load stabilizing capacitor; 62-load resistor; 63-load component; 7-third transistor component. DETAILED DESCRIPTION

[0081] In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application.

[0082] Since in some technologies, the output power of each power output port cannot be adjusted in a multi-output rectifier circuit, in order to solve this technical problem, the present application provides a single-stage adjustable voltage rectifier system with multi-output full-wave rectification. The structures of the various parts of the single-stage adjustable voltage rectifier system with multi-output full-wave rectification are described below:

[0083] For example, the basic structure of the currently used wireless charging system is as follows: Figure 5 As shown, the transmitting end passes through the coil L 1 The alternating current on the receiving end generates an alternating magnetic field. 2 The alternating magnetic field generates an alternating current, which flows through the capacitor C. 2 Generates AC voltage V AC1 、V AC2 Since all electrical equipment needs to be powered by DC voltage, the AC voltage also needs to be converted into DC voltage through a rectifier circuit. The DC voltage V obtained by the rectifier REC The voltage will change with the input voltage and cannot be used directly. It needs to be converted into multiple stable DC voltages that do not change with the input voltage through a subsequent single-input and multiple-output DC-DC circuit (DC-DC circuit).

[0084] Exemplarily, the current rectifier circuit has the following requirements:

[0085] Voltage stabilization requirement: In biomedical wireless energy transmission systems, the relative position change between the transmitting coil (TX) and the receiving coil (RX) often causes fluctuations in the coupling coefficient. This volatility will directly affect the voltage conversion ratio of the entire energy transmission link, and then lead to unstable voltage at the RX end. Because the RX circuit needs to continuously provide a stable DC power supply voltage for each functional module in the biomedical device, the rectifier circuit needs to have the performance of voltage stabilization and voltage regulation.

[0086] Multiple output requirements: As the technology of biomedical devices advances, these devices often require multiple independent power supply voltages to drive different functional modules, such as analog amplifiers, digital logic units, memories, etc. This requirement further increases the complexity of RX circuit design. Traditional RX circuit design includes a rectifier and multiple DC-DC converters (DC-DC converters), which are responsible for converting AC power into DC power to meet the device's needs for power stability and multiple voltage outputs. The DC-DC converter provides an adjustable DC output.

[0087] To achieve the above voltage regulation and multi-output requirements, the current approach is to combine a full-bridge rectifier (FBR) with multiple low-dropout regulators (LDOs), which requires a high-power voltage to be output from the TX end to compensate for different link conditions. At the same time, the required multi-stage structure and additional components inevitably lead to cascade power losses and increase the size and cost of the system. In order to address the limitations of the above multi-stage structure, a single-stage multi-output voltage regulator can be introduced for voltage rectification and regulation to avoid cascade efficiency losses.

[0088] For example, the current single-input multiple-output rectifier circuit is as follows: Figure 6 As shown, V SS (the negative terminal of the comparator supply voltage) is selectively connected to V through a cross-coupled NMOS. AC1 or V AC2 (voltage across the inductor), and different output terminals V OUT1 and V OUT2 The PMOS with active diode structure driven by the comparator is connected to V at different times. AC2 or V AC1 When V AC1 When it is high level, M N2 On, V AC2 is connected to V SS , through the logic circuit control, you can choose M P1 or M P3Enable (cannot be enabled at the same time), if you select M P1 Turn on, then V AC1 Connect to V OUT1 At this time, the rectifier circuit controls the inductor current to V OUT1 Charging; if you select M P3 Turn on, then V AC1 Connect to V OUT2 At this time, the rectifier circuit controls the inductor current to V OUT2 Charging; if V OUT1 and V OUT2 If the voltage is equal to the specified value, then M P1 and M P3 Both are not turned on. At this time, the switch connected in parallel at both ends of the inductor will be closed, and V AC1 and V AC2 Short circuit, the system enters the idling mode to realize the voltage regulation function of the rectifier circuit.

[0089] The current single-input multiple-output rectifier circuit has the following problems:

[0090] 1. The NMOS in the rectifier circuit uses a cross-connection structure, while the PMOS uses an active diode structure. The driving loss of the cross-connection structure NMOS tube is very low. Since the electron mobility of PMOS is lower than that of NMOS, under the same on-resistance, the size and gate parasitic capacitance of NMOS are much smaller than those of PMOS.

[0091] 2. The rectifier circuit uses multiplexing to supply power to different power output ports. When the power supply voltage of the power output port reaches the required voltage of the load, the load connected to the power output port is charged, which realizes efficient power supply and can supply power to multiple power output ports. However, during the application process, when the power supply voltage of some loads in multiple power output ports does not reach the required voltage, and the power supply voltage of some loads reaches the required voltage, the PMOS transistors corresponding to some output DC voltages in the rectifier circuit are not turned on. If the subsequent rectifier circuit is still in the charging mode, the input voltage of the rectifier circuit will exceed the output voltage and the gate voltage of the PMOS transistor, causing the body diode of the PMOS transistor to be turned on, thereby causing the voltage stabilization function of the rectifier circuit to fail or even be damaged; if the rectifier circuit is switched to the idling mode, it will not be able to supply power normally to the power output port corresponding to the load whose power supply voltage does not reach the required voltage, which limits the output power size and the freedom of voltage regulation of the rectifier circuit.

[0092] 3. The rectifier circuit can only be charged once in one cycle, which is half-wave rectification. Under the same conditions, the output ripple of half-wave rectification is twice that of full-wave rectification. Full-wave rectification and half-wave rectification are two basic methods of converting alternating current (AC) to direct current (DC). Half-wave rectification is a simple rectification method that uses only one diode to rectify the positive half-cycle of the alternating current and ignores the negative half-cycle. This means that in each AC cycle, the output voltage is only generated half of the time, resulting in a large pulsating component in the output DC voltage. The efficiency of half-wave rectification is low because all cycles of the alternating current are not fully utilized. Full-wave rectification uses two or four diodes to rectify the positive and negative half-cycles of the alternating current. In full-wave rectification, regardless of whether the alternating current is in the positive half-cycle or the negative half-cycle, the output is a positive DC voltage, which can more effectively utilize the AC power supply. The output DC voltage of full-wave rectification has less pulsation, so it is more stable and efficient than half-wave rectification. In general, full-wave rectification has the following advantages over half-wave rectification: Higher rectification efficiency because the entire cycle of the alternating current is utilized. The output DC voltage has smaller pulsations, so the power quality is better, which is suitable for applications with higher power and can provide a more stable DC power supply.

[0093] Depend on Figure 1 It can be seen that in response to the above problems, the present application provides a single-stage adjustable voltage rectifier system with multiple output full-wave rectification, including: a rectifier and a control module 1, wherein the rectifier is communicatively connected to the control module 1; the control module 1 can receive the charging voltage V out1 and V out2; The rectifier is used to convert AC voltage into DC voltage; the rectifier includes: an electrically connected generating module 2, an idling switch component 3, a first transistor component 4, a second transistor component 5, a load 6, and a third transistor component 7; the generating module 2 is connected in parallel with the idling switch component 3, the idling switch component 3 and the load 6 are connected in parallel with the first transistor component 4 and the second transistor component 5, and the first transistor component 4 is connected in parallel with the second transistor component 5 and the third transistor component 7; the generating module 2 is used to generate an AC input voltage; the specific method of generating the AC input voltage can be referred to the above-mentioned wireless charging system embodiment, which will not be repeated here; the first transistor component 4, the second transistor component 5, and the third transistor component 7 are connected in parallel; The transistor assembly 5 and the third transistor assembly 7 are configured to generate a DC output voltage based on the AC input voltage; the first transistor assembly 4 includes: a plurality of PMOS transistors, and the second transistor assembly 5 includes: a plurality of NMOS transistors; the load 6 is configured to obtain a DC output voltage; the load 6 includes: a plurality of loads, and the loads are charged through a rectifier; the control module 1 is configured to determine a DC output voltage reference level; the DC output voltage reference level is input by the user outside, for example: if the user wants to charge one of the loads 6 to 1.5V, then the value to be charged, that is, the DC output voltage reference level, is input to the control module 1, corresponding to Figure 3 Medium V REF1 and V REF2 ; According to the DC output voltage reference level, a target voltage interval is obtained; when the corresponding load in the load 6 is charged to the corresponding interval, it means that the charging is completed, and the target voltage interval is obtained according to the charge capture capability of the load, that is, when the voltage is in the target voltage interval, it can meet the charging voltage requirement of the load; if the DC output voltage is not within the target voltage interval, then according to the DC output voltage and the DC output voltage reference level, the idling switch component 3, the first transistor component 4, the second transistor component 5, and the third transistor component 7 are controlled to be turned on or off, so that the DC output voltage is within the target voltage interval; wherein, the third transistor component 7 is configured with at least one PMOS transistor or NMOS transistor; the number of the PMOS transistors or the NMOS transistors is determined by the number of the loads 6.

[0094] Exemplarily, each of the third transistor components 7 is configured with a PMOS transistor or an NMOS transistor, and one more load is provided in the load 6 of the system and connected to the corresponding PMOS transistor or NMOS transistor. It can be understood that the single-stage adjustable voltage rectifier system with multi-output full-wave rectification provided in the present application can be connected to several loads.

[0095] The present application provides a single-stage adjustable voltage rectifier system with multi-output full-wave rectification, which obtains the load voltage, i.e., the DC output voltage, in real time through a control module 1, and controls which components of the idling switch component 3, the first transistor component 4, and the second transistor component 5 are turned on by judging the size relationship between the DC output voltage of the load and the voltage to be charged of the load, i.e., the DC output voltage reference level, so as to realize a rectification circuit that can select which components in the rectifier to be turned on according to each load voltage, so that each load voltage is within a target voltage range, thereby completing the power supply work of multiple power output ports of the rectification circuit.

[0096] Depend on Figure 2 It can be seen that the generating module 2 includes: a tapped coil 21, a first resonant capacitor 22, and a second resonant capacitor 23 that are electrically connected, the tapped coil 21 is connected in series with the first resonant capacitor 22 and the second resonant capacitor 23, the first resonant capacitor 22 and the second resonant capacitor 23 are connected in parallel with the tapped coil 21; the tapped coil 21, the first resonant capacitor 22, and the second resonant capacitor 23 correspond to Figure 2 Middle tap coil L R , the first resonant capacitor C R1 , the second resonant capacitor C R2 Among them, the tap of the tapped coil 21 is connected to the position where the first resonant capacitor 22 and the second resonant capacitor 23 are connected in series, and the current is drawn out through the coil tap to charge the lower voltage on the side, avoiding different outputs from squeezing out each other's charging time, improving the maximum output power while ensuring a low cross-regulation rate.

[0097] The idling switch assembly 3 includes: a first idling switch 31 and a second idling switch 32 which are electrically connected, wherein the first idling switch 31 and the second idling switch 32 are connected in series, the first idling switch 31 and the first resonant capacitor 22 are connected in parallel, and the second idling switch 32 and the second resonant capacitor 23 are connected in parallel. Figure 2 The first idle switch S 1 , Second idling switch S 2 .

[0098] Depend on Figure 2 It can be seen that the first transistor component 4 includes: a first PMOS transistor 41 and a second PMOS transistor 42 that are electrically connected; the first PMOS transistor 41 and the second PMOS transistor 42 are cross-connected. The first PMOS transistor 41 and the second PMOS transistor 42 correspond to Figure 2 The first PMOS transistor M P1 , the second PMOS transistor M P2In the rectifier circuit, the PMOS uses a cross-voltage regulation structure, which results in lower driving loss and higher overall efficiency.

[0099] Depend on Figure 2 It can be seen that the second transistor component 5 includes: a first NMOS transistor 51, a second NMOS transistor 52, a first comparator 53, and a second comparator 54 that are electrically connected, the first NMOS transistor 51 and the second NMOS transistor 52 are connected in parallel, the first NMOS transistor 51 and the first comparator 53 are connected in series, and the second NMOS transistor 52 and the second comparator 54 are connected in series; the first NMOS transistor 51 and the second NMOS transistor 52 correspond to Figure 2 The first NMOS transistor M N1 , the second NMOS transistor M N2 The first NMOS transistor 51 and the second NMOS transistor 52 are active diode structures. In the rectifier circuit, the driving loss of the overall circuit using the active diode structure of NMOS is lower and the overall efficiency is higher.

[0100] Depend on Figure 2 It can be seen that the load 6 includes: a load voltage-stabilizing capacitor 61, a load resistor 62, and a load component 63 that are electrically connected. The load voltage-stabilizing capacitor 61, the load resistor 62, and the load component 63 are connected in parallel. The load component 63 is configured with a plurality of load voltage-stabilizing capacitors and load resistors. The load voltage-stabilizing capacitor 61, the load resistor 62, and the load component 63 correspond to Figure 2 Medium load stabilizing capacitor C 1 , load resistance R 1 The load stabilizing capacitor 61 is configured to obtain a first DC output voltage; the load component 63 is configured to obtain a second DC output voltage. The load 6 is a load. It is worth noting that two loads are used for illustration in the embodiment of the present application. The rectifier provided by the present application can be connected to multiple loads and a corresponding number of NMOS transistors and PMOS transistors can be connected.

[0101] In this embodiment, the control module 1 is further configured to: obtain a load current according to the second DC output voltage; obtain a load state of the load current based on the load current; the load state includes: a light load state and a heavy load state; the light load state and the heavy load state are the load capacity of the rectifier circuit, wherein the light load state represents that the load rate of the circuit is less than the load rate of the circuit under the full load state, and the heavy load state represents that the load rate of the circuit is greater than the load rate of the circuit under the full load state; if the load current is a light load state, control the idle switch component 3, the first transistor component 4, the second transistor component 5, and the third transistor component 7 to be turned on or off, so that the first DC output voltage is within the first target voltage range, and the second DC output voltage is within the second target voltage range; if the load current is a heavy load state, control the first PMOS transistor 41 and the third transistor component 7 to be turned on, so that the first DC output voltage is within the first target voltage range, and the second DC output voltage is within the second target voltage range, corresponding to Fig.10 The working mode of the rectifier is: charge distribution mode.

[0102] In this embodiment, the control module 1 is further configured to: when the load current is in a light load state, if the first DC output voltage is less than a first DC output voltage reference level, and the second DC output voltage is less than a second DC output voltage reference level, control the first PMOS transistor 41, the second NMOS transistor 52, and the third transistor component 7 to turn on, so that the first DC output voltage is within a first target voltage range, and the second DC output voltage is within a second target voltage range; correspondingly Figure 7 The working mode of the rectifier is: double-side charging mode; if the first DC output voltage is less than the first DC output voltage reference level, and the second DC output voltage is greater than the second DC output voltage reference level, the first PMOS transistor 41 and the second NMOS transistor 52 are controlled to be turned on, so that the first DC output voltage is within the first target voltage range, and the second DC output voltage is within the second target voltage range; corresponding Figure 8 The working mode of the middle rectifier is: high-side charging mode; if the first DC output voltage is greater than the first DC output voltage reference level, and the second DC output voltage is greater than the second DC output voltage reference level, the freewheeling switch component 3 is controlled to be turned on, so that the first DC output voltage is within the first target voltage range, and the second DC output voltage is within the second target voltage range. Fig. 9 The working mode of the medium rectifier is: idling mode.

[0103] Exemplarily, the rectifier can be configured in four operating modes: double-side charging mode, high-side charging mode, idling mode, and charge sharing mode. The selectable mode depends on the load current at VOUT2 (I 2 ) condition. 2 When under light load, the rectifier operates in double-side charging mode, high-side charging mode, and idling mode.

[0104] Taking half a cycle as an example, in the double-side charging mode, M N2 、M N3 and M P1 In the on state. V OUT1 and V OUT2 The current I AC1 / I AC2 and I AC3 During the half cycle, both loads are charged simultaneously, so the load voltage corresponding to both loads will increase. In high-side charging mode, M N2 and M P1 In the open state, only V OUT1 By I AC1 / I AC2 In idling mode, turn on S 1 and S 2 , V OUT1 and V OUT2 The controller detects V OUT1 and V OUT2 voltage level, producing the corresponding logic state, V OUT1 and V OUT2 Adjust to the hysteresis window [V REF1L , V REF1H ] and [V REF2L , V REF2H ] That is, within the first target voltage interval and the second target voltage interval. During the entire regulation period, the power loss of the rectifier is mainly controlled by the active diode. Compared with the current rectifier structure, the present application uses NMOS instead of PMOS to implement the structure of the active diode, and its number is reduced to three, thereby reducing power loss and higher rectification circuit efficiency, and saving the chip area of ​​the rectifier chip.

[0105] It is worth noting that in the embodiment of the present application, two PMOS transistors are provided, namely, a first PMOS transistor 41 and a second PMOS transistor 42. During the operation of the rectifier, one PMOS transistor is turned on for each half cycle, that is, the rectifier is charged twice in one cycle for full-wave rectification. Fig.13 As shown. Full-wave rectification has the following advantages over half-wave rectification (charging once per cycle): Higher rectification efficiency. Smaller pulsation of the output DC voltage, so the power quality is better. It is suitable for applications with higher power and can provide a more stable DC power supply.

[0106] For example, when I 2When switching to heavy load state, the working mode of the rectifier is converted to charge distribution mode, such as Fig.10 As shown, M N3 and M P1 is in the open state. 2 Switching to heavy load state, voltage regulation (especially V OUT2 ) becomes very challenging. The worst case occurs in idling mode, when V OUT1 and V OUT2 are decreasing. Fig.11 As shown, due to I 2 Switching from light load to heavy load, V OUT2 Start descending along a faster path, reaching V first REF2L That is, it is at the minimum value in the second target voltage range. However, the above situation cannot trigger the double-side charging mode, otherwise V AC1 and V AC2 will increase significantly, thereby P1 and M P2 The body diode to V OUT1 Unnecessary charging is performed. Until V OUT1 Reach V REF1L That is, it is at the minimum value in the first target voltage range, and the idling mode will stop. Therefore, it is impossible to avoid V OUT2 On the other hand, through the proposed charge distribution mode and another reference voltage (V CD ) together. Fig.12 As shown, when V OUT2 Arrival V CD When V OUT2 stops decreasing and starts increasing. In addition, at the end of the double-side charging mode, by turning off M N2 , from V OUT1 To V OUT2 A current path appears and the proposed charge sharing mode is started. Through this current path, in the double-side charging mode, V OUT1 The charge accumulated at V OUT2 The problem of insufficient charging current is solved. The duration of the charge distribution mode (T CD ) to maintain M P1 The high gate-source voltage provides a small M P1 After several cycles, V OUT2 Arrival V REF2H That is, it is at the maximum value within the second target voltage interval, triggering the idling mode. Therefore, the proposed charge distribution mode eliminates the large V OUT2 voltage drop and successfully turns V OUT2 Adjustment within the hysteresis window [VCD , V REF2H ] That is, within the third target voltage range.

[0107] Depend on Figure 3 It can be seen that the control module 1 includes: a first hysteresis comparator 11, a second hysteresis comparator 12, a third hysteresis comparator 13, a D flip-flop component 14, a logic gate component 15, an inverter chain delay circuit 16, and an inverter component 17 that are electrically connected; the logic gate component 15 includes: a NOR gate, an AND gate, or a gate; the first hysteresis comparator 11 is used to generate a voltage according to the first DC output voltage V OUT1 , the first DC output voltage reference level V REF1 , and obtain a first comparison result; the second hysteresis comparator 12 is used to output the second DC output voltage V OUT2 , the second DC output voltage reference level V REF2 , obtain a second comparison result; the third hysteresis comparator 11 is configured to: based on the second DC output voltage reference level V REF2 , get the reference voltage V CD According to the second DC output voltage V REF2 , reference voltage V CD , and obtain a third comparison result; the logic gate component 15 is used to generate a trigger signal according to the first comparison result, the second comparison result, and the third comparison result; the trigger signal is used to control the idling switch component 3, the first transistor component 4, the second transistor component 5, and the third transistor component 7 to turn on or off, so that the first DC output voltage is within the first target voltage range, and the second DC output voltage is within the second target voltage range. The above-mentioned logic gate component 15 is used to generate a trigger signal according to the first comparison result, the second comparison result, and the third comparison result, and control the idling switch component 3, the first transistor component 4, and the second transistor component 5 to turn on or off. The specific process can be referred to the four working mode embodiments of the above-mentioned rectifier configuration, which will not be repeated here. Among them, G CD Represents the charge distribution mode trigger signal, which is used to control the rectifier to enter four working modes; G OFF The gate signal representing the idling mode switch is used to control the idling switch assembly 3 to close.

[0108] In this embodiment, the control module 1 is further configured to: if the load current is in a heavy load state, control the first PMOS transistor 41 and the third NMOS transistor 53 to be turned on, so that the first DC output voltage is within a first target voltage range, and the second DC output voltage is within a third target voltage range [V CD , V REF2H]; the third target voltage interval is obtained by the reference voltage and the second DC output voltage reference level. The effect of setting the third target voltage interval can refer to the effect of the above-mentioned charge distribution mode, which will not be repeated here.

[0109] Depend on Figure 4 It can be known that the first comparator 53 and the second comparator 54 include: a PMOS transistor component 541 and an NMOS transistor component 542 electrically connected; wherein, when the value of the signal to be compared inputted by the first comparator 53 or the second comparator 54 is greater than the positive value of the supply voltage of the first comparator 53 or the second comparator 54, the first comparator 53 or the second comparator 54 outputs a low level; when the value of the signal to be compared inputted by the first comparator 53 or the second comparator 54 is less than or equal to the positive value of the supply voltage of the first comparator 53 or the second comparator 54, the first comparator 53 or the second comparator 54 outputs a high level. Wherein, V IN Represents the signal to be compared at the comparator input, V DD Represents the positive supply voltage of the comparator, V B Represents the gate bias voltage of the NMOS transistor, V SS Represents the negative supply voltage of the comparator, V OUT Represents the output voltage of the comparator. The working principle of the first comparator 53 and the second comparator 54 is as follows: first, the two input terminals of the comparator receive analog signals; second, in the comparison stage, the two input signals are compared with a reference voltage (or another input signal); if the difference between the input signals exceeds a certain threshold (also called a trigger level), the output state of the comparator will change; finally, the comparator outputs a binary signal, usually represented as a high level or a low level; the output signal reflects the magnitude relationship between the input signal and the reference voltage (or another input signal).

[0110] For example, the rectifier chip adopts 180nm complementary metal oxide semiconductor (CMOS) process, and the chip area is 1.63mm 2 . V OUT1 and V OUT2 Maximum load current I 1 and I 2 33mA and 15mA respectively, the maximum P OUT The external resonant capacitor C R1 and C R2 Both are 500pF, and the external output capacitor C OUT1 and C OUT2 150nF and 200nF respectively.

[0111] For example, Figures 14 to 17 The steady-state performance test diagram of the rectifier shows the input and output voltages of the rectifier circuit and the NMOS gate voltage test waveforms under different load conditions. 1 and I 2 Under different light / heavy load combinations, V OUT1 and V OUT2 They are successfully regulated to 3.3V and 1.6V within the corresponding hysteresis windows. Figures 14 to 17 It can be seen that V OUT1 The maximum ripple and V OUT2 The maximum ripple of G is as small as 50mV and 75mV respectively. N1 , G N2 and G N3 It reflects the four working modes of the rectifier. N1 , G N2 and G N3 When both are high level, it is double-side charging mode; G N1 and G N2 When it is high level, G N3 When it is low level, it is high side charging mode; G N1 , G N2 and G N3 When both are low level, it is idle mode; G N1 and G N2 When it is low level, G N3 When it is high, it is charge sharing mode.

[0112] For example, Figure 18 to Figure 19 The figure is a schematic diagram of the transient performance test of the rectifier, showing the two-way output voltage waveform and load switching signal of the rectifier circuit when the load current suddenly changes; it reflects the negligible load transient response and the inconspicuous cross-regulation output between the two. 2 in I 1 When changing from 1mA to 15mA at 33mA, a negligible voltage drop is achieved in case of load switching due to the proposed charge sharing scheme.

[0113] For example, Fig. 20 In order to measure the efficiency of the rectifier circuit under different load sizes, the PMOS active diode is replaced by an NMOS active diode and the number of high-power transistors is reduced to 3. 2 When the current of the proposed rectifier is equal to 1mA, the current of the proposed rectifier is OUT The maximum energy conversion efficiency was 92.2% at 72.6 mW. 2 When the current is equal to 15mA, the rectifier circuit maintains an efficiency of more than 80%, and the maximum energy conversion efficiency is 89.9%.

[0114] The above specific implementation methods further explain in detail the purpose, technical solutions and beneficial effects of the embodiments of the present application. It should be understood that the above are only specific implementation methods of the embodiments of the present application and are not used to limit the protection scope of the embodiments of the present application. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solutions of the embodiments of the present application should be included in the protection scope of the embodiments of the present application.

Claims

1. A single-stage adjustable voltage rectifier system with multiple output full-wave rectification, characterized in that: include: A rectifier and a control module (1), the rectifier being communicatively connected to the control module (1); The rectifier comprises: an electrically connected generating module (2), an idling switch component (3), a first transistor component (4), a second transistor component (5), a load (6), and a third transistor component (7); the generating module (2) is connected in parallel with the idling switch component (3); the idling switch component (3) and the load (6) are connected in parallel with the first transistor component (4), the second transistor component (5), and the third transistor component (7); and the first transistor component (4), the second transistor component (5), and the third transistor component (7) are connected in parallel; The generating module (2) is used to generate an AC input voltage; The first transistor component (4), the second transistor component (5), and the third transistor component (7) are configured as follows: Based on the AC input voltage, generating a DC output voltage; The load (6) is configured as: Get the DC output voltage; The control module (1) is configured as follows: Determine the DC output voltage reference level; According to the DC output voltage reference level, obtaining a target voltage range; If the DC output voltage is not within the target voltage range, the idle switch component (3), the first transistor component (4), the second transistor component (5), and the third transistor component (7) are controlled to be turned on or off according to the DC output voltage and the DC output voltage reference level, so that the DC output voltage is within the target voltage range; The third transistor component (7) is configured with at least one PMOS transistor or NMOS transistor; the number of the PMOS transistor or the NMOS transistor is determined by the number of the loads (6).

2. A single-stage adjustable voltage rectifier system with multiple outputs and full-wave rectification according to claim 1, characterized in that: The generating module (2) comprises: A tapped coil (21), a first resonant capacitor (22), and a second resonant capacitor (23) are electrically connected, the tapped coil (21) being connected in series with the first resonant capacitor (22) and the second resonant capacitor (23), and the first resonant capacitor (22), the second resonant capacitor (23) being connected in parallel with the tapped coil (21); The idling switch assembly (3) comprises: A first idling switch (31) and a second idling switch (32) are electrically connected, wherein the first idling switch (31) and the second idling switch (32) are connected in series, the first idling switch (31) and the first resonant capacitor (22) are connected in parallel, and the second idling switch (32) and the second resonant capacitor (23) are connected in parallel.

3. The single-stage adjustable voltage rectifier system with multiple outputs and full-wave rectification according to claim 1, characterized in that: The first transistor component (4) comprises: A first PMOS transistor (41) and a second PMOS transistor (42) electrically connected; The first PMOS transistor (41) and the second PMOS transistor (42) are in a cross-connection structure.

4. A multi-output full-wave rectifier single-stage adjustable voltage rectifier system according to claim 3, characterized in that: The second transistor component (5) comprises: A first NMOS transistor (51), a second NMOS transistor (52), a first comparator (53), and a second comparator (54) are electrically connected, wherein the first NMOS transistor (51) and the second NMOS transistor (52) are connected in parallel, the first NMOS transistor (51) and the first comparator (53) are connected in series, and the second NMOS transistor (52) and the second comparator (54) are connected in series; The first NMOS transistor (51) and the second NMOS transistor (52) are active diode structures.

5. A single-stage adjustable voltage rectifier system with multiple outputs and full-wave rectification according to claim 4, characterized in that: The load (6) comprises: An electrically connected load voltage-stabilizing capacitor (61), a load resistor (62), and a load component (63), wherein the load voltage-stabilizing capacitor (61), the load resistor (62), and the load component (63) are connected in parallel, and the load component (63) is configured with a plurality of load voltage-stabilizing capacitors and load resistors; The load stabilizing capacitor (61) is configured as: Obtaining a first DC output voltage; The load assembly (63) is configured as follows: A second DC output voltage is obtained.

6. A multi-output full-wave rectifier single-stage adjustable voltage rectifier system according to claim 5, characterized in that: The control module (1) is further configured to: Obtaining a load current according to the second DC output voltage; Based on the load current, obtaining a load state of the load current; the load state includes: a light load state and a heavy load state; If the load current is in a light load state, the idle switch component (3), the first transistor component (4), the second transistor component (5), and the third transistor component (7) are controlled to be turned on or off, so that the first DC output voltage is within a first target voltage range, and the second DC output voltage is within a second target voltage range; If the load current is in a heavy load state, the first PMOS transistor (41) and the third transistor component (7) are controlled to be turned on, so that the first DC output voltage is within a first target voltage range and the second DC output voltage is within a second target voltage range.

7. A single-stage adjustable voltage rectifier system with multiple outputs and full-wave rectification according to claim 6, characterized in that: The control module (1) is further configured to: When the load current is in a light load state, if the first DC output voltage is less than a first DC output voltage reference level, and the second DC output voltage is less than a second DC output voltage reference level, the first PMOS transistor (41), the second NMOS transistor (52), and the third transistor component (7) are controlled to be turned on, so that the first DC output voltage is within a first target voltage range, and the second DC output voltage is within a second target voltage range; If the first DC output voltage is less than a first DC output voltage reference level and the second DC output voltage is greater than a second DC output voltage reference level, the first PMOS transistor (41) and the second NMOS transistor (52) are controlled to be turned on, so that the first DC output voltage is within a first target voltage range and the second DC output voltage is within a second target voltage range; If the first DC output voltage is greater than a first DC output voltage reference level and the second DC output voltage is greater than a second DC output voltage reference level, the free-wheeling switch component (3) is controlled to be turned on so that the first DC output voltage is within a first target voltage range and the second DC output voltage is within a second target voltage range.

8. The single-stage adjustable voltage rectifier system with multiple outputs and full-wave rectification according to claim 7, characterized in that: The control module (1) comprises: A first hysteresis comparator (11), a second hysteresis comparator (12), a third hysteresis comparator (13), a D flip-flop component (14), a logic gate component (15), an inverter chain delay circuit (16), and an inverter component (17) that are electrically connected; The first hysteresis comparator (11) is used to obtain a first comparison result according to the first DC output voltage and a first DC output voltage reference level; The second hysteresis comparator (12) is used to obtain a second comparison result according to the second DC output voltage and a second DC output voltage reference level; The third hysteresis comparator (11) is configured as: Based on the second DC output voltage reference level, obtaining a reference voltage; Obtaining a third comparison result according to the second DC output voltage and the reference voltage; The logic gate component (15) is used to generate a trigger signal according to the first comparison result, the second comparison result, and the third comparison result; the trigger signal is used to control the free-wheeling switch component (3), the first transistor component (4), the second transistor component (5), and the third transistor component (7) to turn on or off, so that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the second target voltage range.

9. A single-stage adjustable voltage rectifier system with multiple outputs and full-wave rectification according to claim 8, characterized in that: The control module (1) is further configured to: If the load current is in a heavy load state, the first PMOS transistor (41) and the third transistor component (7) are controlled to be turned on, so that the first DC output voltage is within a first target voltage range and the second DC output voltage is within a third target voltage range; the third target voltage range is obtained by the reference voltage and the second DC output voltage reference level.

10. The single-stage adjustable voltage rectifier system with multiple outputs and full-wave rectification according to claim 4, characterized in that: The first comparator (53) and the second comparator (54) include: An electrically connected PMOS transistor component (541) and an NMOS transistor component (542); Wherein, when the value of the signal to be compared input by the first comparator (53) or the second comparator (54) is greater than the positive value of the power supply voltage of the first comparator (53) or the second comparator (54), the first comparator (53) or the second comparator (54) outputs a low level; when the value of the signal to be compared input by the first comparator (53) or the second comparator (54) is less than or equal to the positive value of the power supply voltage of the first comparator (53) or the second comparator (54), the first comparator (53) or the second comparator (54) outputs a high level.

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