A high linearity wideband passive mixer

Abstract

The application discloses a high-linearity wide-band passive mixer, which comprises an RF impedance matching network, an IF impedance matching network, an LO pre-driver, a stacked LO driver and a switch core; a radio frequency signal enters from P3 and P4 ports, is transmitted through X and Y ports of the RF impedance matching network, is transmitted to A and B ports to enter the switch core, is finally transmitted to E and F ports to enter the IF impedance matching network; a local oscillator signal enters from P1 and P2 ports, is transmitted through H and Z ports of the LO pre-driver, enters the switch core through a double-path stacked LO driver, is transmitted to the IF impedance matching network through E and F ports, and is finally output as an IF signal through P5 and P6 ports. The application realizes a working frequency range of 7GHz to 20GHz, adopts a hybrid coupling structure for the RF impedance matching network, adopts a low-pass four-order LC structure for the IF impedance matching network, and realizes super-high linearity, low power consumption and super-wide-band performance of the IF signal by cascading the LO pre-driver and the stacked LO driver.

Description

Technical Field

[0001] This invention relates to the field of radio frequency wireless communication technology, and more specifically to a high linearity broadband passive mixer. Background Technology

[0002] A passive mixer is a radio frequency (RF) device whose core function is to combine two signals of different frequencies (typically the input RF signal and the local oscillator signal) to generate a new frequency component without requiring an external power supply to provide gain. Currently, due to the demand for higher data transmission rates, especially in the FR3 band of 7-20 GHz 5G communication, broadband communication systems are receiving increasing attention. These systems employ broadband RF front-ends to support multi-band operation and inter-band carrier aggregation. However, the implementation of these functions comes at the cost of significant unfiltered interference, imposing stringent linearity requirements on components in the RF signal path. In digital beamforming arrays, broadband low-noise amplifiers amplify interference signals, resulting in a significantly increased interference signal level at the mixer input. In RF beamforming arrays, the situation is slightly better because out-of-beam blocking interference is typically attenuated after beam combining before the mixer, reducing interference to subsequent mixer stages. Nevertheless, for arrays containing a large number of components or interference devices in the main beam, both the main signal and interference signal power levels at the mixer input can be very high. Therefore, high-signal linearity (IP1dB) and low-signal linearity (IIP3) are crucial for mixers deployed in broadband systems, especially base stations. The use of these features will inevitably cause interference to broadband systems in the new FR3 band, making the provision of high-linearity broadband passive mixers for the new 5G communication FR3 band particularly commercially valuable and technically significant.

[0003] Looking back, traditional technologies mostly use double-balanced or single-balanced mixers. For example, Chinese patent (CN118381472A) discloses a high harmonic suppression mixer, providing an active mixer based on a single-balanced structure design, including NMOS transistor Q1, HBT transistors Q2 and Q3, and resistor R. 1～3 The local oscillator signal is isolated using HBT transistors Q2 and Q3, reducing interference from the local oscillator signal to the output signal. However, the HBT transistors Q2 and Q3 change with temperature, leading to instability in the static operating point. Furthermore, the active structure in the above technology has poor linearity and a bandwidth of only 6GHz, which is insufficient to meet the high linearity requirements of the broadband FR3 band system in new 5G communication.

[0004] Therefore, existing mixers suffer from poor linearity and low bandwidth, failing to meet the high linearity requirements of broadband systems in the new 5G communication FR3 band. This limits the overall performance of the mixer. To address this, this invention provides a high-linearity broadband passive mixer with ultra-high linearity and ultra-wideband advantages. Summary of the Invention

[0005] This invention provides a high linearity broadband passive mixer, comprising: an RF impedance matching network, an IF impedance matching network, an LO pre-driver, a stacked LO driver, and a switching core;

[0006] The RF impedance matching network is provided with ports P3 and P4 and ports A and B on both sides; the RF impedance matching network includes: capacitor C. m Capacitor C s Capacitor C a Inductor L p Inductor L s Inductor L d Inductor L a ;

[0007] The IF impedance matching network is provided with ports P5, P6 and ports E, F on both sides; the IF impedance matching network includes: capacitors C1, C2, C3, C4, C5, C6, inductors L1, L2, L3, and L4.

[0008] The switch core has ports A and B and ports C and D on both sides; the switch core includes switches S1, S2, S3, and S4, which have the same switch structure; the switch structure includes: NMOS transistor M s1 NMOS transistor M s2 Capacitor C c Capacitor C d Resistance R g Resistance R n ;

[0009] The LO pre-driver has ports P1, P2 and ports H, Z on both sides; the LO pre-driver includes uplink and downlink LO pre-drivers with identical structures; the LO pre-driver includes: PMOS transistors M1, M2, M3, M4, M5, and M6, and capacitor C. b Inductor L g Resistance R d ;

[0010] The stacked LO driver is configured with ports G and S; the stacked LO driver includes uplink and downlink stacked LO drivers, and the stacked LO drivers have the same structure; the stacked LO driver includes: a PMOS transistor M. p1 PMOS transistor M p2 PMOS transistor M p3 NMOS transistor M n1 NMOS transistor M n2 NMOS transistor Mn3 Capacitor C p1 Capacitor C p2 Capacitor C p3 Capacitor C n1 Capacitor C n2 Capacitor C n3 ;

[0011] In the RF impedance matching network, port X is connected to terminal A of the switch core, and terminal Y of the RF impedance matching network is connected to terminal B of the switch core.

[0012] The C terminal of the switch core is connected to the E terminal of the IF impedance matching network, the D terminal of the switch core is connected to the F terminal of the IF impedance matching network, and the P5 and P6 ports of the IF impedance matching network output IF signals.

[0013] The P1 and P2 terminals of the LO pre-driver receive the local oscillator signal. The H terminal of the LO pre-driver is connected to the G terminal of the stacked LO driver, and the Z terminal of the LO pre-driver is connected to the S terminal of the stacked LO driver. The output local oscillator signal of the stacked LO driver is connected to the switching core S. 1～4 The input terminal is connected;

[0014] In the RF impedance matching network, ports P3 and P4 receive RF input signals. The RF signals enter the RF impedance matching network from ports P3 and P4, and are converted by XY ports to output two signals. One signal passes through port A via switch S1 and the other signal passes through port B via switch S3 to port C, and is finally merged at port E. The other signal passes through port A via switch S2 and the other signal passes through port B via switch S4 to port D, and is finally merged at port F. The two signals enter the IF impedance matching network through ports EF, and finally output the IF signal through ports P5 and P6.

[0015] The local oscillator signal enters through ports P1 and P2, and is split into two signals that enter the uplink and downlink LO pre-drivers to ports H and Z. Then, the two signals enter the uplink and downlink stacked LO drivers through ports G and S respectively, obtaining the local oscillator signal, and then enter the switch S in the switching core. 1～4 The signal is used as the local oscillator input.

[0016] Preferably, in the RF impedance matching network, capacitor C m One end is connected to the inductor L p The capacitor C is connected to port P3 and serves as one input to the RF impedance matching network. m The other end is connected to the inductor L s The inductor L is connected to terminal d and serves as one output port X of the RF impedance matching network. p terminal a and inductor Ld The e-terminal is connected to the inductor L. p terminal a and inductor L s The inductor L is coupled at its b-end. s The b terminal and the inductor L a The f terminal of the inductor is connected to and grounded. d g terminal and inductor L a The capacitor C is coupled at the h-end. a One end is connected to the inductor L d The g-terminal is connected to the P4 port and serves as another input terminal of the RF impedance matching network. The capacitor C a The other end is connected to the inductor L a The capacitor C is connected to the h terminal and serves as another output port Y of the RF impedance matching network. s One end is connected to capacitor C m One end and inductor L s The b-end is connected, and the capacitor C s The other end is connected to capacitor C a The other end and inductor L a The h-end connection.

[0017] Preferably, in the IF impedance matching network, one end of capacitor C1 is connected to one end of inductor L1, connected to port E, and serves as one input terminal of the IF impedance matching network. The other end of capacitor C1 is connected to one end of capacitor C4 and grounded. The other end of capacitor C4 is connected to one end of inductor L3, connected to port F, and serves as another input terminal of the IF impedance matching network. The other end of inductor L3 is connected to one end of capacitor C5 and one end of inductor L4. The other end of inductor L1 is connected to one end of capacitor C2 and one end of inductor L2. The other end of capacitor C2 is connected to the other end of capacitor C5 and grounded. The other end of inductor L2 is connected to one end of capacitor C3, connected to port P5, and serves as the output terminal of the IF impedance matching network. The other end of capacitor C3 is connected to one end of capacitor C6 and grounded. The other end of capacitor C6 is connected to the other end of inductor L4 and connected to port P6.

[0018] Preferably, the inductor L in the LO pre-driver g One end of the inductor L is connected to port P1 / P2 and serves as the input of the LO pre-driver. g The other end is connected to capacitor C b One end of the capacitor C is connected to the capacitor C. b The other end is connected to resistor R d One end of the capacitor C is connected to the capacitor C. b The other end is connected to the gate terminal of NMOS transistor M4 and the gate terminal of PMOS transistor M1, and the resistor R dThe other end is connected to the drain of NMOS transistor M4 and the drain of PMOS transistor M1. The source of NMOS transistor M4 is grounded, and the source of PMOS transistor M1 is connected to a power supply voltage of 1.2V. The resistor R d The other end is connected to the gate of NMOS transistor M5 and the gate of PMOS transistor M2. The drain of NMOS transistor M5 is connected to the drain-gate of PMOS transistor M2. The source of NMOS transistor M5 is grounded. The source of PMOS transistor M2 is connected to a power supply voltage of 1.2V. The drain of NMOS transistor M5 is connected to the gate of NMOS transistor M6 and the gate of PMOS transistor M3. The drain of PMOS transistor M2 is connected to the gate of NMOS transistor M6 and the gate of PMOS transistor M3. The source of NMOS transistor M6 is grounded. The source of PMOS transistor M3 is connected to a power supply voltage of 1.2V. The drain of NMOS transistor M6 is connected to the drain-gate of PMOS transistor M3. This connection is made to port H / Z and serves as the output of the LO pre-driver.

[0019] Preferably, the stacked LO driver PMOS transistor M p1 The source terminal is connected to a power supply voltage of 5V, and the PMOS transistor M p1 Drain terminal and PMOS transistor M p2 Source connection, the PMOS transistor M p1 Gate terminal and capacitor C p1 One end of the capacitor C is connected to the capacitor C. p1 The other end is connected to capacitor C p2 One end of the capacitor C is connected to the capacitor C. p2 The other end is connected to the PMOS transistor M p2 The gate terminal is connected, and the PMOS transistor M p2 Drain terminal and PMOS transistor M p3 Source connection, the PMOS transistor M p3 Drain terminal and NMOS transistor M n3 The drain terminal is connected and serves as the output V of the stacked LO driver. out The capacitor C p3 One end is connected to capacitor C p2 one end and capacitor C n3 One end is connected and serves as the input V of the stacked LO driver. in The capacitor C p3 The other end is connected to the PMOS transistor M p3 The gate terminal is connected, and the capacitor C n3 One end is connected to capacitor C n2 One end of the capacitor C is connected to the capacitor C. n3 The other end is connected to the NMOS transistor M n3 The gate terminal is connected, and the NMOS transistor M n3 Source terminal and NMOS transistor M n3 The capacitor C is connected to the drain terminal. n2 One end is connected to capacitor Cn1 One end of the capacitor C is connected to the capacitor C. n2 The other end is connected to the NMOS transistor M n2 The gate terminal is connected, and the NMOS transistor M n2 Source terminal and NMOS transistor M n1 The capacitor C is connected to the drain terminal. n1 The other end is connected to the NMOS transistor M n1 The gate terminal is connected, and the NMOS transistor M n1 The source end is grounded.

[0020] Preferably, the capacitor C in the switch core c One end is connected to capacitor C d One end of the capacitor C is connected to the LO signal. c The other end is connected to the NMOS transistor M s1 Gate and resistor R g One end of the capacitor C is connected to the capacitor C. d The other end is connected to the NMOS transistor M s2 Gate and resistor R n One end is connected, the resistor R n The other end is connected to resistor R g The other end is connected and connected to the power supply voltage V. g The NMOS transistor M s1 The source terminal is connected to IN and serves as the input terminal of the switch; the NMOS transistor M... s1 Drain terminal and NMOS transistor M s2 The source terminal is connected, and the NMOS transistor M s2 The drain terminal is connected to OUT and serves as the output terminal of the switch.

[0021] Compared with the prior art, the technical solution of this application has the following technical effects:

[0022] The CMOS integrated passive mixer presented in this invention has significant advantages in miniaturization and high integration, making it more ideal for broadband system applications in the new 5G communication FR3 band. CMOS technology has strong compatibility with digital circuits, which facilitates the implementation of logic control for multi-phase digital clocks, reduces manufacturing costs, and enhances market competitiveness. Its ultra-wideband and ultra-high linearity performance advantages allow the CMOS integrated passive mixer to be adjusted according to different application requirements and adapt to various frequency communication requirements. These features make it increasingly popular in modern wireless communication systems.

[0023] The present invention utilizes that the switching core consists of four switches configured in a double-balanced structure, and each switch consists of two NMOS devices stacked in series, which improves the breakdown voltage of the source and drain, and realizes a greater RF signal voltage processing capacity; by designing a small Cc and ensuring that Cc < Cgate (the equivalent parasitic capacitance of the transistor gate), a quasi-floating effect of the gate is achieved. In this way, when a large RF signal enters the source, part of it is coupled to the gate, and the equivalent floating gate will track the large signal of the source and drain. As a result, the effective gate-source and gate-drain voltages are reduced, and the distortion risk of the transistor is lowered; the impedance matching networks for RF and IF also achieve the effect of changing the RF / IF impedance, that is, converting the 50Ω impedance of the RF and IF ports into 20Ω seen from the source and drain of the mixer transistor towards the RF and IF ports. The reduced impedance lowers the voltage signal swing of the source and drain, and reduces the degree of distortion.

[0024] The stacked LO driver structure of the present invention expands the frequency range of the local oscillator driver, enabling the mixer to cover a wideband frequency range. The solution of the present invention is a passive mixer structure, which is easy to implement silicon-based integration and has the advantages of small size and low cost.

[0025] The above description is only an overview of the technical solution of this application. In order to be able to understand the technical means of this application more clearly, so as to be implemented in accordance with the content of the specification, and in order to make the above and other purposes, features and advantages of this application more obvious and understandable, the following will be described in detail with reference to the preferred embodiments of this application and the accompanying drawings.

[0026] According to the following detailed description of the specific embodiments of this application in conjunction with the drawings, those skilled in the art will understand the above and other purposes, advantages and features of this application more clearly. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to actual scale.

[0028] Figure 1 is the architecture diagram of the present invention;

[0029] Figure 2 is the schematic diagram of the RF impedance matching network circuit of the present invention;

[0030] Figure 3 is the schematic diagram of the IF impedance matching network circuit of the present invention;

[0031] Figure 4 This is a schematic diagram of the LO pre-driver circuit of the present invention;

[0032] Figure 5 This is a schematic diagram of the stacked LO driver circuit of the present invention;

[0033] Figure 6 The switch S of the present invention 1～4 Circuit diagram;

[0034] Figure 7 This is a schematic diagram of the down-conversion loss of the present invention;

[0035] Figure 8 This is a schematic diagram of the 1-dB compression point of the input power of the present invention;

[0036] Figure 9 This is a schematic diagram of IIP3 of the present invention;

[0037] Figure 10 This is a schematic diagram illustrating the IIP3 efficiency of the present invention;

[0038] Figure 11 This is a power consumption diagram of the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. In the following description, specific details such as specific configurations and components are provided merely to help fully understand the embodiments of this application. Therefore, those skilled in the art should understand that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this application. In addition, for clarity and brevity, descriptions of known functions and structures are omitted in the embodiments.

[0040] It should be understood that the phrase "an embodiment" or "this embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "an embodiment" or "this embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0041] Furthermore, reference numerals and / or letters may be repeated in different examples within this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or settings discussed.

[0042] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, B exists alone, and A and B exist simultaneously. The term " / and" in this article describes another type of relationship between related objects, indicating that two relationships can exist. For example, A / and B can mean: A exists alone, and A and B exist alone. In addition, the character " / " in this article generally indicates that the related objects before and after it are in an "or" relationship.

[0043] In this article, the term "at least one" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, "at least one of A and B" can mean: A exists alone, A and B exist simultaneously, or B exists alone.

[0044] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion.

[0045] Example 1

[0046] This embodiment mainly describes a high linearity broadband passive mixer, such as... Figure 1 As shown, it includes: RF impedance matching network, IF impedance matching network, LO pre-driver, stacked LO driver, and switch core;

[0047] The RF impedance matching network has ports P3 and P4 and ports A and B on both sides; the RF impedance matching network includes: capacitor C. m Capacitor C s Capacitor C a Inductor L p Inductor L s Inductor L d Inductor L a ;

[0048] The IF impedance matching network has ports P5 and P6 and ports E and F on both sides; the IF impedance matching network includes: capacitors C1, C2, C3, C4, C5, C6, inductors L1, L2, L3, and L4.

[0049] The switch core has ports A and B on both sides and ports C and D on both sides; the switch core includes switches S1, S2, S3, and S4, which have the same switch structure; the switch structure includes: NMOS transistor M s1 NMOS transistor M s2 Capacitor C cCapacitor C d Resistance R g Resistance R n ;

[0050] The LO pre-driver has ports P1, P2 and ports H, Z on both sides; the LO pre-driver includes uplink and downlink LO pre-drivers, which have the same structure; the LO pre-driver includes: PMOS transistors M1, M2, M3, M4, M5, and M6, and capacitor C. b Inductor L g Resistance R d ;

[0051] The stacked LO driver sets ports G and S; the stacked LO driver includes uplink and downlink stacked LO drivers, and the stacked LO drivers have the same structure; the stacked LO driver includes: PMOS transistor M. p1 PMOS transistor M p2 PMOS transistor M p3 NMOS transistor M n1 NMOS transistor M n2 NMOS transistor M n3 Capacitor C p1 Capacitor C p2 Capacitor C p3 Capacitor C n1 Capacitor C n2 Capacitor C n3 ;

[0052] In the RF impedance matching network, port X is connected to terminal A of the switch core, and terminal Y of the RF impedance matching network is connected to terminal B of the switch core.

[0053] The C terminal of the switch core is connected to the E terminal of the IF impedance matching network, the D terminal of the switch core is connected to the F terminal of the IF impedance matching network, and the P5 and P6 ports of the IF impedance matching network output the IF signal.

[0054] The P1 and P2 terminals of the LO pre-driver receive the local oscillator signal. The H terminal of the LO pre-driver is connected to the G terminal of the stacked LO driver, and the Z terminal of the LO pre-driver is connected to the S terminal of the stacked LO driver. The output local oscillator signal of the stacked LO driver is connected to the switching core S. 1～4 The input terminal is connected;

[0055] In the RF impedance matching network, ports P3 and P4 receive RF input signals. The RF signals enter the RF impedance matching network from ports P3 and P4, and are converted by the XY ports to output two signals. One signal passes through port A and switches S1, while the other signal passes through port B and switches S3 to port C, and is finally merged at port E. The other signal passes through port A and switches S2, while the other signal passes through port B and switches S4 to port D, and is finally merged at port F. The two signals enter the IF impedance matching network through ports EF, and finally output the IF signal through ports P5 and P6.

[0056] The local oscillator signal enters through ports P1 and P2, splits into two signals, and enters the uplink and downlink LO pre-drivers to ports H and Z. Then, the two signals enter the uplink and downlink stacked LO drivers through ports G and S respectively, obtaining the local oscillator signal, and then enters the switch S in the switching core. 1～4 The signal is used as the local oscillator input.

[0057] Furthermore, such as Figure 2 As shown, the capacitor C in the RF impedance matching network m One end is connected to the inductor L p The capacitor C is connected to the P3 port and serves as one input to the RF impedance matching network. m The other end is connected to the inductor L s The d-end is connected and serves as one output port X of the RF impedance matching network, with inductor L... p terminal a and inductor L d The e-terminal is connected to the inductor L. p terminal a and inductor L s The b-end is coupled, and the inductor L s The b terminal and the inductor L a The f terminal is connected to ground, and the inductor L d g terminal and inductor L a The h-end is coupled, and the capacitor C a One end is connected to the inductor L d The g terminal is connected to the P4 port and serves as another input to the RF impedance matching network. Capacitor C a The other end is connected to the inductor L a The h terminal is connected and serves as another output port Y of the RF impedance matching network, with capacitor C. s One end is connected to capacitor C m One end and inductor L s The b-end is connected to the capacitor C. s The other end is connected to capacitor C a The other end and inductor L a The h-end connection.

[0058] Furthermore, such as Figure 3As shown, in the IF impedance matching network, one end of capacitor C1 is connected to one end of inductor L1, connected to port E, and serves as one input terminal of the IF impedance matching network. The other end of capacitor C1 is connected to one end of capacitor C4 and grounded. The other end of capacitor C4 is connected to one end of inductor L3, connected to port F, and serves as another input terminal of the IF impedance matching network. The other end of inductor L3 is connected to one end of capacitor C5 and one end of inductor L4. The other end of inductor L1 is connected to one end of capacitor C2 and one end of inductor L2. The other end of capacitor C2 is connected to the other end of capacitor C5 and grounded. The other end of inductor L2 is connected to one end of capacitor C3, connected to port P5, and serves as the output terminal of the IF impedance matching network. The other end of capacitor C3 is connected to one end of capacitor C6 and grounded. The other end of capacitor C6 is connected to the other end of inductor L4, connected to port P6.

[0059] Furthermore, such as Figure 4 As shown, the inductor L in the LO pre-driver g One end of the inductor L is connected to port P1 / P2 and serves as the input of the LO pre-driver. g The other end is connected to capacitor C b One end is connected to capacitor C b The other end is connected to resistor R d One end is connected to capacitor C b The other end is connected to the gate of NMOS transistor M4 and the gate of PMOS transistor M1, with resistor R d The other end is connected to the drain of NMOS transistor M4 and the drain of PMOS transistor M1. The source of NMOS transistor M4 is grounded, and the source of PMOS transistor M1 is connected to a power supply voltage of 1.2V. Resistor R d The other end is connected to the gate of NMOS transistor M5 and the gate of PMOS transistor M2. The drain of NMOS transistor M5 is connected to the drain and gate of PMOS transistor M2. The source of NMOS transistor M5 is grounded. The source of PMOS transistor M2 is connected to a power supply voltage of 1.2V. The drain of NMOS transistor M5 is connected to the gate of NMOS transistor M6 and the gate of PMOS transistor M3. The drain of PMOS transistor M2 is connected to the gate of NMOS transistor M6 and the gate of PMOS transistor M3. The source of NMOS transistor M6 is grounded. The source of PMOS transistor M3 is connected to a power supply voltage of 1.2V. The drain of NMOS transistor M6 is connected to the drain and gate of PMOS transistor M3. This connection is made to port H / Z and serves as the output of the LO pre-driver.

[0060] Furthermore, such as Figure 5 As shown, the stacked LO driver PMOS transistor M p1 The source is connected to a 5V power supply, and the PMOS transistor is M. p1 Drain terminal and PMOS transistor M p2 Source connection, PMOS transistor M p1 Gate terminal and capacitor C p1One end is connected to capacitor C p1 The other end is connected to capacitor C p2 One end is connected to capacitor C p2 The other end is connected to the PMOS transistor M p2 Gate connection, PMOS transistor M p2 Drain terminal and PMOS transistor M p3 Source connection, PMOS transistor M p3 Drain terminal and NMOS transistor M n3 The drain terminal is connected and serves as the output V of the stacked LO driver. out Capacitor C p3 One end is connected to capacitor C p2 one end and capacitor C n3 One end is connected and serves as the input V of the stacked LO driver. in Capacitor C p3 The other end is connected to the PMOS transistor M p3 Gate connection, capacitor C n3 One end is connected to capacitor C n2 One end is connected to capacitor C n3 The other end is connected to the NMOS transistor M n3 Gate connection, NMOS transistor M n3 Source terminal and NMOS transistor M n3 Drain connection, capacitor C n2 One end is connected to capacitor C n1 One end is connected to capacitor C n2 The other end is connected to the NMOS transistor M n2 Gate connection, NMOS transistor M n2 Source terminal and NMOS transistor M n1 Drain connection, capacitor C n1 The other end is connected to the NMOS transistor M n1 Gate connection, NMOS transistor M n1 The source end is grounded.

[0061] Furthermore, such as Figure 6 As shown, capacitor C in the core of the switch c One end is connected to capacitor C d One end is connected to the LO signal, and capacitor C c The other end is connected to the NMOS transistor M s1 Gate and resistor R g One end is connected to capacitor C d The other end is connected to the NMOS transistor M s2 Gate and resistor R n One end is connected to resistor R n The other end is connected to resistor R g The other end is connected and connected to the power supply voltage V. g NMOS transistor M s1The source terminal is connected to IN and serves as the input terminal of the switch; the NMOS transistor M... s1 Drain terminal and NMOS transistor M s2 Source connection, NMOS transistor M s2 The drain terminal is connected to OUT and serves as the output terminal of the switch.

[0062] This embodiment demonstrates that the CMOS integrated passive mixer has significant advantages in miniaturization and high integration, making it more ideal for broadband system applications in the new 5G communication FR3 band. CMOS technology has strong compatibility with digital circuits, which facilitates the implementation of logic control for multi-phase digital clocks, reduces manufacturing costs, and enhances market competitiveness. The ultra-wideband and ultra-high linearity performance advantages of the CMOS integrated passive mixer enable it to be adjusted according to different application requirements and adapt to various frequency communication requirements.

[0063] Example 2

[0064] This embodiment, based on Embodiment 1, describes in detail an optimization scheme for a high-linearity broadband passive mixer, specifically including:

[0065] The RF impedance matching network employs a hybrid coupling (magnetic and capacitive) structure, achieving high bandwidth and low insertion loss, such as... Figure 2 As shown; the magnetic coupling employs a low-K value design to improve the self-resonant frequency (SRF), while the feedforward capacitor network (Cm) is used to further extend the bandwidth; on the other hand, the IF impedance matching network is optimized for the 3-7GHz operating frequency and designed as a low-pass fourth-order LC network, with the structure as shown. Figure 3 As shown, this design achieves a wider bandwidth and better out-of-band spurious harmonic suppression. Two impedance-dropping matching networks (MNs) are used at the RF and IF nodes to reduce the standard 50Ω impedance of the external RF and IF ports to a lower 20Ω impedance from the source-drain junction of the switching transistor core towards the external RF and IF ports. This lower impedance effectively improves linearity. The IF impedance matching network can also be placed within the mixer package or on the printed circuit board, depending on the IF frequency band.

[0066] LO pre-drivers such as Figure 4 As shown, this structure provides a two-stage preamplifier to generate rail-to-rail signals to drive stacked LO drivers. These signals are typically used to drive high-power loads, such as local oscillator (LO) drivers, which are used in wireless communication systems to generate stable oscillation signals. Preamplifiers are small power amplifiers that drive the main power amplifier; they amplify the signal amplitude to ensure sufficient power to drive subsequent power amplifiers. The two-stage preamplifier design here means the signal is amplified twice to ensure sufficient drive capability for the stacked LO drivers.

[0067] The stacked LO driver, as Figure 5 shown, depicts a stacked LO driver composed of three layers of NMOS devices and three layers of PMOS devices, operating at a supply voltage of 5V. The input signal is applied to all MOS devices within the stack rather than just the bottommost and topmost devices. Compared to traditional drivers, in the high (low) input signal state, for M n2 and M n3 (M p2 and M p3 ), the V gs (V sg ) is higher, thereby reducing the on-resistance of the MOS devices. Consequently, the driver can maintain a rail-to-rail output swing at higher frequencies, effectively ensuring the bandwidth characteristics of the mixer. At the same time, due to the faster transition time at the driver output, a higher mixer IIP3 can be achieved. Additionally, when M n2 and M n3 (M p2 and M p3 ) devices are in the off state, for the improved driver, the V [[ID=2A]] gs [[ID=2B]](V [[ID=2C]] sg [[ID=2D]]) on M n2 and M n3 (M [[ID=D]] p2 and M p3 ) is lower, thereby reducing the leakage current and improving the driver efficiency. Secondly, by operating the pre-driver from a 1.2V rather than the standard 1V supply to drive the stacked LO driver with a larger voltage swing, a better on-off switching is achieved. Although the higher supply voltage and larger load capacitance increase the power consumption of the pre-driver, since the power consumption of the pre-driver is very small, the increase in total power consumption is negligible.

[0068] The switch core, as Figure 6 shown, consists of four switches configured in a double-balanced structure. Each switch is composed of two NMOS devices stacked in series, enabling a higher voltage handling capacity and improving the linearity of the switch core. The equivalent total on-resistance of a single NMOS transistor is 3 - 4Ω, effectively reducing the insertion loss. To further improve the linearity of the mixer, the capacitor used to couple the LO to the NMOS gate is designed to be relatively small (Cc < Cgate), forming a quasi-floating gate that can track the source and drain voltages and reduce the effective V gs / V gd to enhance the mixer linearity. If Cc is too small, it will be at the cost of a higher driving local oscillator signal strength. Therefore, the optimized results after comprehensive consideration are shown in the following table;

[0069]

[0070] This embodiment provides a high linearity broadband passive mixer implemented using 45nm SOI technology, consuming less than 430mW of power. Its operating frequency covers the 7-20GHz new 5G communication FR3 band. At 7-20GHz RF frequencies, the mixer's analog conversion insertion loss is 8-11.7dB, IP1dB is 20.3-25.1dBm, and IIP3 is 23.5-36dBm at different LO and IF = 3GHz values. Specific component parameter values ​​are shown in the table above.

[0071] like Figure 7 As shown, the simulation results of downconversion loss at an intermediate frequency of 3 GHz are presented. It can be seen that the downconversion loss is 8-11.7 dB in the RF frequency range of 7-20 GHz.

[0072] like Figure 8 As shown in the simulation results, at an intermediate frequency of 3 GHz, the IP1dB is 20.3-25.1dB within the RF frequency range of 7-20 GHz.

[0073] like Figure 9 As shown, the simulation results of IIP3 at an intermediate frequency of 3 GHz are presented. It can be seen that IIP3 is 23.5-36 dBm in the RF frequency range of 7-20 GHz. IIP3 efficiency (dB) is defined as the difference between IIP3 (dBm) and power consumption (dBm), which shows the efficiency of the mixer in achieving specific intermodulation performance.

[0074] like Figure 10 As shown, the IIP3 efficiency is displayed, where IF is set to 3GHz. When the RF frequency is 7-13GHz, the IIP3 efficiency of the mixer is 5-19dB. As the LO frequency increases, the IIP3 efficiency drops to ≈0dB at 20GHz.

[0075] like Figure 11 As shown in the figure, the power consumption results of the mixer are given. The results show that the power consumption is less than 430mW in the LO frequency interval range of 7-20GHz.

[0076] Through comparative analysis of the above-mentioned optimization schemes, this embodiment demonstrates that the superior linearity and bandwidth characteristics of the present invention are very suitable for high linearity reception applications of modern phased arrays.

[0077] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any changes, modifications, substitutions, integrations, and parameter changes made to these embodiments within the spirit and principles of the present invention, without departing from the principles and spirit of the present invention, through conventional substitutions or to achieve the same function, fall within the scope of protection of the present invention.

Claims

1. A high linearity broadband passive mixer, characterized in that, include: RF impedance matching network, IF impedance matching network, LO pre-driver, stacked LO driver, switch core; The RF impedance matching network is provided with ports P3 and P4 and ports A and B on both sides; the RF impedance matching network includes: capacitor C. m Capacitor C s Capacitor C a Inductor L p Inductor L s Inductor L d Inductor L a ; The IF impedance matching network is provided with ports P5, P6 and ports E, F on both sides; the IF impedance matching network includes: capacitors C1, C2, C3, C4, C5, C6, inductors L1, L2, L3, and L4. The switch core has ports A and B and ports C and D on both sides; the switch core includes switches S1, S2, S3, and S4, which have the same switch structure; the switch structure includes: NMOS transistor M s1 NMOS transistor M s2 Capacitor C c Capacitor C d Resistance R g Resistance R n ; The LO pre-driver has ports P1, P2 and ports H, Z on both sides; the LO pre-driver includes uplink and downlink LO pre-drivers with identical structures; the LO pre-driver includes: PMOS transistors M1, M2, M3, M4, M5, and M6, and capacitor C. b Inductor L g Resistance R d ; The stacked LO driver is configured with ports G and S; the stacked LO driver includes uplink and downlink stacked LO drivers, and the stacked LO drivers have the same structure; the stacked LO driver includes: a PMOS transistor M. p1 PMOS transistor M p2 PMOS transistor M p3 NMOS transistor M n1 NMOS transistor M n2 NMOS transistor M n3 Capacitor C p1 Capacitor C p2 Capacitor C p3 Capacitor C n1 Capacitor C n2 Capacitor C n3 ; In the RF impedance matching network, port X is connected to terminal A of the switch core, and terminal Y of the RF impedance matching network is connected to terminal B of the switch core. The C terminal of the switch core is connected to the E terminal of the IF impedance matching network, the D terminal of the switch core is connected to the F terminal of the IF impedance matching network, and the P5 and P6 ports of the IF impedance matching network output IF signals. The P1 and P2 terminals of the LO pre-driver receive the local oscillator signal. The H terminal of the LO pre-driver is connected to the G terminal of the stacked LO driver, and the Z terminal of the LO pre-driver is connected to the S terminal of the stacked LO driver. The output local oscillator signal of the stacked LO driver is connected to the switching core S. 1～4 The input terminal is connected; In the RF impedance matching network, ports P3 and P4 receive RF input signals. The RF signals enter the RF impedance matching network from ports P3 and P4, and are converted by XY ports to output two signals. One signal passes through port A via switch S1 and the other signal passes through port B via switch S3 to port C, and is finally merged at port E. The other signal passes through port A via switch S2 and the other signal passes through port B via switch S4 to port D, and is finally merged at port F. The two signals enter the IF impedance matching network through ports EF, and finally output the IF signal through ports P5 and P6. The local oscillator signal enters through ports P1 and P2, and is split into two signals that enter the uplink and downlink LO pre-drivers to ports H and Z. Then, the two signals enter the uplink and downlink stacked LO drivers through ports G and S respectively, obtaining the local oscillator signal, and then enter the switch S in the switching core. 1～4 The signal is used as the local oscillator input.

2. The high linearity broadband passive mixer according to claim 1, characterized in that, The capacitor C in the RF impedance matching network m One end is connected to the inductor L p The capacitor C is connected to port P3 and serves as one input to the RF impedance matching network. m The other end is connected to the inductor L s The inductor L is connected to terminal d and serves as one output port X of the RF impedance matching network. p terminal a and inductor L d The e-terminal is connected to the inductor L. p terminal a and inductor L s The inductor L is coupled at its b-end. s The b terminal and the inductor L a The f terminal of the inductor is connected to and grounded. d g terminal and inductor L a The capacitor C is coupled at the h-end. a One end is connected to the inductor L d The g-terminal is connected to the P4 port and serves as another input terminal of the RF impedance matching network. The capacitor C a The other end is connected to the inductor L a The capacitor C is connected to the h terminal and serves as another output port Y of the RF impedance matching network. s One end is connected to capacitor C m One end and inductor L s The b-end is connected, and the capacitor C s The other end is connected to capacitor C a The other end and inductor L a The h-end connection.

3. A high linearity broadband passive mixer according to claim 2, characterized in that, In the IF impedance matching network, one end of capacitor C1 is connected to one end of inductor L1, connected to port E, and serves as one input terminal of the IF impedance matching network. The other end of capacitor C1 is connected to one end of capacitor C4 and grounded. The other end of capacitor C4 is connected to one end of inductor L3, connected to port F, and serves as another input terminal of the IF impedance matching network. The other end of inductor L3 is connected to one end of capacitor C5 and one end of inductor L4. The other end of inductor L1 is connected to one end of capacitor C2 and one end of inductor L2. The other end of capacitor C2 is connected to the other end of capacitor C5 and grounded. The other end of inductor L2 is connected to one end of capacitor C3, connected to port P5, and serves as the output terminal of the IF impedance matching network. The other end of capacitor C3 is connected to one end of capacitor C6 and grounded. The other end of capacitor C6 is connected to the other end of inductor L4, connected to port P6.

4. A high linearity broadband passive mixer according to claim 2, characterized in that, Inductor L in LO pre-driver g One end of the inductor L is connected to port P1 / P2 and serves as the input of the LO pre-driver. g The other end is connected to capacitor C b One end of the capacitor C is connected to the capacitor C. b The other end is connected to resistor R d One end of the capacitor C is connected to the capacitor C. b The other end is connected to the gate terminal of NMOS transistor M4 and the gate terminal of PMOS transistor M1, and the resistor R d The other end is connected to the drain of NMOS transistor M4 and the drain of PMOS transistor M1. The source of NMOS transistor M4 is grounded, and the source of PMOS transistor M1 is connected to a power supply voltage of 1.2V. The resistor R d The other end is connected to the gate of NMOS transistor M5 and the gate of PMOS transistor M2. The drain of NMOS transistor M5 is connected to the drain-gate of PMOS transistor M2. The source of NMOS transistor M5 is grounded. The source of PMOS transistor M2 is connected to a power supply voltage of 1.2V. The drain of NMOS transistor M5 is connected to the gate of NMOS transistor M6 and the gate of PMOS transistor M3. The drain of PMOS transistor M2 is connected to the gate of NMOS transistor M6 and the gate of PMOS transistor M3. The source of NMOS transistor M6 is grounded. The source of PMOS transistor M3 is connected to a power supply voltage of 1.2V. The drain of NMOS transistor M6 is connected to the drain-gate of PMOS transistor M3. This connection is made to port H / Z and serves as the output of the LO pre-driver.

5. A high linearity broadband passive mixer according to claim 1, characterized in that, The stacked LO driver PMOS transistor M p1 The source terminal is connected to a power supply voltage of 5V, and the PMOS transistor M p1 Drain terminal and PMOS transistor M p2 Source connection, the PMOS transistor M p1 Gate terminal and capacitor C p1 One end of the capacitor C is connected to the capacitor C. p1 The other end is connected to capacitor C p2 One end of the capacitor C is connected to the capacitor C. p2 The other end is connected to the PMOS transistor M p2 The gate terminal is connected, and the PMOS transistor M p2 Drain terminal and PMOS transistor M p3 Source connection, the PMOS transistor M p3 Drain terminal and NMOS transistor M n3 The drain terminal is connected and serves as the output V of the stacked LO driver. out The capacitor C p3 One end is connected to capacitor C p2 one end and capacitor C n3 One end is connected and serves as the input V of the stacked LO driver. in The capacitor C p3 The other end is connected to the PMOS transistor M p3 The gate terminal is connected, and the capacitor C n3 One end is connected to capacitor C n2 One end of the capacitor C is connected to the capacitor C. n3 The other end is connected to the NMOS transistor M n3 The gate terminal is connected, and the NMOS transistor M n3 Source terminal and NMOS transistor M n3 The capacitor C is connected to the drain terminal. n2 One end is connected to capacitor C n1 One end of the capacitor C is connected to the capacitor C. n2 The other end is connected to the NMOS transistor M n2 The gate terminal is connected, and the NMOS transistor M n2 Source terminal and NMOS transistor M n1 The capacitor C is connected to the drain terminal. n1 The other end is connected to the NMOS transistor M n1 The gate terminal is connected, and the NMOS transistor M n1 The source end is grounded.

6. A high linearity broadband passive mixer according to claim 1, characterized in that, The capacitor C in the core of the switch c One end is connected to capacitor C d One end of the capacitor C is connected to the LO signal. c The other end is connected to the NMOS transistor M s1 Gate and resistor R g One end of the capacitor C is connected to the capacitor C. d The other end is connected to the NMOS transistor M s2 Gate and resistor R n One end is connected, the resistor R n The other end is connected to resistor R g The other end is connected and connected to the power supply voltage V. g The NMOS transistor M s1 The source terminal is connected to IN and serves as the input terminal of the switch; the NMOS transistor M... s1 Drain terminal and NMOS transistor M s2 The source terminal is connected, and the NMOS transistor M s2 The drain terminal is connected to OUT and serves as the output terminal of the switch.

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