Method and apparatus for llr and partial sum update in sscl decoding

Abstract

This invention discloses a method for updating the LLR and partial sums in SSCL decoding, comprising: selecting an f function or a g function based on the corresponding level bit value in the f / g control signal of the current decoding node, and calculating the LLR sequence required for deciding the current decoding node; selecting the L LLR values ​​with the smallest absolute values ​​in the LLR sequence; performing extended decoding decision on the current decoding node to obtain an extended decoding path sequence; calculating the final candidate decoding path using the existing extended decoding path sequence; calculating the f / g control signal of the next node based on the node length and f / g control signal of the current decoding node; and updating the partial sum sequence of each candidate decoding path of the next node using the final candidate decoding path sequence and the f / g control signal of the next node. This invention also discloses a device for updating the LLR and partial sums in SSCL decoding. The technical solution of this invention can effectively improve the calculation speed of the LLR and partial sum update control and reduce the hardware resource consumption of the decoder.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, specifically relating to a method and apparatus for updating LLR and its components in SSCL decoding. Background Technology

[0002] With the continuous development of information and communication technologies, people have increasingly higher requirements for the reliability and fault tolerance of communication systems. Polar codes, as a novel coding method, are coding schemes that have been rigorously mathematically proven to reach the channel capacity limit. They possess advantages such as simple decoding and excellent performance, and have been widely used in communication systems. The Simplified Serial Cancellation List (SSCL) decoding algorithm for polar codes reconstructs the codeword to be decoded according to multiple node types, transforming the decoding method from the traditional single-bit decision to a one-time multi-bit decision. This multi-bit node-based decoding method allows the decoder to terminate the LLR iteration calculation at a higher log-likelihood ratio (LLR) level, directly obtaining bit estimates for multiple codewords. This eliminates redundant calculations, significantly increases the decoder's decoding efficiency, and causes almost no loss in error performance. However, because the lengths of various nodes are not the same, the distribution levels of the nodes are also not the same, which leads to a high degree of complexity in the number of LLR iteration operations and the updating and interpretation of partial sums. This makes it difficult to achieve low hardware area and high throughput in the implementation of the SSCL decoding algorithm, thus limiting the application of SSCL decoders. Summary of the Invention

[0003] To address the aforementioned problems in the prior art, this invention proposes a method and apparatus for updating LLR and partial sums in SSCL decoding, thereby improving the throughput of the SSCL decoder and reducing its hardware area.

[0004] The present invention provides a method for updating LLR and partial sums in SSCL decoding, comprising:

[0005] Step 1: Based on the current decoding node i+1 f / g control signal CTRL i+1 For the corresponding bit value at the current level, select either the f function or the g function to calculate the LLR sequence required to determine the current decoding node;

[0006] Step 2: Select the L LLR values ​​with the smallest absolute values ​​in the LLR sequence to obtain the position index sequence I of the L LLR values ​​with the smallest absolute values ​​in the LLR sequence;

[0007] Step 3: Perform extended decoding decision on the current decoding node to obtain the extended decoding path sequence codeswords_pm;

[0008] Step 4: Calculate the final candidate decoding path using the existing extended decoding path sequence;

[0009] Step 5: Calculate the f / g control signal for the next node based on the node length and f / g control signal of the current decoding node;

[0010] Step 6: Using the final candidate decoding path sequence and the f / g control signal of the next node, update the partial sum and sequence of each candidate decoding path of the next node;

[0011] Step 7: Perform CRC check on each candidate decoding path in the final candidate decoding path sequence; if the CRC check result of a candidate decoding path is 0, select the candidate decoding path with the CRC check result of 0 as the final decoding path; if the CRC check results of all candidate decoding paths are not 0, select the candidate decoding path with the smallest path metric value as the final decoding path.

[0012] Furthermore, step one includes:

[0013] If the j-th bit of the current decoding node's f / g control signal is 0, calculate the LLR sequence of the next level using the f function and the current level's LLR sequence;

[0014]

[0015] If the j-th bit of the current decoding node's f / g control signal is 1, calculate the LLR sequence of the next level using the g function and the current level's LLR sequence;

[0016]

[0017] Use the calculated LLR sequence of the next level as the LLR sequence of the current level, and repeat this step until the LLR sequence R of the current decoding node is obtained. n ;

[0018] in, The q-th LLR value at level j+1; This is the q-th LLR value of level j; For level j, the first Each LLR value, where level j represents the current level; ps q This is the partial sum corresponding to the q-th LLR value of level j.

[0019] Furthermore, step four includes:

[0020] Among the existing extended decoding paths, select the extended decoding path with the smallest path metric value among the L paths as the candidate decoding path;

[0021] For the candidate decoding paths, steps one through four are executed respectively to obtain the complete extended decoding path sequence Decode_path;

[0022] The L extended decoding paths with the smallest path metric values ​​in `Decode_path` are selected as the final candidate decoding path sequence `Decode_path`. final .

[0023] Furthermore, step five includes:

[0024] According to node i+1 Node length B i+1 Get CTRL i+1 The valid field for temp;

[0025]

[0026] Pad temp with zeros on the right to make its bit width log2N, and obtain CTRL. i+2 ;

[0027]

[0028] Among them, CTRL i+1 For the current decoding node's f / g control signal, CTRL i+2 The f / g control signal for the next decoding node; N is the length of the codeword to be decoded; CTRL i+1 [log2N:1] indicates retrieving CTRL. i+1 The bits in the sequence are from log2N to bit 1, and so on.

[0029] Furthermore, step six includes:

[0030] Calculate the partial sum sequence PSUM of the next decoding node. i+2 ;

[0031]

[0032] Based on node length B i+2 and CTRL i+2 The update control signal PSUM_Valid for calculating the partial sum. i+2 ;

[0033]

[0034] According to the PSUM_Valid i+2 Update the PSUM i+2 ;

[0035]

[0036] n = {1, 2, ..., log₂N}

[0037] Among them, ps n For the partial sum of the nth level, For ps n The generator matrix is ​​denoted by , where num represents the latest decoded bits, and N is the length of the codeword to be decoded.

[0038] An LLR and partial update apparatus for SSCL decoding according to the present invention includes:

[0039] The node information acquisition module is used by the decoder to obtain the codeword sequence A to be decoded and the level 1 LLR sequence R1 from the channel;

[0040] The LLR calculation module is used to calculate based on the current decoding node. i+1 f / g control signal CTRL i+1 For the corresponding bit value at the current level, select either the f function or the g function to calculate the LLR sequence required to determine the current decoding node;

[0041] The LLR selection module is used to select R. n The L LLR values ​​with the smallest absolute values ​​are obtained in R. n The position index sequence I in the middle;

[0042] The extended decoding path calculation module is used to calculate the current decoding path for the node. i+1 Perform extended decoding to determine the node. i+1 The extended decoding path sequence codeswords_pm;

[0043] The candidate decoding path selection module is used to calculate the final candidate decoding path Decode_path using the existing extended decoding path sequence codewords_pm. final ;

[0044] The f / g control signal update module is used to update the current decoding node. i+1 Node length and CTRL i+1 Calculate the f / g control signal CTRL for the next node. i+2 ;

[0045] Partial and updated modules for utilizing Decode_path final and CTRL i+2 Update the partial sum sequence PSUM of each candidate decoding path for the next node. i+2 ;

[0046] The final decoding path selection module is used to select the final candidate decoding path sequence Decode_path. final Each candidate decoding path is subjected to CRC verification to obtain the final decoding path;

[0047] If the CRC check result of a candidate decoding path is 0, the candidate decoding path with the CRC check result of 0 is selected as the final decoding path; if the CRC check result of all candidate decoding paths is not 0, the candidate decoding path with the smallest path metric value is selected as the final decoding path.

[0048] Furthermore, the LLR calculation module includes:

[0049] Control signal judgment unit, used to judge node i+1 The f and g operation control signals CTRL i+1 Check if the j-th bit is 0; if so, calculate the next level LLR sequence through the f computing unit; otherwise, calculate the next level LLR sequence through the g computing unit.

[0050] The f-computation unit is used to compute the LLR sequence of the next level using the f function and the LLR sequence of the current level;

[0051]

[0052] The g computation unit is used to compute the LLR sequence of the next level using the g function and the LLR sequence of the current level;

[0053]

[0054] in, The q-th LLR value at level j+1; This is the q-th LLR value of level j; For level j, the first Each LLR value, where level j represents the current level; ps q This is the partial sum corresponding to the q-th LLR value of level j.

[0055] Furthermore, the candidate decoding path selection module includes:

[0056] The candidate decoding path selection unit is used to select the L extended decoding path with the smallest path metric value from the existing extended decoding paths as a candidate decoding path, and send it to the LLR calculation module to perform extended decoding to obtain the candidate decoding path sequence Decode_path.

[0057] The final candidate path acquisition unit is used to select the L extended decoding paths with the smallest path metric values ​​in Decode_path as the final candidate decoding path sequence Decode_path. final .

[0058] Furthermore, the control signal update modules for f and g include:

[0059] Valid field retrieval unit, used to retrieve fields based on node i+1 Node length B i+1 Get CTRL i+1 The valid field for temp;

[0060]

[0061] The control signal update unit is used to pad temp with zeros on the right, making its bit width log2N, and to obtain CTRL. i+2 ;

[0062]

[0063] Among them, CTRL i+1 For the current decoding node's f / g control signal, CTRL i+2 The f / g control signal for the next decoding node; N is the length of the codeword to be decoded; CTRL i+1 [log2N:1] indicates retrieving CTRL. i+1 The bits in the sequence are from log2N to bit 1, and so on.

[0064] Furthermore, the aforementioned part and update module include:

[0065] Partial sum sequence computation unit, used to compute the partial sum sequence PSUM of the next node. i+2 ;

[0066]

[0067] Effective signal calculation unit, used to calculate based on node length B i+2 and control signal CTRL i+2 The update control signal PSUM_Valid for calculating the partial sum. i+2 ;

[0068]

[0069] Partial and update units, used according to the PSUM_Valid i+2 Update the PSUM i+2 ;

[0070]

[0071] n = {1, 2, ..., log₂N}

[0072] Among them, ps n For the partial sum of the nth level, For ps n The generator matrix is ​​denoted by , where num represents the latest decoded bits, and N is the length of the codeword to be decoded.

[0073] In the technical solution of this invention, the effective rules of decoding are utilized to control the operation of the LLR level based on the control signals of the f-function and g-function, as well as the node length. The operation control signals of the f-function and g-function are obtained using the prior known node length. Based on the control signals, the single-bit value at the corresponding position is used to determine whether the f-function and g-function are used for the calculation of each LLR level. Utilizing the effective rules of decoding, the control signals of the f-function and g-function, along with the node length, are used to control whether the partial sum data of each level is updated to the current new value or remains the old value. The above LLR and partial sum data update control method only involves simple operations such as AND, OR, and addition of single-bit data, and the related update control signals can form a one-hot code, allowing the selection structure to compare only one bit. This speeds up hardware execution, improves the calculation speed of LLR and partial sum update control, reduces decoder hardware resource consumption, and increases decoder throughput. Attached Figure Description

[0074] Figure 1 This is a schematic diagram of the binary tree structure of the codeword to be decoded in the technical solution of this invention;

[0075] Figure 2 This is a flowchart of the method in specific embodiment 1 of the present invention;

[0076] Figure 3 This is a schematic diagram of the device structure in specific embodiment 2 of the present invention; Detailed Implementation

[0077] To better illustrate the technical solution of the present invention, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0078] In the following specific embodiments of the present invention, the length of the polar code to be decoded obtained from the channel is N. The codeword to be decoded contains two cases: information bits and frozen bits. Frozen bits are directly determined to be 0 based on a priori known position sequence; information bits, however, need to be determined based on their corresponding LLR values. For example... Figure 2 As shown, the LLR value calculation is performed hierarchically, with the level determined by the length of the codeword to be decoded. A polar code with a codeword length of N has a total of log₂N LLR value sequences. The levels are numbered from top to bottom in ascending order. The top-level LLR sequence is R₁ = {llr₁, llr₂, ..., llrₘ}.N The SSCL decoding algorithm has a candidate list of L bits, and the codeword to be decoded contains four types of special nodes: R0 nodes (fully frozen bits), R1 nodes (fully information bits), REP nodes (the last bit is an information bit, and the rest are frozen bits), and SPC nodes (the first bit is a frozen bit, and the rest are information bits). These four types of special nodes can completely represent the codeword to be decoded. Specific Implementation Example 1

[0080] This embodiment is a preferred implementation of the LLR and partial update method in SSCL decoding of the present invention.

[0081] See Figure 2 ,like Figure 2 As shown, the method in this embodiment includes:

[0082] S101, The decoder obtains the codeword sequence A to be decoded and the level 1 LLR sequence R1 from the channel;

[0083] A = {node1, node2, ..., node} x}

[0084] node i ={T i B i}

[0085] Among them, node i Let T represent the i-th special node. i for node i Node type, B i for node i The node length is x, and the number of nodes contained in A is x.

[0086] S102. Calculate the decision node using the f and g functions. i+1 Required LLR sequence R n ;

[0087] In this specific embodiment, this step may further include:

[0088] S1021, Determine CTRL i+1 If the j-th bit is 0, proceed to step S1022; otherwise, proceed to step S1023.

[0089] S1022. Calculate the LLR sequence of the next level using the f function and the LLR sequence of the current level;

[0090]

[0091] Among them, CTRLi+1 for node i+1 The control signals for the f and g operations, The q-th LLR value at level j+1; This is the q-th LLR value of level j; For level j, the first One LLR value; execute step S1024;

[0092] S1023. Calculate the LLR sequence of the next level using the g function and the LLR sequence of the current level;

[0093]

[0094] Among them, ps q This is the partial sum corresponding to the q-th LLR value of level j.

[0095] S1024. Set the level of the LLR sequence obtained in step S1022 or S1023 to the current level, and repeat steps S1021 to S1023 until the node is obtained. i+1 LLR sequence R at the corresponding level n ;

[0096] S103, Select R n The L LLR values ​​with the smallest absolute values ​​are obtained in R. n The position index sequence I in the middle;

[0097] I = {index L ,index L-1 ,…,index1}

[0098] In I, the position indices are arranged from largest to smallest absolute value of their corresponding LLR values, with index1 being the LLR value with the smallest absolute value in R. n The position index in the middle, index L The Lth smallest absolute value of LLR in R n The position index in the middle.

[0099] S104. For the current decoding node... i+1 Perform extended decoding to determine the node. i+1 The extended decoding path sequence codeswords_pm.

[0100] In this specific embodiment, this step may further include:

[0101] S1041, Determine node i+1If the node type is R0, proceed to step S1042; if the node type is R1, proceed to step S1043; if the node type is SPC, proceed to step S1044; if the node type is REP, proceed to step S1045.

[0102] S1042, R n Extended decoding is performed using the R0 node method, and the path metric value of each extended decoding path is calculated to obtain codewords_pm;

[0103]

[0104] α k =0

[0105] llr k ∈R n , 1≤k≤B i+1 0 < l ≤ L

[0106] Among them, penalty k α is the path penalty value. k For the decision bit;

[0107] S1043, R n Extended decoding is performed using the R1 node method, and the path metric value of each extended decoding path is calculated to obtain the extended decoding path sequence codewords_pm;

[0108] For R n Perform hard decision analysis and calculate the path metric to obtain the optimal decoding path.

[0109]

[0110] llr k ∈R n , 1≤k≤B i+1

[0111] According to R n The L-1 LLR values ​​with the smallest absolute values ​​are used to perform L-1 extension decoding on the optimal decoding path to obtain L-1 extension decoding paths.

[0112] α k =~α k

[0113]

[0114] penalty k =|llr k |

[0115] llrk ∈R n , k∈I

[0116] Where ~ represents a bit flipping operation;

[0117] Based on the path metric value of each decoding path The optimal decoding path and the extended decoding path are sorted in descending order to obtain codewords_pm;

[0118]

[0119] S1044, R n Extended decoding is performed using the SPC node approach, and the path metric for each extended decoding path is calculated to obtain codewords_pm;

[0120] For R n Perform hard decision-making and calculate the path metric to obtain the optimal decoding path.

[0121]

[0122] llr k ∈R n , 1≤k≤B i+1

[0123] Perform a check calculation on the node codeword to obtain the check value λ;

[0124]

[0125] If λ≠0, update the optimal decoding path;

[0126]

[0127] Based on the LLR value corresponding to each position index in I, the optimal decoding path is extended by L-1 times to obtain L-1 extended decoding paths.

[0128]

[0129] Where k1 and k2 are the L-1 pairs of LLR values ​​with the smallest sum of the absolute values ​​of the LLR corresponding to the position indices in I.

[0130] Based on the path metric value of each decoding path The optimal decoding path and the extended decoding path are sorted in descending order to obtain codewords_pm;

[0131]

[0132] S1045, Rn Extended decoding is performed according to the REP node method, and the path metric value of each extended decoding path is calculated to obtain codewords_pm;

[0133] Calculate the path metric PM for candidate paths in all-zero decoding. 0 ;

[0134]

[0135] llr k ∈R n , 1≤k≤B i+1

[0136] Calculate the path metric PM for candidate paths in all-one decoding. 1 ;

[0137]

[0138] llr k ∈R n , 1≤k≤B i+1

[0139] Get codewords_pm;

[0140]

[0141] S1046. Update each decoding path in codeswords_pm using the generator matrix;

[0142]

[0143] in, To generate a matrix, calculate log2B from the fundamental matrix F. i+1 The Kronecker product of order 1 is obtained.

[0144] S105. Using the existing extended decoding path sequence codewords_pm, calculate the final candidate decoding path;

[0145] S1051. Among the existing extended decoding paths, select the extended decoding path with the smallest path metric value among the L paths as the candidate decoding path.

[0146] S1052. For the candidate decoding paths, execute steps S102 to S105 respectively to obtain the complete extended decoding path sequence Decode_path;

[0147] Decode_path={codewords_pm L ,codewords_pm L-1,…,codewords_pm1}

[0148] S1053. Select the L extended decoding paths with the smallest path metric values ​​in Decode_path as the final candidate decoding path sequence Decode_path. final ;

[0149] S106. Based on the current decoding node i+1 Node length and control signal CTRL i+1 Calculate the control signal CTRL for the next node. i+2 ;

[0150] In this specific embodiment, this step may further include:

[0151] According to node i+1 B i+1 Get CTRL i+1 The valid field for temp;

[0152]

[0153] Among them, CTRL i+1 [log2N:1] indicates retrieving CTRL. i+1 The bits in the sequence are from log2N to bit 1, and so on.

[0154] Pad temp with zeros on the right to make its bit width log2N, and obtain CTRL. i+2 ;

[0155]

[0156] S107, Using Decode_path final and CTRL i+2 Update the partial sum sequence PSUM of each candidate decoding path for the next node. i+2 ;

[0157] In this specific embodiment, this step may further include:

[0158] S1071. Calculate the partial sum sequence PSUM of the next node. i+2 ;

[0159]

[0160] Among them, ps n For the partial sum of the nth level, For ps n The generator matrix, where num is the latest decoded num bits;

[0161] S1072, Based on node length B i+2 and control signal CTRL i+2 The update control signal PSUM_Valid for calculating the partial sum. i+2 ;

[0162]

[0163] S1073, According to the PSUM_Valid i+2 Update the PSUM i+2 ;

[0164]

[0165] n = {1, 2, ..., log₂N}

[0166] Repeat steps S102 to S107 until all nodes are decoded;

[0167] S108. Decode_path for the final candidate decoding path sequence respectively. final Each candidate decoding path is subjected to CRC verification to obtain the final decoding path;

[0168] If the CRC check result of a candidate decoding path is 0, the candidate decoding path with the CRC check result of 0 is selected as the final decoding path; if the CRC check result of all candidate decoding paths is not 0, the candidate decoding path with the smallest path metric value is selected as the final decoding path.

[0169] In this specific embodiment, the specific calculation method for the CRC check in this step can use the publicly disclosed CRC check method, such as the paper "Optimized FPGA Implementation of the CRC Using Parallel Pipelining Architecture" published in the 2019 International Conference on Advanced Science and Engineering. Specific Implementation Example 2

[0171] This embodiment is a preferred implementation of the LLR and part of the update device in the SSCL decoding of the present invention.

[0172] See Figure 3 ,like Figure 3 As shown, the apparatus of this embodiment includes:

[0173] The node information acquisition module is used by the decoder to obtain the codeword sequence A to be decoded and the level 1 LLR sequence R1 from the channel;

[0174] A = {node1, node2, ..., node} x}

[0175] node i ={T i B i}

[0176] Among them, node i Let T represent the i-th special node. i for node i Node type, B i for node i The node length is x, and the number of nodes contained in A is x.

[0177] The LLR calculation module is used to calculate the decision node using the f and g functions. i+1 Required LLR sequence R n ;

[0178] In this specific embodiment, this module may further include:

[0179] Control signal judgment unit, used to judge node i+1 The f and g operation control signals CTRL i+1 Check if the j-th bit is 0; if so, calculate the next level LLR sequence through the f computing unit; otherwise, calculate the next level LLR sequence through the g computing unit.

[0180] The f-computation unit is used to compute the LLR sequence of the next level using the f function and the LLR sequence of the current level;

[0181]

[0182] in, The q-th LLR value at level j+1; This is the q-th LLR value of level j; For level j, the first One LLR value;

[0183] The g computation unit is used to compute the LLR sequence of the next level using the g function and the LLR sequence of the current level;

[0184]

[0185] Among them, ps q This is the partial sum corresponding to the q-th LLR value of level j.

[0186] The LLR selection module is used to select R. n The L LLR values ​​with the smallest absolute values ​​are obtained in R. n The position index sequence I in the middle;

[0187] I = {index L ,index L-1 ,…,index1}

[0188] In I, the position indices are arranged from largest to smallest absolute value of their corresponding LLR values, with index1 being the LLR value with the smallest absolute value in R. n The position index in the middle, index L The Lth smallest absolute value of LLR in R n The position index in the middle.

[0189] The extended decoding path calculation module is used to calculate the current decoding path for the node. i+1 Perform extended decoding to determine the node. i+1 The extended decoding path sequence codeswords_pm.

[0190] In this specific embodiment, this module may further include:

[0191] The decoding type selection unit is used to determine the node type of the current decoding node and select the corresponding extended decoding method according to the node type;

[0192] The R0 node decoding unit is used to decode R. n Extended decoding is performed using the R0 node method, and the path metric value of each extended decoding path is calculated to obtain codewords_pm;

[0193]

[0194] α k =0

[0195] llr k ∈R n , 1≤k≤B i+1 0 < l ≤ L

[0196] Among them, penalty k α is the path penalty value. k For the decision bit;

[0197] R1 node decoding unit, used for R nExtended decoding is performed using the R1 node method, and the path metric value of each extended decoding path is calculated to obtain the extended decoding path sequence codewords_pm;

[0198] For R n Perform hard decision analysis and calculate the path metric to obtain the optimal decoding path.

[0199]

[0200] llr k ∈R n , 1≤k≤B i+1

[0201] According to R n The L-1 LLR values ​​with the smallest absolute values ​​are used to perform L-1 extension decoding on the optimal decoding path to obtain L-1 extension decoding paths.

[0202] α k =~α k

[0203]

[0204] penalty k =|llr k |

[0205] llr k ∈R n , k∈I

[0206] Where ~ represents a bit flipping operation;

[0207] Based on the path metric value of each decoding path The optimal decoding path and the extended decoding path are sorted in descending order to obtain codewords_pm;

[0208]

[0209] SPC node decoding unit, used for R n Extended decoding is performed using the SPC node approach, and the path metric for each extended decoding path is calculated to obtain codewords_pm;

[0210] For R n Perform hard decision analysis and calculate the path metric to obtain the optimal decoding path.

[0211]

[0212]

[0213] llr k ∈R n , 1≤k≤B i+1

[0214] Perform a check calculation on the node codeword to obtain the check value λ;

[0215]

[0216] If λ≠0, update the optimal decoding path;

[0217]

[0218] Based on the LLR value corresponding to each position index in I, the optimal decoding path is extended by L-1 times to obtain L-1 extended decoding paths.

[0219]

[0220] Where k1 and k2 are the L-1 pairs of LLR values ​​with the smallest sum of the absolute values ​​of the LLR corresponding to the position indices in I.

[0221] Based on the path metric value of each decoding path The optimal decoding path and the extended decoding path are sorted in descending order to obtain codewords_pm;

[0222]

[0223] REP node decoding unit, used for R n Extended decoding is performed according to the REP node method, and the path metric value of each extended decoding path is calculated to obtain codewords_pm;

[0224] Calculate the path metric PM for candidate paths in all-zero decoding. 0 ;

[0225]

[0226] llr k ∈R n , 1≤k≤B i+1

[0227] Calculate the path metric PM for candidate paths in all-one decoding. 1 ;

[0228]

[0229] llr k ∈R n , 1≤k≤B i+1

[0230] Get codewords_pm;

[0231]

[0232] The decoding path update unit is used to update each decoding path in codeswords_pm;

[0233]

[0234] in, To generate a matrix, calculate log2B from the fundamental matrix F. i+1 The Kronecker product of order 1 is obtained.

[0235] The candidate decoding path selection module is used to calculate the final candidate decoding path Decode_path using the existing extended decoding path sequence codewords_pm. final ;

[0236] In this specific embodiment, this module may further include:

[0237] The candidate decoding path selection unit is used to select the L extended decoding path with the smallest path metric value from the existing extended decoding paths as a candidate decoding path, and send it to the LLR calculation module to perform extended decoding to obtain the candidate decoding path sequence Decode_path.

[0238] Decode_path={codewords_pm L ,codewords_pm L-1 ,…,codewords_pm1}

[0239] The final candidate path acquisition unit is used to select the L extended decoding paths with the smallest path metric values ​​in Decode_path as the final candidate decoding path sequence Decode_path. final ;

[0240] The f / g control signal update module is used to update the current decoding node. i+1 Node length and CTRL i+1 Calculate the CTRL of the next node. i+2 ;

[0241] In this specific embodiment, this module may further include:

[0242] Valid field retrieval unit, used to retrieve fields based on node i+1 B i+1 Get CTRL i+1The valid field for temp;

[0243]

[0244] Among them, CTRL i+1 [log2N:1] indicates retrieving CTRL. i+1 The bits in the sequence are from log2N to bit 1, and so on.

[0245] The control signal update unit is used to pad temp with zeros on the right, making its bit width log2N, and to obtain CTRL. i+2 ;

[0246]

[0247] Partial and update modules, utilizing Decode_path final and CTRL i+2 Update the partial sum sequence PSUM of each candidate decoding path for the next node. i+2 ;

[0248] In this specific embodiment, this module may further include:

[0249] Partial sum sequence computation unit, used to compute the partial sum sequence PSUM of the next node. i+2 ;

[0250]

[0251]

[0252] Among them, ps n For the partial sum of the nth level, For ps n The generator matrix, where num is the latest decoded num bits;

[0253] Effective signal calculation unit, used to calculate based on node length B i+2 and control signal CTRL i+2 The update control signal PSUM_Valid for calculating the partial sum. i+2 ;

[0254]

[0255] Partial and update units, used according to the PSUM_Valid i+2 Update the PSUM i+2 ;

[0256]

[0257] n = {1, 2, ..., log₂N}

[0258] The final decoding path selection module is used to select the final candidate decoding path sequence Decode_path. final Each candidate decoding path is subjected to CRC verification to obtain the final decoding path;

[0259] If the CRC check result of a candidate decoding path is 0, the candidate decoding path with the CRC check result of 0 is selected as the final decoding path; if the CRC check result of all candidate decoding paths is not 0, the candidate decoding path with the smallest path metric value is selected as the final decoding path.

[0260] In this specific embodiment, the specific calculation method for the CRC check of this module can use the publicly disclosed CRC check method, such as the paper "Optimized FPGA Implementation of the CRC Using Parallel Pipelining Architecture" published in the 2019 International Conference on Advanced Science and Engineering.

[0261] In the specific embodiments of the present invention described above, the f and g operation control signals of the current decoding node are first calculated using the prior known node length. Based on the f and g control signals and the node length, the partial sums at each level are updated. In the technical solution of the specific embodiments of the present invention, the update control method for LLR and partial sum data only involves single-bit AND, OR, and simple addition operations. The related update control signals can be easily composed of one-hot codes, so that the selection structure only needs to compare one bit, thereby further accelerating the hardware execution speed. Through the technical solution of the present invention, the calculation speed of LLR and partial sum update control is improved, the hardware resource consumption of the decoder is reduced, and the throughput of the decoder is improved.

[0262] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for updating LLR and partial sums in SSCL decoding, characterized in that, include: Step 1: Based on the current decoding node f / g control signal For the corresponding bit value at the current level, select either the f function or the g function to calculate the LLR sequence required to determine the current decoding node; If the j-th bit of the current decoding node's f / g control signal is 0, calculate the LLR sequence of the next level using the f function and the current level's LLR sequence; If the j-th bit of the current decoding node's f / g control signal is 1, calculate the LLR sequence of the next level using the g function and the current level's LLR sequence; Use the calculated LLR sequence of the next level as the LLR sequence of the current level, and repeat this step until the LLR sequence of the level where the current decoding node is located is obtained. ; Step 2: Select the L LLR values ​​with the smallest absolute values ​​in the LLR sequence to obtain the position index sequence I of the L LLR values ​​with the smallest absolute values ​​in the LLR sequence; Step 3: Perform extended decoding decision on the current decoding node to obtain the extended decoding path sequence. ; Step 4: Calculate the final candidate decoding path using the existing extended decoding path sequence; Step 5: Calculate the f / g control signal for the next node based on the node length and f / g control signal of the current decoding node; according to Node length ,get The valid field for temp; Pad temp with zeros on the right to make its bit width 1. ,get ; Step 6: Using the final candidate decoding path sequence and the f / g control signal of the next node, update the partial sum and sequence of each candidate decoding path of the next node; Calculate the partial sum sequence of the next decoding node. ; Based on node length as well as The calculation of the update control signal of the part and the sum ; According to the above Update the above ; in, For level j+1, the first One LLR value; For level j, the first One LLR value; For level j, the first There are several LLR values, where level j represents the current level; For level j, the first The partial sum corresponding to each LLR value; This is the f / g control signal for the current decoding node. is the f / g control signal for the next decoding node; N is the length of the codeword to be decoded; Indicates taking bits in To bit 1, and so on; For the first The hierarchical structure and results for The generating matrix, For the latest decoding One decoded bit; for The decision bits are in the code, and N is the length of the codeword to be decoded.

2. The method according to claim 1, characterized in that, Step four includes: Among the existing extended decoding paths, select the extended decoding path with the smallest path metric value among the L paths as the candidate decoding path; For the candidate decoding paths, perform steps one through four respectively to obtain the complete extended decoding path sequence. ; choose The L extended decoding paths with the smallest path metric values ​​are selected as the final candidate decoding path sequence. .

3. A device for updating and partially updating LLR in SSCL decoding, characterized in that, include: The node information acquisition module is used by the decoder to obtain the codeword sequence A to be decoded and the LLR sequence of level 1 from the channel. ; The LLR calculation module is used to calculate based on the current decoding node. f / g control signal For the corresponding bit value at the current level, select either the f function or the g function to calculate the LLR sequence required to determine the current decoding node, including: Control signal judgment unit, used to judge of and Operational control signals Is the j-th bit 0? If so, by... The computational unit computes the LLR sequence of the next level; otherwise, it computes it through... The computing unit computes the LLR sequence of the next level; Computing unit, used to utilize The function and the current level's LLR sequence are used to calculate the next level's LLR sequence; Computing unit, used to utilize The function and the current level's LLR sequence are used to calculate the next level's LLR sequence; LLR selection module, used to select The L LLR values ​​with the smallest absolute values ​​are obtained. The position index sequence I in the middle; The extended decoding path calculation module is used to calculate the current decoding path for the current decoding node. Perform extended decoding decision to obtain Extended decoding path sequence ; The candidate decoding path selection module is used to utilize existing extended decoding path sequences. The final candidate decoding path is calculated. ; The f / g control signal update module is used to update the current decoding node. node length and Calculate the f / g control signal for the next node. ,include: Valid field retrieval unit, used to retrieve data based on... Node length ,get The valid field for temp; The control signal update unit is used to pad temp with zeros on the right side to make its bit width 1. ,get ; Partial and updated modules for utilizing and Update the partial sum sequence of each candidate decoding path for the next node. ,include: Partial sum sequence computation unit, used to compute the partial sum sequence of the next node. ; Effective signal calculation unit, used to calculate based on node length and control signals The calculation of the update control signal of the part and the sum ; Partial and updating units, used according to the Update the above ; in, For level j+1, the first One LLR value; For level j, the first One LLR value; For level j, the first There are several LLR values, where level j represents the current level; For level j, the first The partial sum corresponding to each LLR value; This is the f / g control signal for the current decoding node. is the f / g control signal for the next decoding node; N is the length of the codeword to be decoded; Indicates taking bits in To bit 1, and so on; For the first The hierarchical structure and results for The generating matrix, For the latest decoding 1 decoded bit; N is the length of the codeword to be decoded.

4. The apparatus according to claim 3, characterized in that, The candidate decoding path selection module includes: The candidate decoding path selection unit is used to select the L extended decoding path with the smallest path metric value from the existing extended decoding paths as candidate decoding paths, and send them to the LLR calculation module for extended decoding to obtain a sequence of candidate decoding paths. ; The final candidate path acquisition unit is used for selection. The L extended decoding paths with the smallest path metric values ​​are selected as the final candidate decoding path sequence. .

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