Field programmable gate array (FPGA)-based antenna feed system frequency standing-wave ratio measurement method

Abstract

A method for measuring the frequency standing-wave ratio of an antenna feeder system based on an FPGA is characterized by comprising the following steps that 1, the FPGA outputs a sine wave with a single frequency to serve as a transmitting reference frequency sweeping signal; step 2, a signal sampling module samples a transmitting signal and a reflecting signal returned by the radio frequency circuit; 3, an anti-interference narrowband filtering module carries out preliminary filtering on the signals obtained through sampling; 4, the DDC module carries out frequency mixing processing on the filtering data to obtain zero intermediate frequency data; step 5, performing secondary filtering on the zero intermediate frequency data by a low-pass filter to obtain a direct current component; step 6, respectively constructing complex signals by the direct current components of the transmitting signal and the reflecting signal; step 7, dividing the two complex signals to obtain a reflection coefficient; and 8, performing Fourier transform and subsequent operation on the reflection coefficient to obtain a standing-wave ratio. The method has the advantages that the influence of external interference is effectively reduced, and the accuracy of a standing-wave ratio measurement result is improved.

Description

Technical Field

[0001] The invention relates to the technical field of wireless communications, and in particular to a method for measuring the frequency standing wave ratio of an antenna feed system based on FPGA. Background Art

[0002] In wireless communication, antennas and feeders are important parts that connect antennas and devices. They can carry signal transmission. Due to the influence of various factors such as environment, equipment and installation, standing wave phenomenon often occurs in antennas and feeders. Standing wave ratio is an important indicator to measure the performance of antenna and feeder systems. It has an important impact on the transmission quality and efficiency of the system. Therefore, the research on the frequency standing wave ratio measurement method of antenna and feeder systems is particularly important.

[0003] The current method is to use a directional coupler to receive two signals, one for transmission and one for reflection, and then convert the frequency from the RF end to zero intermediate frequency to obtain the DC component to calculate the reflection coefficient and finally obtain the standing wave ratio. However, because it is directly converted to zero intermediate frequency, its anti-interference ability is insufficient.

[0004] Disadvantages of the existing technology: The existing antenna system frequency standing wave ratio measurement method has poor anti-interference ability, which leads to unstable measurement precision and poor measurement accuracy. Summary of the invention

[0005] The present invention provides an FPGA-based antenna feed system frequency standing wave ratio measurement method, which effectively reduces the influence of external interference and improves the accuracy of the standing wave ratio measurement result.

[0006] To achieve the above object, the present invention provides a method for measuring the frequency standing wave ratio of an antenna feed system based on FPGA, the key of which is to include the following steps:

[0007] Step 1: construct a frequency standing wave ratio measurement system based on FPGA, which includes an FPGA and a radio frequency circuit connected to the FPGA, and the radio frequency circuit is also connected to a device to be detected; the FPGA is provided with a reference signal transmitting module and a signal sampling module, and the signal sampling module is connected to an anti-interference narrowband filtering module;

[0008] The anti-interference narrowband filter module is sequentially connected to the first down-conversion DDC module, the first low-pass filter and then the reflection coefficient calculation module, and the anti-interference narrowband filter module is also sequentially connected to the second down-conversion DDC module, the second low-pass filter and then the reflection coefficient calculation module; the reflection coefficient calculation module is connected to the FFT and filtering processing module;

[0009] Step 2: The reference signal transmitting module transmits a frequency sweep signal S to the RF circuit, and the RF circuit divides the reference signal into a first transmitting signal s1 and a second transmitting signal s2, and performs signal processing on the second transmitting signal s2 to obtain a third transmitting signal a0, and sends it to the device to be detected;

[0010] The device to be detected acquires the third transmission signal a0, and feeds back a reflected signal b0 to the radio frequency circuit. The radio frequency circuit processes the reflected signal b0 to obtain a second reflected signal c, and transmits it to the FPGA.

[0011] Step 3: After the signal sampling module in the FPGA collects the first transmission signal s1 and the second reflection signal c, it passes them to the anti-interference narrowband filtering module;

[0012] Step 4: the anti-interference narrowband filtering module performs preliminary filtering on the first transmission signal s1 to obtain a first filtered signal, and transmits it to the first down-conversion DDC module;

[0013] The anti-interference narrowband filtering module performs preliminary filtering on the second reflected signal c to obtain a second filtered signal, and transmits it to the second down-conversion DDC module;

[0014] Step 5: the first down-conversion DDC module performs mixing processing on the first filtered signal to obtain first zero intermediate frequency data, and passes it to the first low-pass filter;

[0015] The second down-conversion DDC module performs mixing processing on the second filtered signal to obtain second zero intermediate frequency data, and passes it to the second low-pass filter;

[0016] Step 6: The first low-pass filter performs secondary filtering on the first zero intermediate frequency data to obtain a first DC component, and transmits it to a reflection coefficient calculation module;

[0017] The second low-pass filter performs secondary filtering on the second zero intermediate frequency data to obtain a second DC component, and transmits the second DC component to the reflection coefficient calculation module;

[0018] Step 7: The reflection coefficient calculation module constructs complex signals for the first DC component and the second DC component respectively to obtain a first complex signal and a second complex signal, and then divides the two complex signals to obtain a reflection coefficient, and transmits it to the FFT and filtering processing module;

[0019] Step 8: The FFT and filtering processing module performs Fourier transform and standing wave ratio calculation on the reflection coefficient to obtain a standing wave ratio value.

[0020] Through the above design, the reference signal transmitting module in the FPGA generates a single-tone signal as a swept frequency signal output, the RF circuit performs a preliminary down-conversion on the received second transmitting signal and transmits it to the device to be detected, and then the RF circuit performs a preliminary down-conversion on the first reflected signal fed back by the device to be detected to obtain a second reflected signal, so as to facilitate subsequent processing after FPGA sampling. After the FPGA samples the signal, it first performs a first-level anti-interference narrowband filtering, then down-converts it to zero frequency and obtains the DC component through low-pass filtering, and finally obtains the reflection coefficient after FFT and filtering, and then calculates the standing wave ratio based on the reflection coefficient.

[0021] The impact of external interference is reduced through multi-stage filtering, and subsequent processing is all handled inside the FPGA, reducing the cost and complexity of the hardware solution.

[0022] Preferably, in step 2, the radio frequency circuit is provided with two power dividers and a signal processing module;

[0023] The two power dividers obtain the frequency sweep signal S and divide it into a first transmit signal s1 and a second transmit signal s2, and then transmit the first transmit signal s1 to the FPGA and transmit the second transmit signal s2 to the signal processing module;

[0024] After the signal processing module processes the second transmission signal s2, it obtains a third transmission signal a0 and sends it to the device to be detected. The device to be detected feeds back a reflected signal b0 to the signal processing module. After the signal processing module processes the reflected signal b0, it obtains a second reflected signal c and transmits it to the FPGA.

[0025] The two power dividers are used to complete the division of the sweep frequency signal, and the signal processing module is used to realize the signal transmission and processing between the FPGA and the device to be detected.

[0026] Preferably, in step 2, the reference signal transmitting module transmits a frequency sweep signal S with a frequency of w(m). Since the signal after power division is a transmitting signal and the initial phase is different when the frequency point is switched, the expression of the first transmitting signal s1 is as follows:

[0027]

[0028] Where, s(m) is the first transmitted signal, m is the number of frequency sweep points, which is related to the measurement frequency bandwidth and the frequency sweep step; A1(m) is the amplitude of the transmitted signal, ω(m) is the angular frequency of the transmitted signal, and t is the time. is the initial phase of the transmitted signal;

[0029] Since the device to be detected has amplitude-phase linear characteristics, and the signal processing module has amplitude-phase linear characteristics, the second reflected signal c has only a linear change in amplitude and a linear increment in phase compared to the transmitted signal, so the expression of the second reflected signal c is as follows:

[0030]

[0031] Among them, A2(m)=k(m)A1(m), k(m) is the linear change rate of amplitude, It is the overall phase increment of all hardware circuits that the transmitted signal passes through before reaching the device to be detected and reflected back to the FPGA.

[0032] As a preference: in the step 5, when each time the frequency sweep signal is stably transmitted and received, the first down-conversion DDC module and the second down-conversion DDC module respectively perform the same down-conversion conversion on the first transmission signal s1 and the second reflection signal c, and the down-conversion carrier frequency is the current frequency sweep frequency w(m), and the digital down-conversion carrier expression is as follows:

[0033] c I (m) = B(m)cos(ω(m)t+γ(m))

[0034] c Q (m) = B(m)sin(ω(m)t+γ(m))

[0035] Among them, B(m) is the carrier amplitude, γ(m) is the phase of the carrier used in the mth frequency sweep, and c I (m), c Q (m) represents a digital down-converted carrier;

[0036] The first transmission signal s1 is down-converted to obtain transmission I and Q signals:

[0037]

[0038] When the working state is in a fixed frequency sweep state and the transmission and reception are stable, the I and Q signals are transmitted. and are all constants, i.e. the first DC component; and the other parts are high-frequency components with a frequency of 2ω(m);

[0039] The second reflected signal c is down-converted to obtain reflected I and Q signals:

[0040]

[0041] When the working state is in a fixed frequency sweep state and the transmission and reception are stable, the reflected I and Q signals and are all constants, namely the second DC component; and the other parts are high-frequency components with a frequency of 2ω(m).

[0042] Preferably, in step 6, a low-pass filter is used to perform low-pass filtering on the down-converted I and Q signals to extract the DC component each time the frequency sweep signal is stably transmitted and received;

[0043] Among them, the filtering result of the transmitted I and Q signals, that is, the first DC component is:

[0044]

[0045] The reflected I and Q signal filtering results, that is, the second DC component is:

[0046]

[0047] The filter introduces an amplitude shift set to 1.

[0048] Preferably, in step 7, the first DC component is constructed as a first complex signal as follows:

[0049]

[0050] The second DC component is constructed as a second complex signal as follows:

[0051]

[0052] Use the complex sequence f(m) to remove the complex sequence z(m) The term and the amplitude term B(m) give the final calculation sequence:

[0053]

[0054] Among them, I(m) represents the real part, Q(m) represents the imaginary part;

[0055] By extracting the real and imaginary parts in the complex division and reversing the sign of the imaginary part, the reflection coefficient expression can be obtained:

[0056]

[0057] Preferably, in step 8, the calibrated reflection coefficient Γ(f) of the device to be tested is obtained according to the calculated reflection coefficient and the calibration of the reflection coefficient at different frequencies. It is easy to know that the reflection coefficient is also a vector. The reflection coefficient is converted according to the standing wave ratio calculation formula:

[0058]

[0059] By performing modulo calculation on the complex number Γ(f), the standing wave ratio result VSWR(f) at the corresponding frequency f is obtained.

[0060] The beneficial effects of the present invention are as follows: the influence of external interference is reduced by multi-stage filtering, and the accuracy of the standing wave ratio measurement result is improved; and the subsequent processing is all processed inside the FPGA, which reduces the cost and complexity of the hardware solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 It is a schematic diagram of the process of the present invention;

[0062] Figure 2 It is a schematic diagram of the structure of the present invention. DETAILED DESCRIPTION

[0063] The present invention is further described in detail below in conjunction with the accompanying drawings and specific examples. The following examples or drawings are used to illustrate the present invention, but are not used to limit the scope of the present invention.

[0064] like Figure 1 , Figure 2 As shown: A method for measuring the frequency standing wave ratio of an antenna feed system based on FPGA, comprising the following steps:

[0065] Step 1: construct a frequency standing wave ratio measurement system based on FPGA, which includes an FPGA and a radio frequency circuit connected to the FPGA, and the radio frequency circuit is also connected to a device to be detected; the FPGA is provided with a reference signal transmitting module and a signal sampling module, and the signal sampling module is connected to an anti-interference narrowband filtering module;

[0066] The anti-interference narrowband filter module is sequentially connected to the first down-conversion DDC module, the first low-pass filter and then the reflection coefficient calculation module, and the anti-interference narrowband filter module is also sequentially connected to the second down-conversion DDC module, the second low-pass filter and then the reflection coefficient calculation module; the reflection coefficient calculation module is connected to the FFT and filtering processing module;

[0067] Step 2: The reference signal transmitting module transmits a frequency sweep signal S to the RF circuit, and the RF circuit divides the reference signal into a first transmitting signal s1 and a second transmitting signal s2, and performs signal processing on the second transmitting signal s2 to obtain a third transmitting signal a0, and sends it to the device to be detected;

[0068] The device to be detected acquires the third transmission signal a0, and feeds back a reflected signal b0 to the radio frequency circuit. The radio frequency circuit processes the reflected signal b0 to obtain a second reflected signal c, and transmits it to the FPGA.

[0069] Step 3: After the signal sampling module in the FPGA collects the first transmission signal s1 and the second reflection signal c, it passes them to the anti-interference narrowband filtering module;

[0070] Step 4: the anti-interference narrowband filtering module performs preliminary filtering on the first transmission signal s1 to obtain a first filtered signal, and transmits it to the first down-conversion DDC module;

[0071] The anti-interference narrowband filtering module performs preliminary filtering on the second reflected signal c to obtain a second filtered signal, and transmits the second filtered signal to the second down-conversion DDC module;

[0072] Step 5: the first down-conversion DDC module performs mixing processing on the first filtered signal to obtain first zero intermediate frequency data, and passes it to the first low-pass filter;

[0073] The second down-conversion DDC module performs mixing processing on the second filtered signal to obtain second zero intermediate frequency data, and passes it to the second low-pass filter;

[0074] Step 6: The first low-pass filter performs secondary filtering on the first zero intermediate frequency data to obtain a first DC component, and transmits it to a reflection coefficient calculation module;

[0075] The second low-pass filter performs secondary filtering on the second zero intermediate frequency data to obtain a second DC component, and transmits the second DC component to the reflection coefficient calculation module;

[0076] Step 7: The reflection coefficient calculation module constructs complex signals for the first DC component and the second DC component respectively to obtain a first complex signal and a second complex signal, and then divides the two complex signals to obtain a reflection coefficient, and transmits it to the FFT and filtering processing module;

[0077] Step 8: The FFT and filtering processing module performs Fourier transform and standing wave ratio calculation on the reflection coefficient to obtain a standing wave ratio value.

[0078] In the step 2, the radio frequency circuit is provided with two power dividers and a signal processing module;

[0079] The two power dividers obtain the frequency sweep signal S and divide it into a first transmit signal s1 and a second transmit signal s2, and then transmit the first transmit signal s1 to the FPGA and transmit the second transmit signal s2 to the signal processing module;

[0080] After the signal processing module processes the second transmission signal s2, it obtains a third transmission signal a0 and sends it to the device to be detected. The device to be detected feeds back a reflected signal b0 to the signal processing module. After the signal processing module processes the reflected signal b0, it obtains a second reflected signal c and transmits it to the FPGA.

[0081] In step 2, the reference signal transmitting module transmits a frequency sweep signal S with a frequency of w(m). Since the signal after power division is a transmitting signal and the initial phase is different when the frequency point is switched, the expression of the first transmitting signal s1 is as follows:

[0082]

[0083] Where, s(m) is the first transmitted signal, m is the number of frequency sweep points, which is related to the measurement frequency bandwidth and the frequency sweep step; A1(m) is the amplitude of the transmitted signal, ω(m) is the angular frequency of the transmitted signal, and t is the time. is the initial phase of the transmitted signal;

[0084] Since the device to be detected has amplitude-phase linear characteristics, and the signal processing module has amplitude-phase linear characteristics, the second reflected signal c has only a linear change in amplitude and a linear increment in phase compared to the transmitted signal, so the expression of the second reflected signal c is as follows:

[0085]

[0086] Among them, A2(m)=k(m)A1(m), k(m) is the linear change rate of amplitude, It is the overall phase increment of all hardware circuits that the transmitted signal passes through before reaching the device to be detected and reflected back to the FPGA.

[0087] In step 5, when each frequency sweep signal is stably transmitted and received, the first down-conversion DDC module and the second down-conversion DDC module respectively perform the same down-conversion conversion on the first transmission signal s1 and the second reflection signal c, and the down-conversion carrier frequency is the current frequency sweep frequency w(m). The digital down-conversion carrier expression is as follows:

[0088] c I (m) = B(m)cos(ω(m)t+γ(m))

[0089] c Q (m) = B(m)sin(ω(m)t+γ(m))

[0090] Among them, B(m) is the carrier amplitude, γ(m) is the phase of the carrier used in the mth frequency sweep, and c I (m), c Q (m) represents a digital down-converted carrier;

[0091] The first transmission signal s1 is down-converted to obtain transmission I and Q signals:

[0092]

[0093] When the working state is in a fixed frequency sweep state and the transmission and reception are stable, the I and Q signals are transmitted. and are all constants, i.e. the first DC component; and the other parts are high-frequency components with a frequency of 2ω(m);

[0094] The second reflected signal c is down-converted to obtain reflected I and Q signals:

[0095]

[0096] When the working state is in a fixed frequency sweep state and the transmission and reception are stable, the reflected I and Q signals and are all constants, namely the second DC component; and the other parts are high-frequency components with a frequency of 2ω(m).

[0097] In step 6, a low-pass filter is used to perform low-pass filtering on the down-converted I and Q signals to extract the DC component each time the frequency sweep signal is stably transmitted and received;

[0098] Among them, the filtering result of the transmitted I and Q signals, that is, the first DC component is:

[0099]

[0100]

[0101] The reflected I and Q signal filtering results, that is, the second DC component is:

[0102]

[0103] The filter introduces an amplitude shift set to 1.

[0104] In step 7, the first DC component is constructed as a first complex signal as follows:

[0105]

[0106] The second DC component is constructed as a second complex signal as follows:

[0107]

[0108] Use the complex sequence f(m) to remove the complex sequence z(m) The term and the amplitude term B(m) give the final calculation sequence:

[0109]

[0110] Among them, I(m) represents the real part, Q(m) represents the imaginary part;

[0111] By extracting the real and imaginary parts in the complex division and reversing the sign of the imaginary part, the reflection coefficient expression can be obtained:

[0112]

[0113] In step 8, according to the calculated reflection coefficient and the calibration of the reflection coefficient at different frequencies, the calibrated reflection coefficient Γ(f) of the device to be tested is obtained. It is easy to know that the reflection coefficient is also a vector. The reflection coefficient is converted according to the standing wave ratio calculation formula:

[0114]

[0115] By performing modulo calculation on the complex number Γ(f), the standing wave ratio result VSWR(f) at the corresponding frequency f is obtained.

[0116] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for measuring frequency standing wave ratio of an antenna feed system based on FPGA, characterized in that: The following steps are involved: Step 1: construct a frequency standing wave ratio measurement system based on FPGA, which includes an FPGA and a radio frequency circuit connected to the FPGA, and the radio frequency circuit is also connected to a device to be detected; the FPGA is provided with a reference signal transmitting module and a signal sampling module, and the signal sampling module is connected to an anti-interference narrowband filtering module; The anti-interference narrowband filter module is sequentially connected to the first down-conversion DDC module, the first low-pass filter and then the reflection coefficient calculation module, and the anti-interference narrowband filter module is also sequentially connected to the second down-conversion DDC module, the second low-pass filter and then the reflection coefficient calculation module; the reflection coefficient calculation module is connected to the FFT and filtering processing module; Step 2: The reference signal transmitting module transmits a frequency sweep signal S to the RF circuit, and the RF circuit divides the reference signal into a first transmitting signal s1 and a second transmitting signal s2, and performs signal processing on the second transmitting signal s2 to obtain a third transmitting signal a0, and sends it to the device to be detected; The device to be detected acquires the third transmission signal a0, and feeds back a reflected signal b0 to the radio frequency circuit. The radio frequency circuit processes the reflected signal b0 to obtain a second reflected signal c, and transmits it to the FPGA. Step 3: After the signal sampling module in the FPGA collects the first transmission signal s1 and the second reflection signal c, it passes them to the anti-interference narrowband filtering module; Step 4: the anti-interference narrowband filtering module performs preliminary filtering on the first transmission signal s1 to obtain a first filtered signal, and transmits it to the first down-conversion DDC module; The anti-interference narrowband filtering module performs preliminary filtering on the second reflected signal c to obtain a second filtered signal, and transmits the second filtered signal to the second down-conversion DDC module; Step 5: the first down-conversion DDC module performs mixing processing on the first filtered signal to obtain first zero intermediate frequency data, and passes it to the first low-pass filter; The second down-conversion DDC module performs mixing processing on the second filtered signal to obtain second zero intermediate frequency data, and passes it to the second low-pass filter; Step 6: The first low-pass filter performs secondary filtering on the first zero intermediate frequency data to obtain a first DC component, and transmits it to a reflection coefficient calculation module; The second low-pass filter performs secondary filtering on the second zero intermediate frequency data to obtain a second DC component, and transmits the second DC component to the reflection coefficient calculation module; Step 7: The reflection coefficient calculation module constructs complex signals for the first DC component and the second DC component respectively to obtain a first complex signal and a second complex signal, and then divides the two complex signals to obtain a reflection coefficient, and transmits it to the FFT and filtering processing module; Step 8: The FFT and filtering processing module performs Fourier transform and standing wave ratio calculation on the reflection coefficient to obtain a standing wave ratio value.

2. The method for measuring frequency standing wave ratio of an antenna feed system based on FPGA according to claim 1, characterized in that: In the step 2, the radio frequency circuit is provided with two power dividers and a signal processing module; The two power dividers obtain the frequency sweep signal S and divide it into a first transmit signal s1 and a second transmit signal s2, and then transmit the first transmit signal s1 to the FPGA and transmit the second transmit signal s2 to the signal processing module; After the signal processing module processes the second transmission signal s2, it obtains a third transmission signal a0 and sends it to the device to be detected. The device to be detected feeds back a reflected signal b0 to the signal processing module. After the signal processing module processes the reflected signal b0, it obtains a second reflected signal c and transmits it to the FPGA.

3. The method for measuring frequency standing wave ratio of an antenna feed system based on FPGA according to claim 2, characterized in that: In step 2, the reference signal transmitting module transmits a frequency sweep signal S with a frequency of w(m). Since the signal after power division is a transmitting signal and the initial phase is different when the frequency point is switched, the expression of the first transmitting signal s1 is as follows: Where, s(m) is the first transmitted signal, m is the number of frequency sweep points, which is related to the measurement frequency bandwidth and the frequency sweep step; A1(m) is the amplitude of the transmitted signal, ω(m) is the angular frequency of the transmitted signal, and t is the time. is the initial phase of the transmitted signal; Since the device to be detected has amplitude-phase linear characteristics, and the signal processing module has amplitude-phase linear characteristics, the second reflected signal c has only a linear change in amplitude and a linear increment in phase compared to the transmitted signal, so the expression of the second reflected signal c is as follows: Among them, A2(m)=k(m)A1(m), k(m) is the linear change rate of amplitude, It is the overall phase increment of all hardware circuits that the transmitted signal passes through before reaching the device to be detected and reflected back to the FPGA.

4. The method for measuring frequency standing wave ratio of an antenna feed system based on FPGA according to claim 3, characterized in that: In step 5, when each frequency sweep signal is stably transmitted and received, the first down-conversion DDC module and the second down-conversion DDC module respectively perform the same down-conversion conversion on the first transmission signal s1 and the second reflection signal c, and the down-conversion carrier frequency is the current frequency sweep frequency w(m). The digital down-conversion carrier expression is as follows: c I (m)=B(m)cos(ω(m)t+γ(m)) c Q (m)=B(m)sin(ω(m)t+γ(m)) Among them, B(m) is the carrier amplitude, γ(m) is the phase of the carrier used in the mth frequency sweep, and c I (m), c Q (m) represents a digital down-converted carrier; The first transmission signal s1 is down-converted to obtain transmission I and Q signals: When the working state is in a fixed frequency sweep state and the transmission and reception are stable, the I and Q signals are transmitted. and are all constants, i.e. the first DC component; and the other parts are high-frequency components with a frequency of 2ω(m); The second reflected signal c is down-converted to obtain reflected I and Q signals: When the working state is in a fixed frequency sweep state and the transmission and reception are stable, the reflected I and Q signals and are all constants, namely the second DC component; and the other parts are high-frequency components with a frequency of 2ω(m).

5. The method for measuring frequency standing wave ratio of an antenna feed system based on FPGA according to claim 4, characterized in that: In step 6, a low-pass filter is used to perform low-pass filtering on the down-converted I and Q signals to extract the DC component each time the frequency sweep signal is stably transmitted and received; Among them, the filtering result of the transmitted I and Q signals, that is, the first DC component is: The reflected I and Q signal filtering results, that is, the second DC component is: The filter introduces an amplitude shift set to 1.

6. The method for measuring frequency standing wave ratio of an antenna feed system based on FPGA according to claim 5, characterized in that: In step 7, the first DC component is constructed as a first complex signal as follows: The second DC component is constructed as a second complex signal as follows: Use the complex sequence f(m) to remove the complex sequence z(m) The term and the amplitude term B(m) give the final calculation sequence: Among them, I(m) represents the real part, Q(m) represents the imaginary part; By extracting the real and imaginary parts in the complex division and reversing the sign of the imaginary part, the reflection coefficient expression can be obtained:

7. The method for measuring frequency standing wave ratio of an antenna feed system based on FPGA according to claim 6, characterized in that: In step 8, according to the calculated reflection coefficient and the calibration of the reflection coefficient at different frequencies, the calibrated reflection coefficient Γ(f) of the device to be tested is obtained. It is easy to know that the reflection coefficient is also a vector. The reflection coefficient is converted according to the standing wave ratio calculation formula: By performing modulo calculation on the complex number Γ(f), the standing wave ratio result VSWR(f) at the corresponding frequency f is obtained.

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