Solid-state imaging device

Abstract

Embodiments provide a solid-state imaging device suitable for appropriately connecting a chip and an analog front end. According to one embodiment, a solid-state imaging device having a chip is provided. The chip has a pixel array, a plurality of signal lines, a plurality of output circuits, and a plurality of output terminals. The pixel array includes a plurality of pixel groups arranged at least in a column direction. Each of the plurality of pixel groups includes two or more pixels. The plurality of signal lines correspond to the plurality of pixel groups. The plurality of signal lines are connected to the corresponding pixel groups, respectively. The plurality of output circuits correspond to the plurality of signal lines. The plurality of output circuits are respectively connected with the corresponding signal lines. The plurality of output terminals correspond to the plurality of output circuits. The plurality of output terminals are connected to the corresponding output circuits, respectively.

Description

[0001] Related Application:

[0002] This application claims priority from Japanese Patent Application No. 2023-153867 (filing date: September 20, 2023) as a prior application, and the present application incorporates the entire contents of the prior application by reference. Technical Field

[0003] This embodiment relates to a solid-state imaging device. Background Art

[0004] In a solid-state imaging device in which a chip and an analog front end are connected to each other, a signal corresponding to an image acquired by the chip is output from the chip to the analog front end. In the solid-state imaging device, it is desirable that the chip and the analog front end be appropriately connected. Summary of the invention

[0005] An object of the present invention is to provide a solid-state imaging device suitable for appropriately connecting a chip to an analog front end.

[0006] According to one embodiment, a solid-state imaging device having a chip is provided. The chip has a pixel arrangement, a plurality of signal lines, a plurality of output circuits, and a plurality of output terminals. The pixel arrangement has a plurality of pixel groups arranged at least in a column direction. The plurality of pixel groups each include more than two pixels. The plurality of signal lines correspond to the plurality of pixel groups. The plurality of signal lines are respectively connected to the corresponding pixel groups. The plurality of output circuits correspond to the plurality of signal lines. The plurality of output circuits are respectively connected to the corresponding signal lines. The plurality of output terminals correspond to the plurality of output circuits. The plurality of output terminals are respectively connected to the corresponding output circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A diagram schematically showing a configuration of a solid-state imaging device according to an embodiment.

[0008] Figure 2 It is a diagram showing a schematic structure of a chip in an embodiment.

[0009] Figure 3 It is a diagram showing the structure of a unit block in the embodiment.

[0010] Figure 4 It is a diagram showing a circuit configuration of a unit block in the embodiment.

[0011] Figure 5 It is a diagram showing a configuration of a solid-state imaging device according to a first modification of the embodiment.

[0012] Figure 6 It is a waveform diagram showing the operation of the solid-state imaging device according to the first modification of the embodiment.

[0013] Figure 7 It is a diagram showing a configuration of a solid-state imaging device according to a second modification of the embodiment.

[0014] Figure 8 It is a waveform diagram showing the operation of the solid-state imaging device according to the second modification of the embodiment.

[0015] Fig. 9 It is a diagram showing a configuration of a solid-state imaging device according to a third modification of the embodiment.

[0016] Fig.10 It is a waveform diagram showing the operation of the solid-state imaging device according to the third modification of the embodiment.

[0017] Fig.11 It is a diagram showing a configuration of a solid-state imaging device according to a fourth modification of the embodiment.

[0018] Fig.12 It is a waveform diagram showing the operation of the solid-state imaging device according to the fourth modification of the embodiment.

[0019] Fig.13 It is a diagram showing a configuration of a solid-state imaging device according to a fifth modification of the embodiment.

[0020] Fig.14 It is a waveform diagram showing the operation of the solid-state imaging device according to the fifth modification of the embodiment.

[0021] Fig.15 It is a diagram showing the structure of a solid-state imaging device according to a sixth modification of the embodiment.

[0022] Fig.16 It is a waveform diagram showing the operation of the solid-state imaging device according to the sixth modification of the embodiment.

[0023] Description of reference numerals:

[0024] 1, 101, 201, 301, 401, 501, 601 solid-state imaging devices; CH, CH1, CH2, CH3, CH1_1~CH1_4, CH2_1~CH2_4, CH3_1~CH3_4 chips; WL, WL1, WL2, WL3, WL11, WL12, WL13 signal wiring; AFE, AFE1, AFE2, AFE3 analog front end. DETAILED DESCRIPTION

[0025] Hereinafter, the solid-state imaging device according to the embodiment will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiment.

[0026] (Implementation Method)

[0027] In the solid-state imaging device according to the embodiment, the chip and the analog front end are connected to each other, and a signal corresponding to an image obtained by the chip is output from the chip to the analog front end. However, an improvement is made for appropriately connecting the chip and the analog front end.

[0028] The solid-state imaging device 1 can be Figure 1 The composition shown. Figure 1 1 is a diagram showing a schematic configuration of the solid-state imaging device 1 .

[0029] The solid-state imaging device 1 includes a chip CH, signal wirings WL, and an analog front end AFE. The chip CH, signal wirings WL, and the analog front end AFE may also be mounted on a substrate PCB.

[0030] Chip CH Figure 2 As shown, it has a pixel arrangement PA, multiple signal lines SL1~SL6, multiple output circuits OC1~OC6, multiple pulse control circuits PL1~PL6, multiple output terminals OS1~OS6, multiple input and output terminals IO, a scanning circuit SR, a boost circuit BS and a timing generation circuit TG.

[0031] Figure 2 is a diagram showing a schematic structure of a chip CH. Figure 2 In the diagram, the longitudinal direction of the chip CH is referred to as a column direction, and the direction perpendicular to the column direction in a plane along the surface of the chip CH is referred to as a row direction.

[0032] In the pixel array PA, a plurality of pixel groups PG1 to PG6 are arranged at least in the column direction. Figure 2 , a structure in which a plurality of pixel groups PG1 to PG6 are arranged in a column direction in a pixel arrangement PA is illustrated. Each pixel group PG includes two or more pixels PX. In each pixel group PG, two or more pixels PX are arranged at least in a column direction. Figure 2 In FIG. 1 , a structure in which two or more pixels PX are arranged in a column direction in each pixel group PG is illustrated. Figure 2 In FIG. 1 , one pixel PX is represented by a set of three quadrilaterals arranged side by side in the row direction.

[0033] The plurality of signal lines SL1 to SL6 correspond to the plurality of pixel groups PG1 to PG6. Each signal line SL is connected to the corresponding pixel group PG. The plurality of signal lines SL1 to SL6 are separated from each other and arranged in parallel in the column direction. Each signal line SL1 to SL6 is arranged between the pixel group PG in the row direction and the output circuit OC.

[0034] The plurality of output circuits OC1 to OC6 correspond to the plurality of signal lines SL1 to SL6. Each output circuit OC is connected to the corresponding signal line SL. The plurality of output circuits OC1 to OC6 are separated from each other and arranged in parallel in the column direction. Each output circuit OC is arranged between the signal line SL in the row direction and the output terminal OS.

[0035] The plurality of pulse control circuits PL1 to PL6 correspond to the plurality of output circuits OC1 to OC6. Each pulse control circuit PL is connected to the corresponding output circuit OC. The plurality of pulse control circuits PL1 to PL6 are separated from each other and arranged in parallel in the column direction. Each pulse control circuit PL is arranged between the signal line SL in the row direction and the output terminal OS.

[0036] The plurality of output terminals OS1 to OS6 correspond to the plurality of output circuits OC1 to OC6. Each output terminal OS is connected to the corresponding output circuit OC. The plurality of output terminals OS1 to OS6 are separated from each other and arranged in the column direction. Each output terminal OS is arranged between the output circuit OC in the row direction and the end of the chip CH.

[0037] The scanning circuit SR is, for example, a shift register, and has a plurality of register units RU1 to RU6. The plurality of register units RU1 to RU6 correspond to the plurality of pixel groups PG1 to PG6. Each register unit RU supplies a control signal to the corresponding pixel group PG.

[0038] The structure including the register unit RU, the pixel group PG, the signal line SL, the output circuit OC, the pulse control circuit PL, and the output terminal OS constitutes a unit block UB. The chip CH includes a plurality of unit blocks UB1 to UB6. The plurality of unit blocks UB1 to UB6 can also be configured to be able to operate independently of each other. Figure 2 In FIG. 1 , a chip CH including six unit blocks UB1 to UB6 is illustrated. However, the number of unit blocks UB included in the chip CH may be 2 to 5, or may be 7 or more.

[0039] Each unit block UB can be Figure 3 and Figure 4 The composition shown. Figure 3 It is a diagram showing the structure of a unit block. Figure 4 It is a diagram showing the circuit configuration of a unit block.

[0040] The unit block UB includes a register unit RU, a pixel group PG, n output lines OL_1 to OL_n, a signal line SL, an output circuit OC, a pulse control circuit PL, an output terminal OS, and one or more input / output terminals IO. n is an arbitrary integer greater than or equal to 2.

[0041] The register unit RU includes n-stage registers RG_1 to RG_n. The n-stage registers RG_1 to RG_n are arranged in parallel in the column direction. The pixel group PG includes n pixels PX_1 to PX_n. The n pixels PX_1 to PX_n are arranged in parallel in the column direction. The n-stage registers RG_1 to RG_n, the n pixels PX_1 to PX_n, and the n output lines OL_1 to OL_n correspond to each other. The n output lines OL_1 to OL_n are arranged in parallel in the column direction. Each output line OL extends in the row direction.

[0042] The pulse control circuit PL is connected to each pixel PX via a control line CL_RS. The pulse control circuit PL controls the pixels PX in accordance with a control signal received from the timing control circuit TG. Generate control signals And it is supplied to each pixel PX through the control line CL_RS.

[0043] Each pixel PX includes a photoelectric conversion unit PD, a transfer unit TX, a charge-voltage conversion unit FD, an amplifier AM, a reset unit RS, and a selection unit SR.

[0044] The selection unit SR controls the selected state / non-selected state of the pixel PX. The selection unit SR includes, for example, a selection transistor. The selection transistor receives an active level control signal from the register RG through a gate. The select transistor is turned on when the gate receives a control signal of an inactive level from the register RG. The pixel PX is turned off at this time, thereby becoming a non-selected state.

[0045] The reset unit RS resets the charge-to-voltage converter FD. The reset unit RS includes, for example, a reset transistor. The reset transistor receives an activation-level control signal from the pulse control circuit PL through a gate. The reset transistor is turned on when the gate receives a control signal of an inactive level from the pulse control circuit PL. It is turned off at this time, thereby releasing the reset of the charge-voltage conversion unit FD.

[0046] The photoelectric converter PD generates and accumulates charges corresponding to light. The transfer unit TX includes, for example, a transfer transistor. The transfer transistor receives a control signal of an inactive level from the booster circuit BS through a gate. The photoelectric converter PD is turned off when the charge voltage converter FD is turned off, thereby disconnecting the photoelectric converter PD from the charge voltage converter FD. As a result, the charge accumulation operation starts in the photoelectric converter PD. When the charge voltage converter FD is reset and the reset is released, the transfer transistor receives the control signal of the activation level from the boost circuit BS through the gate. When the photoelectric converter PD is turned on, the charge in the photoelectric converter PD is transferred to the charge-voltage converter FD. Thus, the charge accumulation operation is completed in the photoelectric converter PD, and a voltage corresponding to the transferred charge is generated in the charge-voltage converter FD.

[0047] When the pixel PX is in the selected state, the amplifier AM performs a source follower operation together with the current source CS connected to the source side, and outputs a signal corresponding to the voltage of the charge-voltage converter FD to the output circuit OC via the output line OL and the signal line SL.

[0048] In the register unit RU, each of the n-stage registers RG_1 to RG_n receives a timing control signal from the timing generation circuit TG. The register unit RU synchronizes the control signal received by the first-stage register RG_1 with the timing control signal. The first-stage register RG_1 → the second-stage register RG_2 → ... → the (n-1)th-stage register RG_(n-1) → the nth-stage register RG_n are sequentially shifted, and control signals are sequentially supplied from their output nodes to pixels PX_1, PX_2, ..., PX_(n-1), PX_n.

[0049] For example, during period TP1, the register unit RU turns the control signal The voltage is supplied to the selection section SR of the pixels PX_1, PX_2, ..., PX_(n-1), and PX_n. As a result, the pixels PX_1, PX_2, ..., PX_(n-1), and PX_n are placed in a non-selected state.

[0050] In the period TP2 later than the period TP1, the transfer section TX (transfer transistor) of each pixel PX_1 to PX_n receives the control signal of the active level through the gate. And the charge of the photoelectric conversion unit PD is transferred to the charge-voltage conversion unit FD.

[0051] In the period TP3 later than the period TP2, the register unit RU activates the control signal The pixels PX_1, PX_2, ..., PX_(n-1), and PX_n are sequentially supplied. As a result, the pixels PX_1, PX_2, ..., PX_(n-1), and PX_n are sequentially selected. Along with this, the amplifiers AM of the pixels PX_1, PX_2, ..., PX_(n-1), and PX_n sequentially output signals to the output circuit OC via the output line OL and the signal line SL.

[0052] That is, each unit block UB in the chip CH can be moved in a predetermined direction (in Figure 3The plurality of pixels PX in the pixel group PG are sequentially scanned in a predetermined direction (in the column direction in the case of Figure 3 The signals output from the pixels PX are sequentially transferred in the row direction (in the case of the pixel PX).

[0053] Figure 2 The booster circuit BS shown is connected to each pixel PX via a control line CL_TX. The booster circuit BS generates a control signal by boosting a voltage received from a power supply circuit (not shown). And it is supplied to each pixel PX via the control line CL_TX.

[0054] The timing generation circuit TG is connected to each pulse control circuit PL1 to PL6 via a control line CL1, connected to the booster circuit BS via a control line CL2, and connected to the scanning circuit SR via a control line CL3. The timing generation circuit TG generates a timing control pulse The timing control pulse is supplied to the pulse control circuit PL of each unit block UB via the control line CL1. The timing generation circuit TG generates the timing control pulse The timing generating circuit TG generates a timing control pulse. And it is supplied to the scanning circuit SR via the control line CL3.

[0055] Figure 1 The signal wiring WL shown is arranged between the chip CH and the analog front end AFE. The signal wiring WL connects the plurality of output terminals OS1 to OS6 of the chip CH to the analog front end AFE.

[0056] The analog front end AFE is configured between the signal wiring WL and the circuit of the subsequent stage. The analog front end AFE receives a signal (analog signal) from the chip CH via the signal wiring WL. The analog front end AFE has a digital processing circuit DPC. The digital processing circuit DPC performs AD conversion on the signal (analog signal) from the chip CH and applies a predetermined process to generate a signal (digital signal). The analog front end AFE outputs the generated signal to the circuit of the subsequent stage.

[0057] In chip CH, Figure 2 As shown, the structure other than the boost circuit BS and the timing control circuit TG is divided or grouped into a plurality of unit blocks UB1 to UB6 that can operate independently of each other. That is, a plurality of pixels PX in the pixel arrangement PA are grouped into a plurality of pixel groups PG. A plurality of output lines OL are grouped into output line groups corresponding to the unit blocks UB. The signal lines SL, output circuits OS, and output terminals OS of each unit block UB are independently configured from other unit blocks UB. Thus, the chip CH becomes multi-output.

[0058] The chip CH can be configured to flexibly cope with changes in the connection structure (structure of the signal wiring WL) between the chip CH and the analog front end AFE according to the use of the solid-state imaging device 1 during its manufacture.

[0059] For example, when the solid-state imaging device 1 is manufactured for a purpose that prioritizes speed, the signal wiring WL is configured to connect the chip CH and the analog front end AFE in parallel. In this case, the chip CH is set to be in parallel with the timing control pulse of the timing generation circuit TG. In accordance with the timing of the output terminals OS1 to OS6, signals are output in parallel.

[0060] Alternatively, when the solid-state imaging device 1 is manufactured for a purpose that prioritizes cost, the signal wiring WL is configured to connect the chip CH and the analog front end AFE in series. In this case, the chip CH is set to be connected to the timing control pulse of the timing generation circuit TG. In accordance with the timing of the output terminals OS1 to OS6, signals are output in series.

[0061] As described above, in the embodiment, in the solid-state imaging device 1, the chip CH includes a plurality of unit blocks UB1 to UB6 that can operate independently of each other. The signal line SL, the output circuit OS, and the output terminal OS of each unit block UB are independently configured from other unit blocks UB. Thus, the output of the chip CH can be made into multiple outputs. Thus, the chip CH can be configured to flexibly cope with changes in the connection structure (the structure of the signal wiring WL) between the chip CH and the analog front end AFE in accordance with the purpose of the solid-state imaging device 1 during its manufacture. As a result, the design and manufacture of the chip CH used in the manufacture of the solid-state imaging device 1 with speed priority and the chip CH used in the manufacture of the solid-state imaging device 1 with cost priority can be made common. Therefore, the manufacture of the chip CH can be QTATized, and the design and manufacturing costs of the chip CH can be reduced respectively.

[0062] Furthermore, as a first modification of the embodiment, when the solid-state imaging device 101 is manufactured for a purpose in which speed is prioritized, the solid-state imaging device 101 may be configured as follows: Figure 5 The composition shown. Figure 5 It is a diagram showing a configuration of a solid-state imaging device 101 according to a first modification of the embodiment.

[0063] The solid-state imaging device 101 includes a chip CH1, a signal line WL1, and an analog front end AFE1. The chip CH1, the signal line WL1, and the analog front end AFE1 may be mounted on a substrate PCB1. The substrate PCB1 may be in a substantially plate shape with the column direction as the longitudinal direction.

[0064] The chip CH1 can be configured similarly to the chip CH in the embodiment.

[0065] The analog front end AFE1 is similar to the embodiment in that it has a digital processing circuit DPC, but is different from the embodiment in that it also has a plurality of input terminals IN1 to IN6. The analog front end AFE1 may also be arranged on the substrate PCB1 at a position separated in the column direction relative to the chip CH1. The plurality of input terminals IN1 to IN6 may also be arranged side by side in the row direction at a portion of the analog front end AFE1 close to the chip side.

[0066] The signal wiring WL1 is configured to connect the plurality of output terminals OS1 to OS6 of the chip CH1 and the plurality of input terminals IN1 to IN6 of the analog front end AFE1 in parallel.

[0067] The signal wiring WL1 includes a plurality of lines LN1 to LN6 . One end of the line LN1 is connected to the output terminal OS1 of the chip CH1 , and the other end thereof is connected to the input terminal IN1 of the analog front end AFE1 .

[0068] One end of the line LN2 is connected to the output terminal OS2 of the chip CH1 , and the other end thereof is connected to the input terminal IN2 of the analog front end AFE1 .

[0069] One end of the line LN3 is connected to the output terminal OS3 of the chip CH1 , and the other end thereof is connected to the input terminal IN3 of the analog front end AFE1 .

[0070] One end of the line LN4 is connected to the output terminal OS4 of the chip CH1 , and the other end thereof is connected to the input terminal IN4 of the analog front end AFE1 .

[0071] One end of the line LN5 is connected to the output terminal OS5 of the chip CH1 , and the other end thereof is connected to the input terminal IN5 of the analog front end AFE1 .

[0072] One end of the line LN6 is connected to the output terminal OS6 of the chip CH1 , and the other end thereof is connected to the input terminal IN6 of the analog front end AFE1 .

[0073] In the chip CH1 , the plurality of output terminals OS1 to OS6 are arranged in parallel and separated from each other in the column direction. Therefore, the plurality of lines LN1 to LN6 can be efficiently laid out in a substantially L-shape that gradually becomes smaller.

[0074] Signals output from the plurality of output terminals OS1 to OS6 of the chip CH1 are supplied to the plurality of input terminals IN1 to IN6 of the analog front end AFE1 via the plurality of lines LN1 to LN6 .

[0075] In the analog front end AFE1, the input side of the digital processing circuit DPC is connected to a plurality of input terminals IN1 to IN6. The signal from the chip CH1 is supplied to the digital processing circuit DPC via the plurality of input terminals IN1 to IN6. The digital processing circuit DPC performs AD conversion on the signal (analog signal) from the chip CH1 and performs predetermined processing to generate a signal (digital signal).

[0076] The analog front end AFE1 outputs the generated signal to a subsequent circuit.

[0077] In the solid-state imaging device 101, the signal wiring WL1 connects the plurality of output terminals OS1 to OS6 of the chip CH1 in parallel with the analog front end AFE1. Accordingly, the chip CH1 is configured to output signals of the plurality of unit blocks UB1 to UB6 in parallel from the plurality of output terminals OS1 to OS6 to the analog front end AFE1.

[0078] For example, in chip CH1, the timing generation circuit TG is Figure 6 Before the timing t1 shown, the timing control pulse of the activation level The pulses are supplied in parallel to the plurality of pulse control circuits PL1 to PL6 . The pulse control circuits PL1 to PL6 activate the corresponding output circuit OC in parallel with each other and transfer the signal of the pixel PX to the output terminal OS.

[0079] Therefore, in Figure 6 During the timing period t1 to t2 shown, signal transfer from output terminal OS1 to input terminal IN1 via line LN1, signal transfer from output terminal OS2 to input terminal IN2 via line LN2, signal transfer from output terminal OS3 to input terminal IN3 via line LN3, signal supply from output terminal OS4 to input terminal IN4 via line LN4, signal transfer from output terminal OS5 to input terminal IN5 via line LN5, and signal transfer from output terminal OS6 to input terminal IN6 via line LN6 are performed in parallel.

[0080] In this way, the chip CH1 can transfer the signals of the plurality of unit blocks UB1 to UB6 to the analog front end AFE1 at high speed.

[0081] In addition, as a second variation of the embodiment, when the solid-state imaging device 201 is manufactured for a purpose with priority given to cost, it may be as follows: Figure 7 The composition shown. Figure 7 It is a diagram showing a configuration of a solid-state imaging device 201 according to a second modification of the embodiment.

[0082] The solid-state imaging device 201 includes a chip CH2, a signal wiring WL2, and an analog front end AFE2. The chip CH2, the signal wiring WL2, and the analog front end AFE2 may also be mounted on a substrate PCB2. The substrate PCB2 may also be in a substantially plate shape with the column direction as the longitudinal direction.

[0083] The chip CH2 can be configured similarly to the chip CH in the embodiment.

[0084] The analog front end AFE2 is similar to the embodiment in that it has a digital processing circuit DPC, but is different from the embodiment in that it further has an input terminal IN. The analog front end AFE2 may be arranged on the substrate PCB2 at a position separated from the chip CH2 in the column direction. The input terminal IN may also be arranged at a portion of the analog front end AFE2 close to the chip side.

[0085] The signal wiring WL2 is configured to connect the plurality of output terminals OS1 to OS6 of the chip CH2 and the analog front end AFE2 in series.

[0086] The signal wiring WL2 includes a plurality of lines LN11 to LN16 and a common line LN10 .

[0087] One end of the common line LN10 extends to the vicinity of the output terminal OS1 of the chip CH2 , and the other end thereof is connected to the input terminal IN of the analog front end AFE2 .

[0088] One end of the line LN11 is connected to the output terminal OS1 of the chip CH2 , and the other end thereof is connected to the common line LN10 .

[0089] One end of the line LN12 is connected to the output terminal OS2 of the chip CH2 , and the other end thereof is connected to the common line LN10 .

[0090] One end of the line LN13 is connected to the output terminal OS3 of the chip CH2 , and the other end thereof is connected to the common line LN10 .

[0091] One end of the line LN14 is connected to the output terminal OS4 of the chip CH2 , and the other end thereof is connected to the common line LN10 .

[0092] One end of the line LN15 is connected to the output terminal OS5 of the chip CH2 , and the other end thereof is connected to the common line LN10 .

[0093] One end of the line LN16 is connected to the output terminal OS6 of the chip CH2 , and the other end thereof is connected to the common line LN10 .

[0094] In chip CH2 , the plurality of output terminals OS1 to OS6 are spaced apart and arranged in the column direction. Therefore, the layout can be efficiently performed such that the common line LN10 extends in the column direction and forms a gradually decreasing substantially L shape with the plurality of lines LN11 to LN16 extending in the row direction.

[0095] Signals output from the plurality of output terminals OS1 to OS6 of the chip CH2 are supplied to the input terminal IN of the analog front end AFE2 via the plurality of lines LN1 to LN6 and the common line LN10 .

[0096] In the analog front end AFE2, the input side of the digital processing circuit DPC is connected to the input terminal IN. The signal output from the chip CH2 is supplied to the digital processing circuit DPC via the input terminal IN. The digital processing circuit DPC performs AD conversion on the signal (analog signal) from the chip CH2 and performs predetermined processing to generate a signal (digital signal).

[0097] The analog front end AFE2 outputs the generated signal to a subsequent circuit.

[0098] In the solid-state imaging device 201, the signal wiring WL2 connects the plurality of output terminals OS1 to OS6 of the chip CH2 in series with the input terminal IN of the analog front end AFE2. Accordingly, the chip CH2 is configured to output the signals of the plurality of unit blocks UB1 to UB6 in series from the plurality of output terminals OS1 to OS6 to the input terminal IN of the analog front end AFE2.

[0099] For example, in chip CH2, the timing generation circuit TG is Figure 8 Before each timing t11 to t16 shown in the figure, the timing control pulse of the activation level is The pulses are supplied in series to the plurality of pulse control circuits PL1 to PL6 . Each of the pulse control circuits PL1 to PL6 activates the corresponding output circuit OC in sequence and transfers the signal of the pixel PX to the output terminal OS.

[0100] thus, Figure 8The signal transfer from the output terminal OS1 to the input terminal IN via the line LN11 and the common line 10 during the period of timing t11 to t12 shown, the signal transfer from the output terminal OS2 to the input terminal IN via the line LN12 and the common line 10 during the period of timing t12 to t13, the signal transfer from the output terminal OS3 to the input terminal IN via the line LN13 and the common line 10 during the period of timing t13 to t14, the signal supply from the output terminal OS4 to the input terminal IN via the line LN14 and the common line 10 during the period of timing t14 to t15, the signal transfer from the output terminal OS5 to the input terminal IN via the line LN15 and the common line 10 during the period of timing t15 to t16, and the signal transfer from the output terminal OS6 to the input terminal IN via the line LN16 and the common line 10 during the period of timing t16 to t17 are performed serially.

[0101] Here, the signal wiring WL2 and the signal wiring WL1 (see Figure 5 ) can be manufactured at a lower cost by shortening the total length. Figure 5 ) compared to the analog front end, the number of input terminals IN is less, the circuit structure between the input terminal IN and the digital processing circuit DPC can be simplified, and a cheap version of the analog front end can be used.

[0102] In this way, the chip CH2 can transfer the signals of the plurality of unit blocks UB1 to UB6 to the analog front end AFE2 at low cost.

[0103] In addition, as a third modification of the embodiment, when the solid-state imaging device 301 is manufactured for a use in consideration of speed and cost, it may be Fig. 9 The composition shown. Fig. 9 It is a diagram showing a configuration of a solid-state imaging device 301 according to a third modification of the embodiment.

[0104] The solid-state imaging device 301 includes a chip CH3, a signal wiring WL3, and an analog front end AFE3. The chip CH3, the signal wiring WL3, and the analog front end AFE3 may also be mounted on a substrate PCB3. The substrate PCB3 may also be in a substantially plate shape with the column direction as the longitudinal direction.

[0105] The chip CH3 can be configured basically similarly to the chip CH in the embodiment, but is different from the embodiment in the following points.

[0106] The plurality of output circuits OC1 to OC6 are grouped into a plurality of output circuit groups each including two or more output circuits OC. The plurality of output circuits OC1 to OC6 may also be grouped into three output circuit groups (OC1, OC2), (OC3, OC4), and (OC5, OC6).

[0107] The plurality of output terminals OS1 to OS6 are grouped into a plurality of output terminal groups each including two or more output terminals OS. The plurality of output terminals OS1 to OS6 may be grouped into three output terminal groups (OS1, OS2), (OS3, OS4), (OS5, OS6).

[0108] The analog front end AFE3 is similar to the embodiment in that it has a digital processing circuit DPC, but is different from the embodiment in that it also has a plurality of input terminals IN11 to IN13. The analog front end AFE3 may also be arranged on the substrate PCB3 at a position separated in the column direction relative to the chip CH3. The plurality of input terminals IN11 to IN13 may also be arranged side by side in the row direction at a portion of the analog front end AFE3 close to the chip side.

[0109] The signal wiring WL3 is configured to connect the plurality of output terminal groups of the chip CH3 and the plurality of input terminals IN11 to IN13 of the analog front end AFE3 in parallel, and to connect two or more output terminals OS of each output terminal group and the input terminals of the analog front end AFE3 in series.

[0110] The signal wiring WL3 includes a plurality of lines LN21 and LN22 , a common line LN23 , a plurality of lines LN24 and LN25 , a common line LN26 , a plurality of lines LN27 and LN28 , and a common line LN29 .

[0111] One end of the common line LN23 extends to the vicinity of the output terminal OS1 of the chip CH3 , and the other end thereof is connected to the input terminal IN11 of the analog front end AFE3 .

[0112] One end of the line LN21 is connected to the output terminal OS1 of the chip CH3 , and the other end thereof is connected to the common line LN23 .

[0113] One end of the line LN22 is connected to the output terminal OS2 of the chip CH3 , and the other end thereof is connected to the common line LN23 .

[0114] One end of the common line LN26 extends to the vicinity of the output terminal OS3 of the chip CH3 , and the other end thereof is connected to the input terminal IN12 of the analog front end AFE3 .

[0115] One end of the line LN24 is connected to the output terminal OS4 of the chip CH3 , and the other end thereof is connected to the common line LN26 .

[0116] One end of the line LN25 is connected to the output terminal OS5 of the chip CH3 , and the other end thereof is connected to the common line LN26 .

[0117] One end of the common line LN29 extends to the vicinity of the output terminal OS5 of the chip CH3 , and the other end thereof is connected to the input terminal IN13 of the analog front end AFE3 .

[0118] One end of the line LN27 is connected to the output terminal OS5 of the chip CH3 , and the other end thereof is connected to the common line LN29 .

[0119] One end of the line LN28 is connected to the output terminal OS6 of the chip CH3 , and the other end thereof is connected to the common line LN29 .

[0120] In the chip CH3, a plurality of output terminal groups are arranged in parallel and separated in the column direction. Therefore, a plurality of lines LN1 to LN6 can be efficiently laid out in a substantially L-shape that gradually becomes smaller for each output terminal group.

[0121] Each output terminal group can be efficiently laid out in such a way that common lines LN23, LN26, and LN29 extend in the column direction and form a gradually decreasing substantially L shape with a plurality of lines LN21, LN22, LN24, LN25, LN27, and LN28 extending in the row direction.

[0122] The signals output from the multiple output terminals OS1 and OS2 of the chip CH3 are supplied to the input terminal IN11 of the analog front end AFE3 via the multiple lines LN21, LN22, and the common line LN23. The signals output from the multiple output terminals OS3 and OS4 of the chip CH3 are supplied to the input terminal IN12 of the analog front end AFE3 via the multiple lines LN24, LN25, and the common line LN26. The signals output from the multiple output terminals OS5 and OS6 of the chip CH3 are supplied to the input terminal IN13 of the analog front end AFE3 via the multiple lines LN27, LN28, and the common line LN29.

[0123] In the analog front end AFE3, the input side of the digital processing circuit DPC is connected to a plurality of input terminals IN11 to IN13. The signal from the chip CH3 is supplied to the digital processing circuit DPC via the plurality of input terminals IN11 to IN13. The digital processing circuit DPC performs AD conversion on the signal (analog signal) from the chip CH3 and performs predetermined processing to generate a signal (digital signal).

[0124] The analog front end AFE3 outputs the generated signal to a subsequent circuit.

[0125] In the solid-state imaging device 301, a plurality of output terminal groups of the chip CH3 are connected in parallel to a plurality of input terminals IN11 to IN13 of the analog front end AFE3, and two or more output terminals OS of each output terminal group are connected in series to the input terminals of the analog front end AFE3. Accordingly, the chip CH3 is configured to output signals of a plurality of unit blocks UB in parallel from a plurality of output terminal groups to a plurality of input terminals IN11 to IN13 of the analog front end AFE3, and to output signals from two or more output terminals OS of each output terminal group to the input terminals of the analog front end AFE3 in series.

[0126] For example, in chip CH3, the timing generation circuit TG is Fig.10 Before each timing t21 shown, the timing control pulse of the activation level The odd-numbered pulse control circuits PL1, PL3, PL5 are supplied in parallel. The odd-numbered pulse control circuits PL1, PL3, PL5 activate the corresponding output circuits OC1, OC3, OC5 in parallel with each other and transfer the signal of the pixel PX to the output terminals OS1, OS3, OS5.

[0127] Thus, during the timing period t21 to t22, the signal transfer from the output terminal OS1 to the input terminal IN11 via the line LN21 and the common line LN23, the signal transfer from the output terminal OS3 to the input terminal IN12 via the line LN24 and the common line LN26, and the signal transfer from the output terminal OS5 to the input terminal IN13 via the line LN27 and the common line LN29 are performed in parallel.

[0128] Just before the timing t22, the timing control pulse of the activation level is The even-numbered pulse control circuits PL2, PL4, PL6 are supplied in parallel. The even-numbered pulse control circuits PL2, PL4, PL6 activate the corresponding output circuits OC2, OC4, OC6 in parallel with each other and transfer the signal of the pixel PX to the output terminals OS2, OS4, OS6.

[0129] Thus, during the timing period t22 to t23, the signal transfer from the output terminal OS2 to the input terminal IN11 via the line LN22 and the common line LN23, the signal transfer from the output terminal OS4 to the input terminal IN12 via the line LN25 and the common line LN26, and the signal transfer from the output terminal OS6 to the input terminal IN13 via the line LN28 and the common line LN29 are performed in parallel.

[0130] That is, signal transfer from the odd-numbered output terminals to the input terminals IN11 to IN13 via the lines and the common line during the period of timing t21 to t22, and signal transfer from the even-numbered output terminals to the input terminals IN11 to IN13 via the lines and the common line during the period of timing t22 to t23 are performed serially.

[0131] Here, the signal wiring WL3 and the signal wiring WL1 (see Figure 5 ) can be manufactured at a lower cost by shortening the total length. Figure 5 ) compared to the analog front end, the number of input terminals IN11~IN13 is smaller, the circuit structure between the input terminals IN11~IN13 and the digital processing circuit DPC can be simplified, and a cheap version of the analog front end can be used.

[0132] In this way, the chip CH3 can transfer the signals of the plurality of unit blocks UB1 to UB6 to the analog front end AFE3 in consideration of both speed and cost.

[0133] In addition, as a fourth variation of the embodiment, the solid-state imaging device 401 is as follows: Fig.11 As shown, in the case of being manufactured for a purpose where speed is a priority, it can also be Fig.11 The figure shows that it is composed of multiple chips. Fig.11 It is a diagram showing a structure of a solid-state imaging device 401 according to a fourth modification of the embodiment.

[0134] The solid-state imaging device 401 is different from the solid-state imaging device 101 (see Figure 5 ) is modified so that the chip CH1 is expanded into a plurality of chips CH1_1 to CH1_4, and the signal wiring WL1 is replaced with the signal wiring WL11.

[0135] The plurality of chips CH1_1 to CH1_4 are separated from each other on the substrate PCB1 and arranged in the column direction. This can increase the read length that can be scanned at one time by the solid-state imaging device 401. The analog front end AFE1 can also be arranged on the substrate PCB1 at a position separated from the plurality of chips CH1_1 to CH1_4 in the column direction.

[0136] The signal wiring WL11 connects the plurality of chips CH1_1 to CH1_4 in series with the analog front end AFE1. The signal wiring WL11 connects the plurality of output terminals OS1 to OS6 of each chip CH1 in parallel with the plurality of input terminals IN1 to IN6 of the analog front end AFE1.

[0137] The signal wiring WL11 includes a plurality of lines LN1_1 to LN6_1, LN1_2 to LN6_2, LN1_3 to LN6_3, and LN1_4 to LN6_4.

[0138] One end of the lines LN1_1 to LN1_4 is connected to the output terminal OS1 of the chips CH1_1 to CH1_4, respectively. The other end of the line LN1_1 is connected to the input terminal IN1 of the analog front end AFE1, and the other ends of the lines LN1_2 to LN1_4 are connected to the line LN1_1, respectively.

[0139] One end of the lines LN2_1 to LN2_4 is connected to the output terminal OS2 of the chips CH1_1 to CH1_4, respectively. The other end of the line LN2_1 is connected to the input terminal IN2 of the analog front end AFE1, and the other ends of the lines LN2_2 to LN2_4 are connected to the line LN2_1, respectively.

[0140] One end of the lines LN3_1 to LN3_4 is connected to the output terminal OS3 of the chips CH1_1 to CH1_4, respectively. The other end of the line LN3_1 is connected to the input terminal IN3 of the analog front end AFE1, and the other ends of the lines LN3_2 to LN3_4 are connected to the line LN3_1, respectively.

[0141] One end of the lines LN4_1 to LN4_4 is connected to the output terminal OS4 of the chips CH1_1 to CH1_4, respectively. The other end of the line LN4_1 is connected to the input terminal IN4 of the analog front end AFE1, and the other ends of the lines LN4_2 to LN4_4 are connected to the line LN4_1, respectively.

[0142] One end of the lines LN5_1 to LN5_4 is connected to the output terminal OS5 of the chips CH1_1 to CH1_4, respectively. The other end of the line LN5_1 is connected to the input terminal IN5 of the analog front end AFE1, and the other ends of the lines LN5_2 to LN5_4 are connected to the line LN5_1, respectively.

[0143] One end of the lines LN6_1 to LN6_4 is connected to the output terminal OS6 of the chips CH1_1 to CH1_4, respectively. The other end of the line LN6_1 is connected to the input terminal IN6 of the analog front end AFE1, and the other ends of the lines LN6_2 to LN6_4 are connected to the line LN6_1, respectively.

[0144] In the substrate PCB1, the plurality of chips CH1_1 to CH1_4 are arranged in parallel and separated in the column direction. Therefore, the layout can be efficiently performed such that the line groups extending in the column direction form a gradually decreasing substantially L shape with the plurality of line groups extending in the row direction.

[0145] In each chip CH1 , the plurality of output terminals OS1 to OS6 are arranged in parallel and spaced apart in the column direction. Therefore, the plurality of lines LN1 to LN6 can be efficiently laid out in a substantially L-shape that gradually becomes smaller.

[0146] In the solid-state imaging device 401, the plurality of chips CH1_1 to CH1_4 are configured to serially output to the analog front end AFE1. Also, each chip CH1 is configured to output signals of the plurality of unit blocks UB1 to UB6 in parallel from the plurality of output terminals OS1 to OS6 to the analog front end AFE1, similarly to the solid-state imaging device 101.

[0147] For example, in chip CH1_1, the timing generation circuit TG is Fig.12 Before the timing t31 shown, the timing control pulse of the activation level The pulses are supplied in parallel to the plurality of pulse control circuits PL1 to PL6 . The pulse control circuits PL1 to PL6 activate the corresponding output circuit OC in parallel with each other and transfer the signal of the pixel PX to the output terminal OS.

[0148] Thus, during the timing period from t31 to t32, with respect to chip CH1_1, signal transfer from output terminal OS1 to input terminal IN1 via line LN1, signal transfer from output terminal OS2 to input terminal IN2 via line LN2, signal transfer from output terminal OS3 to input terminal IN3 via line LN3, signal supply from output terminal OS4 to input terminal IN4 via line LN4, signal transfer from output terminal OS5 to input terminal IN5 via line LN5, and signal transfer from output terminal OS6 to input terminal IN6 via line LN6 are performed in parallel with each other.

[0149] In chip CH1_2, the timing generation circuit TG generates a timing control pulse of the activation level just before the timing t32. The pulses are supplied in parallel to the plurality of pulse control circuits PL1 to PL6 . The pulse control circuits PL1 to PL6 activate the corresponding output circuit OC in parallel with each other and transfer the signal of the pixel PX to the output terminal OS.

[0150] Thus, during the timing period from t32 to t33, with respect to chip CH1_2, signal transfer from output terminal OS1 to input terminal IN1 via line LN1, signal transfer from output terminal OS2 to input terminal IN2 via line LN2, signal transfer from output terminal OS3 to input terminal IN3 via line LN3, signal supply from output terminal OS4 to input terminal IN4 via line LN4, signal transfer from output terminal OS5 to input terminal IN5 via line LN5, and signal transfer from output terminal OS6 to input terminal IN6 via line LN6 are performed in parallel with each other.

[0151] In chip CH1_3, the timing generation circuit TG generates a timing control pulse of the activation level just before the timing t33. The pulses are supplied in parallel to the plurality of pulse control circuits PL1 to PL6 . The pulse control circuits PL1 to PL6 activate the corresponding output circuit OC in parallel with each other and transfer the signal of the pixel PX to the output terminal OS.

[0152] Thus, during the timing period from t33 to t34, with respect to chip CH1_3, signal transfer from output terminal OS1 to input terminal IN1 via line LN1, signal transfer from output terminal OS2 to input terminal IN2 via line LN2, signal transfer from output terminal OS3 to input terminal IN3 via line LN3, signal supply from output terminal OS4 to input terminal IN4 via line LN4, signal transfer from output terminal OS5 to input terminal IN5 via line LN5, and signal transfer from output terminal OS6 to input terminal IN6 via line LN6 are performed in parallel with each other.

[0153] In chip CH1_4, the timing generation circuit TG generates a timing control pulse of the activation level just before the timing t34. The pulses are supplied in parallel to the plurality of pulse control circuits PL1 to PL6 . The pulse control circuits PL1 to PL6 activate the corresponding output circuit OC in parallel with each other and transfer the signal of the pixel PX to the output terminal OS.

[0154] Thus, during the timing period from t34 to t35, with respect to chip CH1_4, signal transfer from output terminal OS1 to input terminal IN1 via line LN1, signal transfer from output terminal OS2 to input terminal IN2 via line LN2, signal transfer from output terminal OS3 to input terminal IN3 via line LN3, signal supply from output terminal OS4 to input terminal IN4 via line LN4, signal transfer from output terminal OS5 to input terminal IN5 via line LN5, and signal transfer from output terminal OS6 to input terminal IN6 via line LN6 are performed in parallel with each other.

[0155] In this way, each of CH1_1 to CH1_4 can transfer the signals of the plurality of unit blocks UB1 to UB6 to the analog front end AFE1 at high speed.

[0156] In addition, as a fifth variation of the embodiment, the solid-state imaging device 501 is as follows: Fig.13 As shown, in the case of manufacturing for cost-oriented purposes, it can also be Fig.13 The figure shows that it is composed of multiple chips. Fig.13 It is a diagram showing a structure of a solid-state imaging device 501 according to a fifth modification of the embodiment.

[0157] The solid-state imaging device 501 is different from the solid-state imaging device 201 (see Figure 7) is modified so that the chip CH2 is expanded into a plurality of chips CH2_1 to CH2_4, and the signal wiring WL2 is replaced with the signal wiring WL12.

[0158] The plurality of chips CH2_1 to CH2_4 are separated from each other on the substrate PCB2 and arranged in the column direction. This can increase the read length that can be scanned at one time by the solid-state imaging device 501. The analog front end AFE2 can also be arranged on the substrate PCB2 at a position separated from the plurality of chips CH2_1 to CH2_4 in the column direction.

[0159] The signal wiring WL12 connects the plurality of chips CH2_1 to CH2_4 in series with the analog front end AFE2. The signal wiring WL12 connects the plurality of output terminals OS1 to OS6 of each chip CH2 in series with the plurality of input terminals IN1 to IN6 of the analog front end AFE2.

[0160] The signal wiring WL12 includes a plurality of lines LN11_1 to LN16_1 , LN11_2 to LN16_2 , LN11_3 to LN16_3 , LN11_4 to LN16_4 , and a common line LN10 .

[0161] One end of the common line LN10 extends to the vicinity of the output terminal OS1 of the chip CH2_1 , and the other end thereof is connected to the input terminal IN of the analog front end AFE2 .

[0162] One ends of the lines LN11_1 to LN11_4 are connected to the output terminals OS1 of the chips CH2_1 to CH2_4 , respectively, and the other ends thereof are connected to the common line LN10 .

[0163] One ends of the lines LN12_1 to LN12_4 are connected to the output terminals OS2 of the chips CH2_1 to CH2_4 , respectively, and the other ends thereof are connected to the common line LN10 .

[0164] One ends of the lines LN13_1 to LN13_4 are connected to the output terminals OS3 of the chips CH2_1 to CH2_4 , respectively, and the other ends thereof are connected to the common line LN10 .

[0165] One ends of the lines LN14_1 to LN14_4 are connected to the output terminals OS4 of the chips CH2_1 to CH2_4 , respectively, and the other ends thereof are connected to the common line LN10 .

[0166] One ends of the lines LN15_1 to LN15_4 are connected to the output terminals OS5 of the chips CH2_1 to CH2_4 , respectively, and the other ends thereof are connected to the common line LN10 .

[0167] One ends of the lines LN16_1 to LN16_4 are connected to the output terminals OS6 of the chips CH2_1 to CH2_4 , respectively, and the other ends thereof are connected to the common line LN10 .

[0168] In the substrate PCB2, the chips CH2_1 to CH2_4 are separated and arranged in the column direction. Therefore, the common line group extending in the column direction can be efficiently laid out so as to form a gradually decreasing L-shape with the line groups extending in the row direction.

[0169] In each chip CH2 , the plurality of output terminals OS1 to OS6 are arranged in parallel and separated from each other in the column direction. Therefore, the plurality of lines LN11 to LN16 can be efficiently laid out in a substantially L-shape that gradually becomes smaller.

[0170] In the solid-state imaging device 501 , the plurality of chips CH2_1 to CH2_4 are configured to serially output to the analog front end AFE2 . Also, each chip CH2 is configured to serially output signals of the plurality of unit blocks UB1 to UB6 from the plurality of output terminals OS1 to OS6 to the analog front end AFE2 , similarly to the solid-state imaging device 201 .

[0171] For example, in chip CH2_1, the timing generation circuit TG is Fig.14 Before each timing t41 to t46 shown in the figure, the timing control pulse of the activation level is The pulses are supplied in parallel to the plurality of pulse control circuits PL1 to PL6 . The pulse control circuits PL1 to PL6 activate the corresponding output circuit OC in parallel with each other and transfer the signal of the pixel PX to the output terminal OS.

[0172] Thus, the signal transfer from the output terminal OS1 to the input terminal IN via the line LN11 and the common line 10 during the period of timing t41 to t42, the signal transfer from the output terminal OS2 to the input terminal IN via the line LN12 and the common line 10 during the period of timing t42 to t43, the signal transfer from the output terminal OS3 to the input terminal IN via the line LN13 and the common line 10 during the period of timing t43 to t44, the signal supply from the output terminal OS4 to the input terminal IN via the line LN14 and the common line 10 during the period of timing t44 to t45, the signal transfer from the output terminal OS5 to the input terminal IN via the line LN15 and the common line 10 during the period of timing t45 to t46, and the signal transfer from the output terminal OS6 to the input terminal IN via the line LN16 and the common line 10 during the period of timing t46 to t47 are performed serially.

[0173] In chip CH2_2, the timing generation circuit TG generates a timing control pulse of an active level just before each timing t47 to t52. The pulses are supplied in parallel to the plurality of pulse control circuits PL1 to PL6 . The pulse control circuits PL1 to PL6 activate the corresponding output circuit OC in parallel with each other and transfer the signal of the pixel PX to the output terminal OS.

[0174] Thus, the signal transfer from the output terminal OS1 to the input terminal IN via the line LN11 and the common line 10 during the period of timing t47 to t48, the signal transfer from the output terminal OS2 to the input terminal IN via the line LN12 and the common line 10 during the period of timing t48 to t49, the signal transfer from the output terminal OS3 to the input terminal IN via the line LN13 and the common line 10 during the period of timing t49 to t50, the signal supply from the output terminal OS4 to the input terminal IN via the line LN14 and the common line 10 during the period of timing t50 to t51, the signal transfer from the output terminal OS5 to the input terminal IN via the line LN15 and the common line 10 during the period of timing t51 to t52, and the signal transfer from the output terminal OS6 to the input terminal IN via the line LN16 and the common line 10 during the period of timing t52 to t53 are performed serially.

[0175] In chip CH2_3, the timing generation circuit TG generates a timing control pulse of the active level just before each timing t53 to t58. The pulses are supplied in parallel to the plurality of pulse control circuits PL1 to PL6 . The pulse control circuits PL1 to PL6 activate the corresponding output circuit OC in parallel with each other and transfer the signal of the pixel PX to the output terminal OS.

[0176] Thus, the signal transfer from the output terminal OS1 to the input terminal IN via the line LN11 and the common line 10 during the period of timing t53 to t54, the signal transfer from the output terminal OS2 to the input terminal IN via the line LN12 and the common line 10 during the period of timing t54 to t55, the signal transfer from the output terminal OS3 to the input terminal IN via the line LN13 and the common line 10 during the period of timing t55 to t56, the signal supply from the output terminal OS4 to the input terminal IN via the line LN14 and the common line 10 during the period of timing t56 to t57, the signal transfer from the output terminal OS5 to the input terminal IN via the line LN15 and the common line 10 during the period of timing t57 to t58, and the signal transfer from the output terminal OS6 to the input terminal IN via the line LN16 and the common line 10 during the period of timing t58 to t59 are performed serially.

[0177] In chip CH2_4, the timing generation circuit TG generates a timing control pulse of the active level just before each timing t59 to t64. The pulses are supplied in parallel to the plurality of pulse control circuits PL1 to PL6 . The pulse control circuits PL1 to PL6 activate the corresponding output circuit OC in parallel with each other and transfer the signal of the pixel PX to the output terminal OS.

[0178] Thus, the signal transfer from the output terminal OS1 to the input terminal IN via the line LN11 and the common line 10 during the timing period t59 to t60, the signal transfer from the output terminal OS2 to the input terminal IN via the line LN12 and the common line 10 during the timing period t60 to t61, the signal transfer from the output terminal OS3 to the input terminal IN via the line LN13 and the common line 10 during the timing period t61 to t62, the signal supply from the output terminal OS4 to the input terminal IN via the line LN14 and the common line 10 during the timing period t62 to t63, the signal transfer from the output terminal OS5 to the input terminal IN via the line LN15 and the common line 10 during the timing period t63 to t64, and the signal transfer from the output terminal OS6 to the input terminal IN via the line LN16 and the common line 10 during the timing period t64 to t65 are performed serially.

[0179] Here, the signal wiring WL12 and the signal wiring WL11 (see Fig.11 ) can be manufactured at a lower cost by shortening the total length. Fig.11 ) compared to the analog front end, the number of input terminals IN is smaller, the circuit structure between the input terminals IN and the digital processing circuit DPC can be simplified, and a cheap version of the analog front end can be used.

[0180] In this way, each of CH2_1 to CH2_4 can transfer the signals of the plurality of unit blocks UB1 to UB6 to the analog front end AFE2 at low cost.

[0181] In addition, as a sixth variation of the embodiment, the solid-state imaging device 601 is as follows: Fig.15 As shown, in the case of being manufactured for use taking into account speed and cost, it can also be as shown Fig.15 The figure shows that it is composed of multiple chips. Fig.15 It is a diagram showing a structure of a solid-state imaging device 601 according to a sixth modification of the embodiment.

[0182] The solid-state imaging device 601 is different from the solid-state imaging device 301 (see Fig. 9 ) is modified so that the chip CH3 is expanded into a plurality of chips CH3_1 to CH3_4, and the signal wiring WL3 is replaced with the signal wiring WL13.

[0183] The plurality of chips CH3_1 to CH3_4 are separated from each other on the substrate PCB3 and arranged in the column direction. This can increase the read length that can be scanned at one time by the solid-state imaging device 601. The analog front end AFE3 can also be arranged on the substrate PCB3 at a position separated from the plurality of chips CH3_1 to CH3_4 in the column direction.

[0184] The signal wiring WL13 connects the multiple chips CH3_1 to CH3_4 in series with the analog front end AFE3. The signal wiring WL13 connects the multiple output terminal groups of each chip CH3 in parallel with the multiple input terminals IN11 to IN13 of the analog front end AFE3, and connects two or more output terminals OS of each output terminal group in series with the input terminals of the analog front end AFE3.

[0185] The signal wiring WL13 includes a plurality of lines LN21_1 to LN21_4, LN22_1 to LN22_4, common lines LN23_1 to LN23_4, a plurality of lines LN24_1 to LN24_4, LN25_1 to LN25_4, common lines LN26_1 to LN26_4, a plurality of lines LN27_1 to LN27_4, LN28_1 to LN28_4, and common lines LN29_1 to LN29_4.

[0186] One end of the common line LN23 extends to the vicinity of the output terminal OS1 of the chip CH3_1 , and the other end thereof is connected to the input terminal IN11 of the analog front end AFE3 .

[0187] One ends of the lines LN21_1 to LN21_4 are connected to the output terminals OS1 of the chips CH3_1 to CH3_4 , respectively, and the other ends thereof are connected to the common line LN23 .

[0188] One ends of the lines LN22_1 to LN22_4 are connected to the output terminals OS2 of the chips CH3_1 to CH3_4 , respectively, and the other ends thereof are connected to the common line LN23 .

[0189] One end of the common line LN26 extends to the vicinity of the output terminal OS3 of the chip CH3_1 , and the other end thereof is connected to the input terminal IN12 of the analog front end AFE3 .

[0190] One ends of the lines LN24_1 to LN24_4 are connected to the output terminals OS3 of the chips CH3_1 to CH3_4 , respectively, and the other ends thereof are connected to the common line LN26 .

[0191] One ends of the lines LN25_1 to LN25_4 are connected to the output terminals OS4 of the chips CH3_1 to CH3_4 , respectively, and the other ends thereof are connected to the common line LN26 .

[0192] One end of the common line LN29 extends to the vicinity of the output terminal OS5 of the chip CH3 , and the other end thereof is connected to the input terminal IN13 of the analog front end AFE3 .

[0193] One ends of the lines LN27_1 to LN27_4 are connected to the output terminals OS5 of the chips CH3_1 to CH3_4 , respectively, and the other ends thereof are connected to the common line LN29 .

[0194] One ends of the lines LN28_1 to LN28_4 are connected to the output terminals OS6 of the chips CH3_1 to CH3_4 , respectively, and the other ends thereof are connected to the common line LN29 .

[0195] In the substrate PCB3, the plurality of chips CH3_1 to CH3_4 are separated and arranged in the column direction, so that the line groups extending in the column direction can be efficiently laid out so as to form a substantially L-shape with the plurality of line groups extending in the row direction.

[0196] In each chip CH3, a plurality of output terminal groups are arranged in parallel and separated in the column direction. Therefore, a plurality of lines LN1 to LN6 can be efficiently laid out in a substantially L-shape that gradually becomes smaller for each output terminal group.

[0197] In the solid-state imaging device 601, a plurality of chips CH3_1 to CH3_4 are configured to output serially to the analog front end AFE3. In addition, each chip CH3 is configured to output signals of a plurality of unit blocks UB in parallel from a plurality of output terminal groups to a plurality of input terminals IN11 to IN13 of the analog front end AFE1, and to output serially from two or more output terminals OS of each output terminal group to the input terminals of the analog front end AFE3, which is the same as the solid-state imaging device 301.

[0198] For example, in chip CH3_1, the timing generation circuit TG is Fig.16 Before each timing t71 shown, the timing control pulse of the activation level The odd-numbered pulse control circuits PL1, PL3, PL5 are supplied in parallel. The odd-numbered pulse control circuits PL1, PL3, PL5 activate the corresponding output circuits OC1, OC3, OC5 in parallel with each other and transfer the signal of the pixel PX to the output terminals OS1, OS3, OS5.

[0199] Thus, during the timing period t71 to t72, the signal transfer from the output terminal OS1 to the input terminal IN11 via the line LN21_1 and the common line LN23, the signal transfer from the output terminal OS3 to the input terminal IN12 via the line LN24_1 and the common line LN26, and the signal transfer from the output terminal OS5 to the input terminal IN13 via the line LN27_1 and the common line LN29 are performed in parallel.

[0200] Just before the timing t72, the timing control pulse of the activation level is The even-numbered pulse control circuits PL2, PL4, PL6 are supplied in parallel. The even-numbered pulse control circuits PL2, PL4, PL6 activate the corresponding output circuits OC2, OC4, OC6 in parallel with each other and transfer the signal of the pixel PX to the output terminals OS2, OS4, OS6.

[0201] Thus, during the timing period t72 to t73, the signal transfer from the output terminal OS2 to the input terminal IN11 via the line LN22_1 and the common line LN23, the signal transfer from the output terminal OS4 to the input terminal IN12 via the line LN25_1 and the common line LN26, and the signal transfer from the output terminal OS6 to the input terminal IN13 via the line LN28_1 and the common line LN29 are performed in parallel.

[0202] That is, signal transfer from the odd-numbered output terminals to the input terminals IN11 to IN13 via the lines and the common line during the period of timing t71 to t72, and signal transfer from the even-numbered output terminals to the input terminals IN11 to IN13 via the lines and the common line during the period of timing t72 to t73 are performed serially.

[0203] In the chip CH3_2, the timing generation circuit TG generates a timing control pulse of the active level just before each timing t73. The odd-numbered pulse control circuits PL1, PL3, PL5 are supplied in parallel. The odd-numbered pulse control circuits PL1, PL3, PL5 activate the corresponding output circuits OC1, OC3, OC5 in parallel with each other and transfer the signal of the pixel PX to the output terminals OS1, OS3, OS5.

[0204] Thus, during the timing period t73 to t74, the signal transfer from the output terminal OS1 to the input terminal IN11 via the line LN21_2 and the common line LN23, the signal transfer from the output terminal OS3 to the input terminal IN12 via the line LN24_2 and the common line LN26, and the signal transfer from the output terminal OS5 to the input terminal IN13 via the line LN27_2 and the common line LN29 are performed in parallel.

[0205] Just before the timing t74, the timing control pulse of the activation level is The even-numbered pulse control circuits PL2, PL4, PL6 are supplied in parallel. The even-numbered pulse control circuits PL2, PL4, PL6 activate the corresponding output circuits OC2, OC4, OC6 in parallel with each other and transfer the signal of the pixel PX to the output terminals OS2, OS4, OS6.

[0206] Thus, during the timing period t74 to t75, the signal transfer from the output terminal OS2 to the input terminal IN11 via the line LN22_2 and the common line LN23, the signal transfer from the output terminal OS4 to the input terminal IN12 via the line LN25_2 and the common line LN26, and the signal transfer from the output terminal OS6 to the input terminal IN13 via the line LN28_2 and the common line LN29 are performed in parallel.

[0207] That is, signal transfer from the odd-numbered output terminals to the input terminals IN11 to IN13 via the lines and the common line during the period of timing t73 to t74, and signal transfer from the even-numbered output terminals to the input terminals IN11 to IN13 via the lines and the common line during the period of timing t74 to t75 are performed serially.

[0208] In the chip CH3_3, the timing generation circuit TG generates a timing control pulse of the active level just before each timing t75. The odd-numbered pulse control circuits PL1, PL3, PL5 are supplied in parallel. The odd-numbered pulse control circuits PL1, PL3, PL5 activate the corresponding output circuits OC1, OC3, OC5 in parallel with each other and transfer the signal of the pixel PX to the output terminals OS1, OS3, OS5.

[0209] Thus, during the timing period t75 to t76, the signal transfer from the output terminal OS1 to the input terminal IN11 via the line LN21_3 and the common line LN23, the signal transfer from the output terminal OS3 to the input terminal IN12 via the line LN24_3 and the common line LN26, and the signal transfer from the output terminal OS5 to the input terminal IN13 via the line LN27_3 and the common line LN29 are performed in parallel.

[0210] Just before the timing t76, the timing control pulse of the activation level is The even-numbered pulse control circuits PL2, PL4, PL6 are supplied in parallel. The even-numbered pulse control circuits PL2, PL4, PL6 activate the corresponding output circuits OC2, OC4, OC6 in parallel with each other and transfer the signal of the pixel PX to the output terminals OS2, OS4, OS6.

[0211] Thus, during the timing period t76 to t77, the signal transfer from the output terminal OS2 to the input terminal IN11 via the line LN22_3 and the common line LN23, the signal transfer from the output terminal OS4 to the input terminal IN12 via the line LN25_3 and the common line LN26, and the signal transfer from the output terminal OS6 to the input terminal IN13 via the line LN28_3 and the common line LN29 are performed in parallel.

[0212] That is, signal transfer from the odd-numbered output terminals to the input terminals IN11 to IN13 via the lines and the common line during the period of timing t75 to t76, and signal transfer from the even-numbered output terminals to the input terminals IN11 to IN13 via the lines and the common line during the period of timing t76 to t77 are performed serially.

[0213] In chip CH3_4, the timing generation circuit TG generates a timing control pulse of the activation level just before each timing t77. The odd-numbered pulse control circuits PL1, PL3, PL5 are supplied in parallel. The odd-numbered pulse control circuits PL1, PL3, PL5 activate the corresponding output circuits OC1, OC3, OC5 in parallel with each other and transfer the signal of the pixel PX to the output terminals OS1, OS3, OS5.

[0214] Thus, during the timing period t77 to t78, the signal transfer from the output terminal OS1 to the input terminal IN11 via the line LN21_4 and the common line LN23, the signal transfer from the output terminal OS3 to the input terminal IN12 via the line LN24_4 and the common line LN26, and the signal transfer from the output terminal OS5 to the input terminal IN13 via the line LN27_4 and the common line LN29 are performed in parallel.

[0215] Just before the timing t78, the timing control pulse of the activation level is The even-numbered pulse control circuits PL2, PL4, PL6 are supplied in parallel. The even-numbered pulse control circuits PL2, PL4, PL6 activate the corresponding output circuits OC2, OC4, OC6 in parallel with each other and transfer the signal of the pixel PX to the output terminals OS2, OS4, OS6.

[0216] Thus, during the timing period t78 to t79, the signal transfer from the output terminal OS2 to the input terminal IN11 via the line LN22_4 and the common line LN23, the signal transfer from the output terminal OS4 to the input terminal IN12 via the line LN25_4 and the common line LN26, and the signal transfer from the output terminal OS6 to the input terminal IN13 via the line LN28_4 and the common line LN29 are performed in parallel.

[0217] That is, signal transfer from the odd-numbered output terminals to the input terminals IN11 to IN13 via the lines and the common line during the period of timing t77 to t78, and signal transfer from the even-numbered output terminals to the input terminals IN11 to IN13 via the lines and the common line during the period of timing t78 to t79 are performed serially.

[0218] Here, the signal wiring WL13 and the signal wiring WL11 (see Fig.11 ) can be manufactured at a lower cost by shortening the total length. Fig.11 ) compared to the analog front end, the number of input terminals IN11~IN13 is smaller, the circuit structure between the input terminals IN11~IN13 and the digital processing circuit DPC can be simplified, and a cheap version of the analog front end can be used.

[0219] In this way, each of the chips CH3_1 to CH3_4 can transfer the signals of the plurality of unit blocks UB1 to UB6 to the analog front end AFE3 in consideration of both speed and cost.

[0220] Several embodiments of the present invention are described above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope or spirit of the invention and are included in the invention described in the claims and their equivalents.

Claims

1. A solid-state imaging device, wherein: With chip, The chip has: A pixel arrangement, wherein a plurality of pixel groups are arranged at least in a column direction, wherein each of the plurality of pixel groups includes more than two pixels; A plurality of signal lines, corresponding to the plurality of pixel groups, and respectively connected to the corresponding pixel groups; A plurality of output circuits corresponding to the plurality of signal lines and connected to the corresponding signal lines respectively; as well as The plurality of output terminals correspond to the plurality of output circuits and are respectively connected to the corresponding output circuits.

2. The solid-state imaging device according to claim 1, wherein The chip further includes a control circuit connected to each of the plurality of output circuits.

3. The solid-state imaging device according to claim 2, wherein: The control circuit controls the plurality of output circuits so that signals are output in series from the plurality of output circuits to the plurality of output terminals.

4. The solid-state imaging device according to claim 2, wherein: The control circuit controls the plurality of output circuits so that signals are output in parallel from the plurality of output circuits to the plurality of output terminals.

5. The solid-state imaging device according to claim 2, wherein: The plurality of output circuits are grouped into a plurality of output circuit groups each including two or more output circuits. The plurality of output terminals are grouped into a plurality of output terminal groups each including two or more output terminals. The control circuit controls the multiple output circuits to output signals in parallel from the multiple output circuit groups to the multiple output terminal groups, and to output signals in series from more than two output circuits in each output circuit group of the multiple output circuit groups to more than two output terminals in the output terminal group.

6. The solid-state imaging device according to claim 2, wherein: The control circuit controls, for each of the plurality of output circuits, whether or not to output a signal to the plurality of output terminals.

7. The solid-state imaging device according to claim 1, wherein: The chip also has a scanning circuit for scanning the pixel arrangement in the column direction. The scanning circuit has a plurality of circuit blocks corresponding to the plurality of pixel groups.

8. The solid-state imaging device according to claim 1, wherein: Also available: Analog front end; and Signal wiring connects the plurality of output terminals in parallel with the analog front end.

9. The solid-state imaging device according to claim 1, wherein: Also available: Analog front end; and Signal wiring connects the plurality of output terminals to the analog front end in series.

10. The solid-state imaging device according to claim 1, wherein The plurality of output terminals are grouped into a plurality of output terminal groups each including two or more output terminals. The solid-state imaging device further comprises: Analog front end; as well as The signal wiring connects the plurality of output terminal groups to the analog front end in parallel, and connects the two or more output terminals to the analog front end in series.

11. The solid-state imaging device according to claim 1, wherein The solid-state imaging device includes a plurality of the chips. The solid-state imaging device further includes an analog front end to which the plurality of chips are connected.

12. The solid-state imaging device according to claim 11, wherein: Also available: Signal wiring connects the multiple chips to the analog front end in series.

13. The solid-state imaging device according to claim 12, wherein: The signal wiring connects the plurality of output terminals of each of the plurality of chips in series with the analog front end.

14. The solid-state imaging device according to claim 12, wherein: The signal wiring connects the plurality of output terminals of each of the plurality of chips in parallel with the analog front end.

15. The solid-state imaging device according to claim 12, wherein: In each of the plurality of chips, the plurality of output terminals are grouped into a plurality of output terminal groups each including two or more output terminals, The signal wiring connects the plurality of output terminal groups in each of the plurality of chips to the analog front end in parallel, and connects the two or more output terminals to the analog front end in series.

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