State monitoring method and device for baseband chip of communication system and baseband chip

Abstract

The invention provides a state monitoring method and device for a baseband chip of a communication system and the baseband chip. The baseband chip comprises a first processor core, a second processor core and a shared memory, a first baseband state monitoring program runs on the first processor core, and a second baseband state monitoring program runs on the second processor core; the method comprises the following steps: for any one of a first baseband state monitoring program and a second baseband state monitoring program, in response to a state frame write-in request for recording baseband state information of a baseband chip, constructing the baseband state information into a baseband state frame, and writing the baseband state frame into a shared memory; and for the first baseband state monitoring program, in response to the state frame processing being triggered, reading and analyzing the baseband state frame from the shared memory to obtain baseband state information. The baseband state monitoring scheme disclosed by the invention is good in universality.

Description

Technical Field

[0001] The present disclosure relates to the field of communications, and in particular to a method for monitoring the status of a baseband chip of a communication system, a device for monitoring the status of a baseband chip of a communication system, a non-transitory computer-readable storage medium, a computer program product, and a baseband chip of a communication system. Background Art

[0002] From 2G, 2.5G, 3G, 4G to 5G, wireless communication systems have developed rapidly. The baseband chip of the communication system is the core component in the user terminal.

[0003] From the perspective of data flow, the basic functions of the baseband chip include synthesizing the baseband signal to be sent (uplink) or decoding the received baseband signal (downlink). From the perspective of functional type, the functions of the baseband chip include communication and application. The application function has low requirements for real-time performance. The communication function includes baseband signal processing and protocol stack. The baseband signal processing part implements the functions of the communication protocol layer (physical layer), such as encoding and decoding, modulation and demodulation, encryption and decryption, synchronization, etc. The protocol stack part implements high-level communication protocol functions and has real-time requirements. Different functional types of baseband chips can be implemented by different processors and different operating systems.

[0004] Currently, the monitoring solutions for communication systems are mainly focused on spectrum monitoring. For baseband chips using different processor architectures and different operating systems, there is a lack of universal monitoring solutions for the baseband status of communication systems to ensure the smooth progress of the research and development process. Summary of the invention

[0005] It would be advantageous to provide a mechanism that mitigates, alleviates or eliminates at least one of the problems discussed above.

[0006] In a first aspect, a state monitoring method for a baseband chip of a communication system is provided. The baseband chip includes a first processor core, a second processor core and a shared memory, a first baseband state monitoring program is run on the first processor core, and a second baseband state monitoring program is run on the second processor core, and the method includes: for any one of the first baseband state monitoring program and the second baseband state monitoring program: in response to a state frame write request for recording baseband state information of the baseband chip, the baseband state information is constructed into a baseband state frame and written into the shared memory; and for the first baseband state monitoring program: in response to a state frame processing being triggered, the baseband state frame is read out and parsed from the shared memory to obtain the baseband state information.

[0007] In a second aspect, a state monitoring device for a baseband chip of a communication system is provided, wherein the state monitoring device comprises a device for executing the above-mentioned state monitoring method.

[0008] In a third aspect, a non-transitory computer-readable storage medium storing machine-executable instructions is provided. When the machine-executable instructions are executed by a baseband chip of a communication system, the baseband chip executes the above-mentioned state monitoring method.

[0009] In a fourth aspect, a computer program product comprising machine executable instructions is provided. When the machine executable instructions are executed by a baseband chip of a communication system, the baseband chip executes the above-mentioned state monitoring method.

[0010] In a fifth aspect, a baseband chip of a communication system is provided, the baseband chip comprising a first processor core, a second processor core and a shared memory, the first processor core and the second processor core being configured to respectively run a first baseband status monitoring program and a second baseband status monitoring program to execute the above-mentioned status monitoring method.

[0011] It should be understood that the invention summary is not intended to identify the key or essential features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects, features and advantages of the present disclosure will become more apparent through a more detailed description of some embodiments of the present disclosure in the accompanying drawings, in which: Figure 1 A schematic diagram of a communication system baseband chip in which exemplary embodiments of the present disclosure may be implemented is shown; Figure 2 A schematic diagram showing the interaction relationship between a processor core and a shared memory according to some embodiments of the present disclosure; Figure 3 A schematic diagram of the structure of a shared memory according to some embodiments of the present disclosure is shown; Figure 4 A schematic diagram showing various modules in a baseband status monitoring system according to some embodiments of the present disclosure is shown; Figure 5 A flowchart showing the steps executed by the initialization module according to some embodiments of the present disclosure is shown; Figure 6 A flowchart showing the steps executed by the status frame writing module according to some embodiments of the present disclosure is shown; Figure 7 A flowchart showing the steps executed by the status frame processing module according to some embodiments of the present disclosure is shown; Figure 8 A flowchart showing steps performed by a user module according to some embodiments of the present disclosure; and Fig. 9 A simplified block diagram of a status monitoring device for a baseband chip of a communication system suitable for implementing an exemplary embodiment of the present disclosure is shown.

[0013] Description of the accompanying drawings in the specific implementation manner: 10. Baseband status monitoring system; 110. Status frame writing module; 120. Status frame processing module; 130. Initialization module; 140. User module; 20. Baseband chip; 210. A first processor core; 220. A second processor core; 30. Shared memory; 31. Shared buffer; 310. Control buffer; 3101. Lock symbol; 3102. Next frame number; 3103. Number to be processed; 3104.Write address; 3105. Read address; 3106. Switch mask; 320. Data buffer; 3201. Baseband status frame; 3202. Header information; 3203.Frame number; 3204. Time information; 3205. Frame level; 3206. Baseband status information length; 3207. Baseband status information. DETAILED DESCRIPTION

[0014] The principle of the present disclosure will now be described with reference to some embodiments. It should be understood that the description of these embodiments is only for illustrative purposes, and helps those skilled in the art to understand and implement the present disclosure, without any limitation to the scope of the present disclosure. The disclosure described herein can be implemented in a manner different from that described below.

[0015] In the following description and claims, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0016] References in this disclosure to "one embodiment," "an embodiment," "an exemplary embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an exemplary embodiment, whether or not explicitly described, those skilled in the art will recognize that such feature, structure, or characteristic affects incorporation into other embodiments.

[0017] It should be understood that although the terms "first" and "second" etc. may be used to describe various elements herein, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The term "and / or" as used herein includes any and all combinations of one or more of the listed terms.

[0018] The terms used herein are only for describing specific embodiments, rather than for limiting exemplary embodiments. The singular forms "one", "an", and "the" used herein also include plural forms, unless the context clearly indicates otherwise. "A group of elements" or "element set" used herein is intended to include one or more elements. It should also be understood that the terms "include", "comprise", "have", "have", "include" and / or "include", when used herein, specify the presence of the features, elements and / or parts, etc., but do not exclude the presence or addition of one or more other features, elements, parts and / or combinations thereof.

[0019] As used in this disclosure, the term "circuitry" may refer to one or more or all of the following: (a) Hardware circuit implementation only (e.g., implementation only in analog and / or digital circuits) (b) a combination of hardware circuitry and software, such as (where applicable): (i) a combination of analog and / or digital hardware circuitry and software / firmware; and (ii) any part of a hardware processor (including a digital signal processor) with software, software and memory that work together to enable a device such as a mobile phone or server to perform various functions, and (c) A hardware circuit and / or processor, such as a microprocessor or portion of a microprocessor, that requires software (eg, firmware) to operate, but where software is not required for operation, the software may not be present.

[0020] This definition of circuitry applies to all uses of this term in this disclosure, including in any claims. As another example, as used in this disclosure, the term circuitry also includes an implementation of merely a hardware circuit or processor (or multiple processors) or a portion of a hardware circuit or processor and its (or their) accompanying software and / or firmware. The term circuitry also includes, for example, if applicable to the particular claim element, a baseband integrated circuit or processor integrated circuit for a mobile device, or a similar integrated circuit in a server, cellular network device, or other computing network device.

[0021] As used herein, the term "communication network" refers to a network that complies with any appropriate communication standard, such as Long Term Evolution (LTE), LTE-Advanced (LTE-A), Wideband Code Division Multiple Access (WCDMA), High Speed ​​Packet Access (HSPA), Narrowband Internet of Things (NB-IoT), New Radio (NR), Non-terrestrial Network (NTN), etc. In addition, the communication between the terminal equipment and the network equipment in the communication network can be performed according to any appropriate generation of communication protocols, including but not limited to the first generation (1G), second generation (2G), 2.5G, 2.75G, third generation (3G), fourth generation (4G), 4.5G, fifth generation (5G), future sixth generation (6G) communication protocols, and / or any other protocols currently known or to be developed in the future. The embodiments of the present disclosure can be applied in satellite communication systems. In view of the rapid development in communication, there will certainly be future types of communication technologies and systems, and the present disclosure can be implemented with these technologies and systems. It should not be considered that the scope of the present disclosure is limited to the aforementioned system.

[0022] The term "terminal device" used herein refers to any terminal device capable of wireless communication. As an example and not a limitation, the terminal device may also be referred to as a communication device, a user terminal, a user equipment (UE), a user station (SS), a portable user station, a mobile station (MS) or an access terminal (AT). The terminal device may include, but is not limited to, a mobile phone, a cellular phone, a smart phone, a voice over IP (VoIP) phone, a wireless local loop phone, a tablet computer, a wearable terminal device, a personal digital assistant (PDA), a portable computer, a desktop computer, an image capture terminal device such as a digital camera, a game terminal device, a music storage and playback device, a vehicle-mounted wireless terminal device, a wireless endpoint, a mobile station, a notebook embedded device (LEE), a laptop computer installation device (LME), a USB dongle, a smart device, a wireless user equipment (CPE), an Internet of Things (IoT) device, a watch or other wearable device, a head-mounted display (HMD), a vehicle, a drone, medical equipment and applications (e.g., remote surgery), industrial equipment and applications (e.g., robots and / or other wireless devices operating in the context of industrial and / or automated processing chains), consumer electronic devices, relay nodes, equipment operating on commercial and / or industrial wireless networks, etc. The mobile terminal (MT) part of the IAB node can perform the functions of a "terminal device" and can therefore operate as a terminal device. In the following description, the terms "terminal device", "communication device", "terminal", "user terminal", "user equipment" and "UE" can be used interchangeably.

[0023] Although the functions described herein may be performed in fixed and / or wireless network nodes in various exemplary embodiments, in other exemplary embodiments, the functions may be implemented in a user equipment device (such as a cellular phone, or a tablet computer, or a laptop computer, or a desktop computer, or a mobile Internet of Things device, or a fixed Internet of Things device). For example, the user equipment device may appropriately have the corresponding capabilities described in relation to fixed and / or wireless network nodes. The user equipment device may be a user device and / or a control device, such as a chipset or a processor, which is configured to control the user device when the user device is installed therein. Examples of these functions include boot server functions and / or home user servers, which may be implemented in a user equipment device by providing the user equipment device with software configured to cause the user equipment device to execute from the perspective of these functions / nodes.

[0024] The traditional baseband chip architecture uses a heterogeneous dual-core processor. The baseband signal processing function of the physical layer is completed by DSP (Digital Signal Processing), and the protocol stack processing function is usually implemented by ARM CPU, which is a processor based on the Reduced Instruction Set Computer (RISC) architecture. If the real-time requirements of the baseband chip protocol stack are taken into consideration, a system with low task scheduling overhead such as a real-time operating system can be selected, while application software without real-time requirements can be selected based on actual performance needs.

[0025] In the process of developing baseband chips for communication systems, a large amount of algorithm testing and evaluation is required, as well as complex real-time scenario verification. In order to ensure the smooth progress of the baseband chip development process, the baseband status needs to be monitored. By collecting, processing, feeding back and storing baseband status information, abnormal or important situations of the physical layer and protocol stack can be further analyzed and processed to ensure the normal operation of the communication system. The baseband status usually includes information such as data flow, synchronization, and scheduling.

[0026] Baseband chips have evolved from single-mode to multi-mode, and from the ARM+DSP dual-core structure of traditional baseband chips to other multi-core structures. The choice of operating system and the division of operating functions of different processors all affect the architecture of baseband chips. As communication requirements continue to increase, the structure of baseband chips is becoming more and more complex.

[0027] At present, the monitoring research of communication systems mainly focuses on spectrum monitoring, ignoring the monitoring needs of real-time acquisition, analysis and processing of baseband status. For baseband chips with different processor architectures and different operating systems, there is a lack of a universal monitoring solution for the baseband status of communication systems to ensure the smooth progress of the research and development process.

[0028] The embodiment of the present disclosure proposes a state monitoring scheme for a baseband chip of a communication system, which is suitable for state monitoring of baseband chips of communication systems with different processor architectures and different operating systems, has good versatility, and can ensure the smooth progress of the baseband chip development process. In this solution, the present disclosure designs the workflow of the first baseband state monitoring program and the second baseband state monitoring program. The present disclosure constructs the first baseband state monitoring program and the second baseband state monitoring program as a baseband state monitoring system, and realizes a dedicated processor core interaction mechanism for monitoring through each software module of the baseband state monitoring system and its functions and workflow. In response to the request or instruction of the first processor core and the second processor core, the baseband state frame is written into the shared memory, and the baseband state information of the baseband chip is parsed from the baseband state frame, which can realize real-time monitoring of the baseband state and timely provide the state information of the baseband chip, which helps to improve the stability and reliability of the communication system (such as a satellite communication system).

[0029] The following will refer to Figure 1 and Figure 4 The principles and implementations of the present disclosure are described in detail.

[0030] Figure 1 A schematic diagram of a communication system baseband chip in which exemplary embodiments of the present disclosure may be implemented is shown. Figure 4 A schematic diagram of each module in a baseband status monitoring system according to some embodiments of the present disclosure is shown.

[0031] The present disclosure proposes a method for monitoring the status of a baseband chip in a communication system. Figure 1 As shown, the baseband chip 20 includes a first processor core 210, a second processor core 220 and a shared memory 30. The first processor core 210 runs a first baseband status monitoring program (not shown in the figure), and the second processor core 220 runs a second baseband status monitoring program (not shown in the figure). In practical applications, the first baseband status monitoring program and the second baseband status monitoring program can be constructed into a baseband status monitoring system 10. Exemplarily, the first processor core 210 is equivalent to a monitoring main core, and the second processor core 220 is equivalent to a non-monitoring main core.

[0032] The status monitoring method disclosed in the present invention includes: for either the first baseband status monitoring program or the second baseband status monitoring program: in response to a status frame write request for recording baseband status information of the baseband chip 20, the baseband status information is constructed into a baseband status frame and written into the shared memory 30; and for the first baseband status monitoring program: in response to the status frame processing being triggered, the baseband status frame is read out and parsed from the shared memory 30 to obtain the baseband status information.

[0033] refer to Figure 1 and Figure 4 As shown, the baseband status monitoring system 10 includes: a status frame writing module 110 and a status frame processing module 120. The status frame writing module 110 can be configured to: in response to a status frame writing request for recording the baseband status information of the baseband chip 20, construct the baseband status information into a baseband status frame and write it into the shared memory 30. The status frame processing module 120 can be configured to: in response to the status frame processing being triggered, read out and parse the baseband status frame from the shared memory 30 to obtain the baseband status information.

[0034] Figure 2 FIG. 1 is a schematic diagram showing the interaction relationship between a processor core and a shared memory according to some embodiments of the present disclosure. Figure 2 As shown, exemplarily, the baseband chip 20 of the communication system can adopt a single-core processor architecture, or a homogeneous or heterogeneous multi-core processor architecture. The processor can be a DSP, an ARM CPU, a RISC_V CPU (fifth-generation reduced instruction processor), etc. For the convenience of description, different IDs can be used to distinguish different core processors. Figure 2 In the figure, a baseband chip 20 using a dual-core processor (CPU0 and CPU1) is taken as an example, but in practice it can also be expanded to a multi-core system.

[0035] For example, Figure 2 As shown, CPU0 is responsible for implementing the physical layer function of the communication protocol, and CPU1 is responsible for implementing the protocol stack function. If it is a multi-core system, there may also be CPU2, CPU3, etc. In practical applications, whether it is a single-core or multi-core processor architecture, CPU0 can be assumed to be the recorder of the baseband status. Other cores record their respective baseband status information through shared memory 30, which is uniformly processed by CPU0 and stored in a specified manner, such as printing and saving as a file through the host computer, storing in FLASH memory (i.e., Flash Memory), etc. In addition, CPU0 can provide a user interface, through which the user can turn on or off all or part of the monitoring function.

[0036] Exemplarily, the baseband status monitoring systems 10 (also referred to as baseband status monitoring modules) of different processor cores communicate via a shared memory 30, and the shared memory 30 is divided into a control buffer 310 and a data buffer 320. The baseband status monitoring system 10 of the communication system disclosed in the present invention is suitable for status monitoring of baseband chips 20 of communication systems with different processor architectures and different operating systems, has good versatility, and can ensure the smooth progress of the development process of the baseband chip 20.

[0037] Figure 3 FIG. 4 shows a schematic diagram of a shared memory structure according to some embodiments of the present disclosure. Figure 2 and Figure 3As shown, in some embodiments, the shared memory 30 includes a shared buffer 31, the shared buffer 31 includes a control buffer 310 and a data buffer 320, the data buffer 320 is used to store multiple baseband status frames 3201; the data structure of the control buffer 310 includes: a lock flag 3101, a next frame number 3102, a number to be processed 3103, a write address 3104, a read address 3105, a switch mask 3106, or any combination thereof; the data structure of the baseband status frame 3201 includes header information 3202 and baseband status information 3207, the header information 3202 includes: a frame number 3203, time information 3204, a frame level 3205, a CPU ID, and a baseband status information length 3206, or any combination thereof.

[0038] Exemplarily, the present disclosure can achieve efficient storage and management of multiple baseband status frames 3201 through the data structure in the shared memory 30, wherein the control buffer 310 can manage the synchronization and status of data access, and the header information 3202 of the baseband status frame 3201 can ensure the orderliness and traceability of the data, thereby jointly improving the capability and efficiency of baseband status data processing.

[0039] refer to Figure 3 As shown, in some embodiments, in the data structure of the control buffer 310: the lock flag 3101 is used to identify whether the shared buffer 31 is locked or unlocked; the next frame sequence number 3102 is used to identify the sequence number of the next baseband status frame in the data buffer 320; the number to be processed 3103 is used to identify the number of baseband status frames to be processed in the data buffer 320; the write address 3104 is used to identify the write address of the next baseband status frame in the data buffer 320; the read address 3105 is used to identify the earliest first address of the baseband status frames to be processed in the data buffer 320; the switch mask 3106 is used to identify whether the monitoring function of the baseband status frame is turned on or off.

[0040] In the header information 3202: the frame number 3203 is used to identify the serial number of the baseband status frame; the time information 3204 is used to identify the time when the baseband status information 3207 is generated; the frame level 3205 is used to identify the importance of the baseband status frame 3201; the CPUID is used to identify the core processor source of the baseband status frame 3201, and the core processor source includes the first processor core 210 and the second processor core 220.

[0041] For example, continue to refer to Figure 3 As shown, the control buffer 310 can be set to a fixed size, the data buffer 320 can be set to a circular buffer, and the data buffer 320 is divided into a plurality of baseband status frame spaces of the same size (maximum length of a single frame). The meaning of each byte of the control buffer 310 is as follows.

[0042] Lock flag 3101 (lockflag): lock flag of shared buffer 31 to avoid memory data conflict caused by different kernels accessing shared memory 30 at different times. lockflag takes a value of 0 or 1. For example, lockflag is 0, indicating locking, and lockflag is 1, indicating unlocking. Only when lockflag is 0 (locked), the kernel is allowed to write to shared buffer 31.

[0043] Next frame sequence number 3102: a sequence number used to write the next baseband status frame in the data buffer 320, initialized to 1.

[0044] Number to be processed 3103: the number of baseband status frames that have not been processed in the data buffer 320, used together with the read address pointer for polling output, initialized to 0.

[0045] Write address 3104: the write position of the next baseband status frame in the data buffer 320, initialized to the first address of the data buffer 320.

[0046] Read address 3105: the first address of the earliest status frame in the unprocessed baseband status frames in the data buffer 320.

[0047] Switch mask 3106: This data is updated after receiving the control command to implement the switch function of the corresponding level frame monitoring. It is initialized to 0xFF, that is, the monitoring function of all levels of baseband status frames is turned on by default.

[0048] Exemplarily, the data buffer 320 is composed of multiple baseband status frames 3201, and the frame has a maximum length limit, which is composed of header information 3202 (i.e., frame header) and baseband status information 3207. The baseband status information 3207 that exceeds the maximum length limit of a single frame can be split, and the header information 3202 is added to occupy the buffer space of the next frame. The header information 3202 includes a frame sequence number 3203, time information 3204, a frame level 3205, a kernel ID (i.e., CPU ID) for writing the baseband status, and a baseband status information length 3206. Since the baseband status information 3207 is split, the same baseband status may be in different frames, and only the baseband status information length 3206 may be different in the header information 3202 of different frames.

[0049] The meanings of the contents of each part of a single frame in the data buffer 320 are as follows.

[0050] Frame number 3203: The value comes from the control buffer 310. After writing, the next frame number 3102 in the control buffer 310 needs to be updated. The frame number 3203 is initialized to 1.

[0051] Time information 3204: the time when the baseband status information 3207 is generated, consisting of year (2B), month (1B), day (1B), hour (1B), minute (1B), and second (1B).

[0052] Frame level 3205: includes Fatal, Error, Warning, Info, Debug, and User (i.e., custom).

[0053] CPU ID: used to identify the kernel source of the baseband status frame 3201 (such as CPU0 or CPU1, etc.).

[0054] Baseband status information length 3206: in bytes, for example, 4B (Byte) means 4 bytes.

[0055] Baseband status information 3207: Baseband status content field, the length of which is uncertain. If the maximum length limit of a single frame is exceeded after adding the header information 3202, it will be split into the frame space of multiple frames.

[0056] Exemplarily, the present disclosure designs the data structure of the control buffer 310 and the header information 3202 of the baseband status frame 3201, so as to realize synchronous control of access to the shared buffer 31, orderly management of data frames, accurate tracking of the number of frames to be processed, efficient positioning of read and write addresses, and flexible monitoring of the baseband status frame 3201, thereby improving the efficiency and accuracy of data processing.

[0057] refer to Figure 4 As shown, exemplarily, in some embodiments, according to functional requirements, the present disclosure divides the baseband status monitoring system 10 into an initialization module 130, a status frame writing module 110, a status frame processing module 120 and a user module 140. Figure 2 As shown, the core CPU0 responsible for uniformly processing the status frame is called the first processor core 210, and CPU1 is called the second processor core 220. CPU1 does not enable the status frame processing module 120 and the user module 140. The initialization module 130 is responsible for initializing the ID of the core, and CPU0 also needs to initialize the shared memory 30 dedicated to the baseband status monitoring system 10. The user module 140 can directly control the frame monitoring switches of different levels of the control buffer 310.

[0058] The initialization module 130 in the baseband status monitoring system 10 is introduced below.

[0059] refer to Figures 2 to 4As shown, in some embodiments, the baseband status monitoring system 10 includes an initialization module 130. In the initialization module 130, for the second baseband status monitoring program, it also includes: responding to the second initialization request of the second processor core 220, initializing the CPU ID; for the first baseband status monitoring program, it also includes: responding to the first initialization request of the first processor core 210, initializing the CPU ID, the processing method of the baseband status frame, and the shared buffer 31.

[0060] Figure 5 A flowchart showing the steps of executing the initialization module according to some embodiments of the present disclosure is shown, referring to Figure 5 As shown, illustratively, the initialization module 130 can complete the initialization function, initialize the local parameters in step S501; and initialize the shared buffer in step S502. In actual applications, the core of the second processor core 220 (CPU1) first initializes the local parameter CPU ID, and the monitoring main core (CPU0) also needs to initialize the baseband state processing mode and the shared memory 30 (including the control buffer 310 and the data buffer 320).

[0061] Exemplarily, through the process executed by the initialization module 130, the baseband status monitoring system 10 can initialize the CPU ID according to different initialization requests (from the second processor core 220 or the first processor core 210), or further initialize the baseband status frame processing method and shared memory 30, thereby realizing flexible configuration and efficient utilization of system resources.

[0062] The status frame writing module 110 in the baseband status monitoring system 10 is introduced below.

[0063] Figure 6 FIG. 1 is a flowchart showing the steps executed by the status frame writing module according to some embodiments of the present disclosure. Figure 3 and Figure 6 As shown, in some embodiments, the baseband status information is constructed as a baseband status frame and written into the shared memory 30, including: Read the switch mask 3106 from the control buffer 310. This step may correspond to Figure 6 Step S602.

[0064] In response to the flag bit of the switch mask 3106 being turned on (eg, the flag bit is 1), the lock flag 3101 is read from the control buffer 310. This step may correspond to Figure 6 Steps S602 and S603.

[0065] In response to the flag bit of the lock flag 3101 being locked (for example, lockflag is 0), wait for the flag bit of the lock flag 3101 to become unlocked (for example, lockflag is 1). This step may correspond to Figure 6 Steps S603 and S604.

[0066] In response to the flag bit of the lock flag 3101 being unlocked, the flag bit of the lock flag 3101 is set to locked, the next frame sequence number 3102 is obtained from the control buffer 310, and the baseband state information 3207 is constructed as a baseband state frame 3201. This step may correspond to Figure 6 Step S605.

[0067] In response to the baseband status information 3207 being greater than a preset length of a single baseband status frame, the baseband status information 3207 is split and at least two baseband status frames are generated. This step may correspond to Figure 6 Steps S606 and S607.

[0068] Obtain the write address 3104 from the control buffer 310, write the baseband status frame into the data buffer 320, and update the write address 3104. This step may correspond to Figure 6 Step S608.

[0069] Exemplarily, the present disclosure can realize the process of automatically reconstructing and writing the state information of the baseband chip 20 into the shared memory 30 by executing the above steps, including controlling the write operation according to the switch mask 3106, supporting the splitting of the super-long information, and dynamically updating the write address 3104. The present disclosure can realize the accurate and efficient storage and management of the baseband state information 3207.

[0070] In some embodiments, splitting the baseband status information 3207 and generating at least two baseband status frames includes: The baseband status information is split 3207 to obtain first baseband status information and second baseband status information, where the first baseband status information and the second baseband status information are less than or equal to a preset length (ie, a maximum limit on the frame length).

[0071] Header information 3202 is added to the first baseband status information and the second baseband status information respectively, so as to obtain at least two baseband status frames.

[0072] Exemplarily, the first baseband status information and the second baseband status information may be multiple. The present disclosure can split the super-long baseband status information 3207 by executing the above steps, and respectively add header information 3202 to generate at least two baseband status frames, thereby achieving effective processing of the super-long baseband status information 3207 and ensuring the integrity and manageability of the information.

[0073] Continue to refer Figure 3and Figure 6 As shown, in some embodiments, after updating the write address 3104, the method further includes: In response to the baseband status frame to be processed in the data buffer 320 being overwritten, the read address 3105 of the control buffer 310 is updated to point to the first address of the earliest baseband status frame to be processed. This step may correspond to Figure 6 Steps S609 and S610.

[0074] Update the pending number 3103 of the control buffer 310. This step may correspond to Figure 6 Step S611.

[0075] Update the next frame number 3102 of the control buffer 310. This step may correspond to Figure 6 Step S612.

[0076] Set the lock flag 3101 to unlock. This step can correspond to Figure 6 Step S613.

[0077] Exemplarily, by executing the above steps, the present disclosure can automatically update the read address 3105, the number of frames to be processed 3103 and the next frame number 3102 of the control buffer 310 to ensure that the earliest baseband status frame to be processed in the data buffer 320 can be processed first, and at the same time unlock the shared memory 30 for subsequent operations, thereby ensuring efficient use of shared resources.

[0078] By way of example, the overall process of the steps executed by the status frame writing module 110 is summarized and described here. Figure 6 As shown in the figure, when a status frame write request occurs, the control buffer is first read to determine whether the status frame monitoring function of this level is shielded and whether the shared buffer is locked. If it is shielded (the switch mask is not 1), the request is ignored and the write request is continued; if it is locked (lockflag is 0), wait for other cores to finish writing the shared buffer and then unlock it (lockflag is 1); if it is not shielded (the switch mask is 1) and it is unlocked (lockflag is 1), then the shared buffer is first locked (lockflag is 0), and the baseband status information and control buffer related information are reassembled according to the status frame format. If the length of the reassembled frame exceeds the maximum limit, the baseband status information is segmented, and each segment plus the header information forms a new frame. Then the write address is obtained from the control buffer, and all frames of the baseband status are written to the specified position of the data buffer and the write address is updated.

[0079] Continue to combine Figure 6As shown, if the value of the pending number to be updated is greater than the maximum number that the data buffer can accommodate, it means that the data buffer is full, and the earliest one or more status frames in the unprocessed status frames are overwritten by the latest status frame. Since the write request of a status frame may occupy the data space of multiple status frames, that is, the overwritten status frame may not be a complete baseband status frame, and the remaining part that is not covered is in the unprocessed status frame, the remaining content needs to be discarded at this time, and no further processing is required. Then update the read address of the control buffer to point to the first address of the status frame with the earliest status frame write request that is not completely covered, and then update the pending number of the control buffer, update the next frame sequence number and unlock the shared buffer (lockflag is 1).

[0080] The status frame processing module 120 in the baseband status monitoring system 10 is introduced below.

[0081] Figure 7 A flowchart showing the steps executed by the status frame processing module according to some embodiments of the present disclosure is shown, referring to Figure 3 and Figure 7 As shown, in some embodiments, reading out and parsing the baseband status frame from the shared memory 30 to obtain the baseband status information includes: Get the number to be processed 3103 from the control buffer 310. This step may correspond to Figure 7 Step S702.

[0082] In response to the number of pending processes 3103 not being 0, a processing method of the baseband status frame is identified, the processing method including any one of FLASH, UART, and custom methods. This step may correspond to Figure 7 Steps S702, S703, S704, S706, and S708.

[0083] Read and parse the baseband status frame 3201 according to the processing method to obtain baseband status information 3207. This step may correspond to Figure 7 Steps S705, S707, and S709.

[0084] For example, UART (Universal Asynchronous Receiver / Transmitter) is a universal asynchronous receiver / transmitter. By executing the above steps, the present disclosure can automatically read and parse the baseband status frame 3201 from the shared memory 30, so as to accurately obtain the baseband status information 3207, thereby realizing automation and efficiency of data processing.

[0085] Continue to refer Figure 3 and Figure 7As shown, in some embodiments, the processing method is UART; reading and parsing the baseband status frame 3201 according to the processing method to obtain baseband status information 3207 includes: Read the lock flag 3101 from the control buffer 310. This step may correspond to Figure 7 Step S709.

[0086] In response to the lock flag 3101 being locked, the number to be processed 3103 is assigned to a preset local variable (eg, outnum). This step may correspond to Figure 7 Steps S709 and S710.

[0087] Read a baseband status frame 3201 from the read address 3105 and parse it, obtain the baseband status information 3207, frame level 3205, time information 3204 and send them to the host computer for printing and saving, decrement the preset local variable (such as outnum) by 1, and update the read address 3105. This step can correspond to Figure 7 Step S711.

[0088] In response to the preset local variable (such as outnum) being 0, the pending number 3103 is updated to 0, and the flag bit of the lock flag 3101 is set to unlock (lockflag is 1). This step may correspond to Figure 7 Steps S712 and S713.

[0089] Exemplarily, the present disclosure executes the above steps, and when the processing method is UART, the security of access to the shared memory 30 is ensured by reading the lock flag 3101, and the baseband status frame 3201 is read and parsed from the read address 3105 in sequence, and key information is sent to the host computer and saved. At the same time, other parameters are dynamically updated until all frames to be processed are processed, and finally the shared memory 30 is unlocked, thereby realizing orderly, secure transmission and efficient processing of data.

[0090] For example, the overall process of the steps executed by the status frame processing module 120 is summarized and described here. Figure 7 As shown in the figure, when the polling time is up, if there is a status frame to be processed in the data buffer, first identify the processing method and then do the corresponding processing. Taking the UART transmission status information to the host computer as an example, first determine whether the shared buffer is locked (lockflag is 0), read out the status frame in turn and parse it, send the frame level information, time information, and baseband status information to the host computer to print and save until the number to be output is 0, and finally set the number of control buffers to be processed to 0 and lockflag to 1 to unlock.

[0091] The user module 140 in the baseband status monitoring system 10 is introduced below.

[0092] Figure 8 A flowchart showing the steps executed by the user module according to some embodiments of the present disclosure is shown, referring to Figure 3 and Figure 8 As shown, in some embodiments, the baseband status monitoring system 10 further includes a user module 140. In the user module 140, for the first baseband status monitoring program, it further includes: in response to a user's control command, updating the switch mask 3106 in the control buffer 310, including: In response to the control command being legal, the lock flag 3101 is read from the control buffer 310. This step may correspond to Figure 8 Steps S802 and S804.

[0093] In response to the lock flag 3101 being locked, the switch mask 3106 is read from the control buffer 310, and the flag bit of the switch mask 3106 is updated according to the control command.

[0094] Set the lock flag 3101 to unlock. This step can correspond to Figure 8 Steps S804, S805, S806, S807, and S808.

[0095] Exemplarily, by executing the above steps, the present disclosure enables the baseband status monitoring system 10 to respond to the user's legitimate control commands and safely update the switch mask 3106 in the control buffer 310, and the user can flexibly adjust the system status.

[0096] For example, the overall process of the steps executed by the user module 140 is summarized and described here. Figure 8 As shown, after receiving the control command, it is first determined whether it belongs to the command in the control list. If it is legal, the switch mask byte in the control buffer is updated when the shared buffer is writable, and finally the shared buffer is unlocked again (lockflag is set to 1).

[0097] Exemplarily, the present disclosure implements a monitoring-specific core processor interaction mechanism by designing the software modules of the baseband status monitoring system 10 (including a first baseband status monitoring program and a second baseband status monitoring program) and their functions and workflows. The mechanism is suitable for status monitoring of baseband chips 20 of communication systems with different processor architectures and different operating systems, has good versatility, and can ensure the smooth progress of the research and development process of the baseband chip 20.

[0098] The present disclosure also proposes a state monitoring device for a baseband chip of a communication system, wherein the state monitoring device includes a device for executing the state monitoring method mentioned above.

[0099] Fig. 9A simplified block diagram of a state monitoring device for a communication system baseband chip suitable for implementing an exemplary embodiment of the present disclosure is shown. For example, a user terminal can be implemented by a device 900. As shown in the figure, the device 900 includes one or more processors 910, one or more memories 920 coupled to the processor 910, and one or more communication modules 940 coupled to the processor 910.

[0100] The communication module 940 is used for two-way communication. The communication module 940 has at least one antenna to facilitate communication. The communication interface may represent any interface necessary for communicating with other network elements.

[0101] Processor 910 may be of any type suitable for the local technology network, and may include, as non-limiting examples, one or more of: a general purpose computer, a special purpose computer, a microprocessor, a digital signal processor (DSP), and a processor based on a multi-core processor architecture. Device 900 may have multiple processors, such as application specific integrated circuit chips, which are driven in time to a clock that synchronizes a master processor.

[0102] The memory 920 may include one or more non-volatile memories and one or more volatile memories. Examples of non-volatile memories include, but are not limited to, read-only memory (ROM) 924, electrically programmable read-only memory (EPROM), flash memory, hard disk, compact disk (CD), digital video disk (DVD), and other magnetic and / or optical memories. Examples of volatile memories include, but are not limited to, random access memory (RAM) 922 and other volatile memories that do not persist during a power outage.

[0103] The computer program 930 includes computer executable instructions that are executed by the associated processor 910. The program 930 may be stored in the ROM 924. The processor 910 may perform any appropriate actions and processes by loading the program 930 into the RAM 922.

[0104] The embodiments of the present disclosure may be implemented by a program 930, so that the device 900 may execute the reference Figures 4 to 8 Any process of the disclosure discussed. The embodiments of the present disclosure may also be implemented by hardware or by a combination of software and hardware.

[0105] In some embodiments, the program 930 may be tangibly contained in a computer-readable medium, which may be contained in the device 900 (e.g., memory 920) or other storage devices accessible to the device 900. The device 900 may load the program 930 from the computer-readable medium to the RAM 922 for execution. The computer-readable medium may include any type of tangible non-volatile memory, such as ROM, EPROM, flash memory, hard disk, CD, DVD, etc. The program 930 is stored on the computer-readable medium.

[0106] Generally, various embodiments of the present disclosure may be implemented in hardware or dedicated circuits, software, logic, or any combination thereof. Certain aspects may be implemented in hardware, while other aspects may be implemented in firmware or software, which may be executed by a controller, microprocessor, or other computing device. Although various aspects of the embodiments of the present disclosure are shown and described as block diagrams, flow charts, or using some other graphical representations, it should be understood that, as non-limiting examples, the blocks, devices, systems, techniques, or methods described herein may be implemented in hardware, software, firmware, dedicated circuits or logic, general hardware or controllers or other computing devices, or some combination thereof.

[0107] The present disclosure also provides at least one computer program product tangibly stored on a non-transitory computer readable storage medium. The computer program product includes computer executable instructions, machine executable instructions, such as instructions included in a program module, which are executed in a device on a target real or virtual processor to perform the above-mentioned reference Figure 5 The process 500, Figure 6 The process 600, Figure 7 The process 700, Figure 8 Described flow 800. Typically, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform specific tasks or implement specific abstract data types. In various embodiments, the functions of program modules can be combined or separated between program modules as needed. Machine executable instructions for program modules can be executed in local or distributed devices. In distributed devices, program modules can be located in local and remote storage media.

[0108] The program code for executing the disclosed method can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer or other programmable data processing equipment so that when the program code is executed by the processor or controller, the function / operation specified in the flow chart and / or block diagram is realized. The program code can be executed completely on the machine as an independent software package, partially on the machine, partially on the machine, partially on a remote machine, partially on a remote machine, or all on a remote machine or server.

[0109] In the context of the present disclosure, computer program codes or related data may be carried by any appropriate carrier to enable a device, apparatus or processor to perform various processes and operations as described above. Examples of carriers include signals, computer readable media, etc.

[0110] The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or apparatuses, or any suitable combination of the foregoing. More specific examples of computer readable storage media include an electrical connection having one or more conductors, a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0111] In addition, although the operations are described in a specific order, this should not be understood as requiring the specific order or sequence shown to be performed, or performing all the operations shown, to obtain the desired result. In some cases, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these details should not be interpreted as limitations on the scope of the present disclosure, but can be interpreted as descriptions of features specific to a particular embodiment. Certain features described in the context of a separate embodiment may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination.

[0112] Although the disclosure has been described in language specific to structural features and / or methodological acts, it should be understood that the disclosure defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

[0113] It should be fully understood that the use of personally identifiable information should be subject to privacy policies and practices generally recognized as meeting or exceeding industry or government requirements for maintaining user privacy. In particular, personally identifiable information data should be managed and processed to minimize the risk of inadvertent or unauthorized access or use, and the nature of authorized use should be clearly indicated to users.

Claims

1. A method for monitoring the status of a baseband chip in a communication system, characterized in that: The baseband chip includes a first processor core, a second processor core and a shared memory, a first baseband status monitoring program runs on the first processor core, and a second baseband status monitoring program runs on the second processor core, and the method includes: For any one of the first baseband status monitoring procedure and the second baseband status monitoring procedure: In response to a status frame write request for recording baseband status information of the baseband chip, constructing the baseband status information into a baseband status frame, and writing the frame into the shared memory; and For the first baseband status monitoring procedure: In response to the status frame processing being triggered, the baseband status frame is read out from the shared memory and parsed to obtain the baseband status information.

2. The method according to claim 1, characterized in that The shared memory includes a shared buffer, the shared buffer includes a control buffer and a data buffer, and the data buffer is used to store a plurality of baseband status frames; The data structure of the control buffer includes: a lock flag, a next frame number, a number to be processed, a write address, a read address, a switch mask, or any combination thereof; The data structure of the baseband status frame includes header information and baseband status information, and the header information includes: one or any combination of frame sequence number, time information, frame level, CPU ID, and baseband status information length.

3. The method according to claim 2, characterized in that The baseband status information is constructed into a baseband status frame and written into the shared memory, including: Reading the switch mask from the control buffer; In response to the flag bit of the switch mask being on, reading the lock flag from the control buffer; In response to the flag bit of the lock flag being locked, waiting for the flag bit of the lock flag to be changed to unlocked; In response to the flag bit of the lock flag being unlocked, setting the flag bit of the lock flag to locked, acquiring the next frame sequence number from the control buffer, and constructing the baseband status information into the baseband status frame; The write address is obtained from the control buffer, the baseband status frame is written into the data buffer, and the write address is updated.

4. The method according to claim 3, characterized in that Acquiring the next frame sequence number from the control buffer and constructing the baseband status information into the baseband status frame includes: In response to the baseband status information being greater than a preset length of a single baseband status frame, the baseband status information is split and at least two baseband status frames are generated.

5. The method according to claim 4, characterized in that Splitting the baseband status information and generating at least two baseband status frames includes: Splitting the baseband state information to obtain first baseband state information and second baseband state information, where the first baseband state information and the second baseband state information are less than or equal to the preset length; The header information is added to the first baseband status information and the second baseband status information respectively, so as to obtain the at least two baseband status frames.

6. The method according to claim 3, characterized in that After updating the write address, the method further includes: In response to a baseband status frame to be processed in the data buffer being overwritten, updating the read address of the control buffer so that the read address points to the first address of the earliest baseband status frame to be processed; Updating the pending number of the control buffer; Updating the next frame sequence number of the control buffer; The flag bit of the lock flag is set to unlock.

7. The method according to claim 2, characterized in that Reading out and parsing the baseband status frame from the shared memory to obtain the baseband status information includes: Obtain the number to be processed from the control buffer; In response to the number to be processed not being 0, identifying a processing method of the baseband status frame, the processing method comprising: any one of FLASH, UART, and a custom method; The baseband status frame is read out and parsed according to the processing method to obtain the baseband status information.

8. The method according to claim 7, characterized in that The processing method is UART; Reading and parsing the baseband status frame according to the processing method to obtain the baseband status information includes: Reading the lock flag from the control buffer; In response to the flag bit of the lock flag being locked, assigning the number to be processed to a preset local variable; Read a baseband status frame from the read address and parse it, obtain the baseband status information, the frame level, the time information and send them to the host computer, decrement the preset local variable by 1, and update the read address; In response to the preset local variable being 0, the number to be processed is updated to 0, and the flag bit of the lock flag is set to unlock.

9. The method according to any one of claims 2 to 8, characterized in that The first baseband status monitoring program further includes: in response to a first initialization request, initializing the CPUID, the processing method of the baseband status frame, and the shared buffer; The second baseband status monitoring program further includes: initializing the CPUID in response to a second initialization request.

10. The method according to any one of claims 2 to 8, characterized in that The first baseband status monitoring program further includes: updating the switch mask in the control buffer in response to a user's control command, including: In response to the control command being legal, reading the lock flag from the control buffer; In response to the flag bit of the lock flag being locked, reading the switch mask from the control buffer, and updating the flag bit of the switch mask according to the control command; The flag bit of the lock flag is set to unlock.

11. The method according to any one of claims 2 to 8, characterized in that In the data structure of the control buffer: the lock flag is used to identify whether the shared buffer is locked or unlocked; the next frame sequence number is used to identify the sequence number of the next baseband status frame in the data buffer; the number to be processed is used to identify the number of baseband status frames to be processed in the data buffer; the write address is used to identify the write address of the next baseband status frame in the data buffer; the read address is used to identify the earliest first address of the baseband status frames to be processed in the data buffer; the switch mask is used to identify whether the monitoring function of the baseband status frame is turned on or off; In the header information: the frame sequence number is used to identify the sequence number of the baseband status frame; The time information is used to identify the time when the baseband status information is generated; the frame level is used to identify the importance of the baseband status frame; the CPU ID is used to identify the core processor source of the baseband status frame, and the core processor source includes the first processor core and the second processor core.

12. A state monitoring device for a baseband chip of a communication system, characterized in that: The condition monitoring device comprises means for executing the condition monitoring method according to any one of claims 1-11.

13. A non-transitory computer-readable storage medium storing machine-executable instructions, characterized in that: When the machine executable instructions are executed by a baseband chip of a communication system, the baseband chip is caused to execute the status monitoring method according to any one of claims 1 to 11.

14. A computer program product comprising machine executable instructions, characterized in that When the machine executable instructions are executed by a baseband chip of a communication system, the baseband chip is caused to execute the status monitoring method according to any one of claims 1 to 11.

15. A baseband chip for a communication system, characterized in that: The baseband chip includes a first processor core, a second processor core and a shared memory, and the first processor core and the second processor core are configured to respectively run a first baseband status monitoring program and a second baseband status monitoring program to execute a status monitoring method as claimed in any one of claims 1-11.

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