State Monitoring Method, Device and Baseband Chip for Communication System Baseband Chip

Abstract

Provided are a method and device for monitoring the status of a baseband chip of a communication system, and a baseband chip. The baseband chip includes a first processor core, a second processor core, and a shared memory. A first baseband status monitoring program runs on the first processor core, and a second baseband status monitoring program runs on the second processor core. The method includes: for any one of the first baseband status monitoring program and the second baseband status monitoring program: in response to a status frame write request for recording baseband status information of the baseband chip, constructing the baseband status information into a baseband status frame and writing it into the shared memory; and for the first baseband status monitoring program: in response to the triggering of status frame processing, reading and parsing the baseband status frame from the shared memory to obtain the baseband status information. The baseband status monitoring solution of the present disclosure has good generality.

Description

Technical Field

[0001] The present disclosure relates to the field of communications, and in particular, to a method for monitoring the status of a baseband chip of a communication system, a device for monitoring the status of a baseband chip of a communication system, a non-transitory computer-readable storage medium, a computer program product, and a baseband chip of a communication system. Background Art

[0002] From 2G, 2.5G, 3G, 4G to 5G, the development of wireless communication systems has been very rapid. The baseband chip of a communication system is a core component in a user terminal.

[0003] From the perspective of data flow direction, the basic functions of a baseband chip include synthesizing the baseband signal to be transmitted (uplink), or decoding the received baseband signal (downlink). From the perspective of function types, the functions of a baseband chip include two aspects: communication and application. The application function has a lower requirement for real-time performance. The communication function includes baseband signal processing and a protocol stack. Among them, the baseband signal processing part implements the functions of the communication protocol layer (physical layer), such as encoding / decoding, modulation / demodulation, encryption / decryption, synchronization, etc.; the protocol stack part implements the functions of high-level communication protocols and has requirements for real-time performance. Different function types of baseband chips can select different processors and different operating systems to implement.

[0004] Currently, the monitoring solutions for communication systems mainly focus on spectrum monitoring. For baseband chips using different processor architectures and different operating systems, there is a lack of a general monitoring solution for the baseband status of communication systems to ensure the smooth progress of the R & D process. Summary of the Invention

[0005] It would be advantageous to provide a mechanism for alleviating, mitigating, or eliminating at least one of the above problems.

[0006] In a first aspect, a method for monitoring the status of a baseband chip of a communication system is provided. The baseband chip includes a first processor core, a second processor core, and a shared memory. A first baseband status monitoring program runs on the first processor core, and a second baseband status monitoring program runs on the second processor core. The method includes: for any one of the first baseband status monitoring program and the second baseband status monitoring program: in response to a status frame write request for recording the baseband status information of the baseband chip, constructing the baseband status information into a baseband status frame and writing it into the shared memory; and for the first baseband status monitoring program: in response to the triggering of status frame processing, reading and parsing the baseband status frame from the shared memory to obtain the baseband status information.

[0007] In a second aspect, a device for monitoring the status of a baseband chip of a communication system is provided. The status monitoring device includes means for executing the above status monitoring method.

[0008] In a third aspect, a non-transitory computer-readable storage medium storing machine-executable instructions is provided. When the machine-executable instructions are executed by a baseband chip of a communication system, the baseband chip is caused to execute the above-described state monitoring method.

[0009] In a fourth aspect, a computer program product including machine-executable instructions is provided. When the machine-executable instructions are executed by a baseband chip of a communication system, the baseband chip is caused to execute the above-described state monitoring method.

[0010] In a fifth aspect, a baseband chip of a communication system is provided. The baseband chip includes a first processor core, a second processor core, and a shared memory. The first processor core and the second processor core are configured to respectively run a first baseband state monitoring program and a second baseband state monitoring program to execute the above-described state monitoring method.

[0011] It should be understood that the summary of the invention section is not used to identify the key or essential features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Through the following description, other features of the present disclosure will become easily understood. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] By describing some embodiments of the present disclosure in more detail in the drawings, the above and other objects, features, and advantages of the present disclosure will become more apparent, where:

[0013] Figure 1 A schematic diagram of a baseband chip of a communication system in which exemplary embodiments of the present disclosure can be implemented is shown;

[0014] Figure 2 A schematic diagram showing the interaction relationship between a processor core and a shared memory according to some embodiments of the present disclosure is shown;

[0015] Figure 3 A schematic diagram of the structure of a shared memory according to some embodiments of the present disclosure is shown;

[0016] Figure 4 A schematic diagram of each module in a baseband state monitoring system according to some embodiments of the present disclosure is shown;

[0017] Figure 5 A flowchart showing the execution steps of an initialization module according to some embodiments of the present disclosure is shown;

[0018] Figure 6 A flowchart showing the execution steps of a status frame writing module according to some embodiments of the present disclosure is shown;

[0019] Figure 7The flowchart showing the steps executed by the status frame processing module according to some embodiments of the present disclosure;

[0020] Figure 8 The flowchart showing the steps executed by the user module according to some embodiments of the present disclosure; and

[0021] Figure 9 The simplified block diagram of a status monitoring device for a baseband chip of a communication system suitable for implementing the exemplary embodiments of the present disclosure.

[0022] Description of the reference numerals in the specific embodiments:

[0023] 10. Baseband status monitoring system;

[0024] 110. Status frame writing module;

[0025] 120. Status frame processing module;

[0026] 130. Initialization module;

[0027] 140. User module;

[0028] 20. Baseband chip;

[0029] 210. First processor core;

[0030] 220. Second processor core;

[0031] 30. Shared memory;

[0032] 31. Shared buffer;

[0033] 310. Control buffer;

[0034] 3101. Lock flag;

[0035] 3102. Next frame sequence number;

[0036] 3103. Number of items to be processed;

[0037] 3104. Write address;

[0038] 3105. Read address;

[0039] 3106. Switch mask;

[0040] 320. Data buffer;

[0041] 3201. Baseband status frame;

[0042] 3202. Header information;

[0043] 3203. Frame sequence number;

[0044] 3204. Time information;

[0045] 3205. Frame level;

[0046] 3206. Baseband status information length;

[0047] 3207. Baseband status information. Detailed implementation manners

[0048] The principles of the present disclosure will now be described with reference to some embodiments. It should be understood that the description of these embodiments is only for illustrative purposes and helps those skilled in the art to understand and implement the present disclosure, without imposing any limitation on the scope of the present disclosure. The disclosure described herein may be implemented in a manner different from that described below.

[0049] In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0050] References in the present disclosure to "one embodiment", "an embodiment", "exemplary embodiment", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not necessarily every embodiment includes the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an exemplary embodiment, whether or not explicitly described, those skilled in the art will appreciate such feature, structure, or characteristic in connection with other embodiments.

[0051] It should be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The term "and / or" used herein includes any and all combinations of one or more of the listed terms.

[0052] The terms used herein are only for describing particular embodiments and are not a limitation on the exemplary embodiments. The singular forms "a", "an", and "the" used herein also include the plural forms unless the context clearly indicates otherwise. The phrase "a set of elements" or "a collection of elements" used herein is intended to include one or more elements. It should also be understood that the terms "comprises", "comprising", "has", "having", "includes", and / or "including", when used herein, specify the presence of the described features, elements, and / or components, etc., but do not preclude the presence or addition of one or more other features, elements, components, and / or combinations thereof.

[0053] As used in this disclosure, the term "circuit" can refer to one or more or all of the following:

[0054] (a) Only hardware circuit implementations (e.g., implemented only in analog and / or digital circuits)

[0055] (b) Combinations of hardware circuits and software, e.g., (where applicable):

[0056] (i) Combinations of analog and / or digital hardware circuits with software / firmware; and

[0057] (ii) Any part of a hardware processor (including a digital signal processor) with software and memory, which work together to enable a device such as a mobile phone or a server to perform various functions, and

[0058] (c) Hardware circuits and / or processors, such as a microprocessor or a part of a microprocessor, which require software (e.g., firmware) to operate, but the software may not be present when not required to operate.

[0059] This definition of circuit applies to all uses of the term in this disclosure, including in any claims. As another example, as used in this disclosure, the term circuit also includes implementations of only a hardware circuit or a processor (or processors) or a part of a hardware circuit or a processor and its (or their) accompanying software and / or firmware. The term circuit also includes, for example, if applicable to a particular claim element, a baseband integrated circuit or a processor integrated circuit for a mobile device, or a similar integrated circuit in a server, a cellular network device, or other computing network devices.

[0060] As used herein, the term "communication network" refers to a network that follows any suitable communication standard, such as Long Term Evolution (LTE), LTE-Advanced (LTE-A), Wideband Code Division Multiple Access (WCDMA), High Speed Packet Access (HSPA), NarrowBand Internet of Things (NB-IoT), New Radio (NR), Non-Terrestrial Network (NTN), etc. Additionally, the communication between terminal devices and network devices in a communication network can be performed according to any suitable generation of communication protocols, including but not limited to the first generation (1G), second generation (2G), 2.5G, 2.75G, third generation (3G), fourth generation (4G), 4.5G, fifth generation (5G), future sixth generation (6G) communication protocols, and / or any other protocols known currently or to be developed in the future. Embodiments of the present disclosure can be applied to satellite communication systems. Considering the rapid development in communications, of course, there will also be future types of communication technologies and systems, and the present disclosure can be implemented with these technologies and systems. The scope of the present disclosure should not be considered limited to the foregoing systems.

[0061] As used herein, the term "terminal device" refers to any terminal device capable of wireless communication. By way of example and not limitation, a terminal device may also be referred to as a communication device, user terminal, user equipment (UE), user station (SS), portable user station, mobile station (MS), or access terminal (AT). The terminal device may include, but is not limited to, mobile phones, cellular phones, smart phones, IP voice (VoIP) phones, wireless local loop phones, tablet computers, wearable terminal devices, personal digital assistants (PDAs), portable computers, desktop computers, image capture terminal devices such as digital cameras, game terminal devices, music storage and playback devices, in-vehicle wireless terminal devices, wireless endpoints, mobile stations, laptop embedded devices (LEEs), laptop mounted devices (LMEs), USB dongles, smart devices, wireless customer premise equipment (CPEs), Internet of Things (IoT) devices, watches or other wearable devices, head-mounted displays (HMDs), vehicles, drones, medical devices and applications (e.g., remote surgery), industrial devices and applications (e.g., robots and / or other wireless devices operating in the context of an industrial and / or automated processing chain), consumer electronic devices, relay nodes, devices operating on commercial and / or industrial wireless networks, etc. The mobile terminal (MT) part of an IAB node may perform the functions of a "terminal device" and thus may operate as a terminal device. In the following description, the terms "terminal device", "communication device", "terminal", "user terminal", "user equipment", and "UE" may be used interchangeably.

[0062] Although the functions described herein may be performed in fixed and / or wireless network nodes in various exemplary embodiments, in other exemplary embodiments, the functions may be implemented in a user equipment device such as a cellular phone, or a tablet computer, or a laptop computer, or a desktop computer, or a mobile IoT device, or a fixed IoT device. For example, the user equipment device may suitably have the corresponding capabilities associated with fixed and / or wireless network nodes. The user equipment device may be a user equipment and / or a control device, such as a chipset or a processor, configured to control the user equipment when the user equipment is installed therein. Examples of such functions include a bootstrapping server function and / or a home subscriber server, which may be implemented in the user equipment device by providing software configured to cause the user equipment device to perform from the perspective of these functions / nodes.

[0063] Traditional baseband chip architectures adopt heterogeneous dual-core processors. The baseband signal processing function at the physical layer is completed by a DSP (Digital Signal Processing), and the processing function of the protocol stack is usually implemented by an ARM CPU, which is a processor based on the Reduced Instruction Set Computer (RISC) architecture. Considering the real-time requirements of the baseband chip protocol stack, a system with relatively low task scheduling overhead such as a real-time operating system can be selected, while application software without real-time requirements can be selected according to actual performance needs.

[0064] During the R & D process of baseband chips in communication systems, a large number of algorithm tests and evaluations are required, and complex real-time scenario verifications are also needed. To ensure the smooth progress of the baseband chip R & D process, it is necessary to monitor the baseband status. By collecting, processing, feedback, and storing baseband status information, abnormal or important situations in the physical layer and protocol stack can be further analyzed and processed, thus ensuring the normal operation of the communication system. Baseband status usually includes information such as data flow direction, synchronization, and scheduling situation.

[0065] Baseband chips have evolved from single-mode to multi-mode, and also from the ARM+DSP dual-core structure of traditional baseband chips to other multi-core structures. The choice of operating system and the division of the operating functions of different processors all affect the architecture of baseband chips. With the continuous improvement of communication requirements, the structure of baseband chips is becoming increasingly complex.

[0066] Currently, the monitoring research of communication systems mainly focuses on spectrum monitoring, ignoring the monitoring requirements for real-time acquisition, analysis, and processing of baseband status. For baseband chips with different processor architectures and different operating systems, there is a lack of a general monitoring scheme for the baseband status of communication systems to ensure the smooth progress of the R & D process.

[0067] Embodiments of the present disclosure propose a status monitoring solution for a baseband chip of a communication system, which is suitable for monitoring the status of baseband chips in communication systems with different processor architectures and different operating systems, has good versatility, and can ensure the smooth progress of the baseband chip R & D process. In this solution, the present disclosure designs the working processes of a first baseband status monitoring program and a second baseband status monitoring program, and constructs the first baseband status monitoring program and the second baseband status monitoring program into a baseband status monitoring system. Through the software modules and their functions and working processes of the baseband status monitoring system, a processor core interaction mechanism dedicated to monitoring is realized. In response to requests or instructions from the first processor core and the second processor core, a baseband status frame is written into the shared memory, and the baseband status information of the baseband chip is parsed from the baseband status frame, so as to realize real-time monitoring of the baseband status and timely provide the status information of the baseband chip, which helps to improve the stability and reliability of the communication system (such as a satellite communication system).

[0068] The following will refer to Figure 1 and Figure 4 to describe the principle and implementation of the present disclosure in detail.

[0069] Figure 1 shows a schematic diagram of a baseband chip of a communication system in which exemplary embodiments of the present disclosure can be implemented, Figure 4 shows a schematic diagram of each module in a baseband status monitoring system according to some embodiments of the present disclosure.

[0070] The present disclosure proposes a status monitoring method for a baseband chip of a communication system. Referring to Figure 1 as shown, the baseband chip 20 includes a first processor core 210, a second processor core 220, and a shared memory 30. A first baseband status monitoring program (not shown in the figure) runs on the first processor core 210, and a second baseband status monitoring program (not shown in the figure) runs on the second processor core 220. In practical applications, the first baseband status monitoring program and the second baseband status monitoring program can be constructed into a baseband status monitoring system 10. Exemplarily, the first processor core 210 is equivalent to the monitoring master core, and the second processor core 220 is equivalent to the non-monitoring master core.

[0071] The status monitoring method of the present disclosure includes: for any one of the first baseband status monitoring program and the second baseband status monitoring program: in response to a status frame write request for recording the baseband status information of the baseband chip 20, constructing the baseband status information into a baseband status frame and writing it into the shared memory 30; and for the first baseband status monitoring program: in response to the triggering of status frame processing, reading and parsing the baseband status frame from the shared memory 30 to obtain the baseband status information.

[0072] Refer to Figure 1 andFigure 4 As shown, the baseband status monitoring system 10 includes a status frame writing module 110 and a status frame processing module 120. The status frame writing module 110 can be configured to: in response to a status frame writing request for recording the baseband status information of the baseband chip 20, construct the baseband status information into a baseband status frame and write it into the shared memory 30. The status frame processing module 120 can be configured to: in response to the triggering of status frame processing, read out and parse the baseband status frame from the shared memory 30 to obtain the baseband status information.

[0073] Figure 2 The figure shows a schematic diagram of the interaction relationship between a processor core and a shared memory according to some embodiments of the present disclosure. Refer to Figure 2 As shown, exemplarily, the baseband chip 20 of the communication system can adopt a single-core processor architecture, or a homogeneous or heterogeneous multi-core processor architecture. The processor can be a DSP, an ARM CPU, a RISC_V CPU (the fifth generation of reduced instruction set processors), etc. For the convenience of description, different kernel processors can be distinguished by different IDs. Figure 2 Taking the baseband chip 20 with a dual-core processor (CPU0 and CPU1) as an example, in practice, it can also be extended to a multi-core system.

[0074] Exemplarily, as Figure 2 shown, CPU0 is responsible for implementing the physical layer functions of the communication protocol, and CPU1 is responsible for implementing the protocol stack functions. If it is a multi-core system, there may also be CPU2, CPU3, etc. In practical applications, whether it is a single-core or multi-core processor architecture, it can be defaulted that CPU0 is the recorder of the baseband status, and other cores record their respective baseband status information through the shared memory 30, which is uniformly processed by CPU0 and stored in a specified manner, such as printed by the host computer and saved as a file, stored in the FLASH memory (i.e., Flash Memory), etc. In addition, CPU0 can provide a user interface through which the user can turn on or off all or part of the monitoring functions.

[0075] Exemplarily, the baseband status monitoring systems 10 (which can also be called baseband status monitoring modules) of different processor cores communicate through the shared memory 30. The shared memory 30 is divided into a control buffer 310 and a data buffer 320. The baseband status monitoring system 10 of the communication system of the present disclosure is suitable for monitoring the status of the baseband chip 20 of communication systems with different processor architectures and different operating systems, and has good versatility, which can ensure the smooth progress of the R & D process of the baseband chip 20.

[0076] Figure 3 The figure shows a schematic diagram of the structure of the shared memory according to some embodiments of the present disclosure. Refer to Figure 2 and Figure 3As shown, in some embodiments, the shared memory 30 includes a shared buffer 31. The shared buffer 31 includes a control buffer 310 and a data buffer 320. The data buffer 320 is used to store multiple baseband status frames 3201. The data structure of the control buffer 310 includes one or any combination of: a lock flag 3101, a next frame sequence number 3102, a number of items to be processed 3103, a write address 3104, a read address 3105, and a switch mask 3106. The data structure of the baseband status frame 3201 includes header information 3202 and baseband status information 3207. The header information 3202 includes one or any combination of: a frame sequence number 3203, time information 3204, a frame level 3205, a CPU ID, and a baseband status information length 3206.

[0077] Exemplarily, through the data structure in the shared memory 30, the present disclosure can achieve efficient storage and management of multiple baseband status frames 3201. Among them, the control buffer 310 can manage the synchronization and status of data access, and the header information 3202 of the baseband status frame 3201 can ensure the orderliness and traceability of data, jointly improving the ability and efficiency of baseband status data processing.

[0078] Reference Figure 3 As shown, in some embodiments, in the data structure of the control buffer 310: the lock flag 3101 is used to identify whether the shared buffer 31 is locked or unlocked; the next frame sequence number 3102 is used to identify the sequence number of the next baseband status frame in the data buffer 320; the number of items to be processed 3103 is used to identify the number of baseband status frames to be processed in the data buffer 320; the write address 3104 is used to identify the write address of the next baseband status frame in the data buffer 320; the read address 3105 is used to identify the earliest start address of the baseband status frames to be processed in the data buffer 320; the switch mask 3106 is used to identify whether the monitoring function of the baseband status frame is enabled or disabled.

[0079] In the header information 3202: the frame sequence number 3203 is used to identify the sequence number of the baseband status frame; the time information 3204 is used to identify the time when the baseband status information 3207 is generated; the frame level 3205 is used to identify the importance of the baseband status frame 3201; the CPU ID is used to identify the source of the kernel processor of the baseband status frame 3201, and the source of the kernel processor includes a first processor core 210 and a second processor core 220.

[0080] Exemplarily, continuing to refer to Figure 3 As shown, the control buffer 310 can be set to a fixed size, and the data buffer 320 can be set to a circular buffer. The data buffer 320 is divided into multiple baseband status frame spaces of the same size (maximum single-frame length). The meanings of each byte of the control buffer 310 are as follows.

[0081] Lock flag 3101 (lockflag): The lock flag bit of the shared buffer 31 to avoid memory data conflict problems that may be caused by the time intersection of different kernels accessing the shared memory 30. The value of lockflag is 0 or 1. For example, when lockflag is 0, it means locked, and when lockflag is 1, it means unlocked. Only when lockflag is 0 (locked), is the kernel allowed to perform write operations on the shared buffer 31.

[0082] Next frame sequence number 3102: Used for the sequence number of the next baseband status frame in the write data buffer 320, initialized to 1.

[0083] Number of items to be processed 3103: The number of unprocessed baseband status frames in the data buffer 320, used for polling output together with the read address pointer, initialized to 0.

[0084] Write address 3104: The write position of the next baseband status frame in the data buffer 320, initialized to the start address of the data buffer 320.

[0085] Read address 3105: The start address of the earliest status frame among the unprocessed baseband status frames in the data buffer 320.

[0086] Switch mask 3106: This data is updated after receiving the control command to implement the switch function for monitoring frames at corresponding levels, initialized to 0xFF, that is, the monitoring function for all levels of baseband status frames is defaultly turned on.

[0087] Exemplarily, the data buffer 320 consists of multiple baseband status frames 3201. The frame has a maximum length limit and is composed of header information 3202 (i.e., frame header) and baseband status information 3207. The baseband status information 3207 that exceeds the single-frame maximum length limit can be split, and the header information 3202 is added to occupy the buffer space of the next frame. The header information 3202 includes frame sequence number 3203, time information 3204, frame level 3205, the kernel ID (i.e., CPU ID) that writes the baseband status, and the length of the baseband status information 3206. Since the baseband status information 3207 is split, the same baseband status may be in different frames, and only the length of the baseband status information 3206 in the header information 3202 of different frames may be different.

[0088] The meanings of the contents of each single frame in the data buffer 320 are as follows.

[0089] Frame sequence number 3203: The value is from the control buffer 310, and the next frame sequence number 3102 in the control buffer 310 needs to be updated after writing. The frame sequence number 3203 is initialized to 1.

[0090] Time information 3204: The time when the baseband status information 3207 is generated, which consists of year (2B), month (1B), day (1B), hour (1B), minute (1B), and second (1B).

[0091] Frame level 3205: Includes Fatal, Error, Warning, Info, Debug, User (i.e., custom).

[0092] CPU ID: Used to identify the core source of the baseband status frame 3201 (such as CPU0 or CPU1, etc.).

[0093] Length of baseband status information 3206: In bytes. For example, 4B (Byte) represents 4 bytes.

[0094] Baseband status information 3207: The baseband status content field, with an uncertain length. If it exceeds the single-frame maximum length limit after adding the header information 3202, it will be split into the frame spaces of multiple frames.

[0095] Exemplarily, through the design of the data structure of the control buffer 310 and the header information 3202 of the baseband status frame 3201, the present disclosure can achieve synchronous control of access to the shared buffer 31, orderly management of data frames, accurate tracking of the number of frames to be processed, efficient positioning of read and write addresses, and flexible monitoring of the baseband status frame 3201, thereby improving the efficiency and accuracy of data processing.

[0096] Reference Figure 4 As shown, exemplarily, in some embodiments, according to functional requirements, the present disclosure divides the baseband status monitoring system 10 into an initialization module 130, a status frame writing module 110, a status frame processing module 120, and a user module 140. Combining Figure 2 As shown, the kernel CPU0 responsible for uniformly processing status frames is called the first processor core 210, and CPU1 is called the second processor core 220. CPU1 does not enable the status frame processing module 120 and the user module 140. The initialization module 130 is responsible for initializing the ID of the kernel. CPU0 also needs to initialize the shared memory 30 dedicated to the baseband status monitoring system 10. The user module 140 can directly control the frame monitoring switches at different levels of the control buffer 310.

[0097] The following introduces the initialization module 130 in the baseband status monitoring system 10.

[0098] Reference Figures 2 to 4As shown, in some embodiments, the baseband status monitoring system 10 includes an initialization module 130. In the initialization module 130, for the second baseband status monitoring program, it further includes: in response to a second initialization request from the second processor core 220, initializing the CPU ID; for the first baseband status monitoring program, it further includes: in response to a first initialization request from the first processor core 210, initializing the CPU ID, the processing method of the baseband status frame, and the shared buffer 31.

[0099] Figure 5 The flowchart showing the steps executed by the initialization module according to some embodiments of the present disclosure is referred to Figure 5 As shown, exemplarily, the initialization module 130 can complete the initialization function. In step S501, local parameters are initialized; in step S502, the shared buffer is initialized. In practical applications, the core of the second processor core 220 (CPU1) first initializes the local parameter CPU ID, and the monitoring main core (CPU0) also needs to initialize the baseband status processing method and the shared memory 30 (including the control buffer 310 and the data buffer 320).

[0100] Exemplarily, through the process executed by the initialization module 130, the baseband status monitoring system 10 can, according to different initialization requests (from the second processor core 220 or the first processor core 210), respectively initialize the CPU ID, or further initialize the processing method of the baseband status frame and the shared memory 30, so as to achieve flexible configuration and efficient utilization of system resources.

[0101] The status frame writing module 110 in the baseband status monitoring system 10 is introduced below.

[0102] Figure 6 The flowchart showing the steps executed by the status frame writing module according to some embodiments of the present disclosure is referred to Figure 3 and Figure 6 As shown, in some embodiments, constructing the baseband status information into a baseband status frame and writing it into the shared memory 30 includes:

[0103] Reading the switch mask 3106 from the control buffer 310. This step can correspond to Figure 6 step S602.

[0104] In response to the flag bit of the switch mask 3106 being on (for example, the flag bit is 1), reading the lock flag 3101 from the control buffer 310. This step can correspond to Figure 6 steps S602 and S603.

[0105] In response to the flag bit of the lock flag 3101 being locked (e.g., lockflag is 0), wait for the flag bit of the lock flag 3101 to become unlocked (e.g., lockflag is 1). This step may correspond to Figure 6 steps S603 and S604.

[0106] In response to the flag bit of the lock flag 3101 being unlocked, set the flag bit of the lock flag 3101 to locked, obtain the next frame sequence number 3102 from the control buffer 310, and construct the baseband status information 3207 into a baseband status frame 3201. This step may correspond to Figure 6 step S605.

[0107] In response to the baseband status information 3207 being greater than the preset length of a single baseband status frame, split the baseband status information 3207 and generate at least two baseband status frames. This step may correspond to Figure 6 steps S606 and S607.

[0108] Obtain the write address 3104 from the control buffer 310, write the baseband status frame into the data buffer 320, and update the write address 3104. This step may correspond to Figure 6 step S608.

[0109] Exemplarily, by executing the above steps, the present disclosure can implement the process of automatically reconstructing the status information of the baseband chip 20 and writing it into the shared memory 30, including controlling the write operation according to the switch mask 3106, supporting the splitting process of ultra-long information, and dynamically updating the write address 3104. The present disclosure can achieve accurate and efficient storage and management of the baseband status information 3207.

[0110] In some embodiments, splitting the baseband status information 3207 and generating at least two baseband status frames includes:

[0111] Split the baseband status information 3207 to obtain first baseband status information and second baseband status information, where the first baseband status information and the second baseband status information are less than or equal to the preset length (i.e., the maximum limit of the frame length).

[0112] Add header information 3202 to the first baseband status information and the second baseband status information respectively, thereby obtaining at least two baseband status frames.

[0113] Exemplarily, the first baseband status information and the second baseband status information may be multiple. By executing the above steps, the present disclosure can split the ultra-long baseband status information 3207 and add header information 3202 respectively to generate at least two baseband status frames, thereby realizing effective processing of the ultra-long baseband status information 3207 and ensuring the integrity and manageability of the information.

[0114] Continue to refer to Figure 3 and Figure 6 As shown, in some embodiments, after updating the write address 3104, it further includes:

[0115] In response to the baseband status frame to be processed in the data buffer 320 being overwritten, update the read address 3105 of the control buffer 310 to make the read address 3105 point to the start address of the earliest baseband status frame to be processed. This step may correspond to Figure 6 steps S609 and S610.

[0116] Update the number of frames to be processed 3103 in the control buffer 310. This step may correspond to Figure 6 step S611.

[0117] Update the next frame sequence number 3102 in the control buffer 310. This step may correspond to Figure 6 step S612.

[0118] Set the flag bit of the lock flag 3101 to unlocked. This step may correspond to Figure 6 step S613.

[0119] Exemplarily, by executing the above steps, the present disclosure can automatically update the read address 3105, the number of frames to be processed 3103, and the next frame sequence number 3102 of the control buffer 310 to ensure that the earliest baseband status frame in the data buffer 320 can be preferentially processed, and at the same time unlock the shared memory 30 for subsequent operations, thereby ensuring the efficient utilization of shared resources.

[0120] Exemplarily, the overall process of the status frame writing module 110 executing steps is summarized and described here. Combining Figure 6 As shown, when a status frame writing request occurs, first read the control buffer to determine whether the status frame monitoring function at this level is masked and whether the shared buffer is locked. If it is masked (the switch mask is not 1), ignore the request and continue to wait for the writing request; if it is in the locked state (lockflag is 0), wait for other kernels to unlock it after writing the shared buffer (lockflag is 1); if it is not masked (the switch mask is 1) and is in the unlocked state (lockflag is 1), then first lock the shared buffer (lockflag is 0), and reorganize the baseband status information and the control buffer related information according to the status frame format. If the length of the reorganized frame exceeds the maximum limit, segment the baseband status information, and add header information to each segment to form a new frame. Then obtain the write address from the control buffer, write all frames of this baseband status to the specified position in the data buffer, and update the write address.

[0121] Continue to combine Figure 6As shown, if the value of the number to be processed to be updated is greater than the maximum number that the data buffer can accommodate, it means that the data buffer is full, and one or more of the earliest status frames in the unprocessed status frames are overwritten by the latest status frames. Since the write request for one status frame may occupy the data space of multiple status frames, that is, the overwritten status frame may not be a complete baseband status frame, and the remaining part that is not overwritten is in the unprocessed status frames. At this time, the remaining content needs to be discarded and no further processing is required. Then update the read address of the control buffer to point to the start address of the status frame where the write request for the earliest status frame that is not completely overwritten occurred, then update the number of items to be processed in the control buffer, update the next frame number, and unlock the shared buffer (lockflag is 1).

[0122] The status frame processing module 120 in the baseband status monitoring system 10 will be introduced below.

[0123] Figure 7 The flowchart showing the steps executed by the status frame processing module according to some embodiments of the present disclosure is referred to Figure 3 and Figure 7 As shown, in some embodiments, the baseband status frame is read out and parsed from the shared memory 30 to obtain baseband status information, including:

[0124] Obtain the number of items to be processed 3103 from the control buffer 310. This step may correspond to Figure 7 step S702.

[0125] In response to the number of items to be processed 3103 not being 0, identify the processing method of the baseband status frame, and the processing methods include any one of FLASH, UART, and custom methods. This step may correspond to Figure 7 steps S702, S703, S704, S706, and S708.

[0126] Read out and parse the baseband status frame 3201 according to the processing method to obtain the baseband status information 3207. This step may correspond to Figure 7 steps S705, S707, and S709.

[0127] Exemplarily, UART (Universal Asynchronous Receiver / Transmitter) is the universal asynchronous receiver / transmitter. By executing the above steps, the present disclosure can automatically read and parse the baseband status frame 3201 from the shared memory 30, so that the baseband status information 3207 can be accurately obtained, realizing the automation and high efficiency of data processing.

[0128] Continue to refer to Figure 3 and Figure 7As shown, in some embodiments, the processing method is UART; read and parse the baseband status frame 3201 according to the processing method to obtain the baseband status information 3207, including:

[0129] Read the lock flag 3101 from the control buffer 310. This step may correspond to Figure 7 Step S709.

[0130] In response to the flag bit of the lock flag 3101 being locked, assign the number of items to be processed 3103 to a preset local variable (such as outnum). This step may correspond to Figure 7 Steps S709 and S710.

[0131] Read and parse a baseband status frame 3201 from the read address 3105 to obtain the baseband status information 3207, frame level 3205, and time information 3204, and send them to the host computer for printing and saving. The preset local variable (such as outnum) is decremented by 1, and the read address 3105 is updated. This step may correspond to Figure 7 Step S711.

[0132] In response to the preset local variable (such as outnum) being 0, update the number of items to be processed 3103 to 0, and set the flag bit of the lock flag 3101 to unlocked (lockflag is 1). This step may correspond to Figure 7 Steps S712 and S713.

[0133] Exemplarily, by executing the above steps, when the processing method is UART, the present disclosure ensures the security of accessing the shared memory 30 by reading the lock flag 3101, sequentially reads and parses the baseband status frame 3201 from the read address 3105, sends and saves the key information to the host computer, and dynamically updates other parameters at the same time until all frames to be processed are processed. Finally, the shared memory 30 is unlocked, realizing the orderly, secure transmission and efficient processing of data.

[0134] Exemplarily, the overall process of the state frame processing module 120 executing steps is summarized and described here. Combining Figure 7 As shown, when the polling time arrives, if there is a status frame to be processed in the data buffer, first identify the processing method, and then perform corresponding processing. Taking the transmission of status information to the host computer via UART as an example, first determine whether the shared buffer is locked (lockflag is 0), sequentially read and parse the status frames, send the frame level information, time information, and baseband status information to the host computer for printing and saving until the number of items to be output is 0, and finally set the number of items to be processed in the control buffer to 0 and set lockflag to 1 to unlock.

[0135] Next, the user module 140 in the baseband status monitoring system 10 is introduced.

[0136] Figure 8 shows a flowchart of steps executed by a user module according to some embodiments of the present disclosure. Referring to Figure 3 and Figure 8 shown, in some embodiments, the baseband status monitoring system 10 further includes a user module 140. In the user module 140, for the first baseband status monitoring program, it further includes: in response to a control command of a user, updating a switch mask 3106 in a control buffer 310, including:

[0137] In response to the control command being legal, reading a lock flag 3101 from the control buffer 310. This step may correspond to Figure 8 steps S802 and S804.

[0138] In response to the lock flag 3101 being locked, reading the switch mask 3106 from the control buffer 310, and updating flag bits of the switch mask 3106 according to the control command.

[0139] Setting the flag bit of the lock flag 3101 to unlocked. This step may correspond to Figure 8 steps S804, S805, S806, S807, and S808.

[0140] Exemplarily, by executing the above steps, the present disclosure enables the baseband status monitoring system 10 to respond to a legal control command of a user and safely update the switch mask 3106 in the control buffer 310, and the user can flexibly adjust the system state.

[0141] Exemplarily, the overall process of steps executed by the user module 140 is summarized and described herein. Combining Figure 8 shown, after receiving a control command, first determine whether it belongs to a command in a control list. If it is legal, wait until the shared buffer is writable and then update the switch mask byte in the control buffer, and finally unlock the shared buffer again (set the lockflag to 1).

[0142] Exemplarily, by designing each software module and its functions and working processes of the baseband status monitoring system 10 (including the first baseband status monitoring program and the second baseband status monitoring program), the present disclosure realizes an interaction mechanism between a monitoring dedicated kernel processor, is suitable for state monitoring of a baseband chip 20 of a communication system with different processor architectures and different operating systems, has good versatility, and can ensure the smooth progress of the R & D process of the baseband chip 20.

[0143] The present disclosure also proposes a status monitoring device for a baseband chip of a communication system. The status monitoring device includes means for executing the status monitoring method described above.

[0144] Figure 9A simplified block diagram of a status monitoring device for a baseband chip of a communication system suitable for implementing exemplary embodiments of the present disclosure is shown. For example, a user terminal may be implemented by device 900. As shown, device 900 includes one or more processors 910, one or more memories 920 coupled to processor 910, and one or more communication modules 940 coupled to processor 910.

[0145] The communication module 940 is used for two-way communication. The communication module 940 has at least one antenna to facilitate communication. The communication interface may represent any interface necessary for communicating with other network elements.

[0146] The processor 910 may be of any type suitable for the local technical network and may include, by way of non-limiting example, one or more of the following: a general-purpose computer, a special-purpose computer, a microprocessor, a digital signal processor (DSP), and a processor based on a multi-core processor architecture. Device 900 may have multiple processors, such as an application-specific integrated circuit chip, which is clocked to synchronize with the main processor in a timely manner.

[0147] The memory 920 may include one or more non-volatile memories and one or more volatile memories. Examples of non-volatile memories include, but are not limited to, read-only memory (ROM) 924, electrically programmable read-only memory (EPROM), flash memory, hard disk, optical disc (CD), digital video disc (DVD), and other magnetic and / or optical memories. Examples of volatile memories include, but are not limited to, random access memory (RAM) 922 and other volatile memories that do not persist during a power outage.

[0148] The computer program 930 includes computer-executable instructions executed by the associated processor 910. The program 930 may be stored in the ROM 924. The processor 910 may execute any appropriate actions and processes by loading the program 930 into the RAM 922.

[0149] Embodiments of the present disclosure may be implemented by the program 930 such that the device 900 may execute any of the disclosed processes discussed with reference to Figures 4 to 8 Embodiments of the present disclosure may also be implemented by hardware or by a combination of software and hardware.

[0150] In some embodiments, the program 930 may be tangibly embodied in a computer-readable medium, which may be included in the device 900 (e.g., the memory 920) or other storage devices accessible to the device 900. The device 900 may load the program 930 from the computer-readable medium into the RAM 922 for execution. The computer-readable medium may include any type of tangible non-volatile memory, such as ROM, EPROM, flash memory, hard disk, CD, DVD, etc. The program 930 is stored on the computer-readable medium.

[0151] Generally, the various embodiments of the present disclosure may be implemented in hardware or special-purpose circuits, software, logic, or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software, which may be executed by a controller, a microprocessor, or other computing devices. Although the various aspects of the embodiments of the present disclosure are shown and described as block diagrams, flowcharts, or using some other graphical representation, it should be understood that, by way of non-limiting example, the blocks, devices, systems, techniques, or methods described herein may be implemented in hardware, software, firmware, special-purpose circuits or logic, general-purpose hardware or controllers, or other computing devices, or some combination thereof.

[0152] The present disclosure also provides at least one computer program product tangibly stored on a non-transitory computer-readable storage medium. The computer program product includes computer-executable instructions, machine-executable instructions, such as instructions included in program modules, which are executed in a device on a target real or virtual processor to perform the processes 500, Figure 5 described above with reference to Figure 6 the process 600, Figure 7 the process 700, Figure 8 the process 800. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform specific tasks or implement specific abstract data types. In various embodiments, the functions of program modules may be combined or separated as needed among the program modules. The machine-executable instructions for program modules may be executed within local or distributed devices. In a distributed device, program modules may be located in local and remote storage media.

[0153] The program code for performing the methods of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the program code is executed by the processor or controller, the functions / operations specified in the flowchart and / or block diagram are implemented. The program code can be executed entirely on the machine as an independent software package, partially on the machine, partially on the machine, partially on a remote machine, partially on a remote machine, or entirely on a remote machine or server.

[0154] In the context of the present disclosure, the computer program code or related data can be carried by any suitable carrier to enable a device, apparatus, or processor to perform the various processes and operations described above. Examples of carriers include signals, computer-readable media, and the like.

[0155] The computer-readable media can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable media can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or apparatuses, or any suitable combination of the foregoing. More specific examples of the computer-readable storage media include electrical connections with one or more wires, portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above.

[0156] Furthermore, although the operations are described in a specific order, this should not be construed as requiring that the operations be performed in the specific order or sequence shown, or that all of the shown operations be performed, to obtain the desired result. In some cases, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these details should not be construed as limitations on the scope of the present disclosure, but rather can be construed as descriptions of specific features particular to a specific embodiment. Certain features described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment can also be implemented separately or in any suitable sub-combination in multiple embodiments.

[0157] Although the present disclosure has been described in a language specific to structural features and / or method acts, it should be understood that the present disclosure as defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

[0158] It should be fully understood that the use of personally identifiable information should follow privacy policies and practices that are generally considered to meet or exceed industry or government requirements for maintaining user privacy. In particular, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly indicated to the user.

Claims

1. A method for monitoring the status of a baseband chip in a communication system, characterized in that: The baseband chip includes a first processor core, a second processor core and a shared memory, a first baseband status monitoring program runs on the first processor core, and a second baseband status monitoring program runs on the second processor core, and the method includes: For any one of the first baseband status monitoring procedure and the second baseband status monitoring procedure: In response to a status frame write request for recording baseband status information of the baseband chip, constructing the baseband status information into a baseband status frame, and writing the frame into the shared memory; and For the first baseband status monitoring procedure: In response to the status frame processing being triggered, reading out and parsing the baseband status frame from the shared memory to obtain the baseband status information; Wherein, the shared memory includes a shared buffer, the shared buffer includes a control buffer and a data buffer, and the data buffer is used to store a plurality of baseband status frames; The data structure of the control buffer includes: lock flag, next frame sequence number, number to be processed, write address, read address, switch mask; The data structure of the baseband status frame includes header information and baseband status information, and the header information includes: frame sequence number, time information, frame level, CPU ID, and baseband status information length.

2. The method according to claim 1, characterized in that The baseband status information is constructed into a baseband status frame and written into the shared memory, including: Reading the switch mask from the control buffer; In response to the flag bit of the switch mask being on, reading the lock flag from the control buffer; In response to the flag bit of the lock flag being locked, waiting for the flag bit of the lock flag to be changed to unlocked; In response to the flag bit of the lock flag being unlocked, setting the flag bit of the lock flag to locked, acquiring the next frame sequence number from the control buffer, and constructing the baseband status information into the baseband status frame; The write address is obtained from the control buffer, the baseband status frame is written into the data buffer, and the write address is updated.

3. The method according to claim 2, characterized in that Acquiring the next frame sequence number from the control buffer and constructing the baseband status information into the baseband status frame includes: In response to the baseband status information being greater than a preset length of a single baseband status frame, the baseband status information is split and at least two baseband status frames are generated.

4. The method according to claim 3, characterized in that Splitting the baseband status information and generating at least two baseband status frames includes: Splitting the baseband state information to obtain first baseband state information and second baseband state information, where the first baseband state information and the second baseband state information are less than or equal to the preset length; The header information is added to the first baseband status information and the second baseband status information respectively, so as to obtain the at least two baseband status frames.

5. The method according to claim 2, characterized in that After updating the write address, the method further includes: In response to a baseband status frame to be processed in the data buffer being overwritten, updating the read address of the control buffer so that the read address points to the first address of the earliest baseband status frame to be processed; Updating the pending number of the control buffer; Updating the next frame sequence number of the control buffer; The flag bit of the lock flag is set to unlock.

6. The method according to claim 1, characterized in that Reading out and parsing the baseband status frame from the shared memory to obtain the baseband status information includes: Obtain the number to be processed from the control buffer; In response to the number to be processed not being 0, identifying a processing method of the baseband status frame, the processing method comprising: any one of FLASH, UART, and a custom method; The baseband status frame is read out and parsed according to the processing method to obtain the baseband status information.

7. The method according to claim 6, characterized in that The processing method is UART; Reading and parsing the baseband status frame according to the processing method to obtain the baseband status information includes: Reading the lock flag from the control buffer; In response to the flag bit of the lock flag being locked, assigning the number to be processed to a preset local variable; Read a baseband status frame from the read address and parse it, obtain the baseband status information, the frame level, the time information and send them to the host computer, decrement the preset local variable by 1, and update the read address; In response to the preset local variable being 0, the number to be processed is updated to 0, and the flag bit of the lock flag is set to unlock.

8. The method according to any one of claims 1 to 7, characterized in that The first baseband status monitoring program further includes: in response to a first initialization request, initializing the CPUID, the processing method of the baseband status frame, and the shared buffer; The second baseband status monitoring program further includes: initializing the CPUID in response to a second initialization request.

9. The method according to any one of claims 1 to 7, characterized in that The first baseband status monitoring program further includes: updating the switch mask in the control buffer in response to a user's control command, including: In response to the control command being legal, reading the lock flag from the control buffer; In response to the flag bit of the lock flag being locked, reading the switch mask from the control buffer, and updating the flag bit of the switch mask according to the control command; The flag bit of the lock flag is set to unlock.

10. The method according to any one of claims 1 to 7, characterized in that In the data structure of the control buffer: the lock flag is used to identify whether the shared buffer is locked or unlocked; the next frame sequence number is used to identify the sequence number of the next baseband status frame in the data buffer; the number to be processed is used to identify the number of baseband status frames to be processed in the data buffer; the write address is used to identify the write address of the next baseband status frame in the data buffer; the read address is used to identify the earliest first address of the baseband status frames to be processed in the data buffer; the switch mask is used to identify whether the monitoring function of the baseband status frame is turned on or off; In the header information: the frame sequence number is used to identify the sequence number of the baseband status frame; The time information is used to identify the time when the baseband status information is generated; the frame level is used to identify the importance of the baseband status frame; the CPU ID is used to identify the core processor source of the baseband status frame, and the core processor source includes the first processor core and the second processor core.

11. A state monitoring device for a baseband chip of a communication system, characterized in that: The condition monitoring device comprises means for executing the condition monitoring method according to any one of claims 1-10.

12. A non-transitory computer-readable storage medium storing machine-executable instructions, characterized in that: When the machine executable instructions are executed by a baseband chip of a communication system, the baseband chip is caused to execute the status monitoring method according to any one of claims 1 to 10.

13. A computer program product comprising machine executable instructions, characterized in that When the machine executable instructions are executed by a baseband chip of a communication system, the baseband chip is caused to execute the status monitoring method according to any one of claims 1 to 10.

14. A baseband chip for a communication system, characterized in that: The baseband chip includes a first processor core, a second processor core and a shared memory, and the first processor core and the second processor core are configured to respectively run a first baseband status monitoring program and a second baseband status monitoring program to execute the status monitoring method as described in any one of claims 1-10.

Images