LED dimming system and control circuit thereof

Abstract

The invention discloses an LED dimming system and a control circuit thereof. The control circuit controls the opening and closing of a clock signal through an oscillator control circuit according to a feedback signal of the output voltage of the power conversion circuit and a dimming control signal, so that the opening of the power conversion circuit can be synchronized with the rising edge of the dimming control signal; according to the power conversion circuit provided by the invention, the minimum turn-on time of the power conversion circuit each time is ensured, and some dimming periods can be adaptively strided when the turn-on time of the dimming switch is relatively short, so that the problem that the output voltage drops when the dimming switch is turned on can be avoided, the output ripple of the circuit can be reduced, and the dimming ratio can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of LED driving, and more particularly to an LED dimming system and a control circuit thereof. Background Art

[0002] A light-emitting diode (LED) is a solid-state semiconductor device that converts electrical energy into visible light. LEDs offer advantages such as high luminous intensity, ease of control, low-voltage DC drive, and long life. Consequently, they are widely used in a variety of applications, including lighting and display backlighting.

[0003] Currently, the main dimming methods for LED systems are silicon-controlled rectifier (TRIAC) dimming and pulse-width modulation (PWM) dimming. PWM dimming uses a PWM signal with a specific duty cycle to open and close the current flowing through the LED string, thereby adjusting the brightness of the LED string. A key advantage of PWM dimming over TRIAC dimming is that it prevents visible flicker. The higher the dimming frequency, the less noticeable the flicker is to the human eye. When the dimming frequency is greater than 3kHz, the flicker is essentially imperceptible to the human eye. Therefore, PWM dimming is increasingly favored by the industry.

[0004] Figure 1 and Figure 2 A circuit schematic diagram and a waveform schematic diagram of an LED dimming system in the prior art are respectively shown. Figure 1 The present invention shows a peak current mode LED dimming system 100, comprising a power conversion circuit 101, a controller 102, a dimming controller 103, and dimming switches S2 and S3. The power conversion circuit 101 is configured to provide an output voltage Vout to an LED light strip 104 based on an input voltage Vin. The controller 102 is configured to control the on and off state of the power switch T1 in the power conversion circuit 101 to ensure a stable output from the power conversion circuit 101. The dimming controller 103 is configured to generate a dimming control signal PWM_dim based on an external dimming signal to control the on and off states of the dimming switches S2 and S3 connected in series with the LED light strip 104, thereby controlling the brightness of the LED light strip 104. The controller 102 is configured to control the power switch T1 to turn on when a pulse of the clock signal CLK provided by the oscillator 122 arrives, thereby causing the inductor current in the power conversion circuit 101 to begin to rise. When the peak value of the inductor current reaches the output value of the error amplifier 121, the controller 102 turns off the power switch T1, thereby causing the inductor current to begin to decrease, ultimately stabilizing the output voltage Vout of the power conversion circuit 101 at an appropriate value.

[0005] exist Figure 1In the LED dimming system 100, the dimming control signal PWM_dim not only controls the on and off of the dimming switch, but also controls the output of the error amplifier 121 and the on and off of the power switch T1. Figure 2 As shown, the drive control signal PWM_CTL is the control signal of the power switch T1 in the power conversion circuit. When the dimming control signal PWM_dim is at a low level, the dimming switch is disconnected, and the current ILED in the LED light bar 104, which serves as the load of the power conversion circuit 101, is also at a low level. Therefore, the power switch T1 in the power conversion circuit 101 needs to be turned off at the same time to prevent excess energy from accumulating on the output capacitor Cout. At the same time, the peak information of the inductor current is stored on the capacitor C1. In this way, when the dimming control signal PWM_dim is at a high level again, the controller 102 can respond quickly to enable the power conversion circuit 101 to quickly establish the inductor current under steady-state operation.

[0006] However, there is a problem in the existing LED dimming system 100, that is, when the dimming control signal PWM_dim turns to a high level, the clock signal CLK may not be able to turn to a high level at the same time, which will cause a gap between the effective pulse of the clock signal CLK and the rising edge of the dimming control signal PWM_dim. Figure 2 The delay time t1 shown in FIG. 1 prevents the power conversion circuit 101 from quickly establishing a stable inductor current when the dimming control signal PWM_dim switches to a high level, which in turn causes the output voltage Vout to drop. This not only results in large output voltage ripple but, in severe cases, may also introduce noise. Furthermore, in applications with high LED dimming ratios, the duty cycle of the dimming control signal PWM_dim becomes very small, resulting in a shorter inductor current establishment time, making the aforementioned situation even more severe. Therefore, in conventional LED dimming systems, it is difficult to achieve a very short on-time, severely limiting further improvements in the LED dimming ratio. Summary of the Invention

[0007] In view of the above problems, the object of the present invention is to provide an LED dimming system and a control circuit thereof. By synchronizing the start-up of the power conversion circuit with the rising edge of the dimming control signal, and by ensuring the minimum start-up time of the power conversion circuit each time and adaptively skipping some dimming cycles when the dimming switch is on for a short time, the problem of output voltage drop when the dimming switch is on can be avoided, and the output ripple of the circuit can be reduced and the dimming ratio can be improved.

[0008] According to one aspect of the present invention, a control circuit for an LED dimming system is provided, wherein the LED dimming system includes a power switch and a dimming switch, and the on and off switching of the dimming switch is controlled by a dimming control signal, wherein the control circuit includes: a feedback circuit for generating a feedback signal based on the current flowing through the LED load; an oscillator for generating a clock signal, wherein the clock signal includes a plurality of continuous pulses; a logic circuit for controlling the conduction of the power switch based on the clock signal, wherein the effective edges of adjacent pulses define a switching cycle; and an oscillator control circuit for receiving the feedback signal and the dimming control signal and providing a synchronization control signal to the oscillator based on the effective edge of the dimming control signal when the feedback signal is less than a second reference voltage, wherein the oscillator generates pulses of the clock signal based on the synchronization control signal to achieve synchronous turning on of the load switch and the dimming switch.

[0009] Optionally, when the feedback signal is less than the second reference voltage, the effective edge of the synchronization control signal is synchronized with the effective edge of the dimming control signal, and the invalid edge of the synchronization control signal is delayed by a first time relative to the invalid edge of the dimming control signal.

[0010] Optionally, the first time is equal to one switching cycle.

[0011] Optionally, the effective level time of the synchronization control signal is greater than / equal to a minimum on-time, wherein the minimum on-time is equal to M switching cycles, and M is an integer greater than 1.

[0012] Optionally, the control circuit further includes: a peak current detection module, configured to compare the feedback signal with a first reference voltage to generate an error amplification signal, and generate a peak current detection signal when the current detection signal representing the inductor current of the LED dimming system reaches the error amplification signal, wherein the logic circuit is configured to control the shutdown of the power switch in each switching cycle according to the peak current detection signal.

[0013] Optionally, the second reference voltage is greater than the first reference voltage.

[0014] Optionally, the oscillator control circuit includes: a first RS latch, a set terminal for receiving the dimming control signal, a reset terminal for receiving the clock signal, and an output terminal for generating a first trigger signal; a first comparator, a non-inverting input terminal for receiving the second reference voltage, an inverting input terminal for receiving the feedback signal, and an output terminal for generating a first comparison signal; a unilateral delay unit, for delaying an invalid edge of the first comparison signal by a second time to obtain a delayed signal, wherein the second time is greater than the first time; a first AND gate, for performing an AND logic operation on the first trigger signal and the delayed signal to generate a second trigger signal; a minimum on-time module, for counting the period of the clock signal at the start time of the synchronization control signal and generating the minimum on-time signal after a preset time, wherein the period count value of the clock signal within the preset time period represents the minimum on-time; and a second RS latch, a set terminal for receiving the second trigger signal, a reset terminal for receiving the minimum on-time signal, and an output terminal for providing the synchronization control signal.

[0015] Optionally, the minimum on-time module includes: an OR gate, a first input terminal for receiving the clock signal, and a second input terminal for receiving the minimum on-time signal; and M cascaded D flip-flops, the data terminal and the negative output terminal of each D flip-flop being short-circuited, the reset terminal of each D flip-flop being used to receive the synchronization control signal, the clock terminal of the first D flip-flop among the M D flip-flops being connected to the output terminal of the OR gate, the clock terminals of the second to Mth D flip-flops among the M D flip-flops being connected to the negative output terminal of the previous D flip-flop, and the positive output terminal of the Mth D flip-flop among the multiple D flip-flops being used to provide the minimum on-time signal.

[0016] Optionally, the oscillator includes: a ramp generating module for generating a ramp signal; a second comparator for comparing the ramp signal with a reference voltage to generate a second comparison signal; a third RS latch, whose set end is used to receive the second comparison signal, the reset end is used to receive the inverted signal of the clock signal, and the output end is used to provide a third trigger signal; a second AND gate for performing an AND logic operation on the third trigger signal and the synchronization control signal; and a single pulse module for generating the clock signal based on the output of the second AND gate.

[0017] Optionally, the ramp generating module includes: a first current source and a first capacitor connected in series between a power supply voltage and ground; and a first transistor, a first end of which is connected to an intermediate node between the first current source and the first capacitor, a second end of which is connected to the ground, and a control end of which is connected to the output of the second AND gate, wherein the first transistor generates the ramp signal at an intermediate node between the two by controlling the charging and discharging process of the first current source on the first capacitor.

[0018] Optionally, the peak current detection module includes: an error amplifier, whose inverting input terminal is used to receive the feedback signal, whose non-inverting input terminal is used to receive the first reference voltage, and whose output terminal is used to generate an error amplification signal; and a third comparator, whose inverting input terminal is used to receive the error amplification signal, whose non-inverting input terminal is used to receive the current detection signal, and whose output terminal is used to generate the peak current detection signal, wherein the current detection signal is obtained through a sampling resistor connected to the power switch.

[0019] Optionally, the peak current detection module further includes: a first switch connected between the output terminal of the error amplifier and the inverting input terminal of the first comparator, wherein the dimming control signal is used to control the on and off switching of the first switch; and a second capacitor connected between the inverting input terminal of the third comparator and ground.

[0020] Optionally, the logic circuit includes: a fourth RS latch, a set end for receiving the clock signal, a reset end for receiving the peak current detection signal, and an output end for generating a drive control signal, wherein the drive control signal is used to control the on and off switching of the power switch.

[0021] According to another aspect of the present invention, there is provided an LED dimming system, comprising: a power conversion circuit including at least one power switch, the power conversion circuit being configured to provide an output voltage to an LED load based on an input voltage; a dimming switch being configured to be connected in series with the LED load; a dimming controller being configured to generate a dimming control signal based on an external dimming signal, the dimming control signal being configured to control the on and off of the dimming switch; and the control circuit being configured to generate a drive control signal, the drive control signal being configured to control the on and off of the at least one power switch.

[0022] An embodiment of the present invention provides an LED dimming system and its control circuit based on a peak current mode control architecture. The control circuit controls the on and off of a clock signal according to a feedback signal of the output voltage of a power conversion circuit and a dimming control signal through an oscillator control circuit, thereby synchronizing the on-state of the power conversion circuit with the rising edge of the dimming control signal, thereby avoiding the problem of output voltage drop when the dimming switch is turned on and reducing the output ripple of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0024] Figure 1 A circuit diagram of an LED dimming system in the prior art is shown.

[0025] Figure 2 A waveform diagram of an LED dimming system in the prior art is shown.

[0026] Figure 3 A schematic structural diagram of an LED dimming system according to an embodiment of the present invention is shown.

[0027] Figure 4 A circuit diagram of a peak current detection circuit according to an embodiment of the present invention is shown.

[0028] Figure 5 A circuit diagram of an oscillator control circuit according to an embodiment of the present invention is shown.

[0029] Figure 6 FIG. 1 is a circuit diagram of an oscillator according to an embodiment of the present invention.

[0030] Figure 7 A waveform diagram of the LED dimming system according to an embodiment of the present invention is shown when the dimming switch changes from a longer on-time to a shorter on-time.

[0031] Figure 8 The figure shows a simulation waveform diagram of the LED dimming system according to the embodiment of the present invention when the dimming switch changes from a longer on-time to a shorter on-time. DETAILED DESCRIPTION

[0032] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0033] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the present disclosure. Therefore, appearances of the phrases "in one embodiment" or "in an embodiment" throughout this specification do not necessarily refer to the same embodiment. The verbs "comprise" and "have" are used herein as open limitations that neither exclude nor require the presence of unrecited features. Unless expressly stated otherwise, features recited in the dependent claims may be freely combined with one another. References throughout this document to "a" or "an" (i.e., in the singular) identifying an element do not exclude a plurality of such elements. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Unless otherwise indicated, the term "connected" is used to designate a direct electrical connection between circuit elements, while the term "coupled" is used to designate an electrical connection between circuit elements that may be direct or via one or more other elements. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When referring to the voltage of a node or terminal, unless otherwise indicated, the voltage is considered to be the voltage between the node and a reference potential (usually ground). Furthermore, when referring to the potential of a node or terminal, the potential is considered to refer to the reference potential unless otherwise indicated. The voltage and potential of a given node or terminal will further be designated by the same reference numerals. A signal that alternates between a first logic state (e.g., a logic low state) and a second logic state (e.g., a logic high state) is referred to as a "logic signal." Different logic signals of the same electronic circuit may have different high and low states. In particular, the high and low states of a logic signal may correspond to voltages or currents that may not be completely constant in the high or low state.

[0034] In this application, a power switch is a transistor that operates in a switching mode to provide a current path, and includes a transistor selected from a metal oxide semiconductor field effect transistor, an insulated gate bipolar transistor, and a bipolar transistor. The first terminal and the second terminal of the power switch are respectively a high potential terminal and a low potential terminal in the current path, and the control terminal is used to receive a drive signal to control the conduction and shutdown of the switch.

[0035] The present invention will be further described below with reference to the accompanying drawings and examples.

[0036] Figure 3 FIG. 2 is a circuit diagram of an LED dimming system 200 according to an embodiment of the present invention. Figure 3 In the illustrated embodiment, the LED dimming system 200 includes a power conversion circuit 201 , a control circuit 202 , a dimming controller 203 , an LED load 204 , a dimming switch 205 , and a current bias circuit 206 .

[0037] The input terminal of the power conversion circuit 201 is used to receive an input voltage Vin, and the output terminal of the power conversion circuit 201 is connected to the LED load 204. The power conversion circuit 201 includes at least one power switch, and by controlling the on and off switching of the at least one power switch, an output voltage is provided at the output terminal of the power conversion circuit 201 to drive the LED load 204.

[0038] exist Figure 3 In the illustrated embodiment, the power conversion circuit 201 is illustrated as a power conversion circuit of a BOOST topology architecture. Specifically, the power conversion circuit 201 includes an inductor L1, a power switch T1, a freewheeling diode D1, an output capacitor Cout, and a sampling resistor Rs. The inductor L1, the power switch T1, and the sampling resistor Rs are connected in series between the input voltage Vin and the reference ground, and the common node of the inductor L1 and the power switch T1 is marked as the switch node SW. The freewheeling diode D1 is connected between the switch node SW and the output end of the power conversion circuit 201. The output capacitor Cout is connected between the output end of the power conversion circuit 201 and the reference ground. It should be understood that in other embodiments, the power conversion circuit 201 may also select other types of suitable isolated or non-isolated topologies, such as a BUCK topology, a FLYBACK topology, a resonant half-bridge topology, etc.

[0039] In addition, Figure 3In the illustrated embodiment, the power switch T1 is illustrated as an N-type metal-oxide semiconductor field-effect transistor (MOSFET), and the freewheeling diode D1 is illustrated as an uncontrollable diode. Those skilled in the art will appreciate that in other embodiments, the power switch T1 may also include other suitable semiconductor power switching device types, such as a junction field-effect transistor (JFET), an insulated-gate bipolar transistor (IGBT), and a double-diffused metal-oxide semiconductor (DMOS). The freewheeling diode D1 may also be replaced by a power switching device, such as a synchronous rectifier. The on and off switching of the power switch T1 is controlled by a drive control signal PWM_CTL generated by the control circuit 202. In the embodiment where the freewheeling diode D1 is replaced by a power switching device, the control circuit 202 also generates an inverse signal of the drive control signal PWM_CTL to control the on and off switching of the synchronous rectifier. Those skilled in the art will understand that the inverted signal of the driving control signal PWM_CTL refers to a signal that is logically complementary to the driving control signal PWM_CTL.

[0040] Furthermore, the LED load 204 of this embodiment is, for example, an LED light string formed by connecting a plurality of LEDs in series.

[0041] In one embodiment, the dimming switch 205 is a dimming switch group, the number of which is determined by the number of LED light strings. Figure 3 In the illustrated embodiment, the dimmer switch 205 includes two dimmer switches S2 and S3. The dimmer switches S2 and S3 are respectively connected between the two parallel LED light strings of the LED load 204 and the current bias circuit 206. Specifically, the dimmer switch S2 is connected between the first LED light string and the first current terminal of the current bias circuit 206, and the dimmer switch S3 is connected between the second LED light string and the second current terminal of the current bias circuit 206. Those skilled in the art will appreciate that in a dimming system, the number and arrangement of LED light strings can vary depending on the application and are not limited to the two parallel LED light strings shown here. The dimmer switch 205 is controlled by the dimming control signal PWM_dim generated by the dimming controller 203. The dimming control signal PWM_dim controls the conduction or shutdown of the dimmer switch 205, thereby closing or disconnecting the current flowing through the LED light string, thereby achieving the purpose of LED dimming.

[0042] Furthermore, the dimming controller 203 generates the dimming control signal PWM_dim according to the LED dimming set point provided by the external dimming signal. In one embodiment, the dimming controller 203 may include a microcontroller unit (MCU), and the dimming control signal PWM_dim is a digital pulse width modulation signal with logic high and low levels.

[0043] Furthermore, current bias circuit 206 is configured to provide current to multiple LED strings in LED load 204. In one embodiment, current bias circuit 206 includes a bias current source Ib and a current mirror formed by transistors M1 to M3. Transistors M1 to M3 are, for example, N-type MOSFETs. The sources of transistors M1 to M3 are connected to a reference ground. One end of bias current source Ib is connected to a power supply voltage, and the other end is connected to the drain and gate of transistor M1. The drain of transistor M2 serves as a first current terminal of current bias circuit 206 and is connected to the first LED string. The gate of transistor M2 is connected to the gate and drain of transistor M1. The drain of transistor M3 serves as a second current terminal of current bias circuit 206 and is connected to the second LED string. The gate of transistor M3 is connected to the gate and drain of transistor M1. Furthermore, the size ratio of transistors M1, M2, and M3 is 1:N:N, where N is an integer greater than 1. Therefore, current bias circuit 206 can provide a set current of N*Ib to the LED strings in LED load 204.

[0044] exist Figure 3 In the illustrated embodiment, the control circuit 202 uses a peak current mode to control the power conversion circuit 201 , which includes a feedback circuit 210 , an oscillator 211 , a peak current detection circuit 212 , a logic circuit 213 , a driver 214 , and an oscillator control circuit 215 .

[0045] The feedback circuit 211 is used to sample the current flowing through the LED load 204 and generate a feedback signal Vfb. For example, the feedback circuit 211 compares and generates a minimum voltage of the VDS of the current sinks under each channel LED string, and uses this minimum voltage as the feedback signal Vfb.

[0046] The oscillator 211 is used to generate a clock signal CLK. The clock signal CLK has a plurality of consecutive pulses, each pulse being used to determine the turn-on time of the power switch T1 in each switching cycle. In this embodiment, the effective edges of adjacent pulses of the clock signal CLK define a switching cycle.

[0047] The peak current detection circuit 212 is configured to detect the peak value of the inductor current of the power conversion circuit 201 based on the feedback signal Vfb, the reference voltage Vref1, and the current detection signal Vs to generate a peak current detection signal IPEAK. This peak current detection circuit IPEAK is used to determine the turn-off time of the power switch T1 during each switching cycle. In this embodiment, the peak current detection module 212 is configured to compare the feedback signal Vfb with the reference voltage Vref1 to generate an error amplification signal, and to generate the peak current detection signal IPEAK when the current detection signal Vs reaches the error amplification signal. For example, the current detection signal Vs can be obtained via a sampling resistor Rs connected to the power switch T1.

[0048] Logic circuit 213 implements the circuit's logic control functions. It receives the clock signal CLK, the peak current detection signal IPEAK, and the dimming control signal PWM_dim, and generates the drive control signal PWM_CTL to control the on and off of power switch T1. In this embodiment, logic circuit 213 is implemented as an RS latch, whose set terminal receives the clock signal CLK and whose reset terminal receives the peak current detection signal IPEAK. When a pulse of the clock signal CLK is generated, power switch T1 is turned on, and the inductor current begins to increase. When the peak value of the inductor current reaches the error amplification signal, power switch T1 is turned off, and the inductor current begins to decrease.

[0049] The driver 214 is connected between the gate of the power switch T1 and the output of the logic circuit 213 , and is configured to drive the power switch T1 to be turned on or off according to the driving control signal PWM_CTL generated by the logic circuit 213 .

[0050] The oscillator control circuit 215 is configured to receive the feedback signal Vfb and the dimming control signal PWM_dim, and control the enabling or disabling of the oscillator 211 based on the feedback signal Vfb and the dimming control signal PWM_dim. For example, the oscillator control circuit 215 is configured to compare the feedback signal Vfb with a reference voltage Vref2 and, if the feedback signal Vfb is less than the reference voltage Vref2, provide a synchronization control signal OSC_CTL to the oscillator 211 based on an active edge (e.g., a rising edge) of the dimming control signal PWM_dim. The oscillator 211 generates pulses of the clock signal CLK based on the synchronization control signal OSC_CTL, synchronizing the clock signal CLK with the active edge of the dimming control signal PWM_dim. This ultimately enables the power switch T1 and the dimming switch 205 to be turned on synchronously, thereby reducing output ripple of the circuit.

[0051] Figure 4 FIG. 1 shows a schematic diagram of a peak current detection circuit according to an embodiment of the present invention. Figure 4 As shown, the peak current detection circuit 212 of this embodiment includes an error amplifier 2101, a switch S1, a capacitor C1, and a comparator 2102. The error amplifier 2101 has a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal is used to receive the reference voltage Vref1, the inverting input terminal is used to receive the feedback signal Vfb, and the output terminal is used to output the error amplified signal Vea. The comparator 2102 has a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal is used to receive the current detection signal Vs, the inverting input terminal is connected to the output terminal of the error amplifier 2101 via the switch S1, and the output terminal is used to provide the peak current detection signal IPEAK. The capacitor C1 is connected between the inverting input terminal of the comparator 2102 and the reference ground.

[0052] In this embodiment, error amplifier 2101 is used to adjust the peak current threshold of the inductor current. For example, error amplifier 2101 can compare the actual current of LED load 204 (which can be represented by feedback signal Vfb) with a desired LED current (which can be represented by reference voltage Vref1). This desired LED current can be established by a fixed or adjustable reference voltage source (not shown). The output of error amplifier 2101 can be used to set the peak current threshold of the inductor current. Capacitor C1 can be used to maintain a voltage representing the peak current threshold level. When dimming control signal PWM_dim transitions to an inactive state (e.g., a low level), switch S1 is turned off, disconnecting capacitor C1 from the output of error amplifier 2101. Comparator 2102 functions as a peak current comparator, comparing current sense signal Vs representing the actual inductor current with error amplified signal Vea representing the peak current threshold. When the dimming control signal PWM_dim remains active (e.g., high) for a prolonged period, the inductor current can increase to a peak current threshold. The logic circuit 213 then turns off the power switch T1, causing the inductor current to begin decreasing. If the dimming control signal PWM_dim remains active at this time, the logic circuit 210 can turn on the power switch T1 again upon receiving another clock pulse, causing the inductor current to begin increasing again. This allows the switching cycle of the inductor L1 to continue repeating until the dimming control signal PWM_dim reaches an inactive edge (e.g., a falling edge), at which point the power switch T1 is simultaneously turned off. This prevents excess energy from accumulating on the output capacitor Cout. Furthermore, because the voltage at the peak current threshold is stored on the capacitor C1, the power conversion circuit 201 can quickly establish a steady-state inductor current when the dimming control signal PWM_dim becomes active again (e.g., high).

[0053] Figure 5 FIG. 2 shows a schematic circuit diagram of an oscillator control circuit 215 according to an embodiment of the present invention. Figure 5 As shown, the oscillator control circuit 215 includes a comparator 2103 , a unilateral delay unit 2104 , an AND gate 2106 , RS latches 2105 and 2107 , and a minimum on-time module 2108 .

[0054] Comparator 2103 has a non-inverting input, an inverting input, and an output. The non-inverting input is used to receive a reference voltage Vref2, the inverting input is used to receive the feedback signal Vfb, and the output is used to output a comparison signal V1. In this embodiment, reference voltage Vref2 is greater than reference voltage Vref1. In this embodiment, comparator 2103 is a hysteresis comparator.

[0055] The unilateral delay unit 2104 is configured to delay an invalid edge (eg, a falling edge) of the comparison signal V1 for a first time to obtain a delayed signal V2.

[0056] The set terminal of the RS latch 2105 is connected to the dimming control signal PWM_dim, the reset terminal is connected to the clock signal CLK, and the output terminal is used to provide a trigger signal Ka.

[0057] One input terminal of the AND gate 2106 is connected to the delay signal V2, and the other input terminal is connected to the output terminal of the RS latch 2105, and is used to perform an AND logic operation on the trigger signal Ka and the delay signal V2 to generate a trigger signal Kb.

[0058] The minimum on-time module 2108 is configured to receive the clock signal CLK and, at the start of each cycle of the synchronization control signal OSC_CTL, generate a minimum on-time signal Tmin, such that the active level duration of the synchronization control signal OSC_CTL is greater than or equal to the minimum on-time. In one embodiment, the start time of the synchronization control signal OSC_CTL is the rising edge of the synchronization control signal OSC_CTL. In other embodiments, if the synchronization control signal OSC_CTL is active low, the start time is the falling edge of the synchronization control signal OSC_CTL.

[0059] In this embodiment, the minimum on-time module 2108 is used to count the cycles of the clock signal CLK at the start time of the synchronization control signal OSC_CTL, and generate the minimum on-time signal Tmin after a preset time period. Therefore, the minimum on-time can be represented by the cycle count value of the clock signal CLK within the preset time period (i.e., the count value of the switching cycle). Figure 5In the illustrated embodiment, when the cycle count value of the clock signal CLK reaches a predetermined value M, the minimum on-time signal Tmin changes from a logic low level to a logic high level. Therefore, the minimum on-time of this embodiment is equal to M switching cycles, where M is an integer greater than 1.

[0060] Specifically, the minimum on-time module 2108 includes an OR gate 2109 and a plurality of M cascaded D flip-flops DFF. The data terminal and the negative output terminal of each D flip-flop are short-circuited, the reset terminal of each D flip-flop is used to receive the synchronization control signal OSC_CTL, the clock terminal of the first D flip-flop among the M D flip-flops is connected to the output terminal of the OR gate 2109, the clock terminals of the second to Mth D flip-flops among the M D flip-flops are connected to the negative output terminal of the previous D flip-flop, and the positive output terminal of the Mth D flip-flop among the multiple D flip-flops is used to provide the minimum on-time signal Tmin.

[0061] Taking M=2 as an example, one input terminal of OR gate 2109 is used to receive the clock signal CLK, and the other input terminal is used to receive the minimum on-time signal. The data terminal and negative output terminal of D flip-flops DFF1 and DFF2 are short-circuited, and the reset terminals of D flip-flops DFF1 and DFF2 are used to receive the synchronization control signal OSC_CTL. The clock terminal of D flip-flop DFF1 is connected to the output of OR gate 2109, the clock terminal of D flip-flop DFF2 is connected to the negative output terminal of D flip-flop DFF1, and the positive output terminal of D flip-flop DFF2 is used to provide the minimum on-time signal Tmin.

[0062] The RS latch 2107 is used to generate the synchronization control signal OSC_CTL according to the trigger signal Kb and the minimum on-time signal Tmin. In this embodiment, the set terminal of the RS latch 2107 is connected to the trigger signal Kb, the reset terminal of the RS latch 2107 is connected to the minimum on-time Tmin, and the output terminal is used to provide the synchronization control signal OSC_CTL.

[0063] In this embodiment, when the dimming switch is on for a long time, the feedback signal Vfb decreases due to the dimming switch being on, so the output signal V1 of the comparator 2103 is high. Therefore, when the rising edge of the dimming control signal PWM_dim arrives, the output signal Kb of the AND gate 2106 becomes high, thereby causing the synchronization control signal OSC_CTL to change from a low level to a high level. When the dimming switch is on for a short time, the time during which the LED load 204 draws current from the output capacitor Cout becomes very short during each dimming cycle. Therefore, if the power conversion circuit 201 is turned on during each dimming cycle, the output voltage Vout will be significantly increased, resulting in increased output ripple. Therefore, in order to reduce the output ripple, when the on-time of the dimming switch is short, if the feedback signal Vfb is greater than the reference voltage Vref2, the output signal V1 of the comparator 2103 is maintained at a low level. In this case, when the rising edge of the dimming control signal PWM_dim arrives, the output of the RS latch 2107 still does not become a high level, so that the power conversion circuit 201 will not be turned on in some dimming cycles. Until the feedback signal Vfb is less than the reference voltage Vref2, the RS latch 2107 will change the synchronization control signal OSC_CTL to a high level when the rising edge of the dimming control signal PWM_dim arrives.

[0064] Figure 6 FIG. 2 shows a circuit diagram of the oscillator 211 according to an embodiment of the present invention. Figure 6 As shown, the oscillator 211 of this embodiment includes a ramp generating module 2112 , a comparator 2113 , an RS latch 2114 , an AND gate 2115 , a single pulse module 2116 and an inverter 2117 .

[0065] Among them, the ramp generating module 2112 is used to generate the ramp signal RAMP. In one embodiment, the ramp signal RAMP is a triangular wave signal. Specifically, the ramp generating module 2112 includes a current source Is, a capacitor Cs and a transistor Ms. The current source Is and the capacitor Cs are connected in series between the power supply voltage VDD and the reference ground, the first end of the transistor Ms is connected to the middle node between the current source Is and the capacitor Cs, and the second end of the transistor Ms is connected to the reference ground. The transistor Ms generates the ramp signal RAMP at the middle node between the two by controlling the charging and discharging process of the current source Is on the capacitor Cs. For example, the transistor Ms can be an N-type MOSFET.

[0066] Comparator 2113 is configured to compare the ramp signal RAMP with a reference voltage Vbg to generate a comparison signal V3. In one embodiment, comparator 2113 is a hysteresis comparator. RS latch 2114 has a set terminal connected to comparison signal V3, a reset terminal connected to clock signal CLK via inverter 2117 to receive an inverted version of clock signal CLK, and an output terminal configured to provide a trigger signal Kd. AND gate 2115 is configured to perform an AND logic operation on trigger signal Kd and synchronization control signal OSC_CTL. The single pulse module 2116 is connected to the output of AND gate 2115 to generate the clock signal CLK based on the output of AND gate 2115.

[0067] In this embodiment, when the synchronous control signal OSC_CTL is at a low level, the output of the AND gate 2115 is at a low level, so the transistor Ms is turned off, the current source Is charges the capacitor Cs, and the ramp signal RAMP gradually increases. When the ramp signal RAMP is greater than the reference voltage Vbg, the comparison signal V3 flips to a high level, so the output signal Kd of the RS latch 2114 flips to a high level. Therefore, when the synchronous control signal OSC_CTL flips to a high level, the output of the AND gate 2115 immediately becomes a high level, and then the single pulse module 2116 generates a pulse of the clock signal CLK, thereby controlling the inductor current of the power conversion circuit 201 to increase.

[0068] Figure 7 A waveform diagram of the LED dimming system according to an embodiment of the present invention is shown when the dimming switch changes from a longer on-time to a shorter on-time. Figure 7 The waveforms shown in the figure show a conceptual example of the dimming control signal PWM_dim, the synchronization control signal OSC_CTL, the clock signal and the inductor current. Figures 3 to 7 The principle of the LED dimming system according to the embodiment of the present invention is described.

[0069] For longer dimmer switch on times (e.g. Figure 7During the time period t0-t1 in the dimmer switch, in one embodiment, the dimmer switch's on-time is greater than the minimum on-time set by the minimum on-time module 2108 (e.g., two switching cycles). When the dimming control signal PWM_dim rises, the output Ka of the RS latch 2105 goes high. Simultaneously, due to the dimming switch's on-time, the feedback signal Vfb decreases, causing the output signal V1 of the comparator 2103 to also go high (in this case, the comparator's output is a rising-edge flip, with no delay). Consequently, the output signal Kb of the AND gate 2106 goes high, causing the synchronization control signal OSC_CTL to transition from low to high. Consequently, the rising edge of the synchronization control signal OSC_CTL synchronizes with the rising edge of the dimming control signal PWM_dim. After the synchronization control signal OSC_CTL goes high, the oscillator 211 is controlled to generate pulses of the clock signal CLK, gradually increasing the inductor current and preventing a drop in the output voltage Vout. Since the reference voltage Vref2 is greater than the reference voltage Vref1, when the dimming control signal PWM_dim is at a high level, the feedback signal Vfb is adjusted by the error amplifier 2101 to be equal to the reference voltage Vref1. Therefore, the output V1 of the comparator 2103 is always at a high level, so that the synchronization control signal OSC_CTL can also be maintained at a high level, and the oscillator 211 continues to output continuous pulses.

[0070] Furthermore, because the high-level duration of the dimming control signal PWM_dim is greater than the minimum on-time, when the falling edge of the dimming control signal PWM_dim arrives, the minimum on-time signal Tmin has already reached a high level. Simultaneously, the dimmer switch's turning off causes the feedback signal Vfb to go high. However, due to the presence of the unilateral delay unit 2104, the falling edge of the signal V2 is delayed relative to the falling edge of the signal V1. Therefore, the synchronous control signal OSC_CTL remains high at this time. Only when the next pulse of the clock signal CLK arrives, pulling the trigger signal Ka low, does the output Kb of the AND gate 2106 go low. At this point, the set terminal of the RS latch 2107 is at a low level "0" and the reset terminal is at a high level "1," causing the synchronous control signal OSC_CTL to go low. Therefore, in this embodiment, the inactive edge (e.g., the falling edge) of the synchronous control signal OSC_CTL is delayed by the first time relative to the inactive edge of the dimming control signal PWM_dim. In one embodiment, the first time is equal to one switching cycle, so that after the dimming control signal PWM_dim turns to a low level, the synchronization control signal OSC_CTL does not turn to a low level immediately, but waits until the clock signal CLK pulses for at least one more cycle before turning to a low level, so that the power conversion circuit 201 can replenish additional charge to the output capacitor Cout to ensure that when the dimming control signal PWM_dim turns high again, the voltage on the output capacitor Cout is sufficient.

[0071] For shorter dimmer switch on times (e.g. Figure 7In the time period t2-t3 in FIG, in one embodiment, the on-time of the dimmer switch is less than the minimum on-time set by the minimum on-time module 2108. For example, the on-time of the dimmer switch is less than one switching cycle. The rising edge process of the dimming control signal PWM_dim is the same as described above and will not be further described here. The only difference is that when the falling edge of the dimming control signal PWM_dim arrives, the count value of the minimum on-time module 2108 has not reached the cycle count value corresponding to the minimum on-time. Therefore, the minimum on-time signal Tmin is low, which causes the set and reset terminals of the RS latch 2107 to be low "0". Therefore, the output of the RS latch 2107 remains high "1". Only when the count value of the minimum on-time module 2108 reaches the set value and the minimum on-time signal Tmin becomes high does the synchronization control signal OSC_CTL go low. Through this setting, the effective level of the synchronization control signal OSC_CTL can always be greater than the minimum turn-on time, ensuring that the power conversion circuit 201 can work for at least 2 switching cycles each time it is turned on, so that the charge provided by the power conversion circuit 201 to the output capacitor Cout can meet the charge required to be consumed by the LED load during the dimming cycle.

[0072] Figure 8 The figure shows a simulation waveform diagram of the LED dimming system according to the embodiment of the present invention when the dimming switch changes from a longer on-time to a shorter on-time. Figure 8 FIG shows the simulated waveforms of the dimming control signal PWM_dim, the inductor current IL, the LED current ILED and the output voltage Vout. Figure 8 As shown, when the dimming switch suddenly switches from a longer on-time to a shorter on-time, the time during which the LED load draws current from the output capacitor Cout becomes very short during each dimming cycle. Therefore, if the power conversion circuit 201 is enabled during each dimming cycle, the output voltage Vout will be significantly increased. Therefore, to reduce output ripple, the LED dimming system of this embodiment of the present invention does not enable the power conversion circuit 201 during each dimming cycle. Instead, it adaptively skips some dimming cycles to achieve a balance between the charge drawn from the LED load on the output capacitor and the charge replenished by the power conversion circuit. This not only reduces output voltage ripple but also enables a higher dimming ratio. Furthermore, when the oscillator control circuit detects the need to replenish charge to the output capacitor, the LED dimming system of this embodiment can control the power conversion circuit to turn on without delay upon the rising edge of the dimming control signal PWM_dim, thereby beginning to build inductor current and replenish charge to the output capacitor.

[0073] Furthermore, when transitioning from a longer dimming switch on time to a shorter dimming switch on time, the LED dimming system will experience a longer adjustment time. During this process, the output of the error amplifier in the control circuit 202 will also slowly decrease, thereby gradually reducing the peak value of the inductor current, and ultimately stabilizing the output of the error amplifier at a suitable value, ensuring that the charge provided to the output capacitor by the power conversion circuit each time it is turned on is equal to the charge consumed by the LED load during the dimming cycle, thereby maintaining the output voltage of the circuit within a reasonable range and achieving a smaller output voltage ripple.

[0074] An embodiment of the present invention provides an LED dimming system and its control circuit based on a peak current mode control architecture. The control circuit controls the on and off of a clock signal according to a feedback signal of the output voltage of a power conversion circuit and a dimming control signal through an oscillator control circuit, thereby synchronizing the on-state of the power conversion circuit with the rising edge of the dimming control signal, thereby avoiding the problem of output voltage drop when the dimming switch is turned on and reducing the output ripple of the circuit.

[0075] The oscillator control circuit of the present invention also includes a minimum on-time module, which ensures the minimum on-time of the power conversion circuit each time, so that the power conversion circuit can provide sufficient charge to the output capacitor when the on-time of the dimming switch is short, so that the on-time of the dimming switch is no longer limited by the switching cycle of the power conversion circuit, which can significantly improve the dimming ratio of the circuit.

[0076] Furthermore, the LED dimming system of the embodiment of the present invention can also adaptively skip some dimming cycles when the on-time of the dimming switch is short, so that the power conversion circuit is not turned on in every dimming cycle, thereby avoiding the problem of the output voltage being raised due to the dimming cycle being too short, and then achieving a balance between the charge extracted by the LED load on the output capacitor and the charge supplemented by the power conversion circuit, which can effectively reduce the output ripple of the circuit at a high dimming ratio.

[0077] The embodiments of the present invention are described above, but these embodiments do not describe all details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and modify and use it based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A control circuit for an LED dimming system, wherein: The LED dimming system includes a power switch and a dimming switch, wherein the on and off switching of the dimming switch is controlled by a dimming control signal, wherein the control circuit includes: A feedback circuit, used for generating a feedback signal according to a current flowing through the LED load; An oscillator, configured to generate a clock signal, wherein the clock signal comprises a plurality of continuous pulses; a logic circuit for controlling the conduction of the power switch according to the clock signal, wherein the effective edges of adjacent pulses define a switching cycle; and An oscillator control circuit is used to receive the feedback signal and the dimming control signal, and when the feedback signal is less than a second reference voltage, provide a synchronization control signal to the oscillator according to the effective edge of the dimming control signal, and the oscillator generates a pulse of the clock signal according to the synchronization control signal to achieve synchronous opening of the load switch and the dimming switch.

2. The control circuit according to claim 1, wherein: When the feedback signal is less than the second reference voltage, the effective edge of the synchronization control signal is synchronized with the effective edge of the dimming control signal, and the invalid edge of the synchronization control signal is delayed by a first time relative to the invalid edge of the dimming control signal.

3. The control circuit according to claim 2, wherein: The first time is equal to one switching cycle.

4. The control circuit according to claim 2, wherein: The effective level time of the synchronous control signal is greater than / equal to the minimum on time, wherein the minimum on time is equal to M switching cycles, and M is an integer greater than 1.

5. The control circuit according to claim 1, wherein: Also includes: a peak current detection module, configured to compare the feedback signal with a first reference voltage to generate an error amplification signal, and to generate a peak current detection signal when a current detection signal representing an inductor current of the LED dimming system reaches the error amplification signal, The logic circuit is used to control the shutdown of the power switch in each switching cycle according to the peak current detection signal.

6. The control circuit according to claim 5, wherein: The second reference voltage is greater than the first reference voltage.

7. The control circuit according to claim 4, wherein: The oscillator control circuit comprises: A first RS latch, wherein a set terminal is used to receive the dimming control signal, a reset terminal is used to receive the clock signal, and an output terminal is used to generate a first trigger signal; A first comparator, wherein the non-inverting input terminal is used to receive the second reference voltage, the inverting input terminal is used to receive the feedback signal, and the output terminal is used to generate a first comparison signal; a unilateral delay unit, configured to delay an invalid edge of the first comparison signal by a second time to obtain a delayed signal, wherein the second time is greater than the first time; a first AND gate, configured to perform an AND logic operation on the first trigger signal and the delay signal to generate a second trigger signal; a minimum on-time module, configured to count the period of the clock signal at the start time of the synchronization control signal, and generate the minimum on-time signal after a preset time has elapsed, wherein the period count value of the clock signal within the preset time period represents the minimum on-time; and The second RS latch has a set terminal for receiving the second trigger signal, a reset terminal for receiving the minimum on-time signal, and an output terminal for providing the synchronization control signal.

8. The control circuit according to claim 7, wherein: The minimum opening time module includes: an OR gate, a first input terminal for receiving the clock signal, and a second input terminal for receiving the minimum on-time signal; and M cascaded D flip-flops, the data terminal and the negative output terminal of each D flip-flop are short-circuited, the reset terminal of each D flip-flop is used to receive the synchronization control signal, the clock terminal of the first D flip-flop among the M D flip-flops is connected to the output terminal of the OR gate, the clock terminals of the second to Mth D flip-flops among the M D flip-flops are connected to the negative output terminal of the previous D flip-flop, and the positive output terminal of the Mth D flip-flop among the multiple D flip-flops is used to provide the minimum turn-on time signal.

9. The control circuit according to claim 1, wherein: The oscillator comprises: A ramp generating module, used for generating a ramp signal; a second comparator, used for comparing the ramp signal with a reference voltage to generate a second comparison signal; A third RS latch, wherein the set terminal is used to receive the second comparison signal, the reset terminal is used to receive the inverted signal of the clock signal, and the output terminal is used to provide a third trigger signal; A second AND gate, configured to perform an AND logic operation on the third trigger signal and the synchronization control signal; and A single pulse module is used to generate the clock signal according to the output of the second AND gate.

10. The control circuit according to claim 9, wherein: The ramp generation module comprises: A first current source and a first capacitor connected in series between a power supply voltage and ground; and a first transistor, a first terminal connected to an intermediate node between the first current source and the first capacitor, a second terminal connected to ground, and a control terminal connected to an output of the second AND gate, The first transistor generates the ramp signal at an intermediate node between the first current source and the first capacitor by controlling the charging and discharging process of the first current source on the first capacitor.

11. The control circuit according to claim 5, wherein: The peak current detection module comprises: an error amplifier, wherein the inverting input terminal is used to receive the feedback signal, the non-inverting input terminal is used to receive the first reference voltage, and the output terminal is used to generate an error amplification signal; and The third comparator has an inverting input terminal for receiving the error amplification signal, a non-inverting input terminal for receiving the current detection signal, and an output terminal for generating the peak current detection signal, wherein the current detection signal is obtained through a sampling resistor connected to the power switch.

12. The control circuit according to claim 11, wherein: The peak current detection module also includes: a first switch connected between the output terminal of the error amplifier and the inverting input terminal of the first comparator, wherein the dimming control signal is used to control on and off switching of the first switch; and The second capacitor is connected between the inverting input terminal of the third comparator and the ground.

13. The control circuit according to claim 5, wherein: The logic circuit comprises: The fourth RS latch has a set end for receiving the clock signal, a reset end for receiving the peak current detection signal, and an output end for generating a drive control signal, wherein the drive control signal is used to control the on and off switching of the power switch.

14. An LED dimming system, comprising: A power conversion circuit, comprising at least one power switch, wherein the power conversion circuit is used to provide an output voltage to an LED load according to an input voltage; A dimming switch, used to be connected in series with the LED load; A dimming controller, used to generate a dimming control signal according to an external dimming signal, wherein the dimming control signal is used to control the on and off of the dimming switch; as well as The control circuit according to any one of claims 1 to 13, wherein the control circuit is used to generate a drive control signal, and the drive control signal is used to control the on and off of the at least one power switch.

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