Via hole optimization structure for high bandwidth and test board

Abstract

The invention relates to the field of test boards, in particular to a via hole optimization structure for high bandwidth and a test board. The via hole optimization structure for high bandwidth comprises a signal via hole and an accompanying ground hole which are arranged on a PCB (Printed Circuit Board), wherein the effective transmission path of the signal via hole is from the upper surface layer of the PCB to the wiring layer; the accompanying ground hole is located around the signal via hole and comprises an upper blind hole and a lower blind hole, and the center distance between the upper blind hole and the signal via hole is smaller than the center distance between the lower blind hole and the signal via hole; the upper blind hole extends from the upper surface layer to a reference layer of the PCB, the lower blind hole extends from the lower surface layer of the PCB to the reference layer, the reference layer is closer to the upper surface layer than the wiring layer, and the upper blind hole and the lower blind hole are electrically connected through a circuit of the reference layer. According to the invention, the problem of impedance continuity caused by overlarge distance between the ground hole and the signal via hole can be improved, so that the requirement of high-bandwidth via hole bandwidth can be met.

Description

Technical Field

[0001] The invention relates to the field of test boards, and in particular to a via optimization structure and a test board for high bandwidth. Background Art

[0002] The bandwidth of differential vias is a key parameter in electronic design. It usually refers to the effective frequency range that the differential signal can support when passing through the via. The bandwidth of the differential via determines whether the differential signal can maintain signal integrity and stability during high-speed transmission. In high-speed circuit design, the bandwidth of the differential via becomes a key factor affecting signal quality.

[0003] Impedance consistency is an important factor affecting bandwidth and needs to be paid special attention to. In ATE boards (test boards), chip connections, vias, and winding bulges are all impedance discontinuities. In the interconnection paths of multilayer boards, the impedance continuity of vias is of utmost importance, and due to the complexity of vias, they always require extra attention when optimizing the impedance consistency of high-speed paths (such as 224Gbps, etc.).

[0004] For high-speed vias, the pad size, anti-pad size in the via path, stub size, hole depth, aperture, differential pair spacing, etc. will affect the impedance of the differential via, causing resonance in the differential via insertion loss and affecting the bandwidth of the differential via.

[0005] The current test board faces the following problems:

[0006] (1) As the signal transmission rate increases, the margin for interconnection lines in the PCB design of the high-frequency bandwidth differential loopback circuit for ATE chip testing becomes smaller and smaller. Any impedance discontinuity in the path will deteriorate the signal transmission quality.

[0007] (2) More and more signal pins on chips need to meet the requirements of high-bandwidth application scenarios.

[0008] The above problems make it more difficult to optimize the impedance consistency of the differential interconnect paths of ATE boards used for high-speed chip testing, affecting the propagation quality of high-speed signals. Summary of the invention

[0009] The technical problem to be solved by the present invention is to overcome the defects of the prior art and provide an optimized via structure for high bandwidth, which can improve the impedance continuity problem introduced by the excessive distance between the ground hole and the signal via to meet the bandwidth requirements of the high bandwidth via.

[0010] In order to solve the above technical problems, the technical solution of the present invention is: a via optimization structure for high bandwidth, including a signal via and a concomitant ground via arranged on a PCB board; wherein,

[0011] The effective transmission path of the signal via is from the upper surface layer of the PCB board to the routing layer;

[0012] The accompanying hole is located around the signal via hole, including an upper blind hole and a lower blind hole, and the center distance between the upper blind hole and the signal via hole is smaller than the center distance between the lower blind hole and the signal via hole;

[0013] The upper blind via extends from the upper surface layer to the reference layer of the PCB board, and the lower blind via extends from the lower surface layer of the PCB board to the reference layer. The reference layer is closer to the upper surface layer than the routing layer. The upper blind via and the lower blind via are electrically connected through the circuit of the reference layer.

[0014] In order to further allow for more wiring in the circuit layer above the reference layer of the PCB board, the aperture of the upper blind hole is smaller than the aperture of the lower blind hole.

[0015] In order to further optimize impedance continuity without affecting the routing of the routing layer, the reference layer is an upper layer of the routing layer.

[0016] Furthermore, the signal vias are differential vias and are arranged in pairs.

[0017] Further, a single signal via is configured with at least two accompanying ground vias.

[0018] Furthermore, the axial directions of the upper blind hole, the lower blind hole and the signal via hole are respectively perpendicular to the PCB board.

[0019] Furthermore, the ring widths of the pad of the signal via and the pad of the accompanying ground via are respectively greater than or equal to 1 mil;

[0020] The apertures of the signal via hole and the accompanying ground hole are respectively greater than or equal to 2 mil;

[0021] The center distance between two adjacent signal vias and the center distance between adjacent upper blind vias and signal vias are respectively greater than or equal to 9.8 mils.

[0022] Furthermore, the center distance between the lower blind hole and the signal via hole is 0.65 mm, and the center distance between the upper blind hole and the signal via hole is 0.4 mm.

[0023] The invention also relates to a test board comprising a via optimized structure for high bandwidth.

[0024] After adopting the above technical scheme, the present invention arranges the accompanying ground hole into staggered upper blind holes and lower blind holes, the hole depth of the upper blind hole is controlled above the routing layer, and the upper blind hole is arranged at a position closer to the signal via hole, thereby lowering the impedance, optimizing the continuity of the signal via impedance, optimizing the return loss, optimizing the insertion loss resonant bandwidth, and improving the propagation quality of high-speed signals. In addition, the integrity of the routing layer and the routing layers below the routing layer can be ensured, and the impact on the inner fan-out line can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A top view of a conventional via structure used for high bandwidth;

[0026] Figure 2 for Figure 1 AA section view;

[0027] Figure 3 This is a schematic diagram of the structure of a traditional via structure used for high bandwidth, where only the routing layer is retained on the PCB;

[0028] Figure 4 A top view of a via optimization structure for high bandwidth according to the present invention;

[0029] Figure 5 for Figure 4 BB cross-sectional view;

[0030] Figure 6 This is a schematic diagram of the structure of the via optimization structure for high bandwidth of the present invention in which only the routing layer is retained on the PCB;

[0031] Figure 7 It is a comparison diagram of impedance curves of the embodiment of the present invention and the comparative example;

[0032] Figure 8 It is a comparison diagram of return loss curves of the embodiment of the present invention and the comparative example;

[0033] Fig. 9 It is a comparison diagram of insertion loss curves of the embodiment of the present invention and the comparative example;

[0034] In the figure, 1, signal via; 2, accompanying ground via; 21, upper blind via; 22, lower blind via; 3, upper surface layer; 4, routing layer; 5, reference layer; 6, lower surface layer; 7, pad. DETAILED DESCRIPTION

[0035] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments in conjunction with the accompanying drawings.

[0036] like Figure 4 , Figure 5 and Figure 6As shown, a via optimization structure for high bandwidth includes a signal via 1 and a ground via 2 arranged on a PCB board; wherein,

[0037] The effective transmission path of the signal via 1 is from the upper surface layer 3 to the routing layer 4 of the PCB board;

[0038] The accompanying hole 2 is located around the signal via 1, including an upper blind hole 21 and a lower blind hole 22, and the center distance between the upper blind hole 21 and the signal via 1 is smaller than the center distance between the lower blind hole 22 and the signal via 1;

[0039] The upper blind via 21 extends from the upper surface layer 3 to the reference layer 5 of the PCB board, and the lower blind via 22 extends from the lower surface layer 6 of the PCB board to the reference layer 5. The reference layer 5 is closer to the upper surface layer 3 than the routing layer 4. The upper blind via 21 and the lower blind via 22 are electrically connected through the line of the reference layer 5.

[0040] For conventional ATE boards, signal vias 1 and accompanying ground vias 2 are directly punched and fanned out with reference to the chip arrangement. Accompanying ground vias 2 are through-holes, and signal vias 1 are back-drilled or blind-holes to achieve the connection between each signal in the chip pin and the corresponding signal in the PCB. From the perspective of the traditional conventional structure, the chip signal arrangement fan-out is followed to perfectly match the chip pin with the signal in the PCB, that is, the pitch between signal vias 1 and the pitch between signal vias 1 and accompanying ground vias 2 are arranged completely according to the chip signal spacing. The effective transmission path of signal via 1 is from the upper surface layer 3 of the PCB board to the routing layer 4. In order not to affect the routing of the circuit layers below the routing layer 4, the accompanying ground vias 2 can only be set at a position far away from the signal via 1. For details, see Figure 1 , Figure 2 and Figure 3 This condition results in excessive impedance, which results in low insertion loss bandwidth.

[0041] In this embodiment, the accompanying ground hole 2 is set to be an upper blind hole 21 and a lower blind hole 22 that are staggered. The hole depth of the upper blind hole 21 is controlled above the routing layer 4. Therefore, the upper blind hole 21 can be set to a position closer to the signal via 1, thereby lowering the impedance, optimizing the impedance continuity, and improving the propagation quality of high-speed signals. The specific adjustment position can be determined by simulation, and the integrity of the routing layer 4 and the routing layers below the routing layer 4 can also be guaranteed, reducing the impact on the inner layer fan-out line. In addition, in order to ensure the normal fan-out of the chip, the signal via 1 can use the chip pinmap to fan out normally, and the pad 7 of the accompanying ground hole 2 can also use the chip pinmap arrangement to fan out normally, and be connected to the upper blind hole 21 through metals such as copper. In order not to affect the routing space of each channel of the chip and to facilitate the differential signal output, the lower blind hole 22 can continue to refer to the chip pinmap fan-out.

[0042] It should be noted that the high bandwidth in this embodiment refers to above 70 GHz.

[0043] In one embodiment, the diameter of the upper blind hole 21 is smaller than the diameter of the lower blind hole 22 .

[0044] Specifically, the conventional accompanying hole 2 is a through hole, and the drilling is relatively deep. In order to meet the drilling depth, the diameter of the drill bit is relatively large. In this embodiment, the upper blind hole 21 and the lower blind hole 22 do not penetrate the PCB board, and the hole depth is relatively small, so a drill bit with a smaller diameter can be used to obtain a hole with a smaller aperture. The distance between the upper blind hole 21 and the signal via 1 is the key to controlling the signal performance. If the aperture of the upper blind hole 21 is set smaller, the upper blind hole 21 can be closer to the signal via 1, and the optimal position can be confirmed through simulation within a larger range, thereby better reducing the impedance, optimizing the impedance continuity of the signal via 1, and improving the performance. In addition, it can also have a larger wiring space, lay more wires, and play a role in optimizing the space.

[0045] In one embodiment, the reference layer 5 is an upper layer of the routing layer 4 .

[0046] In this way, the upper blind via 21 can be made as deep as possible without affecting the routing layer 4 and the routing layers below the routing layer 4, thereby better improving the performance.

[0047] In one embodiment, Figure 4 and Figure 6 As shown, signal vias 1 are differential vias, which are arranged in pairs.

[0048] In one embodiment, Figure 4 , Figure 5 and Figure 6 As shown, a single signal via 1 is configured with at least two accompanying ground vias 2 .

[0049] In one embodiment, Figure 4 , Figure 5 and Figure 6 As shown, the axes of the upper blind hole 21, the lower blind hole 22 and the signal via 1 are respectively perpendicular to the PCB board.

[0050] In one embodiment, the ring widths of the pad 7 of the signal via 1 and the pad 7 of the accompanying via 2 are respectively greater than or equal to 1 mil;

[0051] The aperture of the signal via 1 and the aperture of the accompanying via 2 are both greater than or equal to 2 mil;

[0052] The center distance between two adjacent signal vias 1 and the center distance between the adjacent upper blind via 21 and the signal via 1 are both greater than or equal to 9.8 mil.

[0053] In one embodiment, the center distance between the lower blind hole 22 and the signal via 1 is 0.65 mm, and the center distance between the upper blind hole 21 and the signal via 1 is 0.4 mm. This data is the preferred data obtained through simulation.

[0054] In one embodiment, a test board includes the via optimization structure for high bandwidth in any of the above embodiments.

[0055] In the following, in combination with specific embodiments and comparative examples, the optimized via structure for high bandwidth involved in the above embodiments and the conventional via structure (such as the via structure mentioned in the background art) are compared. Figure 1 , Figure 2 and Figure 3 The via structure shown is compared with the comparative example.

[0056] Example: Figure 4 , Figure 5 and Figure 6 As shown, the PCB board has ten metal layers, and the adjacent metal layers are separated by dielectric layers. From top to bottom, the first layer is the upper surface layer 3, the fifth layer is the reference layer 5, the sixth layer is the routing layer 4, and the tenth layer is the lower surface layer 6. The two signal vias 1 (differential vias) are surrounded by ten accompanying ground holes 2. In each accompanying ground hole 2, the center distance between the lower blind hole 22 and the corresponding signal via 1 is 0.65mm, and the center distance between the upper blind hole 21 and the corresponding signal via 1 is 0.4mm. The apertures of the signal via 1, the upper blind hole 21, and the lower blind hole 22 are all 5.1mil, and the diameter of the pad 7 is 13.87mil.

[0057] Comparative example: Figure 1 , Figure 2 and Figure 3 As shown, the PCB board has ten metal layers, and the adjacent metal layers are separated by dielectric layers. The periphery of two signal vias 1 (differential vias) is surrounded by ten accompanying ground holes 2, each of which runs through the entire PCB board, and the center distance between each accompanying ground hole 2 and the corresponding signal via 1 is 0.65mm. The apertures of the signal vias 1 and the accompanying ground holes 2 are both 5.1mil, and the diameter of the pad 7 is 13.87mil.

[0058] The performance comparison between the embodiment and the comparative example is as follows: Figure 7 , Figure 8 and Fig. 9 shown.

[0059] Figure 7 : is a comparison diagram of impedance curves of the embodiment and the comparative example (the solid line represents the embodiment, and the dotted line represents the comparative example). In the comparative example, the maximum impedance of the signal via 1 is 94.75Ω, but the impedance of the signal via 1 of the embodiment is reduced to 91Ω.

[0060] Figure 8It is a comparison diagram of the return loss curves of the embodiment and the comparative example (the solid line represents the embodiment, and the dotted line represents the comparative example). In the comparative example, at a frequency of 60 GHz, the return loss can reach below -20 dB, while in the embodiment, by adjusting the position of the upper blind hole 21 of the accompanying ground hole 2 from the signal via 1, the frequency can be increased to 77.96 GHz, and the return loss can still reach below -20 dB.

[0061] Fig. 9 : is a comparison diagram of insertion loss curves of the embodiment and the comparative example (the solid line represents the embodiment, and the dotted line represents the comparative example). In the comparative example, the insertion loss will have obvious resonance at 86.8 GHz, while the insertion loss resonance point is increased to 99.9 GHz in the embodiment.

[0062] In summary, compared with the comparative example, the embodiment can optimize the impedance continuity of the signal via 1, thereby optimizing the return loss and the insertion loss resonance bandwidth.

[0063] Based on the above ideal embodiments of the present invention, the relevant staff can make various changes and modifications without departing from the technical concept of the present invention through the above description. The technical scope of the present invention is not limited to the contents of the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A via optimization structure for high bandwidth, characterized in that: It comprises a signal via hole (1) and a corresponding ground hole (2) arranged on a PCB board; wherein: The effective transmission path of the signal via (1) is from the upper surface layer (3) of the PCB board to the wiring layer (4); The accompanying hole (2) is located around the signal via (1), and includes an upper blind hole (21) and a lower blind hole (22), and the center distance between the upper blind hole (21) and the signal via (1) is smaller than the center distance between the lower blind hole (22) and the signal via (1); The upper blind hole (21) extends from the upper surface layer (3) to the reference layer (5) of the PCB board, and the lower blind hole (22) extends from the lower surface layer (6) of the PCB board to the reference layer (5); the reference layer (5) is closer to the upper surface layer (3) than the routing layer (4); and the upper blind hole (21) and the lower blind hole (22) are electrically connected via a circuit of the reference layer (5).

2. The via optimization structure for high bandwidth according to claim 1, characterized in that: The aperture of the upper blind hole (21) is smaller than the aperture of the lower blind hole (22).

3. The via optimization structure for high bandwidth according to claim 1, characterized in that: The reference layer (5) is an upper layer of the routing layer (4).

4. The via optimization structure for high bandwidth according to claim 1, characterized in that: The signal vias (1) are differential vias and are arranged in pairs.

5. The via optimization structure for high bandwidth according to claim 1, characterized in that: A single signal via (1) is provided with at least two accompanying ground vias (2).

6. The via optimization structure for high bandwidth according to claim 1, characterized in that: The axial directions of the upper blind hole (21), the lower blind hole (22) and the signal via hole (1) are respectively perpendicular to the PCB board.

7. The via optimization structure for high bandwidth according to claim 1, characterized in that: The ring widths of the pad (7) of the signal via (1) and the pad (7) of the accompanying via (2) are respectively greater than or equal to 1 mil; The apertures of the signal via hole (1) and the accompanying via hole (2) are respectively greater than or equal to 2 mil; The center distance between two adjacent signal vias (1) and the center distance between adjacent upper blind holes (21) and signal vias (1) are respectively greater than or equal to 9.8 mil.

8. The via optimization structure for high bandwidth according to claim 7, characterized in that: The center distance between the lower blind hole (22) and the signal via hole (1) is 0.65 mm, and the center distance between the upper blind hole (21) and the signal via hole (1) is 0.4 mm.

9. A test board, characterized in that: The invention comprises a via optimization structure for high bandwidth as described in any one of claims 1 to 8.

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