Nonvolatile memory cell and manufacturing method thereof
By forming specific floating gate layer, dielectric layer and gate layer structures on the semiconductor substrate, the voltage stress problem of memory cells is solved, the reliability and performance of the memory is improved, and the manufacturing process is simplified.
Patent Information
- Application Number
- CN202411267702.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-12
- Filing Date
- 2024-09-11
- Publication Date
- 2025-03-25
AI Technical Summary
When manufacturing nonvolatile memory, the prior art is difficult to effectively solve the voltage stress problem of memory cells, affecting the reliability and performance of the memory.
Using a nonvolatile memory cell manufacturing method, by forming a specific structure on a semiconductor substrate, including a floating gate layer, a dielectric layer and a gate layer, the floating gate layer is ensured to be completely surrounded, and the electrical characteristics of the memory cell are optimized through the overlap of part of the gate layer and the floating gate layer.
This method effectively improves the voltage stress capability of memory cells, enhances the reliability and performance of memory, and can simultaneously produce peripheral circuits and memory cell arrays, simplifying the manufacturing process.
Smart Images
Figure CN119697992A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a memory cell and a manufacturing method thereof, and more particularly to a nonvolatile memory cell and a manufacturing method thereof. Background Art
[0002] As we all know, non-volatile memory can still save data after the power is lost. Therefore, non-volatile memory has been widely used in electronic products. Generally speaking, non-volatile memory includes peripheral circuits and memory cell arrays, and the peripheral circuits and memory cell arrays are made on the same semiconductor substrate. For example, the peripheral circuit includes: bit line driver, word line driver, source line driver and control unit, etc. The memory cell array is composed of multiple non-volatile memory cells.
[0003] When manufacturing non-volatile memory, designers divide the layout area of the semiconductor substrate into a logic device area and a memory device area. The components manufactured in the logic device area can form the peripheral circuit of the non-volatile memory, and the components manufactured in the memory device area can form a memory cell array.
[0004] Generally, the devices in the logic device area can be further divided into input / output devices (IO devices, referred to as IO devices) and core devices. The devices in the memory device area are memory cells.
[0005] Furthermore, core components can be called low voltage devices (LV components), such as low voltage P-type transistors (LV P-type transistors) and low voltage N-type transistors (LV N-type transistors). Input and output components can be called high voltage devices (HV components), such as high voltage P-type transistors (HVP-type transistors) and high voltage N-type transistors (HV N-type transistors). Among them, low voltage components can withstand lower voltage stress, and high voltage components can withstand higher voltage stress. Summary of the invention
[0006] The present invention is a non-volatile memory cell, comprising: a semiconductor substrate; a well region formed on the semiconductor substrate; a first dielectric layer, the first dielectric layer is in contact with the surface of the well region; a floating gate layer, covering the first dielectric layer; a second dielectric layer, the second dielectric layer is in contact with the surface of the well region, and the second dielectric layer is in contact with the sidewall and the top of the floating gate layer, wherein the floating gate layer is completely surrounded by the first dielectric layer and the second dielectric layer; a first gate layer and a second gate layer, the first gate layer and the second gate layer are formed on the second dielectric layer, wherein the first gate layer and the second gate layer are respectively located on two sides of the floating gate layer, and the first gate layer is in contact with the sidewall of the floating gate layer. The invention relates to a first well region, a second well region, a second dielectric layer on the well region surface and the floating gate layer; the second gate layer contacts the second dielectric layer on the sidewall of the floating gate layer; and a portion of the first gate layer and the floating gate layer overlap each other; a first doped region and a second doped region, the first doped region and the second doped region are located in the surface of the well region, wherein the first gate layer, the second gate layer and the floating gate layer are located above the surface of the well region between the first doped region and the second doped region; a first connecting line electrically connected to the first doped region; a second connecting line electrically connected to the first gate layer; a third connecting line electrically connected to the second doped region; and a fourth connecting line electrically connected to the second doped region.
[0007] The present invention is a method for manufacturing a non-volatile memory cell, comprising the following steps: (A) forming a first dielectric layer on the surface of a semiconductor substrate; (B) forming a floating gate layer covering the first dielectric layer; (C) forming a second dielectric layer on the surface of the semiconductor substrate; wherein the second dielectric layer contacts the sidewall and the top of the floating gate layer, and the floating gate layer is completely surrounded by the first dielectric layer and the second dielectric layer; (D) forming a first gate layer on the second dielectric layer; wherein the first gate layer contacts the sidewall and the top of the floating gate layer. (E) forming a second gate layer on the second dielectric layer; wherein the second gate layer contacts the second dielectric layer at the sidewall of the floating gate layer, and the first gate layer and the second gate layer are respectively located on two sides of the floating gate layer; wherein the semiconductor substrate includes a well region, and the well region includes a first doped region and a second doped region below the surface, and the first gate layer, the second gate layer and the floating gate layer are located above the surface of the well region between the first doped region and the second doped region.
[0008] In order to better understand the above and other aspects of the present invention, preferred embodiments are specifically described below with reference to the accompanying drawings for detailed description as follows: BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figures 1A to 1J is a flow chart of a method for manufacturing a memory cell according to a first embodiment of the present invention;
[0010] Figure 2A For the first embodiment of the memory cell Cell 1 Schematic diagram of performing programming actions;
[0011] Figure 2B For the first embodiment of the memory cell Cell 1 、Cell 2 Schematic diagram of performing an erasing action;
[0012] Figure 2C For the first embodiment of the memory cell Cell 1 A schematic diagram of performing a reading action;
[0013] Figure 2D For the first embodiment of the memory cell Cell 2 A schematic diagram of performing a reading action;
[0014] FIG. 3A to FIG. 3E is a flow chart of a method for manufacturing a memory cell according to a second embodiment of the present invention;
[0015] FIG. 4A to FIG. 4D is a flow chart of a method for manufacturing a memory cell according to a third embodiment of the present invention;
[0016] FIG. 5A to FIG. 5C is a flow chart of a method for manufacturing a memory cell according to a fourth embodiment of the present invention;
[0017] 6A to 6H is a flow chart of a method for manufacturing a memory cell according to a fifth embodiment of the present invention;
[0018] 7A to 7E is a flow chart of a method for manufacturing a memory cell according to a sixth embodiment of the present invention;
[0019] FIG. 8A to FIG. 8E is a flow chart of a method for manufacturing a memory cell according to a seventh embodiment of the present invention; and
[0020] 9A to 9E FIG. 4 is a flow chart of a method for manufacturing a memory cell according to an eighth embodiment of the present invention.
[0021]
Explanation of symbols
[0022] 102, 103, 104, 105, 106, 107, 502, 503, 504, 505, 506, 507, 602, 603, 604, 605, 606, 607, 702, 703, 704, 705, 706, 707, 802, 803, 804, 805, 806, 807, 902, 903, 904, 905, 906, 907: Isolation structure
[0023] 111, 111a, 111b, 311, 311a, 311b, 511, 511a, 511b, 611, 611a, 611b, 711, 711a, 711b, 811, 811a, 811b, 911, 911a, 911b: floating gate dielectric layer
[0024] 112, 112a, 112b, 312, 312a, 312b, 512, 512a, 512b, 612, 612a, 612b, 712, 712a, 712b, 812, 812a, 812b, 912, 912a, 912b: floating gate layer
[0025] 117, 122, 132, 412, 517, 817, 818: Photoresist layer
[0026] 120, 320, 420, 620, 720: input and output gate dielectric layer
[0027] 124, 324, 424: core gate dielectric layer
[0028] 130, 130a, 130b, 130c, 130d, 130e 130f, 130g, 130h, 330a, 330b, 330c, 330d, 630a, 630b, 630c, 630d, 730a, 730b, 730c, 730d: gate layer
[0029] 136a, 136b, 136c, 136d, 136e, 136f, 136g, 136h, 336a, 336b, 336c, 336d, 636a, 636b, 636c, 636d, 736a, 736b, 736c, 736d: spacer
[0030] 139: Metal silicide layer
[0031] 141, 142, 143, 145, 148: p-doped regions
[0032] 144, 147: n-doped region
[0033] 151,152,153,154,155,156,161,162,163,164,165,166,171,172,173,174,175,176,177,371,372,373,374,375,376,377,671,672,673,674,675,676,677,771,772,773,774,775,776,777: connecting line
[0034] 180: Interlayer dielectric layer
[0035] 313, 613, 713, 813, 913: Silicon nitride layer
[0036] 321, 322, 622, 622a, 622b, 921, 922: protruding dielectric layer
[0037] 415, 416, 417: p-type lightly doped drain region
[0038] 623, 623a, 623b3: Silicon dioxide layer
[0039] 625, 626: Residual dielectric layer DETAILED DESCRIPTION
[0040] The present invention discloses a method for manufacturing a non-volatile memory cell. This method can simultaneously manufacture a core device, an IO device, and a non-volatile memory cell on a semiconductor substrate. That is, after utilizing the manufacturing process method disclosed in the present invention, all the components required for the peripheral circuit and the memory cell array can be manufactured on a semiconductor substrate to form a non-volatile memory. The non-volatile memory cell is referred to as a memory cell hereinafter.
[0041] Please refer to Figures 1A to 1J , which is a flow chart of a method for manufacturing a memory cell according to a first embodiment of the present invention.
[0042] like Figure 1A As shown, an isolation structure formation process is performed. First, a plurality of isolation structures 102 to 107 are formed in the semiconductor substrate Psub. The semiconductor substrate Psub is a P-type substrate, and the isolation structures 102 to 107 are shallow trench isolation structures (STI structures for short).
[0043] like Figure 1A As shown, on the surface of the semiconductor substrate Psub, the area between the isolation structure 102 and the isolation structure 106 is the logic device area, and the area between the isolation structure 106 and the isolation structure 107 is the memory device area. The elements manufactured in the logic device area can form a peripheral circuit of a non-volatile memory. The elements manufactured in the memory device area are memory cells, and can form a memory cell array.
[0044] Furthermore, the logic component area can be further divided into the input and output component area and the core component area. Figure 1A As shown, the area between the isolation structure 104 and the isolation structure 106 is the IO device area, and the area between the isolation structure 102 and the isolation structure 104 is the core device area. The IO device includes a high voltage P-type transistor (HV P-type transistor) and a high voltage N-type transistor (HV N-type transistor). The core device includes a low voltage P-type transistor (LV P-type transistor) and a low voltage N-type transistor (LV N-type transistor).
[0045] In this embodiment, a high voltage N-type transistor (HV N-type transistor) is fabricated between the isolation structure 105 and the isolation structure 106, a high voltage P-type transistor (HV P-type transistor) is fabricated between the isolation structure 104 and the isolation structure 105, a low voltage N-type transistor (LV N-type transistor) is fabricated between the isolation structure 103 and the isolation structure 104, and a low voltage P-type transistor (LV P-type transistor) is fabricated between the isolation structure 102 and the isolation structure 103.
[0046] Next, multiple well formation processes are performed. By using ion implantation process, an N-type well region (N-well) NW1 is formed below the surface of the semiconductor substrate Psub in the memory element region, and N-type well regions NW2, NW3 and P-type well regions (P-well) PW1, PW2 are formed below the surface of the semiconductor substrate Psub in the logic element region.
[0047] like Figure 1A As shown, the N-type well region NW1 is formed between the isolation structure 106 and the isolation structure 107. The N-type well region NW2 is formed between the isolation structure 104 and the isolation structure 105. The P-type well region PW1 is formed between the isolation structure 105 and the isolation structure 106. The N-type well region NW3 is formed between the isolation structure 102 and the isolation structure 103. The P-type well region PW2 is formed between the isolation structure 103 and the isolation structure 104.
[0048] like Figure 1B As shown, a floating gate dielectric layer 111 and a floating gate layer 112 are formed on the surface of the semiconductor substrate Psub. Then, a photoresist layer 117 is formed in the memory element region to cover a portion of the floating gate dielectric layer 111. For example, the floating gate dielectric layer is silicon oxide, and the floating gate layer 112 is made of polysilicon.
[0049] In this embodiment, before the well region forming process, a sacrificial oxide layer (not shown) may be formed on the surface of the semiconductor substrate Psub. After the well region forming process, the sacrificial oxide layer on the surface of the semiconductor substrate Psub is removed. Figure 1B The floating gate dielectric layer 111 and the floating gate layer 112 are shown.
[0050] like Figure 1C As shown, an etching process is performed to remove the floating gate dielectric layer 111 and the floating gate layer 112 that are not covered by the photoresist layer 117. After removing the photoresist layer 117, as shown in FIG. Figure 1C As shown, the remaining floating gate layers 112a and 112b are respectively used as floating gates of two memory cells.
[0051] like Figure 1D As shown, an IO gate dielectric layer 120 is formed, and the IO gate dielectric layer 120 is formed on the exposed surface of the semiconductor substrate Psub, and is formed on the sidewalls and the top of the floating gate layers 112a and 112b. Therefore, the floating gate layer 112a is completely surrounded by the floating gate dielectric layer 111a and the IO gate dielectric layer 120, and the floating gate layer 112b is completely surrounded by the floating gate dielectric layer 111b and the IO gate dielectric layer 120. For example, the IO gate dielectric layer 120 is silicon dioxide.
[0052] like Figure 1E As shown, a photoresist layer 122 is formed to cover the memory device region and the input / output device region. Next, an etching process is performed to remove the input / output gate dielectric layer 120 on the surface of the semiconductor substrate Psub in the core device region.
[0053] like Figure 1F As shown, the photoresist layer 122 is removed, and a core gate dielectric layer 124 is formed on the surface of the semiconductor substrate Psub in the core device area, and the input and output gate dielectric layer 120 is slightly thickened. The thickness of the core gate dielectric layer 124 is less than the thickness of the input and output gate dielectric layer 120.
[0054] Next, a gate structure formation process and a doping process are performed, wherein the gate structure formation process and the doping process are compatible with the CMOS process and are briefly described below.
[0055] like Figure 1G As shown, a gate layer 130 is formed to cover the logic element region and the memory element region. That is, the gate layer 130 covers the input / output gate dielectric layer 120 and the core gate dielectric layer 124. Next, a photoresist layer 132 is formed on the gate layer 130 to cover a portion of the gate layer 130. For example, the material of the gate layer 130 may be polysilicon.
[0056] like Figure 1H As shown, an etching process is performed to remove the gate layer 130 not covered by the photoresist layer 132. Then, the photoresist layer 132 is removed. Therefore, gate layers 130a, 130b, 130c, and 130d are formed in the memory device region, gate layers 130e and 130f are formed in the input / output device region, and gate layers 130g and 130h are formed in the core device region.
[0057] In the memory element region, gate layers 130a and 130b are formed on the input / output gate dielectric layer 120 and are respectively located on two sides of the floating gate layer 112a. The gate layer 130a contacts the input / output gate dielectric layer 120 on the sidewall and a portion of the upper surface of the floating gate layer 112a. In other words, a portion of the gate layer 130a overlaps with the floating gate layer 112a. In addition, the gate layer 130b at least contacts the input / output gate dielectric layer 120 on the sidewall of the floating gate layer 112a. Of course, the gate layer 130b may also slightly overlap with the floating gate layer 112a. Similarly, a portion of the gate layer 130c overlaps with the floating gate layer 112b, and the gate layer 130d at least contacts the input / output gate dielectric layer 120 on the sidewall of the floating gate layer 112b.
[0058] Afterwards, if Fig. 1I As shown, in the input / output device region, the sidewalls of the gate layers 130e and 130f form spacers 136e and 136f, respectively. In the core device region, the sidewalls of the gate layers 130g and 130h form spacers 136g and 136h, respectively. In the memory device region, the sidewalls of the gate layers 130a, 130b, 130c, and 130d form spacers 136a, 136b, 136c, and 136d. In addition, in the process of forming the spacers 136a to 136h, the input / output gate dielectric layer 120 and the core gate dielectric layer 124 exposed on the semiconductor substrate Psub are also etched and removed, and the surface of the semiconductor substrate Psub is exposed.
[0059] After multiple doping processes, in the input / output device region, two n-doped regions 144 are formed in the P-type well region PW1 and are located on both sides of the gate layer 130e, and two p-doped regions 145 are formed in the N-type well region NW2 and are located on both sides of the gate layer 130f. Furthermore, in the core device region, two n-doped regions 147 are formed in the P-type well region PW2 and are located on both sides of the gate layer 130g, and two p-doped regions 148 are formed in the N-type well region NW3 and are located on both sides of the gate layer 130h. In addition, in the memory device region, three p-doped regions 141, 142, and 143 are formed in the N-type well region NW1. The p-doped region 143 is formed on one side of the gate layer 130a, the p-doped region 141 is formed on one side of the gate layer 130c, the p-doped region 142 is formed on one side of the gate layer 130b, and the p-doped region 142 is formed on one side of the gate layer 130d. That is, the p-doped region 142 is formed between the gate layer 130b and the gate layer 130d.
[0060] Basically, the doping process is performed multiple times before and after forming the spacers 136a-136h, and the doping process includes: a lightly doped drain process (LDD process for short) and / or a halo implantation process, etc. In other words, the doping regions 141-148 may selectively include a lightly doped drain region (LDD region) and / or a halo region.
[0061] A metal silicide layer 139 is formed on the exposed surfaces of the p-doped regions 141 to 143 , 148 , and 145 , the exposed surfaces of the n-doped regions 144 and 147 , and the exposed surfaces of the gate layers 130 a to 130 h .
[0062] like Figure 1J As shown, a conducting line process is performed. First, an interlayer dielectric (ILD) layer 180 is formed to cover the surface of the semiconductor substrate Psub, the gate layers 130a-130h and the spacers 136a-136h. Next, a plurality of contact holes are formed in the ILD layer 180 and filled with conductive materials as connecting lines 151-156, 161-166, 171-177.
[0063] Among them, the conducting lines 171, 174, and 177 are respectively in contact with the metal silicide layer 139 on the surfaces of the three p-doped regions 143, 142, and 141, the conducting line 172 is in contact with the metal silicide layer 139 on the surface of the gate layer 130a, the conducting line 173 is in contact with the metal silicide layer 139 on the surface of the gate layer 130b, the conducting line 175 is in contact with the metal silicide layer 139 on the surface of the gate layer 130d, and the conducting line 176 is in contact with the metal silicide layer 139 on the surface of the gate layer 130c. In other words, the conducting lines 171, 174, and 177 are respectively electrically connected to the three p-doped regions 143, 142, and 141, and the conducting lines 172, 173, 175, and 176 are respectively connected to the four gate layers 130a, 130b, 130d, and 130c.
[0064] Similarly, the connection lines 151, 153, 161, 163 are electrically connected to the four p-doped regions 148, 145 respectively, the connection lines 154, 156, 164, 166 are electrically connected to the four n-doped regions 147, 144 respectively, and the connection lines 152, 155, 162, 165 are electrically connected to the four gate layers 130h, 130g, 130f, 130e respectively.
[0065] like Figure 1J As shown, the P-type well region PW1, the two n-doped regions 144 and the gate layer 130e form a high-voltage N-type transistor M N_HV The N-type well region NW2, the two p-doped regions 145 and the gate layer 130f form a high-voltage P-type transistor M P_HV The P-type well region PW2, the two n-doped regions 147 and the gate layer 130g form a low-voltage N-type transistor M N_LV The N-type well region NW3, the two p-doped regions 148 and the gate layer 130h form a low-voltage P-type transistor M P_LV The N-type well region NW1, the two p-doped regions 142, 143, the floating gate layer 112a and the gate layers 130a, 130b form a memory cell. 1 The N-type well region NW1, the two p-doped regions 141, 142, the floating gate layer 112b and the gate layers 130c, 130d form another memory cell Cell. 2 .
[0066] In the storage cell 1In the embodiment, the floating gate dielectric layer 111a contacts the surface of the N-type well region NW1, and the floating gate layer 112a covers the floating gate dielectric layer 111a. In addition, the input / output gate dielectric layer 120 covers the surface of the N-type well region NW1 and the floating gate layer 112a. The gate layers 130a and 130b are located on the input / output gate dielectric layer 120. The gate layer 130a contacts the sidewall of the floating gate layer 112a and the input / output gate dielectric layer 120 thereon. The gate layer 130b contacts the input / output gate dielectric layer 120 on the sidewall of the floating gate layer 112a. Furthermore, the p-doped regions 142 and 143 are formed below the surface of the N-type well region NW1, and the floating gate layer 112a, the gate layers 130a and 130b are located above the surface of the N-type well region NW1 between the two p-doped regions 142 and 143. The connection line 171 is electrically connected to the p-doped region 143 , the connection line 172 is electrically connected to the gate layer 130 a , the connection line 173 is electrically connected to the gate layer 130 b , and the connection line 174 is electrically connected to the p-doped region 142 .
[0067] Similarly, in the storage cell 2 In the embodiment, the floating gate dielectric layer 111b contacts the surface of the N-type well region NW1, and the floating gate layer 112b covers the floating gate dielectric layer 111b. In addition, the input / output gate dielectric layer 120 covers the surface of the N-type well region NW1 and the floating gate layer 112b. The gate layers 130c and 130d are located on the input / output gate dielectric layer 120. The gate layer 130c contacts the sidewall of the floating gate layer 112b and the input / output gate dielectric layer 120 thereon. The gate layer 130d contacts the input / output gate dielectric layer 120 on the sidewall of the floating gate layer 112b. Furthermore, the p-doped regions 141 and 142 are formed below the surface of the N-type well region NW1, and the floating gate layer 112b, the gate layers 130c and 130d are located above the surface of the N-type well region NW1 between the two p-doped regions 141 and 142. The connection line 177 is electrically connected to the p-doped region 141, the connection line 176 is electrically connected to the gate layer 130c, the connection line 175 is electrically connected to the gate layer 130d, and the connection line 174 is electrically connected to the p-doped region 142. In addition, the connection line 171 can be used as a bit line BL 1 , the connection line 177 can be used as the bit line BL 2 , the connection line 174 can be used as the source line SL, the connection lines 172 and 176 can be used as the erase line EL, and the connection line 173 can be used as the word line WL 1 , the connection line 175 can be used as a word line WL 2 .
[0068] Please refer to Figure 2A , which illustrates the memory cell Cell of the first embodiment 1 Schematic diagram of programming action. Please refer to Figure 2B, which illustrates the memory cell Cell of the first embodiment 1 、Cell 2 Schematic diagram of the erase operation. Please refer to Figure 2C , which illustrates the memory cell Cell of the first embodiment 1 Schematic diagram of reading operation. Figure 2D , which illustrates the memory cell Cell of the first embodiment 2 Schematic diagram of the reading operation.
[0069] like Figure 2A As shown, the storage cell 1 Perform programming actions without changing the Cell 2 When programming, a turn-on voltage (V ON ) to word line WL 1 , turn off the transformer (off voltage, V OFF ) to word line WL 2 、Program voltage (V PP ) to the source line SL, ground voltage (0V) to the bit line BL 1 BL 2 , the first erase line voltage (eraseline voltage, V EL1 ) to the erase line EL. Furthermore, a programming voltage V PP To the N-type well region NW1. For example, the turn-on voltage V ON 0V~V PP / 2, turn off voltage V OFF V PP , programming voltage V PP is 7V, the first erase line voltage V EL1 Greater than or equal to the ground voltage (0V), for example, the first erase line voltage V EL1 Between 0V and V PP Of course, during the programming process, the first erase line voltage V EL1 It can also be increased gradually, for example, from 0V to V PP (7V).
[0070] like Figure 2A As shown, in the memory cell 1 In the case of bit line WL 1 The opening voltage is received, so that the channel region under the floating gate layer 112a is opened, generating a program current I PGN From source line SL to bit line BL 1Therefore, a channel hothole induced hot electron injection effect (CHHIHE injection effect) occurs in the channel region, and electrons are injected into the floating gate layer 112a through the floating gate dielectric layer 111a, causing the memory cell Cell 1 Change to programming state (programstate).
[0071] In the storage cell 2 In the word line WL 2 Receive shutdown voltage V OFF , so that the channel region below the floating gate layer 112b cannot be turned on, and the source line SL and the bit line BL 2 Therefore, the CHHIHE injection effect cannot occur, and electrons are not injected into the floating gate layer 112b, making the memory cell Cell 2 Not programmed and maintained in the original state, such as the erased state.
[0072] like Figure 2B As shown, the storage cell 1 、Cell 2 When performing an erase operation, a ground voltage (0V) is provided to the word line WL. 1 , WL 2 , ground voltage (0V) to source line SL, ground voltage (0V) to bit line BL 1 BL 2 , erase voltage (erasevoltage, V EE ) to the erase line EL. Furthermore, a ground voltage (0V) is provided to the N-type well region NW1. For example, the erase voltage V EE is 12V.
[0073] like Figure 2B As shown, in the memory cell 1 In the process, since the erase line EL receives the erase voltage V EE The FN tunneling effect (Fowler-Nordheim tunneling effect, referred to as FN tunneling effect) occurs between the floating gate layer 112a and the gate layer 130a. Electrons pass through the floating gate layer 112a through the input / output dielectric layer 120 and are ejected to the erase line EL, making the memory cell Cell 1 Change to the erase state. In addition, in the memory cell 2 In the example, since no electrons are stored in the floating gate layer 112b, no FN tunneling effect occurs, and the memory cell Cell2 Maintain in erase state.
[0074] According to the first embodiment of the present invention, since a portion of the gate layer 130a overlaps with the floating gate layer 112a, during the erasing operation, electrons are more likely to exit from the corner of the floating gate layer 112a to the erase line EL due to tip discharge.
[0075] Basically, during the reading operation, different reading currents I READ , and use it to determine the storage cell 1 、Cell 2 storage status.
[0076] like Figure 2C As shown, the storage cell 1 When performing a read operation, a turn-on voltage V is provided ON To word line WL 1 , turn off the transformer V OFF To word line WL 2 、Read voltage (V READ ) to the source line SL, ground voltage (0V) to the bit line BL 1 BL 2 , the second erase line voltage V EL2 To the erase line EL. Furthermore, a read voltage V READ To the N-type well region NW1. For example, the turn-on voltage V ON 0V, turn off voltage V OFF V READ , read the voltage V READ is 2V, the second erase line voltage V EL2 Greater than or equal to the ground voltage (0V), for example, between 0V and V READ between.
[0077] like Figure 2C As shown, due to the storage cell Cell 1 The floating gate layer 112a stores electrons, so that a channel is formed under the floating gate layer 112a. 1 Receiver start voltage V ON When the storage cell 1 That is, a larger read current I is generated. READ From source line SL to bit line BL 1 , so we can judge the storage cell Cell 1 It is programming state.
[0078] like Figure 2D As shown, the storage cell 2 When performing a read operation, a turn-on voltage V is provided ON To word line WL 2 , turn off the transformer V OFF To word line WL 1 , the other bias voltages are the same as Figure 2C .
[0079] Because the storage cell 2 The floating gate layer 112b does not store electrons, so that a channel cannot be formed under the floating gate layer 112b. 2 Receiver start voltage V ON Since the channel is not formed, the memory cell 2 Generates a small (almost zero) read current I READ , so we can judge the storage cell Cell 2 The state is erased.
[0080] In the first embodiment of the present invention, the memory cell Cell 1 、Cell 2 In the embodiment, the corners above the floating gate layers 112a and 112b are right angles. During the erasing operation, due to the tip discharge, electrons are withdrawn from the corners of the floating gate layer 112a to the erase line EL. Furthermore, the present invention can further modify the process. For example, the corners above the floating gate of the memory cell are made to be sharp, which makes it easier for electrons to withdraw from the corners of the floating gate layer to the erase line EL, thereby improving the erase efficiency of the memory cell.
[0081] Please refer to FIG. 3A to FIG. 3E , which is a flow chart of a method for manufacturing a memory cell according to a second embodiment of the present invention. Figure 1A Continue under the structure.
[0082] like Figure 3A As shown, a floating gate dielectric layer 311, a floating gate layer 312 and a silicon nitride layer (SiN layer) 313 are formed on the surface of the semiconductor substrate Psub. Then, the silicon nitride layer 313 is etched, and two openings are formed in the memory element region to expose the floating gate layer 312. The floating gate layer 312 is made of polysilicon.
[0083] Next, a heating oxidation process is performed. Figure 3BAs shown, during the thermal oxidation process, the floating gate layer 312 at the edge of the opening of the silicon nitride layer 313 oxidizes more slowly, while the floating gate layer 312 at the middle of the opening oxidizes more quickly. Therefore, tip shape dielectric layers 321 and 322 are formed, which are made of silicon dioxide.
[0084] like Figure 3C As shown, a wet etching process is used to remove the silicon nitride layer 313. Next, the etching rates of the polysilicon and its oxide are adjusted to enable a fast polysilicon etching rate and a very slow oxide etching rate. In other words, the raised dielectric layers 321 and 322 can be used as hard masks to selectively etch the floating gate layer 312 and the floating gate dielectric layer 311. When the etching process of the polysilicon and its oxide is completed, the floating gate layer 312 and the floating gate dielectric layer 311 that are not covered by the raised dielectric layers 321 and 322 will be removed, leaving only the raised dielectric layers 321 and 322. Figure 3C As shown, the raised dielectric layers 321, 322 and the floating gate dielectric layers 311a, 311b and floating gate layers 312a, 312b thereunder. Figure 3C In the embodiment, the remaining floating gate layers 312a and 312b will become floating gates of two memory cells respectively, and the corners of the floating gate layers 312a and 312b are sharp angles.
[0085] Then, if Figure 3D As shown, an input / output gate dielectric layer 320 is formed in the input / output device region and the memory device region, and a core gate dielectric layer 324 is formed in the core device region. The input / output gate dielectric layer 320 is formed on the surface of the semiconductor substrate Psub and covers the sidewalls of the floating gate layers 312a and 312b and the protruding dielectric layers 321 and 322. Therefore, the floating gate layers 312a and 312b are completely surrounded. In the second embodiment, the dielectric layer above the floating gate layer 312a is a merged dielectric layer, which is stacked by two sub-dielectric layers. That is, the dielectric layer above the floating gate layer 312a is stacked by the protruding dielectric layer 321 and the input / output gate dielectric layer 320. Similarly, the dielectric layer above the floating gate layer 312b is stacked by the protruding dielectric layer 322 and the input / output gate dielectric layer 320.
[0086] Furthermore, the subsequent manufacturing process of the memory cell of the second embodiment is the same as Figure 1G to Figure 1J , I will not go into details here. In other words, Figure 3DAfter the structure of the gate structure is formed through the gate structure forming process, doping process, spacer forming process, metal silicide forming process and wiring process, gate layers 330a, 330b, 330c, 330d, spacers 336a, 336b, 336c, 336d, metal silicide layer 139 and connection lines 371-377 are formed in the memory element area. Figure 3E As shown, a high voltage N-type transistor M is formed on the semiconductor substrate. N_HV , a high voltage P-type transistor M P_HV , a low voltage N-type transistor M N_LV , a low voltage P-type transistor M P_LV And storage cells 1 、Cell 2 Furthermore, the connection lines 371 and 377 can be used as bit lines BL 1 BL 2 , the connection line 374 can be used as the source line SL, the connection lines 372 and 376 can be used as the erase line EL, and the connection line 373 can be used as the word line WL 1 , the connection line 375 can be used as a word line WL 2 .
[0087] Compared with the memory cell Cell of the first embodiment 1 、Cell 2 ,exist Figure 3E Memory Cell 1 、Cell 2 In the embodiment, the floating gate layers 312a and 312b are formed by a combined dielectric layer, which is formed by stacking two sub-dielectric layers. In addition, in the floating gate layer 312a, the corner adjacent to the gate layer 330a is an acute angle. In the floating gate layer 312b, the corner adjacent to the gate layer 330c is an acute angle.
[0088] In the first embodiment of the present invention, the memory cell Cell 1 In the embodiment, the channel region is located between the two p-doped regions 142 and 143. The present invention can further modify the manufacturing process to shorten the channel length of the memory cell. Therefore, during programming, it is easier to inject electrons from the channel region into the floating gate layer to improve the programming efficiency of the memory cell.
[0089] Please refer to FIG. 4A to FIG. 4D , which is a flow chart of a method for manufacturing a memory cell according to a third embodiment of the present invention. Figure 1C Continue under the structure.
[0090] like Figure 4AAs shown, a photoresist layer 412 is used to cover the semiconductor substrate Psub and the floating gate layers 112 a and 112 b , and expose the surface of the semiconductor substrate Psub in the memory device region.
[0091] Next, after performing a light doped drain process (LDD process for short), the photoresist layer 412 is removed. Figure 4B As shown, three p-type lightly doped drain regions (p-LDD regions) 415, 416, and 417 are formed below the surface of the N-type well region NW1. The p-type lightly doped drain region 415 is located on the first side of the floating gate layer 112a, the p-type lightly doped drain region 417 is located on the first side of the floating gate layer 112b, and the p-type lightly doped drain region 416 is located between the second side of the floating gate layer 112a and the second side of the floating gate layer 112b.
[0092] like Figure 4C As shown, an input / output gate dielectric layer 420 is formed in the input / output device region and the memory device region, and a core gate dielectric layer 424 is formed in the core device region. The input / output gate dielectric layer 420 is formed on the surface of the semiconductor substrate Psub and covers the sidewalls and the upper part of the floating gate layers 112a and 112b. Therefore, the floating gate layers 112a and 112b are completely surrounded.
[0093] Furthermore, the subsequent process of the third embodiment is the same as Figure 1G to Figure 1J , I will not go into details here. In other words, Figure 4C After the structure undergoes gate structure formation process, doping process, spacer formation process, metal silicide formation process and wiring process, Figure 4D As shown, a high voltage N-type transistor M is formed on the semiconductor substrate. N_HV , a high voltage P-type transistor M P_HV , a low voltage N-type transistor M N_LV , a low voltage P-type transistor M P_LV And storage cells 1 、Cell 2 .
[0094] Compared to Figure 1J of Figure 4D The structure of the two is different only in the storage cell 1 、Cell 2 The doping region structure in the embodiment is the same as that in the embodiment of the present invention, and the rest of the structure is the same, and will not be described in detail here. Figure 4D Memory Cell 1 、Cell 2In the embodiment, the p-doped region 141 and the p-type lightly doped drain region 417 form a first merged doped region, the p-doped region 143 and the p-type lightly doped drain region 415 form a second merged doped region, and the p-doped region 142 and the p-type lightly doped drain region 416 form a third merged doped region. For example, the p-doped region 143 and an extended doped region form a first merged doped region, the extended doped region is located below the surface of the N-type well region NW1, and the extended doped region extends from one side of the gate layer 130a to below the gate layer 130a. Similarly, the p-doped region 141 and another extended doped region form a second merged doped region, the extended doped region is located below the surface of the N-type well region NW1, and the extended doped region extends from one side of the gate layer 130c to below the gate layer 130c.
[0095] Of course, the memory cell Cell of the third embodiment 1 、Cell 2 Further modifications are also possible. For example, the storage cell Cell of the third embodiment 1 、Cell 2 The floating gate layers 112a and 112b are modified into floating gate layers having sharp angles.
[0096] Compared with the first embodiment, the memory cell Cell of the third embodiment of the present invention 1 、Cell 2 Therefore, during programming, it is easier for electrons to be injected from the channel region into the floating gate layer, thereby improving the programming efficiency of the memory cell.
[0097] In the above three embodiments, the memory cell is manufactured after the isolation structure forming process and the well region forming process are completed. 1 、Cell 2 In other embodiments, the memory cell Cell may be fabricated before the isolation structure formation process or the well region formation process. 1 、Cell 2 The floating gate layer is described below.
[0098] Please refer to FIG. 5A to FIG. 5C , which is a flow chart of a method for manufacturing a memory cell according to a fourth embodiment of the present invention.
[0099] like Figure 5A As shown, an isolation structure forming process is first performed on the semiconductor substrate Psub to form a plurality of isolation structures 502 to 507. Next, a floating gate dielectric layer 511 and a floating gate layer 512 are formed on the surface of the semiconductor substrate Psub. Afterwards, a photoresist layer 517 is formed in the memory element region to cover a portion of the floating gate dielectric layer 511.
[0100] like Figure 5B As shown, an etching process is performed to remove the floating gate dielectric layer 511 and the floating gate layer 512 that are not covered by the photoresist layer 517. Afterwards, the photoresist layer 517 is removed. Therefore, the remaining floating gate layers 512a and 512b will become the floating gates of the two memory cells respectively.
[0101] Next, multiple well region formation processes are performed. By ion implantation, an N-type well region (N-well) NW1 is formed below the surface of the semiconductor substrate Psub in the memory element region, and N-type well regions NW2, NW3 and P-type well regions (P-well) PW1, PW2 are formed below the surface of the semiconductor substrate Psub in the logic element region.
[0102] According to the fourth embodiment of the present invention, before the well region forming process is performed, the floating gate layers 512a and 512b have been formed on the surface of the semiconductor substrate Psub. Figure 5B As shown, after the well region forming process is performed, the depth of the N-type well region NW1 below the floating gate layers 512a and 512b will be shallower, but will not affect the operation of the memory cell.
[0103] Furthermore, Figure 5B The structure is similar to Figure 1C Therefore, the subsequent manufacturing process of the memory cell of the fourth embodiment is the same as Figures 1D to 1J , I will not go into details here. In other words, Figure 5B The structure of the device is then subjected to the processes of forming an input / output gate dielectric layer, forming a core gate dielectric layer, forming a gate structure, doping, forming a spacer, forming a metal silicide and wiring. Figure 5C As shown, a high voltage N-type transistor M is formed on the semiconductor substrate. N_HV , a high voltage P-type transistor M P_HV , a low voltage N-type transistor M N_LV , a low voltage P-type transistor M P_LV And storage cells 1 、Cell 2 .
[0104] Compared to Figure 1J The memory cell of the first embodiment 1 、Cell 2 ,exist Figure 5C Memory Cell of the Fourth Embodiment 1 、Cell 2 Only the shape of the N-type well NW1 is slightly different. All other structures are the same as Figure 1J , I will not go into details here.
[0105] In addition, when the well region forming process is performed, a sacrificial silicon oxide layer is first formed on the surface of the semiconductor substrate Psub. After the well region forming process, the sacrificial oxide layer is removed. 1 、Cell 2 In the embodiment, the floating gate dielectric layers 511a and 511b below the floating gate layers 512a and 512b may also be replaced by a sacrificial oxide layer.
[0106] Similarly, the memory cell Cell of the fourth embodiment 1 、Cell 2 In the embodiment, the corners above the floating gate layers 512a and 512b are right angles. The present invention can further modify the manufacturing process, such as the manufacturing method of the second embodiment, so that the corners above the floating gate of the memory cell are sharp angles, making it easier for electrons to exit from the corners of the floating gate layer to the erase line EL, thereby improving the erase efficiency of the memory cell.
[0107] Please refer to 6A to 6H , which is a flow chart of a method for manufacturing a memory cell according to a fifth embodiment of the present invention.
[0108] like Fig. 6A As shown, an isolation structure forming process is first performed on the semiconductor substrate Psub, and a plurality of isolation structures 602-607 are formed. Next, a floating gate dielectric layer 611, a floating gate layer 612, and a silicon nitride layer (SiN layer) 613 are formed on the surface of the semiconductor substrate Psub. Afterwards, the silicon nitride layer 613 is etched, and an opening is formed in the memory element region to expose the floating gate layer 612. The floating gate layer 312 is made of polysilicon.
[0109] Next, a heating oxidation process is performed. Figure 6B As shown, during the thermal oxidation process, the floating gate layer 612 at the edge of the opening of the silicon nitride layer 613 oxidizes more slowly, while the floating gate layer 612 at the middle of the opening oxidizes more quickly. Therefore, a tip shape dielectric layer 622 is formed, which is made of silicon dioxide.
[0110] like Figure 6C As shown, a silicon dioxide layer 623 is deposited on the silicon nitride layer 613 and the protruding dielectric layer 622 .
[0111] Next, the silicon dioxide layer 623 and the protruding dielectric layer 622 are etched. Fig.6DAs shown, in the memory element region, two residual dielectric layers 625 and 626 are formed on the sidewalls of the silicon nitride layer 613. The residual dielectric layer 625 includes a portion of the silicon dioxide layer 623a and a portion of the protruding dielectric layer 622a. The residual dielectric layer 626 includes a portion of the silicon dioxide layer 623b and a portion of the protruding dielectric layer 622b.
[0112] like Fig. 6E As shown, the silicon nitride layer 613 is removed. Next, Fig. 6F As shown in FIG. 1 , the etching rate of polysilicon and its oxide is adjusted to enable a fast polysilicon etching rate and a very slow oxide etching rate. That is, the residual dielectric layers 625 and 626 can be used as hard masks to selectively etch the floating gate layer 612 and the floating gate dielectric layer 611. When the etching process of polysilicon and its oxide is completed, the floating gate layer 612 and the floating gate dielectric layer 611 not covered by the residual dielectric layers 625 and 626 will be removed, leaving only the residual dielectric layers 625 and 626. Fig. 6F As shown, the residual dielectric layers 625, 626 and the floating gate dielectric layers 611a, 611b and floating gate layers 612a, 612b thereunder are formed. Fig. 6F In the embodiment, the remaining floating gate layers 612a and 612b will become floating gates of two memory cells respectively, and the corners of the floating gate layers 612a and 612b are sharp angles.
[0113] Then, if Figure 6G As shown, multiple well region forming processes are performed. By ion implantation, an N-type well region (N-well) NW1 is formed below the surface of the semiconductor substrate Psub in the memory element region, and N-type well regions NW2, NW3 and P-type well regions (P-well) PW1, PW2 are formed below the surface of the semiconductor substrate Psub in the logic element region.
[0114] Furthermore, Figure 6G The structure is similar to Figure 1C and Figure 5B , the difference lies in that the shapes of the floating gate layers 612a and 612b are different, and there are dielectric layers 625 and 626 on the floating gate layers 612a and 612b. Therefore, the subsequent manufacturing process of the memory cell of the fifth embodiment is the same as Figures 1D to 1J , I will not go into details here. In other words, Figure 6G After the structure of the memory device is further processed through the process of forming an input / output gate dielectric layer, a core gate dielectric layer, a gate structure, a doping process, a spacer forming process, a metal silicide forming process and a wiring process, gate layers 630a, 630b, 630c, 630d, spacers 636a, 636b, 636c, 636d, a metal silicide layer 139 and connection lines 671-677 are formed in the memory device area. Therefore, if Figure 6H As shown, a high voltage N-type transistor M is formed on the semiconductor substrate. N_HV , a high voltage P-type transistor M P_HV , a low voltage N-type transistor M N_LV , a low voltage P-type transistor M P_LV And storage cells 1 、Cell 2 Furthermore, the connection lines 671 and 677 can be used as bit lines BL 1 BL 2 , the connection line 674 can be used as the source line SL, the connection lines 672 and 676 can be used as the erase line EL, and the connection line 673 can be used as the word line WL 1 , the connection line 675 can be used as a word line WL 2 .
[0115] Compared with the memory cell Cell of the first embodiment 1 、Cell 2 ,exist Figure 6H Memory Cell 1 、Cell 2 In the figure, the floating gate layers 612a and 612b are formed by stacking three sub-dielectric layers. For example, the floating gate layer 612a includes: a portion of the protruding dielectric layer 622a, a portion of the silicon dioxide layer 623a, and the input / output gate dielectric layer 620, which are stacked to form a merged dielectric layer. The floating gate layer 612b includes: a portion of the protruding dielectric layer 622b, a portion of the silicon dioxide layer 623b, and the input / output gate dielectric layer 620, which are stacked to form a merged dielectric layer. In addition, in the floating gate layer 612a, the corner adjacent to the gate layer 630a is an acute angle. In the floating gate layer 612b, the corner adjacent to the gate layer 630c is an acute angle.
[0116] Please refer to 7A to 7E , which is a flow chart of a method for manufacturing a memory cell according to a sixth embodiment of the present invention.
[0117] like Fig. 7A As shown, an isolation structure forming process is first performed on the semiconductor substrate Psub, and a plurality of isolation structures 702-707 are formed. Next, a floating gate dielectric layer 711 and a silicon nitride layer (SiN layer) 713 are formed on the surface of the semiconductor substrate Psub. Next, the silicon nitride layer 613 is etched, and two openings are formed in the memory element region to expose the floating gate dielectric layer 711. Thereafter, a floating gate layer 712 is formed to cover the floating gate dielectric layer 711 and the silicon nitride layer 713. The floating gate dielectric layer 711 may be a pad oxide layer, and the floating gate layer 712 is made of polysilicon.
[0118] like Figure 7B As shown, the floating gate layer 712 is etched. Therefore, in the memory element region, two residual floating gate layers 712a and 712b are formed on the sidewalls of the silicon nitride layer 713. The residual floating gate layers 712a and 712b will become floating gates of two memory cells respectively, and the corners of the floating gate layers 712a and 712b are sharp angles.
[0119] like Figure 7C As shown, the silicon nitride layer 713 is removed. Then, an oxide etching process is performed. Fig.7D As shown, the floating gate dielectric layer 711 other than the floating gate layers 712a and 712b is removed, leaving only the floating gate dielectric layers 711a and 711b.
[0120] Please refer to Fig.7D , followed by multiple well region formation processes. For example, by ion implantation, an N-type well region (N-well) NW1 is formed below the surface of the semiconductor substrate Psub in the memory element region, and N-type well regions NW2, NW3 and P-type well regions (P-well) PW1, PW2 are formed below the surface of the semiconductor substrate Psub in the logic element region.
[0121] Furthermore, Fig.7D The structure is similar to Figure 1C and Figure 5B Therefore, the subsequent manufacturing process of the memory cell of the sixth embodiment is the same as Figures 1D to 1J , I will not go into details here. In other words, Fig.7D After the structure of the input / output gate dielectric layer formation process, the core gate dielectric layer formation process, the gate structure formation process, the doping process, the spacer formation process, the metal silicide formation process and the wiring process, the input / output gate dielectric layer 720, the gate layer 730a, 730b, 730c, 730d, the spacer 736a, 736b, 736c, 736d, the metal silicide layer 139 and the connection lines 771-777 are formed in the memory element area. Therefore, if Fig. 7E As shown, a high voltage N-type transistor M is formed on the semiconductor substrate. N_HV , a high voltage P-type transistor M P_HV , a low voltage N-type transistor M N_LV , a low voltage P-type transistor M P_LV And storage cells 1 、Cell 2 Furthermore, the connection lines 771 and 777 can be used as bit lines BL 1 BL 2, the connection line 774 can be used as the source line SL, the connection lines 772 and 776 can be used as the erase line EL, and the connection line 773 can be used as the word line WL 1 , the connection line 775 can be used as the word line WL 2 In addition, in the floating gate layer 712a, the corner adjacent to the gate layer 730a is an acute angle. In the floating gate layer 712b, the corner adjacent to the gate layer 730c is an acute angle.
[0122] Please refer to FIG. 8A to FIG. 8E , which is a flow chart of a method for manufacturing a memory cell according to a seventh embodiment of the present invention.
[0123] First, an isolation structure forming process is performed on the semiconductor substrate Psub. Fig. 8A As shown, a floating gate dielectric layer 811, a floating gate layer 812, a silicon nitride layer 813, and a photoresist layer 817 are formed on the surface of the semiconductor substrate Psub. A plurality of openings are formed on the photoresist layer 817.
[0124] like Figure 8B As shown, the silicon nitride layer 813 , the floating gate layer 812 , the floating gate dielectric layer 811 and the semiconductor substrate Psub that are not covered by the photoresist layer 817 are etched, and a plurality of recessed regions are formed on the semiconductor substrate Psub.
[0125] like Figure 8C As shown, a plurality of isolation structures 802 ˜ 807 are formed in a plurality of recessed regions on the semiconductor substrate Psub. Next, the silicon nitride layer 813 is removed, and a photoresist layer 818 is formed in the memory device region to cover a portion of the floating gate layer 812 .
[0126] like Fig.8D As shown, the floating gate layer 812 and the floating gate dielectric layer 811 that are not covered by the photoresist layer 818 are etched. Afterwards, the photoresist layer 818 is removed. Among them, the remaining floating gate layers 812a and 812b will become the floating gates of the two memory cells respectively. In addition, after removing the photoresist layer 817, multiple well region formation processes are performed. That is, by ion implantation, an N-type well region (N-well) NW1 is formed under the surface of the semiconductor substrate Psub in the memory element area, and N-type well regions NW2, NW3 and P-type well regions (P-well) PW1, PW2 are formed under the surface of the semiconductor substrate Psub in the logic element area.
[0127] Furthermore, Fig.8D The structure is similar to Figure 1C and Figure 5B Therefore, the subsequent manufacturing process of the memory cell of the seventh embodiment is the same as Figures 1D to 1J , I will not go into details here.
[0128] Compared to Figure 1J The memory cell of the first embodiment 1 、Cell 2 ,exist Fig. 8E Memory Cell of the Seventh Embodiment 1 、Cell 2 Only the shape of the N-type well NW1 is slightly different. All other structures are the same as Figure 1J , I will not go into details here.
[0129] Please refer to 9A to 9E , which is a flow chart of a method for manufacturing a memory cell according to an eighth embodiment of the present invention.
[0130] First, an isolation structure forming process is performed on the semiconductor substrate Psub. Fig.9A As shown, a floating gate dielectric layer 911, a floating gate layer 912, and a silicon nitride layer 913 are formed on the surface of the semiconductor substrate Psub. Next, a plurality of openings are formed in the silicon nitride layer 913, and the floating gate layer 912, the floating gate dielectric layer 911, and the semiconductor substrate Psub that are not covered by the silicon nitride layer 913 are etched, and a plurality of recessed regions are formed on the semiconductor substrate Psub. Thereafter, a plurality of isolation structures 902-907 are formed in the plurality of recessed regions on the semiconductor substrate Psub.
[0131] like Fig. 9B As shown, two openings are formed in the silicon nitride layer 913 on the memory element region to expose the floating gate layer 912. Then, a thermal oxidation process is performed. Fig. 9B As shown, during the heating oxidation process, the floating gate layer 912 at the edge of the opening of the silicon nitride layer 913 oxidizes more slowly, while the floating gate layer 912 at the middle of the opening oxidizes more quickly. Therefore, convex dielectric layers 921 and 922 are formed, which are made of silicon dioxide.
[0132] like Fig. 9C As shown, the photoresist layer 917 is removed. Fig.9D As shown in FIG. 1 , the etching rate of polysilicon and its oxide is adjusted to enable a fast polysilicon etching rate and a very slow oxide etching rate. In other words, the raised dielectric layers 921 and 922 can be used as hard masks to selectively etch the floating gate layer 912 and the floating gate dielectric layer 911. When the etching process of polysilicon and its oxide is completed, the floating gate layer 312 and the floating gate dielectric layer 911 not covered by the raised dielectric layers 921 and 922 will be removed, leaving only the raised dielectric layers 921 and 922. Fig.9D As shown, the raised dielectric layers 921, 922 and the floating gate dielectric layers 911a, 911b and floating gate layers 912a, 912b thereunder. Fig.9DIn the embodiment, the remaining floating gate layers 912a and 912b will become floating gates of two memory cells respectively, and the corners of the floating gate layers 912a and 912b are sharp angles.
[0133] like Fig.9D As shown, multiple well region forming processes are continued. That is, by ion implantation, an N-type well region (N-well) NW1 is formed below the surface of the semiconductor substrate Psub in the memory element region, and N-type well regions NW2, NW3 and P-type well regions (P-well) PW1, PW2 are formed below the surface of the semiconductor substrate Psub in the logic element region.
[0134] Furthermore, Fig.9D The structure is similar to Figure 3D , but the input / output gate dielectric layer and the core gate dielectric layer have not yet been formed. Therefore, the subsequent manufacturing process of the memory cell of the eighth embodiment is the same as Figures 1D to 1J , I will not go into details here.
[0135] Compared to Figure 3E The memory cell of the second embodiment 1 、Cell 2 ,exist Fig.9E Memory Cell of the Eighth Embodiment 1 、Cell 2 Only the shape of the N-type well NW1 is slightly different. All other structures are the same as Figure 1J , I will not go into details here.
[0136] From the above description, it can be seen that the present invention provides a non-volatile memory cell and a manufacturing method thereof. Using the manufacturing method disclosed in the above various embodiments, the memory cell can be modified. 1 、Cell 2 For example, according to the manufacturing method of the third embodiment, the memory cell Cell in the second embodiment, the fifth embodiment and the sixth embodiment can be changed. 1 、Cell 2 Channel length is used to increase the memory cell 1 、Cell 2 Furthermore, the bias voltages for programming, erasing, and reading the memory cells Cell1 and Cell2 in all embodiments of the present invention are similar to FIG. 2A to FIG. 2D , I will not go into details here.
[0137] In addition, the memory cell described above 1 、Cell 2 All are realized by using P-type transistors (N-type well region and p-doped region). Of course, the memory cell of the present invention 1 、Cell2 It can also be implemented with N-type transistors (P-type well region and n-doped region). Compared with the p-type transistors in the above embodiment, the memory cell Cell is implemented with N-type transistors. 1 、Cell 2 When performing programming, the voltage condition (bias condition) during programming can be adjusted according to the actual situation to activate the channel hot electron injection (CHEI) effect or the source side hot electron injection (SSI) effect to achieve programming. 1 When programming, a start voltage V is provided. ON (For example, V PP / 8) to word line WL 1 , programming voltage V PP To bit line BL 1 , ground voltage (0V) to the source line SL and the P-type well area, and the erase line voltage V EL To the erase line EL. In addition, the bias voltages for both the erase and read operations are similar to FIG. 2B to FIG. 2D , I will not go into details here.
[0138] In summary, although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined in the attached claims.
Claims
1. A non-volatile memory cell, comprising: Semiconductor substrates; A well region is formed in the semiconductor substrate; A first dielectric layer, the first dielectric layer contacts the surface of the well region; A floating gate layer covering the first dielectric layer; A second dielectric layer, the second dielectric layer contacts the surface of the well region, and the second dielectric layer contacts the sidewall and the top of the floating gate layer, wherein the floating gate layer is completely surrounded by the first dielectric layer and the second dielectric layer; A first gate layer and a second gate layer, the first gate layer and the second gate layer are formed on the second dielectric layer, wherein the first gate layer and the second gate layer are respectively located on two sides of the floating gate layer, the first gate layer contacts the sidewall of the floating gate layer and the second dielectric layer above the floating gate layer; the second gate layer contacts the second dielectric layer on the sidewall of the floating gate layer; and a portion of the first gate layer and the floating gate layer overlap each other; A first doping region and a second doping region, wherein the first doping region and the second doping region are located in the surface of the well region, wherein the first gate layer, the second gate layer and the floating gate layer are located above the surface of the well region between the first doping region and the second doping region; A first connecting line electrically connected to the first doped region; A second connection line electrically connected to the first gate layer; A third connecting line electrically connected to the second doped region; as well as The fourth connecting line is electrically connected to the second doped region. 2 . The nonvolatile memory cell as claimed in claim 1 , wherein in the floating gate layer, a corner adjacent to the first gate layer is a right angle or an acute angle. 3 . The nonvolatile memory cell as claimed in claim 1 , wherein the second dielectric layer above the floating gate layer is a merged dielectric layer including a plurality of stacked sub-dielectric layers. 4 . The nonvolatile memory cell as claimed in claim 1 , wherein the second dielectric layer is an input / output gate dielectric layer. 5 . The nonvolatile memory cell as claimed in claim 1 , wherein the first dielectric layer is a floating gate dielectric layer, a sacrificial oxide layer or a pad oxide layer.
6. The nonvolatile memory cell as claimed in claim 1, wherein the first doped region and the extended doped region form a combined doped region, the extended doped region is located below a surface of the well region, and the extended doped region extends from one side of the first gate layer to below the first gate layer. 7 . The nonvolatile memory cell as claimed in claim 1 , wherein the first connection line is a bit line, the second connection line is an erase line, the third connection line is a word line, and the fourth connection line is a source line.
8. The nonvolatile memory cell as described in claim 7, wherein during a programming operation, a turn-on voltage is provided to the word line, a programming voltage is provided to the source line, a ground voltage is provided to the bit line, and an erase line voltage is provided to the erase line; a channel region below the floating gate layer is turned on, and a programming current flows from the source line to the bit line through the channel region; and a plurality of electrons are injected from the channel region into the floating gate layer through the first dielectric layer.
9. The nonvolatile memory cell as claimed in claim 7, wherein during an erase operation, a ground voltage is provided to the word line, the source line and the bit line, an erase voltage is provided to the erase line; and a plurality of electrons exit from the floating gate layer through the second dielectric layer to the erase line.
10. The non-volatile memory cell as described in claim 7, wherein during a read operation, a turn-on voltage is provided to the word line, a read voltage is provided to the source line, a ground voltage is provided to the bit line, and an erase line voltage is provided to the erase line; and the storage state of the non-volatile memory cell is determined according to the magnitude of a read current flowing from the source line to the bit line.
11. A method for manufacturing a non-volatile memory cell, comprising the following steps: (A) forming a first dielectric layer on a surface of a semiconductor substrate; (B) forming a floating gate layer covering the first dielectric layer; (C) forming a second dielectric layer on the surface of the semiconductor substrate; wherein, The second dielectric layer contacts the sidewall and the top of the floating gate layer, and the floating gate layer is completely surrounded by the first dielectric layer and the second dielectric layer; (D) forming a first gate layer on the second dielectric layer; wherein the first gate layer contacts the sidewall of the floating gate layer and the second dielectric layer above the floating gate layer, and a portion of the first gate layer and the floating gate layer overlap each other; and (E) forming a second gate layer on the second dielectric layer; wherein the second gate layer contacts the second dielectric layer at the sidewall of the floating gate layer, and the first gate layer and the second gate layer are respectively located on two sides of the floating gate layer; The semiconductor substrate includes a well region, and the well region includes a first doping region and a second doping region below the surface, and the first gate layer, the second gate layer and the floating gate layer are located above the well region surface between the first doping region and the second doping region.
12. The method for manufacturing a non-volatile memory cell according to claim 11, further comprising the following steps: (F) forming a first connecting line, a second connecting line, a third connecting line and a fourth connecting line; wherein, The first connection line is electrically connected to the first doped region, the second connection line is electrically connected to the first gate layer, the third connection line is electrically connected to the second gate layer, and the fourth connection line is electrically connected to the second doped region. 13 . The method for manufacturing a nonvolatile memory cell according to claim 12 , wherein the first connection line is a bit line, the second connection line is an erase line, the third connection line is a word line, and the fourth connection line is a source line. 14 . The method for manufacturing a non-volatile memory cell as claimed in claim 11 , wherein the floating gate layer is subjected to a thermal oxidation process so that a corner of the floating gate layer adjacent to the first gate layer is an acute angle. 15 . The method for manufacturing a non-volatile memory cell as claimed in claim 11 , wherein the floating gate layer is subjected to an etching process so that a corner of the floating gate layer adjacent to the first gate layer is an acute angle. 16 . The method for manufacturing a non-volatile memory cell as claimed in claim 11 , wherein the second dielectric layer above the floating gate layer is a merged dielectric layer, and the merged dielectric layer includes a plurality of stacked sub-dielectric layers. 17 . The method for manufacturing a non-volatile memory cell as claimed in claim 11 , wherein the second dielectric layer is an input / output gate dielectric layer. 18 . The method for manufacturing a non-volatile memory cell as claimed in claim 11 , wherein the first dielectric layer is a floating gate dielectric layer, a sacrificial oxide layer or a pad oxide layer.
19. The method for manufacturing a non-volatile memory cell as described in claim 11, further comprising a step for forming an extended doping region, wherein the first doping region and the extended doping region form a combined doping region, the extended doping region is located below the surface of the well region, and the extended doping region extends from one side of the first gate layer to below the first gate layer.
20. The method for manufacturing a non-volatile memory cell as claimed in claim 11, wherein the well region is formed after the floating gate layer is completed, or the well region is formed before the floating gate layer is completed.