Memory chip structure and preparation method thereof

Abstract

The invention discloses a memory chip structure and a preparation method thereof, and the structure is characterized in that a dielectric layer is arranged on bottom metal, the dielectric layer is provided with a bottom through hole, and the bottom through hole is filled with a conductive material to form a bottom through hole structure; the storage bit is arranged on the bottom through hole structure, and the top metal is arranged above the storage bit; when the storage bit is prepared, the dielectric layer is etched firstly, and a height difference exists between the etched dielectric layer and the bottom through hole structure; depositing a thin film on the dielectric layer and the bottom through hole structure, depositing a dielectric material on the thin film on the top of the dielectric layer and flattening the dielectric material, so that the upper surface of the dielectric material on the thin film on the top of the dielectric layer is flush with the upper surface of the thin film on the top of the bottom through hole structure; and photoetching and etching off the thin film in a partial region on the bottom through hole structure to form a storage bit. When the storage bit is obtained, the exposed area of the storage bit is reduced, and the performance problem of the storage bit caused by thin film backwash is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of memory chips, and in particular relates to a memory chip structure and a preparation method thereof. Background Art

[0002] The development of the Internet of Things has put forward higher requirements for data storage. New memories represented by magnetic random access memory (MRAM) have the advantages of non-volatility, high-speed reading and writing, and high reliability. They are new storage with great potential. The core of the MRAM chip is the magnetic tunnel junction (MTJ). Through current drive, it can realize the conversion of high and low resistance, thereby achieving the purpose of "0" and "1" storage. In the manufacture of new memory chips, the memory unit is integrated in the CMOS back-end process. The memory units are electrically interconnected through bottom interconnection and top interconnection. In addition to the storage array, the memory chip also has a logic control circuit, and this area only has a back-end interconnection structure.

[0003] In the traditional new memory manufacturing process, the thin film materials required for the memory cell are deposited on a flat substrate surface. In the memory cell patterning process, especially the etching process, the thin film between the memory cells is splashed back during ion bombardment, and the splashed appendages are likely to adhere to the sidewalls of the memory cell, causing problems such as memory cell damage or short circuit. This problem is more prominent in high-density memory arrays. Summary of the invention

[0004] In order to solve the problems of the prior art, the present invention provides a memory chip structure and a preparation method. By adopting a new bit preparation process, the risk of memory bit failure caused by the current process bottleneck in the chip preparation process is greatly reduced, and the chip yield and reliability are improved.

[0005] The technical solution adopted by the present invention is as follows:

[0006] In a first aspect, the present invention discloses a memory chip structure, including a bottom metal, a memory bit, and a top metal;

[0007] A dielectric layer is disposed on the bottom metal, a bottom through hole is opened on the dielectric layer, and the bottom through hole is filled with a conductive material to form a bottom through hole structure;

[0008] The storage bit is disposed on the bottom through-hole structure, and the top metal is disposed above the storage bit;

[0009] When preparing the storage bit, the dielectric layer is first etched, and there is a height difference between the etched dielectric layer and the bottom through-hole structure; a thin film is deposited on the dielectric layer and the bottom through-hole structure, and then a dielectric material is deposited on the thin film on the top of the dielectric layer and flattened, so that the upper surface of the dielectric material on the thin film on the top of the dielectric layer is flush with the upper surface of the thin film on the top of the bottom through-hole structure; and the thin film in a partial area above the bottom through-hole structure is photoetched to form a storage bit.

[0010] Furthermore, the memory chip structure further includes a bottom electrode, which is prepared on the upper surface of the bottom through-hole structure, and the bottom electrode is located below the memory bit and in contact with the memory bit.

[0011] In a second aspect, the present invention discloses a method for preparing the memory chip structure, comprising the following steps:

[0012] 1) preparing a bottom metal layer composed of a bottom metal;

[0013] 2) depositing a first dielectric material and a second dielectric material on the bottom metal layer from bottom to top, thereby forming a first dielectric layer and a second dielectric layer in sequence, punching holes in the first dielectric layer and the second dielectric layer above the bottom metal to form a bottom through hole, filling the bottom through hole with a conductive material to form a bottom through hole structure, using the bottom through hole structure as a mask, etching the second dielectric layer by a self-aligned etching method to form a groove, and a height difference exists between the bottom through hole structure and the etched second dielectric layer;

[0014] 3) depositing a thin film on the groove and the bottom through-hole structure, wherein the upper surface of the thin film on the second dielectric layer is lower than the upper surface of the bottom through-hole structure; and then depositing a third dielectric material on the thin film on top of the second dielectric layer and planarizing the thin film, so that the upper surface of the third dielectric material is flush with the upper surface of the thin film on top of the bottom through-hole structure;

[0015] 4) photolithographically etching the third dielectric material and the thin film in the partial area above the bottom through-hole structure, wherein the upper surface of the third dielectric material is not higher than the upper surface of the bottom through-hole structure when the etching stops; when photolithographically etching the thin film in the partial area, the etching stops at the upper surface of the bottom through-hole structure to form a storage bit;

[0016] 5) depositing a fourth dielectric material and planarizing it, and photolithographically etching all the fourth dielectric material, all the third dielectric material and all the thin films on the second dielectric layer to expose the second dielectric layer;

[0017] 6) Depositing a fifth dielectric material and planarizing it, and forming a top metal on the fifth dielectric material above the storage bit using a Damascene process, thereby finally forming a storage chip structure.

[0018] The present invention also discloses a method for preparing the memory chip structure, comprising the following steps:

[0019] 1) preparing a bottom metal layer including a bottom metal;

[0020] 2) depositing a first dielectric material and a second dielectric material on the bottom metal layer from bottom to top, thereby forming a first dielectric layer and a second dielectric layer in sequence, drilling holes in the first dielectric layer and the second dielectric layer above the bottom metal to form a bottom through hole, and filling the bottom through hole with a conductive material to form a bottom through hole structure, preparing a bottom electrode on the bottom through hole structure, the size of the bottom electrode is larger than the size of the bottom through hole structure, etching the second dielectric layer by a self-aligned etching method, and stopping the etching at the second dielectric layer;

[0021] 3) depositing a thin film on the bottom electrode and the second dielectric layer, wherein the upper surface of the thin film on the second dielectric layer is lower than the lower surface of the bottom electrode; then depositing a third dielectric material on the thin film on top of the second dielectric layer and flattening the thin film, so that the upper surface of the third deposited dielectric material is flush with the upper surface of the thin film on top of the bottom electrode;

[0022] 4) photolithographically etching the third dielectric material and the thin film in the partial area above the bottom electrode, wherein the upper surface of the third dielectric material is not higher than the upper surface of the bottom electrode when the etching stops; and when photolithographically etching the thin film in the partial area, the etching stops at the upper surface of the bottom electrode to form a storage bit;

[0023] 5) depositing and planarizing a fourth dielectric material, and photolithographically etching the fourth dielectric material, the third dielectric material, and the thin film on the second dielectric layer to expose part or all of the current second dielectric layer;

[0024] 6) Depositing a fifth dielectric material and planarizing it, and forming a top metal on the fifth dielectric material above the storage bit using a Damascene process, thereby finally forming a storage chip structure.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] The present invention adopts a new architecture and manufacturing technology. After the storage bit film is deposited, a step difference is formed. Therefore, the problem of device failure caused by the back splash of the metal film in the etching process in the existing memory chip manufacturing technology is overcome, thereby improving the chip yield and reliability. At the same time, the step difference formed after the storage bit film is deposited is helpful for photolithography alignment recognition, eliminating indirect alignment marks and reducing process steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a flow chart of preparing a memory chip structure according to a specific embodiment 1 of the present invention;

[0028] Figure 2 A flow chart of preparing a memory chip structure according to a specific embodiment 2 of the present invention;

[0029] Figure 3 This is a flow chart of preparing a memory chip structure according to a specific embodiment 3 of the present invention;

[0030] Figure 4 It is a structural schematic diagram of the present invention.

[0031] Description of component numbers in the figure: 100-substrate; 201-bottom metal layer; 202-bottom through-hole structure; 203-bottom electrode; 204-storage bit; 205-top metal; 101-sixth dielectric material; 102-first dielectric material; 103-second dielectric material; 104-fourth dielectric material; 105-fifth dielectric material. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0034] In addition, in the present invention, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0035] In the present invention, unless otherwise clearly specified and limited, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, a physical connection, or a wireless communication connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0036] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0037] The present invention is further described in detail below in conjunction with the accompanying drawings.

[0038] like Figure 4 As shown, this embodiment provides a memory chip structure, including: a substrate 100; a bottom metal 201 arranged on the substrate; a plurality of bottom through-hole structures 202 prepared on the bottom metal; a bottom electrode 203 prepared on the bottom through-hole structure; a memory bit 204 prepared on the bottom electrode; a top metal 205 prepared above the memory bit 204; and a top metal 205 prepared above the bottom metal 201 in the logic area of ​​the memory chip structure. The material of the memory bit includes MRAM, PCRAM or RRAM; the bottom metal is a metal material such as copper and aluminum; the top metal is a metal material such as copper and aluminum; the substrate includes a CMOS layer and a multi-layer metal layer arranged from bottom to top; Figure 4 A substrate is provided, which also includes an array area and a logic area; the CMOS layer is a general structure in this field without any special design; the metal layer is composed of metal materials such as copper and aluminum.

[0039] like Figure 1 As shown, the method for preparing the memory chip structure of this embodiment includes the following steps:

[0040] a) If Figure 1 In (a)-(d), a bottom metal layer including a bottom metal is prepared, and a sixth dielectric material 101 is filled between two adjacent bottom metals; a first dielectric material 102 and a second dielectric material 103 are sequentially deposited from bottom to top on the bottom metal layer, thereby sequentially forming a first dielectric layer and a second dielectric layer; a bottom through hole is formed by drilling holes in the first dielectric layer and the second dielectric layer above the bottom metal, and the bottom through hole is filled with a conductive material to form a bottom through hole structure; a bottom electrode is prepared above the bottom through hole structure, and the size of the bottom electrode is larger than the size of the bottom through hole structure; the second dielectric layer is etched by a self-aligned etching method and the etching stops at the second dielectric layer; wherein the first dielectric material 102 and the second dielectric material 103 are different dielectric materials, and the dielectric materials may be insulating dielectric materials such as silicon oxide, silicon nitride or low-k; the self-aligned etching method is a dry method or a wet method; the conductive material includes but is not limited to copper, aluminum, titanium nitride, titanium, tantalum nitride, tantalum, tungsten, etc.;

[0041] b) If Figure 1 In (e)-(f), a thin film is deposited on the bottom electrode and the second dielectric layer, and the upper surface of the thin film on the second dielectric layer is lower than the lower surface of the bottom electrode; a third dielectric material is deposited on the thin film on top of the second dielectric layer and planarized, so that the upper surface of the third deposited dielectric material is flush with the upper surface of the thin film on top of the bottom electrode; the material of the thin film includes MRAM, PCRAM or RRAM; the third dielectric material is an insulating dielectric material such as silicon oxide, silicon nitride or low-k; the material of the bottom electrode includes but is not limited to copper, aluminum, titanium nitride, titanium, tantalum nitride, tantalum, tungsten, etc.;

[0042] c) If Figure 1 (g) in which the third dielectric material and the thin film in a partial area above the bottom electrode are photolithographically etched, and when the etching stops, the upper surface of the third dielectric material is flush with the upper surface of the bottom electrode; when the thin film in the partial area is photolithographically etched, the etching stops at the upper surface of the bottom electrode, and the bottom electrode is exposed to form a storage bit 204;

[0043] d) If Figure 1 In (h)-(i), a fourth dielectric material 104 is deposited and planarized, and all the fourth dielectric material 104, all the third dielectric material and all the thin films on the second dielectric layer are photoetched to expose the entire current second dielectric layer; the fourth dielectric material 104 is an insulating dielectric material such as silicon oxide, silicon nitride or low-k;

[0044] e) If Figure 1 In (j), the fifth dielectric material 105 is deposited and planarized, and a top metal 205 is formed on the fifth dielectric material 105 above the storage bit 204 using a Damascene process; a top metal 205 is also formed on the bottom metal 201 of the array logic area using a Damascene process; a storage chip structure is formed, and finally the following is prepared: Figure 4 The memory chip structure shown in FIG. 1 is a memory chip structure shown in FIG. 1 , wherein the fifth dielectric material 105 is an insulating dielectric material such as silicon oxide, silicon nitride or low-k.

[0045] like Figure 2 As shown, the method for preparing the memory chip structure of this embodiment includes the following steps:

[0046] a) If Figure 2In (a)-(d), a bottom metal layer including a bottom metal is prepared, and a sixth dielectric material 101 is filled between two adjacent bottom metals; a first dielectric material 102 and a second dielectric material 103 are sequentially deposited from bottom to top on the bottom metal layer, thereby sequentially forming a first dielectric layer and a second dielectric layer; a bottom through hole is formed by drilling holes in the first dielectric layer and the second dielectric layer above the bottom metal, and the bottom through hole is filled with a conductive material to form a bottom through hole structure; a bottom electrode is prepared above the bottom through hole structure, and the size of the bottom electrode is larger than the size of the bottom through hole structure; the second dielectric layer is etched by a self-aligned etching method and the etching stops at the second dielectric layer; wherein the first dielectric material 102 and the second dielectric material 103 are different dielectric materials, and the dielectric materials can be insulating dielectric materials such as silicon oxide, silicon nitride or low-k; and the self-aligned etching method is a dry method or a wet method;

[0047] b) If Figure 2 In (e)-(f), a thin film is deposited on the bottom electrode and the second dielectric layer, and the upper surface of the thin film on the third dielectric layer is lower than the lower surface of the bottom electrode; a third dielectric material is deposited on the thin film on top of the second dielectric layer and flattened, so that the upper surface of the third deposited dielectric material is flush with the upper surface of the thin film on top of the bottom electrode; the material of the thin film includes MRAM, PCRAM or RRAM; the third dielectric material is an insulating dielectric material such as silicon oxide, silicon nitride or low-k; the material of the bottom electrode includes but is not limited to copper, aluminum, titanium nitride, titanium, tantalum nitride, tantalum, tungsten, etc.;

[0048] c) If Figure 2 (g) in which the third dielectric material and the thin film in a partial area above the bottom electrode are photolithographically etched, and when the etching stops, the upper surface of the third dielectric material is flush with the upper surface of the bottom electrode; when the thin film in the partial area is photolithographically etched, the etching stops at the upper surface of the bottom electrode, and the bottom electrode is exposed to form a storage bit 204;

[0049] d) If Figure 2 In (h)-(i), a fourth dielectric material 104 is deposited and planarized, and the fourth dielectric material 104, the third dielectric material and the thin film on the second dielectric layer are photoetched to expose a portion of the current second dielectric layer; the fourth dielectric material 104 is an insulating dielectric material such as silicon oxide, silicon nitride or low-k;

[0050] e) If Figure 2In (j), a fifth dielectric material 105 is deposited and planarized, and a top metal 205 is formed on the fifth dielectric material 105 above the storage bit 204 using a damascene process; a top metal 205 is also formed above the bottom metal 201 in the array logic area using a damascene process; and finally a memory chip structure is formed; wherein the fifth dielectric material 105 is an insulating dielectric material such as silicon oxide, silicon nitride or low-k.

[0051] This embodiment also provides a memory chip structure, including: a substrate 100; a bottom metal 201 arranged on the substrate; a plurality of bottom through-hole structures 202 prepared on the bottom metal; a memory bit 204 prepared on the bottom through-hole structure 202; and a top metal 205 prepared above the memory bit 204.

[0052] like Figure 3 As shown, the method for preparing the memory chip structure of this embodiment includes the following steps:

[0053] a) If Figure 3 In (a)-(b), a bottom metal layer including a bottom metal is prepared, and a sixth dielectric material 101 is filled between two adjacent bottom metals; a first dielectric material 102 and a second dielectric material 103 are sequentially deposited from bottom to top on the bottom metal layer, thereby sequentially forming a first dielectric layer and a second dielectric layer; a bottom through hole is punched in the first dielectric layer and the second dielectric layer above the bottom metal to form a bottom through hole, and the bottom through hole is filled with a conductive material to form a bottom through hole structure; the bottom through hole structure is used as a mask, and the second dielectric layer is etched by a self-aligned etching method to form a groove, and there is a height difference between the bottom through hole structure and the etched second dielectric layer, and the upper surface of the bottom through hole structure is higher than the upper surface of the etched second dielectric layer; wherein the first dielectric material 102 and the second dielectric material 103 are different dielectric materials, and the dielectric material can be an insulating dielectric material such as silicon oxide, silicon nitride or low-k; the self-aligned etching method is a dry method or a wet etching method;

[0054] b) If Figure 3 In (c)-(d), a thin film is deposited on the groove and the bottom through-hole structure, and the upper surface of the thin film on the second dielectric layer is lower than the upper surface of the bottom through-hole structure; a third dielectric material is deposited on the thin film on the top of the second dielectric layer and flattened, so that the upper surface of the third deposited dielectric material is flush with the upper surface of the thin film on the top of the bottom through-hole structure; wherein the material of the thin film includes MRAM, PCRAM or RRAM; the third dielectric material is an insulating dielectric material such as silicon oxide, silicon nitride or low-k;

[0055] c) If Figure 3In (d)-(e), the third dielectric material and the thin film in the partial area above the bottom through hole structure are photolithographically etched, and when the etching stops, the upper surface of the third dielectric material is flush with the upper surface of the bottom through hole; when the thin film in the partial area is photolithographically etched, the etching stops at the upper surface of the bottom through hole structure, thereby forming a storage bit 204;

[0056] d) If Figure 3 In (f)-(g), a fourth dielectric material 104 is deposited and planarized, and all the fourth dielectric material 104, all the third dielectric material and all the thin films on the second dielectric layer are photoetched to expose the entire current second dielectric layer; the fourth dielectric material 104 is an insulating dielectric material such as silicon oxide, silicon nitride or low-k;

[0057] e) If Figure 3 In (h)-(i), a fifth dielectric material 105 is deposited and planarized, and a top metal 205 is formed on the fifth dielectric material 105 above the storage bit 204 using a damascene process; a top metal 205 is also formed above the bottom metal 201 in the array logic area using a damascene process, and finally a memory chip structure is formed; wherein the fifth dielectric material 105 is an insulating dielectric material such as silicon oxide, silicon nitride or low-k.

[0058] The above-mentioned embodiments only express several implementation modes of the present invention, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. For those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A memory chip structure, characterized in that: Includes bottom metal, storage bits, and top metal; A dielectric layer is disposed on the bottom metal, a bottom through hole is opened on the dielectric layer, and the bottom through hole is filled with a conductive material to form a bottom through hole structure; The storage bit is disposed on the bottom through-hole structure, and the top metal is disposed above the storage bit; When preparing the storage bit, the dielectric layer is first etched, and there is a height difference between the etched dielectric layer and the bottom through-hole structure; A thin film is deposited on the dielectric layer and the bottom through-hole structure, and then a dielectric material is deposited on the thin film on the top of the dielectric layer and flattened so that the upper surface of the dielectric material on the thin film on the top of the dielectric layer is flush with the upper surface of the thin film on the top of the bottom through-hole structure; the thin film in a partial area above the bottom through-hole structure is etched away by photolithography to form a storage bit.

2. The memory chip structure according to claim 1, characterized in that: The memory chip structure further includes a bottom electrode, which is prepared on the upper surface of the bottom through-hole structure, and the bottom electrode is located below the memory bit and in contact with the memory bit.

3. The memory chip structure according to claim 1 or 2, characterized in that: The memory chip structure also includes a substrate, which is located below the bottom metal and in contact with the bottom metal, and the substrate includes a CMOS layer and a multi-layer metal layer arranged from bottom to top.

4. A method for preparing the memory chip structure according to claim 1, characterized in that: The following steps are involved: 1) preparing a bottom metal layer composed of a bottom metal; 2) depositing a first dielectric material and a second dielectric material on the bottom metal layer from bottom to top in sequence to form a first dielectric layer and a second dielectric layer in sequence, punching holes in the first dielectric layer and the second dielectric layer above the bottom metal to form a bottom through hole, filling the bottom through hole with a conductive material to form a bottom through hole structure, using the bottom through hole structure as a mask, etching the second dielectric layer by a self-aligned etching method to form a groove, wherein there is a height difference between the bottom through hole structure and the etched second dielectric layer; 3) depositing a thin film on the groove and the bottom through-hole structure, wherein the upper surface of the thin film on the second dielectric layer is lower than the upper surface of the bottom through-hole structure; Then, a third dielectric material is deposited on the thin film on top of the second dielectric layer and planarized so that the upper surface of the third dielectric material is flush with the upper surface of the thin film on top of the bottom through-hole structure; 4) photolithographically etching the third dielectric material and the thin film in the partial area above the bottom through-hole structure, wherein the upper surface of the third dielectric material is not higher than the upper surface of the bottom through-hole structure when the etching stops; when photolithographically etching the thin film in the partial area, the etching stops at the upper surface of the bottom through-hole structure to form a storage bit; 5) depositing a fourth dielectric material and planarizing it, and photolithographically etching all the fourth dielectric material, all the third dielectric material and all the thin films on the second dielectric layer to expose the second dielectric layer; 6) Depositing a fifth dielectric material and planarizing it, and forming a top metal on the fifth dielectric material above the storage bit using a Damascene process, thereby finally forming a storage chip structure.

5. A method for preparing the memory chip structure according to claim 2, characterized in that: The following steps are involved: 1) preparing a bottom metal layer including a bottom metal; 2) depositing a first dielectric material and a second dielectric material on the bottom metal layer from bottom to top, thereby forming a first dielectric layer and a second dielectric layer in sequence, drilling holes in the first dielectric layer and the second dielectric layer above the bottom metal to form a bottom through hole, and filling the bottom through hole with a conductive material to form a bottom through hole structure, preparing a bottom electrode on the bottom through hole structure, the size of the bottom electrode is larger than the size of the bottom through hole structure, etching the second dielectric layer by a self-aligned etching method, and stopping the etching at the second dielectric layer; 3) depositing a thin film on the bottom electrode and the second dielectric layer, wherein the upper surface of the thin film on the second dielectric layer is lower than the lower surface of the bottom electrode; then depositing a third dielectric material on the thin film on top of the second dielectric layer and flattening the thin film, so that the upper surface of the third deposited dielectric material is flush with the upper surface of the thin film on top of the bottom electrode; 4) photolithographically etching the third dielectric material and the thin film in the partial area above the bottom electrode, wherein the upper surface of the third dielectric material is not higher than the upper surface of the bottom electrode when the etching stops; and when photolithographically etching the thin film in the partial area, the etching stops at the upper surface of the bottom electrode to form a storage bit; 5) depositing and planarizing a fourth dielectric material, and photolithographically etching the fourth dielectric material, the third dielectric material, and the thin film on the second dielectric layer to expose part or all of the current second dielectric layer; 6) Depositing a fifth dielectric material and planarizing it, and forming a top metal on the fifth dielectric material above the storage bit using a Damascene process, thereby finally forming a storage chip structure.

6. The preparation method according to claim 4 or 5, characterized in that: In step 2), the self-aligned etching method is dry etching or wet etching.

7. The preparation method according to claim 4 or 5, characterized in that: The material of the storage bit includes MRAM, PCRAM or RRAM.

8. The preparation method according to claim 4 or 5, characterized in that: The first dielectric material, the second dielectric material, the third dielectric material, the fourth dielectric material and the fifth dielectric material are silicon oxide, silicon nitride or low-k material; wherein the first dielectric material and the second dielectric material are different.

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