Electronic component including stacked semiconductor chips and method of manufacturing same

Abstract

The invention provides an electronic component and a preparation method thereof. The electronic component comprises a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip and electrically connected with the first semiconductor chip through hybrid bonding. The third semiconductor chip is stacked on the second semiconductor chip and is electrically connected with the second semiconductor chip through a plurality of bumps.

Description

[0001] Cross-references

[0002] This application claims priority to U.S. patent application No. 18 / 371,588 (i.e., the priority date is "September 22, 2023"), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to an electronic component and a method for preparing the same, and more particularly to an electronic component including stacked semiconductor chips and a method for preparing the same. Background Art

[0004] Semiconductor electronic components are widely used in various electronic fields, and the size of semiconductor electronic components is constantly shrinking to meet current application requirements. However, various problems will arise in the process of size reduction, affecting the final electrical characteristics, quality, cost and output. For example, heat dissipation.

[0005] The above description of “prior art” is only to provide background technology, and does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present disclosure. Summary of the invention

[0006] One aspect of the present disclosure provides an electronic component, comprising a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip and electrically connected to the first semiconductor chip through hybrid bonding. The third semiconductor chip is stacked on the second semiconductor chip and electrically connected to the second semiconductor chip through a plurality of bumps.

[0007] Another aspect of the present disclosure provides an electronic component, including a first package and a second package. The first package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip through hybrid bonding. The second package includes a third semiconductor chip and a fourth semiconductor chip stacked on the third semiconductor chip and electrically connected to the third semiconductor chip through hybrid bonding. The second package is electrically connected to the first package through the plurality of bumps.

[0008] Another aspect of the present disclosure provides a preparation method. The preparation method includes providing a first package, including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip through hybrid bonding; providing a second package, including a third semiconductor chip and a fourth semiconductor chip stacked on the third semiconductor chip and electrically connected to the third semiconductor chip through hybrid bonding; and electrically connecting the second package to the first package through the plurality of bumps.

[0009] The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those skilled in the art to which the present disclosure belongs that such equivalent constructions cannot depart from the concept and scope of the present disclosure as defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more complete understanding of the disclosure of this application may be obtained by referring to the detailed description and claims taken in conjunction with the accompanying drawings, and:

[0011] Figure 1 is a cross-sectional view illustrating electronic components of some embodiments of the present disclosure.

[0012] Figure 2 is a cross-sectional view illustrating electronic components of some embodiments of the present disclosure.

[0013] Figure 3 is a cross-sectional view illustrating a semiconductor structure according to some embodiments of the present disclosure.

[0014] Figures 4 to 19 2 is a cross-sectional view illustrating various stages of a method for manufacturing an electronic component according to some embodiments of the present disclosure.

[0015] Fig. 20 is a flow chart illustrating a method for preparing an electronic component according to some embodiments of the present disclosure.

[0016] Description of reference numerals:

[0017] 1: The first semiconductor chip

[0018] 1': First wafer

[0019] 1": Unit

[0020] 1a: Sixth semiconductor chip

[0021] 1b: The eighth semiconductor chip

[0022] 2: Second semiconductor chip

[0023] 2': Second wafer

[0024] 2a: Seventh semiconductor chip

[0025] 2b: The ninth semiconductor chip

[0026] 3: The third semiconductor chip

[0027] 3": Unit

[0028] 4: The fourth semiconductor chip

[0029] 4': The fourth wafer

[0030] 5: Base semiconductor chip

[0031] 6: Electronic components

[0032] 6a: Electronic components

[0033] 8: Interposer

[0034] 9: Semiconductor structure

[0035] 10: First base

[0036] 11: Bottom surface

[0037] 11": Bottom surface

[0038] 12: Top surface

[0039] 12": Top surface

[0040] 13: Side surface

[0041] 13": Side surface

[0042] 14: First conductive structure

[0043] 15: The first lower structure

[0044] 16: First upper structure

[0045] 17: First conductive via

[0046] 18: First packaging layer

[0047] 19: Separation line

[0048] 20: Second base

[0049] 21: Bottom surface

[0050] 22: Top surface

[0051] 23: Side surface

[0052] 24: Second conductive structure

[0053] 25: The second structure

[0054] 26: Second upper structure

[0055] 27: Second conductive via

[0056] 29: Separation line

[0057] 30: Third base

[0058] 31: Bottom surface

[0059] 31": Bottom surface

[0060] 32: Top surface

[0061] 32": Top surface

[0062] 33: Side surface

[0063] 33": Side surface

[0064] 34: The third conductive structure

[0065] 35: The third structure

[0066] 36: The third upper structure

[0067] 37: The third conductive via

[0068] 38: The third encapsulation layer

[0069] 40: Fourth base

[0070] 41: Bottom surface

[0071] 42: Top surface

[0072] 43: Side surface

[0073] 44: Fourth conductive structure

[0074] 45: The fourth structure

[0075] 49: Separation line

[0076] 50: Fifth base

[0077] 51: Bottom surface

[0078] 52: Top surface

[0079] 53: Side surface

[0080] 54: Fifth conductive structure

[0081] 55: Fifth upper structure

[0082] 57: Fifth conductive via

[0083] 61: Bump

[0084] 62: Bottom filling

[0085] 63: Electrical connector

[0086] 64: Protective Materials

[0087] 65: Peripheral packaging layer

[0088] 66: External connector

[0089] 71: First package

[0090] 72: Second package

[0091] 71a: Third package

[0092] 71b: The fourth package

[0093] 80: Base

[0094] 84: Conductive structure

[0095] 85: Upper structure

[0096] 87: Conductive vias

[0097] 92: Semiconductor components

[0098] 94: Solder

[0099] 96: External connector

[0100] 101: First Surface

[0101] 102: Second Surface

[0102] 151: First lower dielectric layer

[0103] 152: First pad

[0104] 161: First upper dielectric layer

[0105] 162: First pad

[0106] 181: First surface

[0107] 182: Second Surface

[0108] 201: First Surface

[0109] 202: Second Surface

[0110] 251: Second lower dielectric layer

[0111] 252: Second down pad

[0112] 261: Second upper dielectric layer

[0113] 262: Second pad

[0114] 351: The third lower dielectric layer

[0115] 352: The third pad

[0116] 361: Third upper dielectric layer

[0117] 362: The third pad

[0118] 381: First Surface

[0119] 382: Second Surface

[0120] 401: First surface

[0121] 451: Fourth lower dielectric layer

[0122] 452: The fourth pad

[0123] 501: First surface

[0124] 502: Second surface

[0125] 551: Fifth upper dielectric layer

[0126] 552: Fifth pad

[0127] 851: Dielectric layer

[0128] 852: Solder pad

[0129] 900: Preparation method

[0130] S901: Steps

[0131] S902: Steps

[0132] S903: Steps DETAILED DESCRIPTION

[0133] Embodiments, or examples, of the present disclosure illustrated in the accompanying drawings will now be described in specific language. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as would normally be done by one of ordinary skill in the art to which the present disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment are applicable to another embodiment, even if they share the same reference numerals.

[0134] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers or parts, these elements, components, regions, layers or parts are not limited by these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part without departing from the teaching of the concept of the present invention.

[0135] The terms used herein are only used to describe specific embodiments and are not intended to limit the concepts of the present invention. As used herein, the singular forms of "a", "an" and "the" also include plural forms unless the context clearly indicates. It should be further understood that the terms "comprising" and "including", when used in this specification, indicate the presence of the features, integers, steps, operations, elements or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or groups thereof.

[0136] Figure 1 is a cross-sectional view illustrating an electronic component 6 of some embodiments of the present disclosure. In some embodiments, the electronic component 6 may be a semiconductor electronic component or a semiconductor electronic structure, including a plurality of semiconductor chips stacked on each other. Therefore, the electronic component 6 may be a stacked structure, including a plurality of stacked memory elements (e.g., dynamic random access memory (DRAM)). For example, the electronic component 6 may be a high bandwidth memory (HBM). In some embodiments, the electronic component 6 may include a first package 71 (e.g., including a first semiconductor chip 1 and a second semiconductor chip 2), a second package 72 (e.g., including a third semiconductor chip 3 and a fourth semiconductor chip 4), a plurality of bumps 61, a bottom fill 62, a plurality of electrical connectors 63, a protective material 64, a base semiconductor chip 5, a peripheral packaging layer 65, and a plurality of external connectors 66.

[0137] The first semiconductor chip 1 may have a bottom surface 11 (e.g., a first surface), a top surface 12 (e.g., a second surface), and a side surface 13 extending between the bottom surface 11 and the top surface 12. The first semiconductor chip 1 may include a first base 10, a first conductive structure 14, a first lower structure 15, a first upper structure 16, a plurality of first conductive vias 17, and a first encapsulation layer 18. The first semiconductor chip 1 may be a memory chip, such as a dynamic random access memory (DRAM) chip.

[0138] The first base 10 may be a semiconductor substrate, for example, may include silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP) or other IV-IV, III-V or II-VI semiconductor materials. In some embodiments, the first base 10 may include a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-insulator (SGOI) substrate or a germanium-insulator (GOI) substrate. The first base 10 may have a first surface 101 (e.g., a bottom surface) and a second surface 102 (e.g., a top surface) opposite to the first surface 101.

[0139] The first conductive structure 14 may be disposed on the first surface 101 (e.g., the bottom surface) of the first base 10. In some embodiments, the first conductive structure 14 may include a plurality of front-end-of-line (FEOL) components, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (pFETs), n-type field effect transistors (nFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, fin field effect transistors (FinFETs), other suitable integrated circuit components, or combinations thereof. In some embodiments, the first conductive structure 14 may further include at least one back-end-of-line (BEOL) interconnect pattern, such as a plurality of patterned circuit layers, electrically connected to the front-end-of-line (FEOL) components. In some embodiments, the first conductive structure 14 may further include at least one dielectric layer or at least one dielectric structure, covering the front-end-of-line (FEOL) components and the back-end-of-line (BEOL) interconnect pattern.

[0140] The first conductive via 17 may extend through the first base 10 and may be electrically connected to the first conductive structure 14. In some embodiments, the bottom end of the first conductive via 17 may extend beyond the first surface 101 (e.g., the bottom surface) of the first base 10 and may extend into the first conductive structure 14. Therefore, the first conductive via 17 may be an integral structure, and the length of the first conductive via 17 may be greater than the thickness of the first base 10. In some embodiments, the top surface of the first conductive via 17 may be substantially coplanar with the second surface 102 (e.g., the top surface) of the first base 10. Therefore, the top surface of the first conductive via 17 may be exposed by the second surface 102 (e.g., the top surface) of the first base 10.

[0141] The first lower structure 15 may be disposed on the first conductive structure 14. The first lower structure 15 may be a hybrid bonding (HB) structure or a solder bonding structure, and may include a first lower dielectric layer 151 and a plurality of first lower pads 152. The first lower dielectric layer 151 may be a hybrid bonding (HB) dielectric layer, and may include SiO2, SiCN, and / or SiON. Each of the first lower pads 152 may be a hybrid bonding (HB) pad, and may include copper or aluminum. The first lower pad 152 may be embedded in the first lower dielectric layer 151, and may be exposed by the first lower dielectric layer 151. The first lower pad 152 may be surrounded by the first lower dielectric layer 151. The first lower pad 152 may be electrically connected to a back-end-of-line (BEOL) interconnection pattern of the first conductive structure 14. Therefore, the first lower pad 152 may be electrically connected to the first conductive via 17 through the first conductive structure 14.

[0142] In some embodiments, the bottom surface of the first lower pad 152 may be substantially aligned with the bottom surface of the first lower dielectric layer 151. Therefore, the bottom surface of the first lower pad 152 may be exposed by the bottom surface of the first lower dielectric layer 151. In some embodiments, the top surface of the first lower pad 152 may be substantially aligned with the top surface of the first lower dielectric layer 151. Therefore, the top surface of the first lower pad 152 may contact the first conductive structure 14. In some embodiments, the thickness of the first lower pad 152 may be substantially equal to the thickness of the first lower dielectric layer 151.

[0143] The first upper structure 16 may be disposed on the second surface 102 (eg, the top surface) of the first base 10. The first upper structure 16 may be a hybrid bonding (HB) structure, and may include a first upper dielectric layer 161 and a plurality of first upper pads 162.

[0144] The first upper dielectric layer 161 may be a hybrid bonding (HB) dielectric layer and may include SiO2, SiCN and / or SiON. Each first upper pad 162 may be a hybrid bonding (HB) pad and may include copper or aluminum. The first upper pad 162 may be embedded in the first upper dielectric layer 161 and may be exposed by the first upper dielectric layer 161. The first upper pad 162 may be surrounded by the first upper dielectric layer 161. The first upper pad 162 may be electrically connected to the first conductive via 17. In some embodiments, the first upper pad 162 may directly contact the first conductive via 17. The first upper pad 162 may be electrically connected to the first lower pad 152 through the first conductive via 17 and the first conductive structure 14.

[0145] In some embodiments, the top surface of the first upper pad 162 may be substantially aligned with the top surface of the first upper dielectric layer 161. Therefore, the top surface of the first upper pad 162 may be exposed by the top surface of the first upper dielectric layer 161. In some embodiments, the bottom surface of the first upper pad 162 may be substantially aligned with the bottom surface of the first upper dielectric layer 161. Therefore, the bottom surface of the first upper pad 162 may contact the first conductive via 17. In some embodiments, the thickness of the first upper pad 162 may be substantially equal to the thickness of the first upper dielectric layer 161.

[0146] The first encapsulation layer 18 may be disposed around the first base 10, the first conductive structure 14, the first lower structure 15, and the first upper structure 16. The first encapsulation layer 18 may include a molding compound containing or not containing a filler. In some embodiments, the side surfaces of the first base 10, the side surfaces of the first conductive structure 14, the side surfaces of the first lower structure 15, and the side surfaces of the first upper structure 16 may be aligned or coplanar with each other. Therefore, the first encapsulation layer 18 may cover and contact the side surfaces of the first base 10, the side surfaces of the first conductive structure 14, the side surfaces of the first lower structure 15, and the side surfaces of the first upper structure 16.

[0147] In some embodiments, the bottom surface 11 of the first semiconductor chip 1 may include a bottom surface of the first lower pad 152, a bottom surface of the first lower dielectric layer 151, and a bottom surface of the first encapsulation layer 18. The top surface 12 of the first semiconductor chip 1 may include a top surface of the first upper pad 162, a top surface of the first upper dielectric layer 161, and a top surface of the first encapsulation layer 18. The side surface 13 of the first semiconductor chip 1 may be a side surface of the first encapsulation layer 18. In some embodiments, the first semiconductor chip 1 may not include the first encapsulation layer 18.

[0148] The second semiconductor chip 2 may be stacked on the first semiconductor chip 1 and may be electrically connected to the first semiconductor chip 1 by hybrid bonding or metal-to-metal bonding. The second semiconductor chip 2 may have a bottom surface 21 (e.g., a first surface), a top surface 22 (e.g., a second surface), and a side surface 23 extending between the bottom surface 21 and the top surface 22. The bottom surface 21 (e.g., the first surface) of the second semiconductor chip 2 may directly contact the top surface 12 of the first semiconductor chip 1. The side surface 23 of the second semiconductor chip 2 may be substantially aligned or aligned with the side surface 13 of the first semiconductor chip 1.

[0149] The second semiconductor chip 2 may include a second base 20, a second conductive structure 24, a second lower structure 25, a second upper structure 26, and a plurality of second conductive vias 27. The second semiconductor chip 2 may be a memory chip, such as a dynamic random access memory (DRAM) chip.

[0150] The second base 20 of the second semiconductor chip 2 may be the same as or similar to the first base 10 of the first semiconductor chip 1. The second base 20 may be a semiconductor substrate, for example, may include silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP) or other IV-IV, III-V or II-VI semiconductor materials. In some embodiments, the second base 20 may include a semiconductor insulator substrate, such as a silicon insulator (SOI) substrate, a silicon germanium insulator (SGOI) substrate or a germanium insulator (GOI) substrate. The second base 20 may have a first surface (such as a bottom surface) and a second surface (such as a top surface) opposite to the first surface. Figure 1 As shown, the width of the second base portion 20 of the second semiconductor chip 2 may be greater than the width of the first base portion 10 of the first semiconductor chip 1 .

[0151] The second conductive structure 24 of the second semiconductor chip 2 may be the same as or similar to the first conductive structure 14 of the first semiconductor chip 1. The second conductive structure 24 may be disposed on a first surface (e.g., a bottom surface) of the second base 20. In some embodiments, the second conductive structure 24 may include a plurality of front-end-of-line (FEOL) elements, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (pFETs), n-type field effect transistors (nFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, fin field effect transistors (FinFETs), other suitable integrated circuit elements, or combinations thereof. In some embodiments, the second conductive structure 24 may further include at least one back-end-of-line (BEOL) interconnect pattern, such as a plurality of patterned circuit layers electrically connected to the front-end-of-line (FEOL) elements. In some embodiments, the second conductive structure 24 may further include at least one dielectric layer or at least one dielectric structure covering the front-end-of-line (FEOL) elements and the back-end-of-line (BEOL) interconnect pattern. Figure 1 As shown, the width of the second conductive structure 24 of the second semiconductor chip 2 may be greater than the width of the first conductive structure 14 of the first semiconductor chip 1 .

[0152] The second conductive via 27 may extend through the second base 20 and may be electrically connected to the second conductive structure 24. In some embodiments, the bottom end of the second conductive via 27 may extend beyond the first surface (e.g., bottom surface) of the second base 20 and may extend into the second conductive structure 24. Therefore, the second conductive via 27 may be an integral structure, and the length of the second conductive via 27 may be greater than the thickness of the second base 20. In some embodiments, the top surface of the second conductive via 27 may be substantially coplanar with the second surface (e.g., top surface) of the second base 20. Therefore, the top surface of the second conductive via 27 may be exposed from the second surface (e.g., top surface) of the second base 20.

[0153] The second lower structure 25 of the second semiconductor chip 2 may be the same as or similar to the first lower structure 15 of the first semiconductor chip 1. The second lower structure 25 may be disposed on the second conductive structure 24. The second lower structure 25 may be a hybrid bonding (HB) structure and may include a second lower dielectric layer 251 and a plurality of second lower pads 252. The second lower dielectric layer 251 may be a hybrid bonding (HB) dielectric layer and may include SiO2, SiCN and / or SiON. Each second lower pad 252 may be a hybrid bonding (HB) pad and may include copper or aluminum. The second lower pad 252 may be embedded in the second lower dielectric layer 251 and may be exposed by the second lower dielectric layer 251. The second lower pad 252 may be surrounded by the second lower dielectric layer 251. The second lower pad 252 may be electrically connected to the back-end process (BEOL) interconnection pattern of the second conductive structure 24. Therefore, the second lower pad 252 may be electrically connected to the second conductive via 27 through the second conductive structure 24.

[0154] In some embodiments, the bottom surface of the second lower pad 252 may be substantially aligned with the bottom surface of the second lower dielectric layer 251. Therefore, the bottom surface of the second lower pad 252 may be exposed through the bottom surface of the second lower dielectric layer 251. In some embodiments, the top surface of the second lower pad 252 may be substantially aligned with the top surface of the second lower dielectric layer 251. Therefore, the top surface of the second lower pad 252 may contact the second conductive structure 24. In some embodiments, the thickness of the second lower pad 252 may be substantially equal to the thickness of the second lower dielectric layer 251.

[0155] like Figure 1As shown, the width of the second lower structure 25 of the second semiconductor chip 2 can be greater than the width of the first lower structure 15 of the first semiconductor chip 1. The second lower structure 25 of the second semiconductor chip 2 can be bonded and electrically connected to the first upper structure 16 of the first semiconductor chip 1 by hybrid bonding. For example, the second lower dielectric layer 251 of the second semiconductor chip 2 can be attached, bonded or adhered to the first upper dielectric layer 161 and the first packaging layer 18 of the first semiconductor chip 1. The second lower dielectric layer 251 of the second semiconductor chip 2 can be bonded to the first upper dielectric layer 161 of the first semiconductor chip 1 by dielectric-to-dielectric bonding. Therefore, the second semiconductor chip 2 can directly contact the first packaging layer 18 of the first semiconductor chip 1.

[0156] The second lower pad 252 of the second semiconductor chip 2 may be connected to the first upper pad 162 of the first semiconductor chip 1 by metal-to-metal bonding, or may be electrically connected to the first upper pad 162 of the first semiconductor chip 1. Therefore, the second lower pad 252 of the second semiconductor chip 2 may directly contact the first upper pad 162 of the first semiconductor chip 1. The width of the second lower pad 252 of the second semiconductor chip 2 may be substantially equal to the width of the first upper pad 162 of the first semiconductor chip 1. The second semiconductor chip 2 and the first semiconductor chip 1 may be in face-to-face contact.

[0157] The second upper structure 26 of the second semiconductor chip 2 may be the same as or similar to the first upper structure 16 of the first semiconductor chip 1. The second upper structure 26 may be disposed on a second surface (e.g., a top surface) of the second base 20. The second upper structure 26 may be a hybrid bonding (HB) structure or a solder bonding structure, and may include a second upper dielectric layer 261 and a plurality of second upper pads 262.

[0158] The second upper dielectric layer 261 may be a hybrid bonding (HB) dielectric layer and may include SiO2, SiCN and / or SiON. Each second upper pad 262 may be a hybrid bonding (HB) pad and may include copper or aluminum. The second upper pad 262 may be embedded in the second upper dielectric layer 261 and may be exposed through the second upper dielectric layer 261. The second upper pad 262 may be surrounded by the second upper dielectric layer 261. The second upper pad 262 may be electrically connected to the second conductive via 27. In some embodiments, the second upper pad 262 may directly contact the second conductive via 27. The second upper pad 262 may be electrically connected to the second lower pad 252 through the second conductive via 27 and the second conductive structure 24.

[0159] In some embodiments, the top surface of the second upper pad 262 may be substantially aligned with the top surface of the second upper dielectric layer 261. Therefore, the top surface of the second upper pad 262 may be exposed through the top surface of the second upper dielectric layer 261. In some embodiments, the bottom surface of the second upper pad 262 may be substantially aligned with the bottom surface of the second upper dielectric layer 261. Therefore, the bottom surface of the second upper pad 262 may contact the second conductive via 27. In some embodiments, the thickness of the second upper pad 262 may be substantially equal to the thickness of the second upper dielectric layer 261.

[0160] In some embodiments, the bottom surface 21 of the second semiconductor chip 2 may include the bottom surface of the second lower pad 252 and the bottom surface of the second lower dielectric layer 251. The top surface 22 of the second semiconductor chip 2 may include the top surface of the second upper pad 262 and the top surface of the second upper dielectric layer 261. The side surface 23 of the second semiconductor chip 2 may include the side surface of the second base 20, the side surface of the second conductive structure 24, the side surface of the second lower structure 25, and the side surface of the second upper structure 26. In some embodiments, the side surface of the second base 20, the side surface of the second conductive structure 24, the side surface of the second lower structure 25, and the side surface of the second upper structure 26 may be aligned or coplanar with each other.

[0161] The second package 72 can be stacked on the first package 71. The second package 72 can be spaced apart from the first package 71. The second package 72 may include a third semiconductor chip 3 and a fourth semiconductor chip 4 stacked on the third semiconductor chip 3, and electrically connected to the third semiconductor chip 3 by hybrid bonding. The second package 72 can be electrically connected to the first package 71 through a bump 61. The bump 61 may include a reflowable material such as AgSn. Therefore, the bump 61 may include a solder ball, a solder bump or a microbump. In addition, the bottom fill 62 may be arranged between the second package 72 and the first package 71, and may cover the bump 61.

[0162] The third semiconductor chip 3 may be stacked on the second semiconductor chip 2 and may be electrically connected to the second semiconductor chip 2 through the bumps 61. The third semiconductor chip 3 may have a bottom surface 31 (e.g., a first surface), a top surface 32 (e.g., a second surface), and a side surface 33 extending between the bottom surface 31 and the top surface 32. The bottom surface 31 (e.g., the first surface) of the third semiconductor chip 3 may be spaced a certain distance from the top surface 22 of the second semiconductor chip 2. The bottom fill 62 may be disposed between the bottom surface 31 of the third semiconductor chip 3 and the top surface 22 of the second semiconductor chip 2 to cover the bumps 61.

[0163] The third semiconductor chip 3 may be the same as or similar to the first semiconductor chip 1. The third semiconductor chip 3 may include a third base 30, a third conductive structure 34, a third lower structure 35, a third upper structure 36, a plurality of third conductive vias 37, and a third encapsulation layer 38. The third semiconductor chip 3 may be a memory chip, such as a dynamic random access memory (DRAM) chip.

[0164] The third base 30 of the third semiconductor chip 3 may be the same as or similar to the first base 10 of the first semiconductor chip 1. The third base 30 may have a first surface (eg, a bottom surface) and a second surface (eg, a top surface) opposite to the first surface. Figure 1 As shown, the width of the third base portion 30 of the third semiconductor chip 3 may be substantially equal to the width of the first base portion 10 of the first semiconductor chip 1 .

[0165] The third conductive structure 34 of the third semiconductor chip 3 may be the same as or similar to the first conductive structure 14 of the first semiconductor chip 1. The third conductive structure 34 may be disposed on a first surface (e.g., a bottom surface) of the third base 30. In some embodiments, the third conductive structure 34 may include a plurality of front-end-of-line (FEOL) elements and at least one back-end-of-line (BEOL) interconnection pattern. Figure 1 As shown, the width of the third conductive structure 34 of the third semiconductor chip 3 may be substantially equal to the first conductive structure 14 of the first semiconductor chip 1 .

[0166] The third conductive via 37 may extend through the third base 30 and may be electrically connected to the third conductive structure 34. In some embodiments, the bottom end of the third conductive via 37 may extend beyond the first surface (e.g., bottom surface) of the third base 30 and may extend into the third conductive structure 34. In some embodiments, the top surface of the third conductive via 37 may be substantially coplanar with the second surface (e.g., top surface) of the third base 30.

[0167] The third lower structure 35 of the third semiconductor chip 3 may be the same as or similar to the first lower structure 15 of the first semiconductor chip 1. The third lower structure 35 may be disposed on the third conductive structure 34. The third lower structure 35 may be a hybrid bonding (HB) structure or a solder bonding structure, and may include a third lower dielectric layer 351 and a plurality of third lower pads 352. The third lower dielectric layer 351 may be a hybrid bonding (HB) dielectric layer, and may include SiO2, SiCN and / or SiON. Each third lower pad 352 may be a hybrid bonding (HB) pad, and may include copper or aluminum. The third lower pad 352 may be embedded in the third lower dielectric layer 351, and may be exposed through the third lower dielectric layer 351. The third lower pad 352 may be electrically connected to the back-end process (BEOL) interconnection pattern of the third conductive structure 34. Therefore, the third lower pad 352 may be electrically connected to the third conductive via 37 through the third conductive structure 34.

[0168] like Figure 1 As shown, the width of the third lower structure 35 of the third semiconductor chip 3 may be substantially equal to the width of the first lower structure 15 of the first semiconductor chip 1. The third lower pad 352 of the third lower structure 35 of the third semiconductor chip 3 may be bonded and electrically connected to the second upper pad 262 of the second upper structure 26 of the second semiconductor chip 2 through the bump 61.

[0169] The third upper structure 36 of the third semiconductor chip 3 may be the same as or similar to the first upper structure 16 of the first semiconductor chip 1. The third upper structure 36 may be disposed on the second surface (e.g., top surface) of the third base 30. The third upper structure 36 may be a hybrid bonding (HB) structure and may include a third upper dielectric layer 361 and a plurality of third upper pads 362.

[0170] The third upper dielectric layer 361 may be a hybrid bonding (HB) dielectric layer and may include SiO2, SiCN and / or SiON. Each third upper pad 362 may be a hybrid bonding (HB) pad and may include copper or aluminum. The third upper pad 362 may be embedded in the third upper dielectric layer 361 and may be exposed through the third upper dielectric layer 361. The third upper pad 362 may be electrically connected to the third conductive via 37. In some embodiments, the third upper pad 362 may be electrically connected to the third lower pad 352 through the third conductive via 37 and the third conductive structure 34.

[0171] The third encapsulation layer 38 of the third semiconductor chip 3 may be the same as or similar to the first encapsulation layer 18 of the first semiconductor chip 1. The third encapsulation layer 38 may be disposed around the third base 30, the third conductive structure 34, the third lower structure 35, and the third upper structure 36. The third encapsulation layer 38 may cover and contact the side surfaces of the third base 30, the side surfaces of the third conductive structure 34, the side surfaces of the third lower structure 35, and the side surfaces of the third upper structure 36.

[0172] In some embodiments, the bottom surface 31 of the third semiconductor chip 3 may include a bottom surface of a third lower pad 352, a bottom surface of a third lower dielectric layer 351, and a bottom surface of a third encapsulation layer 38. The top surface 32 of the third semiconductor chip 3 may include a top surface of a third upper pad 362, a top surface of a third upper dielectric layer 361, and a top surface of a third encapsulation layer 38. The side surface 33 of the third semiconductor chip 3 may be a side surface of the third encapsulation layer 38. In some embodiments, the third semiconductor chip 3 may not include a third encapsulation layer 38.

[0173] The fourth semiconductor chip 4 may be stacked on the third semiconductor chip 3 and may be electrically connected to the third semiconductor chip 3 by hybrid bonding or metal-to-metal bonding. The fourth semiconductor chip 4 may have a bottom surface 41 (e.g., a first surface), a top surface 42 (e.g., a second surface), and a side surface 43 extending between the bottom surface 41 and the top surface 42. The bottom surface 41 (e.g., the first surface) of the fourth semiconductor chip 4 may directly contact the top surface 32 of the third semiconductor chip 3. The side surface 43 of the fourth semiconductor chip 4 may be substantially aligned or aligned with the side surface 33 of the third semiconductor chip 3.

[0174] The fourth semiconductor chip 4 may be the same as or similar to the second semiconductor chip 2. The fourth semiconductor chip 4 may include a fourth base 40, a fourth conductive structure 44, and a fourth lower structure 45. The fourth semiconductor chip 4 may be a memory chip, such as a dynamic random access memory (DRAM) chip.

[0175] The fourth base portion 40 of the fourth semiconductor chip 4 may be the same as or similar to the second base portion 20 of the second semiconductor chip 2. Figure 1 As shown, the width of the fourth base portion 40 of the fourth semiconductor chip 4 may be greater than the width of the third base portion 30 of the third semiconductor chip 3 . The thickness of the fourth base portion 40 of the fourth semiconductor chip 4 may be greater than the thickness of the third base portion 30 of the third semiconductor chip 3 .

[0176] The fourth conductive structure 44 of the fourth semiconductor chip 4 may be the same as or similar to the second conductive structure 24 of the second semiconductor chip 2. The fourth conductive structure 44 may be disposed on a first surface (e.g., a bottom surface) of the fourth base 40. In some embodiments, the fourth conductive structure 44 may include a plurality of front-end-of-line (FEOL) elements and at least one back-end-of-line (BEOL) interconnect pattern. Figure 1 As shown, the width of the fourth conductive structure 44 of the fourth semiconductor chip 4 may be greater than the width of the third conductive structure 34 of the third semiconductor chip 3 .

[0177] The fourth semiconductor chip 4 may or may not include a conductive via extending in the fourth base 40 and electrically connecting the fourth conductive structure 44 .

[0178] The fourth lower structure 45 of the fourth semiconductor chip 4 may be the same or similar to the third lower structure 35 of the third semiconductor chip 3. The fourth lower structure 45 may be disposed on the fourth conductive structure 44. The fourth lower structure 45 may be a hybrid bonding (HB) structure and may include a fourth lower dielectric layer 451 and a plurality of fourth lower pads 452. The fourth lower dielectric layer 451 may be a hybrid bonding (HB) dielectric layer and may include SiO2, SiCN and / or SiON. Each fourth lower pad 452 may be a hybrid bonding (HB) pad and may include copper or aluminum. The fourth lower pad 452 may be embedded in the fourth lower dielectric layer 451 and may be exposed by the fourth lower dielectric layer 451. The fourth lower pad 452 may be electrically connected to the back-end process (BEOL) interconnection pattern of the fourth conductive structure 44.

[0179] like Figure 1 As shown, the width of the fourth lower structure 45 of the fourth semiconductor chip 4 can be greater than the width of the third lower structure 35 of the third semiconductor chip 3. The fourth lower structure 45 of the fourth semiconductor chip 4 can be bonded and electrically connected to the third upper structure 36 of the third semiconductor chip 3 by hybrid bonding. For example, the fourth lower dielectric layer 451 of the fourth semiconductor chip 4 can be attached, bonded or adhered to the third upper dielectric layer 361 and the third packaging layer 38 of the third semiconductor chip 3. The fourth lower dielectric layer 451 of the fourth semiconductor chip 4 can be bonded to the third upper dielectric layer 361 of the third semiconductor chip 3 by dielectric-to-dielectric bonding. Therefore, the fourth semiconductor chip 4 can directly contact the third packaging layer 38 of the third semiconductor chip 3.

[0180] The fourth lower pad 452 of the fourth semiconductor chip 4 may be attached, joined or electrically connected to the third upper pad 362 of the third semiconductor chip 3 by metal-to-metal bonding. The fourth semiconductor chip 4 and the third semiconductor chip 3 may be in face-to-face contact.

[0181] In some embodiments, bottom surface 41 of fourth semiconductor chip 4 may include bottom surfaces of fourth lower pad 452 and fourth lower dielectric layer 451. Top surface 42 of fourth semiconductor chip 4 may include second surface (eg, top surface) of fourth base 40.

[0182] The base semiconductor chip 5 (or fifth semiconductor chip 5) may have a bottom surface 51 (e.g., a first surface), a top surface 52 (e.g., a second surface), and a side surface 53 extending between the bottom surface 51 and the top surface 52. The base semiconductor chip 5 may include a fifth base 50, a fifth conductive structure 54, a fifth upper structure 55, and a plurality of fifth conductive vias 57. The base semiconductor chip 5 may be a controller chip, such as an application processor (AP) chip.

[0183] The fifth base 50 may be a semiconductor substrate, for example, may include silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP) or other IV-IV, III-V or II-VI semiconductor materials. The fifth base 50 may have a first surface 501 (e.g., a top surface) and a second surface 502 (e.g., a bottom surface) opposite to the first surface 501.

[0184] The fifth conductive structure 54 may be disposed on the first surface 501 (eg, top surface) of the fifth base 50. In some embodiments, the fifth conductive structure 54 may include a plurality of front end of line (FEOL) elements and at least one back end of line (BEOL) interconnection pattern.

[0185] The fifth conductive via 57 may extend through the fifth base 50 and may be electrically connected to the fifth conductive structure 54. In some embodiments, one end of the fifth conductive via 57 may extend into the fifth conductive structure 54.

[0186] The fifth upper structure 55 may be disposed on the fifth conductive structure 54. The fifth upper structure 55 may be a hybrid bonding (HB) structure or a solder bonding structure, and may include a fifth upper dielectric layer 551 and a plurality of fifth upper pads 552. The fifth upper dielectric layer 551 may be a hybrid bonding (HB) dielectric layer, and may include SiO2, SiCN, and / or SiON. Each of the fifth upper pads 552 may be a hybrid bonding (HB) pad, and may include copper or aluminum. The fifth upper pad 552 may be embedded in the fifth upper dielectric layer 551, and may be exposed by the fifth upper dielectric layer 551. The fifth upper pad 552 may be electrically connected to a back-end-of-line (BEOL) interconnection pattern of the fifth conductive structure 54.

[0187] In some embodiments, bottom surface 51 of base semiconductor chip 5 may include second surface 502 (eg, bottom surface) of fifth base 50 . Top surface 52 of base semiconductor chip 5 may include top surfaces of fifth upper pad 552 and fifth upper dielectric layer 551 .

[0188] The first lower pad 152 of the first lower structure 15 of the first semiconductor chip 1 can be bonded and electrically connected to the fifth upper pad 552 of the fifth upper structure 55 of the base semiconductor chip 5 through the electrical connector 63. The electrical connector 63 may include a reflowable material such as AgSn. Therefore, the electrical connector 63 may include a solder ball, a solder bump or a microbump. In addition, a protective material 64 (such as a bottom filler) may be provided between the first semiconductor chip 1 and the base semiconductor chip 5, and may cover the electrical connector 63.

[0189] The peripheral encapsulation layer 65 may be a molding compound with or without filler. The peripheral encapsulation layer 65 may encapsulate the top surface 52 of the first semiconductor chip 1, the second semiconductor chip 2, the third semiconductor chip 3, the fourth semiconductor chip 4, and the base semiconductor chip 5. The peripheral encapsulation layer 65 may cover the side surface 13 of the first semiconductor chip 1, the side surface 23 of the second semiconductor chip 2, the side surface 33 of the third semiconductor chip 3, the side surface 43 of the fourth semiconductor chip 4, and the top surface 52 of the base semiconductor chip 5.

[0190] The external connector 66 may be disposed on the bottom surface 51 of the base semiconductor chip 5 for external connection. The external connector 66 may include a reflowable material, such as AgSn. Therefore, the external connector 66 may include a solder ball, a solder bump or a microbump. The external connector 66 may be disposed on the fifth conductive via 57.

[0191] exist Figure 1 In the illustrated embodiment, the thermal conductivity (or heat dissipation efficiency) of the bottom fill 62 may be greater than the thermal conductivity (or heat dissipation efficiency) of the second semiconductor chip 2. Figure 1 In the illustrated embodiment, the thermal conductivity (or heat dissipation efficiency) of the bottom fill 62 may be greater than the thermal conductivity (or heat dissipation efficiency) of the second semiconductor chip 2 (e.g., including the second base 20, the second conductive structure 24, the second lower structure 25, and the second upper structure 26) and the thermal conductivity (or heat dissipation efficiency) of the third semiconductor chip 3 (e.g., including the third base 30, the third conductive structure 34, the third lower structure 35, the third upper structure 36, and the third packaging layer 38). Therefore, the heat generated by the second semiconductor chip 2 and the third semiconductor chip 3 can be easily and quickly dissipated or transferred to the peripheral packaging layer 65 through the bottom fill 62.

[0192] In addition, the thermal conductivity (or heat dissipation efficiency) of the protective material 64 may be greater than the thermal conductivity (or heat dissipation efficiency) of the first semiconductor chip 1 (for example, including the first base 10, the first conductive structure 14, the first lower structure 15, the first upper structure 16 and the first packaging layer 18) and the thermal conductivity (or heat dissipation efficiency) of the base semiconductor chip 5. Therefore, the heat generated by the first semiconductor chip 1 can be easily and quickly dissipated or transferred to the peripheral packaging layer 65 through the protective material 64.

[0193] Therefore, the reliability and service life of the electronic component 6 can be improved.

[0194] Figure 2 1 is a cross-sectional view illustrating an electronic component 6a of some embodiments of the present disclosure. The electronic component 6a may be similar to Figure 1 The electronic components 6 in the embodiment are described below.

[0195] The electronic component 6a may also include a third package 71a and a fourth package 71b disposed between the first package 71 and the second package 72. The third package 71a and the fourth package 71b may be the same or similar to the first package 71. The third package 71a may include a sixth semiconductor chip 1a and a seventh semiconductor chip 2a that are the same or similar to the first semiconductor chip 1 and the second semiconductor chip 2, respectively. The third package 71a may be bonded and electrically connected to the first package 71 through a plurality of bumps. In addition, the fourth package 71b may include an eighth semiconductor chip 1b and a ninth semiconductor chip 2b that are the same or similar to the first semiconductor chip 1 and the second semiconductor chip 2, respectively. The fourth package 71b may be bonded and electrically connected to the third package 71a through a plurality of bumps. In addition, the second package 72 may be bonded and electrically connected to the fourth package 71b through a plurality of bumps. The peripheral package layer 65 may encapsulate the top surface 52 of the first semiconductor chip 1, the second semiconductor chip 2, the sixth semiconductor chip 1a, the seventh semiconductor chip 2a, the eighth semiconductor chip 1b, the ninth semiconductor chip 2b, the third semiconductor chip 3, the fourth semiconductor chip 4, and the base semiconductor chip 5.

[0196] Figure 3 2 is a cross-sectional view illustrating a semiconductor structure 9 according to some embodiments of the present disclosure. The semiconductor structure 9 may include an interposer 8, an electronic component 6, a semiconductor component 92, and a plurality of external connectors 96.

[0197] The interposer 8 may include a base 80, a conductive structure 84, an upper structure 85, and a plurality of conductive vias 87. The base 80 may be a semiconductor substrate, for example, may include silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials.

[0198] The conductive structure 84 may be disposed on the base 80 . In some embodiments, the conductive structure 84 may include a redistribution layer (RDL) structure. The conductive via 87 may extend through the base 80 and may be electrically connected to the conductive structure 84 .

[0199] The upper structure 85 may be disposed on the conductive structure 84. The upper structure 85 may include a dielectric layer 851 and a plurality of pads 852. The dielectric layer 851 may be a solder mask layer. The pads 852 may be embedded in the dielectric layer 851 and may be exposed through the dielectric layer 851.

[0200] External connector 96 may be disposed on the bottom surface of interposer 8 for external connection. External connector 96 may include a reflowable material such as AgSn. Therefore, external connector 96 may include a solder ball, a solder bump, or a microbump. External connector 96 may be disposed on conductive via 87.

[0201] Fig. 9 The electronic component 6 may be Figure 1 The electronic component 6 in the embodiment of the present invention can be bonded and electrically connected to the pad 852 of the interposer 8 through the external connector 66.

[0202] The semiconductor element 92 may be a logic chip or a logic die. The semiconductor element 92 may be bonded and electrically connected to the pads 852 of the interposer 8 through a plurality of solders 94. Therefore, the electronic component 6 may be electrically connected to the semiconductor element 92 through the interposer 8.

[0203] Figures 4 to 19 2 is a cross-sectional view illustrating various stages of a method for preparing an electronic component 6 according to some embodiments of the present disclosure.

[0204] See also Figures 4 to 12 , a first package 71 including a first semiconductor chip 1 and a second semiconductor chip 2 may be provided. The preparation process of the first package 71 is as follows.

[0205] See also Figure 4 , a first wafer 1 ′ may be provided. The first wafer 1 ′ may include a first base 10 , a first conductive structure 14 , a first lower structure 15 and a plurality of first conductive vias 17 . Figure 4 The first base 10, the first conductive structure 14, the first lower structure 15 and the first conductive via 17 can be respectively Figure 1 The first base 10, the first conductive structure 14, the first lower structure 15 and the first conductive via 17 are the same or similar. The first wafer 1' may define a plurality of separation lines 19. The first base 10 may have a first surface 101 (e.g., a bottom surface) and a second surface 102 (e.g., a top surface) opposite to the first surface 101.

[0206] The first conductive structure 14 may be disposed on the first surface 101 (e.g., the bottom surface) of the first base 10. The first conductive via 17 may extend in the first base 10 and may be electrically connected to the first conductive structure 14. The first lower structure 15 may be disposed on the first conductive structure 14. The first lower structure 15 may include a first lower dielectric layer 151 and a plurality of first lower pads 152. The first lower pads 152 may be embedded in the first lower dielectric layer 151 and may be exposed by the first lower dielectric layer 151.

[0207] See also Figure 5, the first base 10 may be thinned from its second surface 102 (e.g., top surface) to expose the first conductive via 17. Then, the first upper structure 16 may be formed on the second surface 102 (e.g., top surface) of the first base 10. The first upper structure 16 may include a first upper dielectric layer 161 and a plurality of first upper pads 162. The first upper pads 162 may be embedded in the first upper dielectric layer 161 and may be exposed by the first upper dielectric layer 161. The first upper pads 162 may be electrically connected to the first conductive via 17.

[0208] See also Figure 6 , the first wafer 1' can be separated along separation lines 19 to form a plurality of units 1". The unit 1" has a bottom surface 11" (eg, a first surface), a top surface 12" (eg, a second surface), and a side surface 13" extending between the bottom surface 11" and the top surface 12".

[0209] See also Figure 7 , a second wafer 2 ′ may be provided. The second wafer 2 ′ may include a second base 20 , a second conductive structure 24 , a second lower structure 25 and a plurality of second conductive vias 27 . Figure 7 The second base 20, the second conductive structure 24, the second lower structure 25 and the second conductive through hole 27 can be respectively Figure 1 The second base 20, the second conductive structure 24, the second lower structure 25 and the second conductive via 27 are the same or similar. The second base 20 may have a first surface 201 (eg, a bottom surface) and a second surface 202 (eg, a top surface) opposite to the first surface 201.

[0210] The second conductive structure 24 may be disposed on the first surface 201 (e.g., the bottom surface) of the second base 20. The second conductive via 27 may extend in the second base 20 and may be electrically connected to the second conductive structure 24. The second lower structure 25 may be disposed on the second conductive structure 24. The second lower structure 25 may include a second lower dielectric layer 251 and a plurality of second lower pads 252. The second lower pads 252 may be embedded in the second lower dielectric layer 251 and may be exposed from the second lower dielectric layer 251.

[0211] See also Figure 8 , multiple units 1" can be attached to the second wafer 2' by hybrid bonding. The first upper dielectric layer 161 of the unit 1" can be attached, bonded or adhered to the second lower dielectric layer 251 of the second wafer 2' by dielectric-to-dielectric bonding. The first upper pad 162 of the unit 1" can be attached, bonded or electrically connected to the second lower pad 252 of the second wafer 2' by metal-to-metal bonding.

[0212] See also Fig. 9, a first encapsulation layer 18 may be formed or disposed on the second lower structure 25 to cover the unit 1". The first encapsulation layer 18 may have a first surface 181 (e.g., a bottom surface) and a second surface 182 (e.g., a top surface) opposite to the first surface 181. The second surface 182 of the first encapsulation layer 18 may contact the second lower structure 25. The first surface 181 of the first encapsulation layer 18 may be lower than the bottom surface 11" of the unit 1". Therefore, the first encapsulation layer 18 may cover the side surface 13" and the bottom surface 11" of the unit 1".

[0213] See also Fig.10 , the second base 20 may be thinned from its second surface 202 (e.g., top surface) to expose the second conductive via 27. Then, a second upper structure 26 may be formed on the second surface 202 (e.g., top surface) of the second base 20. The second upper structure 26 may include a second upper dielectric layer 261 and a plurality of second upper pads 262. The second upper pads 262 may be embedded in the second upper dielectric layer 261 and may be exposed from the second upper dielectric layer 261. The second upper pads 262 may be electrically connected to the second conductive via 27.

[0214] See also Fig.11 , the first packaging layer 18 can be thinned starting from its first surface 181 (e.g., bottom surface) to expose the unit 1". The first surface 181 (e.g., bottom surface) of the first packaging layer 18 can be substantially coplanar with the bottom surface 11" of the unit 1". Then, a plurality of electrical connectors 63 can be formed or set on the first lower pad 152 of the first lower structure 15 of the unit 1". The electrical connectors 63 may include a reflowable material, such as AgSn. At the same time, the second wafer 2' and the first packaging layer 18 can define a plurality of separation lines 29.

[0215] See also Fig.12 , the second wafer 2' and the first packaging layer 18 can be separated along the separation line 29 to form a plurality of first packages 71. The first package 71 may include a first semiconductor chip 1 and a second semiconductor chip 2 stacked on the first semiconductor chip 1 and electrically connected to the first semiconductor chip 1 through hybrid bonding. The first semiconductor chip 1 may include a cell 1" and a first packaging layer 18. The second semiconductor chip 2 may be a portion separated from the second wafer 2'. Fig.12 The first package 71 can be connected with Figure 1 The first package 71 is the same or similar.

[0216] See also Figures 13 to 18 , a second package 72 including the third semiconductor chip 3 and the fourth semiconductor chip 4 may be provided. The preparation process of the second package 72 is as follows.

[0217] See also Fig.13, a fourth wafer 4 ′ may be provided. The fourth wafer 4 ′ may include a fourth base 40 , a fourth conductive structure 44 and a fourth lower structure 45 . Fig.13 The fourth base 40, the fourth conductive structure 44 and the fourth lower structure 45 in the Figure 1 The fourth base 40, the fourth conductive structure 44 and the fourth lower structure 45 are the same or similar.

[0218] The fourth conductive structure 44 may be disposed on the first surface 401 (e.g., the bottom surface) of the fourth base portion 40. The fourth lower structure 45 may be disposed on the fourth conductive structure 44. The fourth lower structure 45 may include a fourth lower dielectric layer 451 and a plurality of fourth lower pads 452. The fourth lower pads 452 may be embedded in the fourth lower dielectric layer 451 and may be exposed from the fourth lower dielectric layer 451.

[0219] See also Fig.14 , a plurality of cells 3" may be provided. The cells 3" may be the same as or similar to the cells 1". The cells 3" may have a bottom surface 31" (e.g., a first surface), a top surface 32" (e.g., a second surface), and a side surface 33" extending between the bottom surface 31" and the top surface 32". The third semiconductor chip 3 may be the same as or similar to the first semiconductor chip 1. The cells 3" may include a third base 30, a third conductive structure 34, a third lower structure 35, a third upper structure 36, and a plurality of third conductive vias 37, which are respectively connected to the third conductive vias 37. Figure 1 The third base 30, the third conductive structure 34, the third lower structure 35, the third upper structure 36 and the third conductive via 37 are the same or similar.

[0220] See also Fig.15 , the unit 3" can be attached to the fourth wafer 4' by hybrid bonding. The third upper dielectric layer 361 of the unit 3" can be attached, bonded or adhered to the fourth lower dielectric layer 451 of the fourth wafer 4' by dielectric-to-dielectric bonding. The third upper pad 362 of the unit 3" can be attached, bonded or electrically connected to the fourth lower pad 452 of the fourth wafer 4' by metal-to-metal bonding.

[0221] See also Fig.16 , a third encapsulation layer 38 may be formed or disposed on the fourth lower structure 45 to cover the unit 3". The third encapsulation layer 38 may have a first surface 381 (e.g., a bottom surface) and a second surface 382 (e.g., a top surface) opposite to the first surface 381. The second surface 382 of the third encapsulation layer 38 may contact the fourth lower structure 45. The third encapsulation layer 38 may cover the side surface 33" and the bottom surface 31" of the unit 3.

[0222] Then, the third encapsulation layer 38 may be thinned from its first surface 381 (eg, bottom surface) to expose the cell 3 ″. The first surface 381 (eg, bottom surface) of the third encapsulation layer 38 may be substantially coplanar with the bottom surface 31 ″ of the cell 3 ″.

[0223] See also Fig.17 A plurality of bumps 61 may be formed or disposed on the third lower pad 352 of the third lower structure 35 of the unit 3 ″. The bumps 61 may include a reflowable material, such as AgSn. Meanwhile, the fourth wafer 4 ′ and the third packaging layer 38 may define a plurality of separation lines 49 .

[0224] See also Fig.18 , the fourth wafer 4' and the third packaging layer 38 can be separated along the separation line 49 to form a plurality of second packages 72. The second package 72 may include a third semiconductor chip 3 and a fourth semiconductor chip 4 stacked on the third semiconductor chip 3 and electrically connected to the third semiconductor chip 3 by hybrid bonding. The third semiconductor chip 3 may include a unit 3" and a third packaging layer 38. The fourth semiconductor chip 4 may be a portion separated from the fourth wafer 4'. Fig.18 The second package 72 can be connected with Figure 1 The second package 72 in is the same or similar.

[0225] See also Fig.19 , the second package 72 may be bonded and electrically connected to the first package 71 through the bumps 61. Then, an underfill 62 may be formed or disposed in a space between the second package 72 and the first package 71 to cover the bumps 61.

[0226] Then, the first package 71 and the second package 72 may be bonded and electrically connected to the base semiconductor chip 5 through the electrical connector 63. Then, a protective material 64 may be formed or disposed between the first semiconductor chip 1 and the base semiconductor chip 5 to cover the electrical connector 63.

[0227] Then, a peripheral encapsulation layer 65 may be formed to encapsulate the top surface 52 of the first semiconductor chip 1, the second semiconductor chip 2, the third semiconductor chip 3, the fourth semiconductor chip 4, and the base semiconductor chip 5, thereby obtaining Figure 1 Electronic components 6.

[0228] Fig. 20 is a flow chart illustrating a method 900 for preparing an electronic component 6 according to some embodiments of the present disclosure.

[0229] In some embodiments, the preparation method 900 may include step S901, providing a first package, including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip through hybrid bonding. Fig.12As shown, a first package 71 may be provided. The first package 71 includes a first semiconductor chip 1 and a second semiconductor chip 2 stacked on a first semiconductor chip 1 and electrically connected to the first semiconductor chip 1 through hybrid bonding.

[0230] In some embodiments, the preparation method 900 may include step S902, providing a second package including a third semiconductor chip and a fourth semiconductor chip stacked on the third semiconductor chip and electrically connected to the third semiconductor chip through hybrid bonding. Fig.18 As shown, a second package 72 may be provided. The second package 72 includes a third semiconductor chip 3 and a fourth semiconductor chip 4 stacked on the third semiconductor chip 3 and electrically connected to the third semiconductor chip 3 through hybrid bonding.

[0231] In some embodiments, the preparation method 900 may include step S903, electrically connecting the second package to the first package through a plurality of bumps. Fig.19 As shown, the second package 72 may be electrically connected to the first package 71 via a plurality of bumps 61 .

[0232] One aspect of the present disclosure provides an electronic component, including a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip and electrically connected to the first semiconductor chip through hybrid bonding. The third semiconductor chip is stacked on the second semiconductor chip and electrically connected to the second semiconductor chip through a plurality of bumps.

[0233] Another aspect of the present disclosure provides an electronic component including a first package and a second package. The first package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip through hybrid bonding. The second package includes a third semiconductor chip and a fourth semiconductor chip stacked on the third semiconductor chip and electrically connected to the third semiconductor chip through hybrid bonding. The second package is electrically connected to the first package through a plurality of bumps.

[0234] Another aspect of the present disclosure provides a preparation method. The preparation method includes providing a first package, including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip through hybrid bonding; providing a second package, including a third semiconductor chip and a fourth semiconductor chip stacked on the third semiconductor chip and electrically connected to the third semiconductor chip through hybrid bonding; and electrically connecting the second package to the first package through a plurality of bumps.

[0235] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the concept and scope of the present disclosure defined by the claims. For example, many of the above processes can be implemented in different ways, and other processes, or combinations thereof, can be used to replace many of the above processes.

[0236] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, material compositions, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, material compositions, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, these processes, machines, manufactures, material compositions, means, methods, or steps are included in the claims of the present application.

Claims

1. An electronic component, comprising: a first semiconductor chip; a second semiconductor chip configured to be stacked on the first semiconductor chip and electrically connected to the first semiconductor chip through hybrid bonding; as well as A third semiconductor chip is configured to be stacked on the second semiconductor chip and electrically connected to the second semiconductor chip through a plurality of bumps. 2 . The electronic component as claimed in claim 1 , wherein a bottom surface of the second semiconductor chip contacts a top surface of the first semiconductor chip. 3 . The electronic component as claimed in claim 1 , wherein a bottom surface of the third semiconductor chip is spaced apart from a top surface of the second semiconductor chip. 4 . The electronic component as claimed in claim 3 , further comprising an underfill disposed between the bottom surface of the third semiconductor chip and the top surface of the second semiconductor chip to cover the plurality of bumps. 5 . The electronic component as claimed in claim 1 , wherein the first semiconductor chip comprises a first base and a first packaging layer disposed around the first base.

6. The electronic component as claimed in claim 5, wherein the first semiconductor chip further comprises: A first conductive structure is disposed on a first surface of the first base; a first lower structure disposed on the first conductive structure; as well as A first upper structure is disposed on a second surface of the first base, and the second surface is opposite to the first surface of the first base.

7. An electronic component as described in claim 6, wherein the first semiconductor chip also includes a plurality of first conductive vias extending through the first base, wherein the first lower structure includes a first lower dielectric layer and a plurality of first lower pads embedded in the first lower dielectric layer and exposed by the first lower dielectric layer, and the plurality of first lower pads are electrically connected to the plurality of first conductive vias through the first conductive structure. 8 . The electronic component as claimed in claim 7 , wherein the plurality of first conductive vias extend to the first conductive structure.

9. The electronic component as claimed in claim 7, wherein the first upper structure comprises a first upper dielectric layer and a plurality of first upper pads embedded in the first upper dielectric layer and exposed from the first upper dielectric layer, and the plurality of first upper pads are in contact with the plurality of first conductive vias. 10 . The electronic component as claimed in claim 1 , further comprising a fourth semiconductor chip stacked on the third semiconductor chip and electrically connected to the third semiconductor chip through hybrid bonding.

11. An electronic component comprising: A first package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip through hybrid bonding; as well as A second package includes a third semiconductor chip and a fourth semiconductor chip stacked on the third semiconductor chip and electrically connected to the third semiconductor chip through hybrid bonding, wherein the second package is electrically connected to the first package through a plurality of bumps.

12. The electronic component of claim 11, wherein the plurality of bumps comprise a reflowable material. 13 . The electronic component as claimed in claim 11 , further comprising a bottom filler disposed between the second package and the first package and covering the plurality of bumps. 14 . The electronic component of claim 11 , wherein the second semiconductor chip is in face-to-face contact with the first semiconductor chip, the fourth semiconductor chip is in face-to-face contact with the third semiconductor chip, and the first package is spaced apart from the second package.

15. The electronic component as claimed in claim 11, wherein the first semiconductor chip comprises: a first base; A first conductive structure is disposed on a first surface of the first base; a first lower structure disposed on the first conductive structure; as well as A first upper structure is disposed on a second surface of the first base, and the second surface is opposite to the first surface of the first base; The second semiconductor chip includes: a second base; A second conductive structure is disposed on the second base; a second lower structure disposed on the second conductive structure; and A second upper structure is disposed on the second base. 16 . The electronic component as claimed in claim 15 , wherein the first semiconductor chip further comprises a first packaging layer disposed to surround the first base, the first conductive structure, the first lower structure and the first upper structure, wherein the second semiconductor chip contacts the first packaging layer.

17. The electronic component as claimed in claim 11, wherein the third semiconductor chip comprises: a third base; a third conductive structure disposed on the third base; a third lower structure disposed on the third conductive structure; as well as a third upper structure disposed on the third base; The fourth semiconductor chip includes: a fourth base; a fourth conductive structure disposed on the fourth base; and A fourth lower structure is disposed on the fourth conductive structure. 18 . The electronic component as claimed in claim 17 , wherein the third semiconductor chip further comprises a third packaging layer disposed to surround the third base, the third conductive structure, the third lower structure and the third upper structure, wherein the fourth semiconductor chip contacts the third packaging layer.

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