Preparation method of semiconductor device of micro gate field plate for radio frequency

Abstract

The invention discloses a preparation method of a semiconductor device of a micro gate field plate for radio frequency. The preparation method comprises the following steps: providing a heterogeneous crystal circle; depositing a passivation layer on the surface of the heterogeneous crystal circle, depositing a dielectric layer on the surface of the passivation layer, and depositing a hard mask layer on the surface of the dielectric layer; etching the hard mask layer, the dielectric layer and the passivation layer to form a gate groove; corroding the dielectric layer on which the gate groove is formed, so that a partial region of the gate groove is expanded on the dielectric layer; the size of the gate groove in the dielectric layer is equal to the length of the micro field plate; corroding off the hard mask layer; photoetching a gate region on the surface of the dielectric layer and in the gate groove, depositing gate metal in the gate region, evaporating the gate metal, and stripping to form a gate; and corroding the dielectric layer to form the micro field plate grid. According to the invention, the preparation process of the micro field plate grid can be simplified.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology, and in particular relates to a method for preparing a semiconductor device of a radio frequency micro-gate field plate. Background Art

[0002] In recent years, as the radio frequency of 5G and 6G wireless communication systems has entered the millimeter wave frequency band and expanded to the higher frequency range of the terahertz band, challenges have been posed to the comprehensive characteristics of the device, such as frequency characteristics and power density. In order to achieve higher application frequencies of devices, the frequency characteristics of the device can be improved by reducing the gate length of the HEMT device, using N+GaN regrowth to reduce parasitic resistance, shortening the source-drain spacing, etc.; however, non-ideal factors such as current collapse and breakdown voltage related to the peak electric field between the gate and the drain limit the improvement of power density.

[0003] GaN HEMT devices can use a field plate structure connected to the gate to improve power density characteristics. The gate field plate structure can optimize the peak electric field distribution from the gate to the drain, effectively reducing the current collapse and knee voltage drift phenomenon. However, the longer gate field plate leads to an increase in gate-drain capacitance. Although the characteristic frequency fT is mainly limited by the gate-source capacitance, the larger gate-drain capacitance also reduces fT, which inhibits the improvement of high-frequency performance. In order to improve the device breakdown characteristics and output power density, while minimizing the impact on frequency performance, a micro-gate field plate structure with a T-type gate combined with a gate cap is currently used. This structure is usually completed by multiple electron beam lithography. For example: the first photolithography of the gate groove, the second use of three layers of photoresist, and the layered photolithography of the field plate and gate cap. This process requires high-precision photolithography overlay technology, the number of photoresist layers is large, the exposure and development are complex, the process is difficult, and it takes a long time. There are problems such as high cost and difficulty in large-scale application.

[0004] Therefore, there is an urgent need to provide a method for preparing a semiconductor device with a micro gate field plate to solve the defects of the above-mentioned prior art. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a method for preparing a semiconductor device of a micro-gate field plate for radio frequency. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] In a first aspect, the present invention provides a method for preparing a semiconductor device of a radio frequency micro-gate field plate, comprising:

[0007] Providing a heterogeneous crystal circle;

[0008] Depositing a passivation layer on the surface of the heterogeneous crystal circle, depositing a dielectric layer on the surface of the passivation layer, and depositing a hard mask layer on the surface of the dielectric layer;

[0009] Etching the hard mask layer, the dielectric layer and the passivation layer to form a gate groove;

[0010] The dielectric layer forming the gate groove is corroded so that a part of the gate groove is extended in the dielectric layer; the size of the gate groove in the dielectric layer is the length of the micro field plate;

[0011] etching away the hard mask layer;

[0012] Photolithography of a gate region is performed on the surface of the dielectric layer and in the gate groove, a gate metal is deposited in the gate region, and the gate metal is evaporated and then peeled off to form a gate;

[0013] The dielectric layer is etched away to form a micro field plate gate.

[0014] Beneficial effects of the present invention:

[0015] The present invention provides a method for preparing a semiconductor device of a micro-gate field plate for radio frequency. The method utilizes the different properties of dry and wet etching of the three-layer materials of the hard mask layer, the dielectric layer, and the passivation layer. By etching different materials, the micro-field plate structure is formed by one-time photolithography, which simplifies the production steps of the micro-field plate gate and reduces the process difficulty. In addition, the process is in line with the current mainstream production line capacity of GaN and III-V compound semiconductors, and can effectively realize the combination of high frequency characteristics and power characteristics of GaN HEMT devices.

[0016] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of a micro field plate gate preparation process provided by the prior art;

[0018] Figure 2 It is another schematic diagram of the micro field plate gate preparation process provided by the prior art;

[0019] Figure 3 It is a flow chart of a method for preparing a semiconductor device of a radio frequency micro-gate field plate provided by an embodiment of the present invention;

[0020] Figures 4a to 4f It is a schematic diagram of a method for preparing a semiconductor device of a radio frequency micro-gate field plate provided by an embodiment of the present invention;

[0021] Figures 5a to 5g It is a schematic diagram of a method for preparing a semiconductor device of a radio frequency micro-gate field plate provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0023] In the prior art, such as Figure 1 As shown, first prepare a wafer with an AlGaN / GaN heterojunction on the surface, deposit a dielectric passivation layer on the surface, and apply an electron beam special anti-etching agent; then use electron beam lithography to expose and develop the gate groove, and etch the dielectric to remove the anti-etching agent to make a gate groove structure on the dielectric layer; then apply three layers of electron beam anti-etching agent on the wafer surface, and use electron beam lithography to make the three layers of electron beam anti-etching agent present three different sizes of windows: medium, large, and small, and finally deposit metal to form a micro field plate gate structure. The size of the micro field plate depends on the size of the minimum window. Use such as Figure 1 The preparation method requires two electron beam lithography processes, which is costly and time-consuming, and is not conducive to large-scale use; and precise alignment is required between the two lithography processes. For example, for a micro field plate width of 50nm, it is necessary to ensure that the position of the second electron beam lithography is no more than 50nm relative to the position of the first lithography pattern, which places great demands on the overlay accuracy of the lithography and also leads to a decrease in the yield rate. When using electron beam lithography grid caps and micro field plates, three layers of photoresist need to be used at the same time. Such a multi-layer photoresist causes the total superimposed photoresist thickness to be too thick, often reaching about 1um. During the exposure process, the electron beam current will scatter in the photoresist, and the excessive thickness of the photoresist will also cause greater scattering, causing the pattern to expand to a certain extent. In order to fully develop the photoresist at the bottom layer, it often leads to serious over-development, and the pattern expansion is more serious, further increasing the process difficulty.

[0024] like Figure 2 As shown, first prepare a wafer with an AlGaN / GaN heterojunction on the surface, deposit a dielectric passivation layer, a sacrificial layer and an etch stop layer on the surface in sequence, use photolithography technology to make a photoresist groove on the surface, and etch the gate groove to the dielectric passivation layer; then use PECVD to deposit a dielectric layer on the surface, and the dielectric layer can be attached to the side wall of the gate groove; then use ICP dry etching to etch the wafer surface, first etch off the surface deposited in the previous step and the dielectric layer at the bottom of the groove, and then etch off the dielectric passivation layer at the bottom of the groove. Since the side wall is relatively thick, the dielectric layer attached to the side wall is retained; finally, the dielectric layer and the etch stop layer attached to the side wall are etched away to form a micro field plate structure, and then the gate cap is photolithographically processed, and the metal is evaporated to produce a micro field plate gate, and the sacrificial layer is etched away. Use such as Figure 2In the preparation method, a total of four dielectric layers are deposited, and the dry and wet etching options of the four dielectric layers are different. For example, the passivation dielectric layer needs to have etching selectivity relative to the sacrificial layer and the etching stop layer; the dielectric layer needs to have etching selectivity relative to the etching stop layer, and the etching stop layer and the dielectric layer need to have etching selectivity relative to the sacrificial layer, which greatly increases the complexity of the etching process. In addition, the length of the final gate is equal to the length of the first-step gate groove minus the width of the fourth-step sidewall; the length of the micro-field plate is equal to the width of the fourth-step sidewall plus the width of the final gate. If the length of the final gate needs to be fixed and the length of the micro-field plate needs to be optimized, the length of the first-step gate groove and the thickness of the sidewall (i.e., the thickness of the deposited dielectric layer and the lateral etching width) need to be changed at the same time, without using parameter optimization.

[0025] In view of this, in order to address the shortcomings of the prior art in that the micro field plate photolithography process is difficult and time-consuming, the present invention provides a method for preparing a semiconductor device with a micro gate field plate for radio frequency, wherein three layers of passivation, dielectric, and hard mask materials are deposited above the heterojunction, and the micro gate field plate is manufactured by wet etching of the intermediate layer material after photolithography, thereby forming a micro field plate structure by one-time photolithography, simplifying the steps of manufacturing the micro field plate gate, reducing the process difficulty, and being able to effectively achieve the combination of high frequency characteristics and power characteristics of GaN HEMT devices.

[0026] See also Figure 3 and Figure 4a to Figure 4f , Figure 3 is a flow chart of a method for preparing a semiconductor device of a radio frequency micro-gate field plate provided by an embodiment of the present invention, Figures 4a to 4f 1 is a schematic diagram of a method for preparing a semiconductor device with a micro-gate field plate for radio frequency provided by an embodiment of the present invention. The method for preparing a semiconductor device with a micro-gate field plate for radio frequency provided by the present invention comprises:

[0027] S101, providing a heterogeneous crystal circle.

[0028] Specifically, in this embodiment, the heterogeneous crystal wafer includes a stacked substrate, a gallium nitride layer, and a barrier layer.

[0029] S102, depositing a passivation layer on the surface of the heterogeneous crystal circle, depositing a dielectric layer on the surface of the passivation layer, and depositing a hard mask layer on the surface of the dielectric layer, such as Figure 4a shown.

[0030] Specifically, see Figure 4a In this embodiment, a passivation layer, a dielectric layer and a hard mask layer are sequentially deposited on the surface of the AlGaN / GaN heterogeneous crystal circle. The hard mask layer can use one or more metals such as aluminum, nickel, titanium, tungsten, etc., the passivation layer can be a silicon nitride layer or an aluminum oxide layer, and the dielectric layer can be a silicon dioxide layer.

[0031] S103, etching the hard mask layer, the dielectric layer and the passivation layer to form a gate groove, such as Figure 4b shown.

[0032] Specifically, see Figure 4b In this embodiment, a gate groove is etched on the surface of the wafer using photolithography and etching technology.

[0033] An optional method is to coat a photoresist on the surface of the hard mask layer in consideration of the etching depth, and to sequentially etch the hard mask layer, the dielectric layer and the passivation layer using a photolithography and etching process to form a gate groove.

[0034] Another optional method is to coat a photoresist on the surface of the hard mask layer and etch the hard mask layer using a photolithography etching process;

[0035] The photoresist coated on the surface of the hard mask layer is removed, and a photolithography and etching process is used to etch the dielectric layer and the passivation layer using the hard mask layer to form a gate groove.

[0036] In an optional embodiment, F-based plasma is used to etch the dielectric layer and the passivation layer.

[0037] It should be noted that when the dielectric layer and the passivation layer are etched using F-based plasma, the barrier layer will not be etched.

[0038] S104, etching the dielectric layer forming the gate groove so that a part of the gate groove is extended in the dielectric layer; the size of the gate groove in the dielectric layer is the length of the micro field plate, such as Figure 4c shown.

[0039] Specifically, see Figure 4c In this embodiment, BOE etching solution is used to etch the middle dielectric layer from the gate groove to make it expand laterally. The concentration of the etching solution and the etching time are controlled to control the length of the lateral expansion. The length of the lateral expansion is the length of the micro field plate.

[0040] It should be noted that the BOE etching solution is selective to the passivation layer and the hard mask layer, and has relatively weak corrosion to the passivation layer and the hard mask layer materials; in this embodiment, the BOE etching solution is a buffered oxide etchant (Boe 6:1 concentration), and is diluted as needed in actual use.

[0041] This embodiment cleverly utilizes the different selectivity of wet etching to dielectrics and passivation and hard masks, and manufactures a micro field plate structure on a wafer through photolithography, etching and corrosion. Compared with the prior art solution that uses three layers of photoresist to layeredly expose the gate cap and the micro field plate, which is prone to the disadvantage of pattern expansion, this embodiment can reduce the difficulty of the process while making it easy to control the length of the micro field plate.

[0042] It should be noted that the corresponding etching scheme is selected according to the materials of the dielectric layer and the passivation layer. When BoE wet etching is used, a lot of the dielectric layer will be etched away, and the passivation layer will basically not change, or the change is very small, for example, the etching selectivity (rate ratio) is 1:10.

[0043] S105, etching away the hard mask layer, such as Figure 4d shown.

[0044] Specifically, see Figure 4d In this embodiment, other etching solutions are used to etch away the hard mask layer, and the etching solution is selected according to the material of the hard mask layer; for example, if nickel metal is used as the hard mask layer, FeCl3 solution can be used as the etching solution.

[0045] S106, photolithography a gate region on the surface of the dielectric layer and in the gate groove, depositing a gate metal in the gate region, evaporating the gate metal and then peeling it off to form a gate, such as Figure 4e shown.

[0046] Specifically, see Figure 4e In this embodiment, the gate is first photolithographically processed, and the gate metal is evaporated and then peeled off.

[0047] In this embodiment, after preparing the micro field plate structure, the hard mask layer is etched away, and the gate is directly photolithographically evaporated to produce a micro field plate gate; that is, a micro field plate structure is etched on the basis of the gate groove, and then the micro field plate gate is directly formed. There is no need to perform high-precision photolithography overlay of the micro field plate structure on the gate groove, which reduces the process difficulty, saves cost, and increases the yield rate.

[0048] S107, etching away the dielectric layer to form a micro field plate gate, such as Figure 4f shown.

[0049] Specifically, see Figure 4f In this embodiment, BOE etching solution is used to etch away the dielectric layer to reduce parasitic capacitance and form a micro field plate gate.

[0050] In summary, the present invention provides a method for preparing a semiconductor device of a micro-gate field plate for radio frequency, which utilizes the different properties of dry and wet etching of the three-layer materials of the hard mask layer, the dielectric layer, and the passivation layer, and forms a micro-field plate structure by one-time photolithography through etching of different materials, thereby simplifying the production steps of the micro-field plate gate and reducing the process difficulty. In addition, the process is in line with the current mainstream production line capacity of GaN and III-V compound semiconductors, and can effectively realize the combination of high frequency characteristics and power characteristics of GaN HEMT devices.

[0051] In an optional embodiment of the present invention, a semiconductor device of a micro-field plate is prepared by the following steps, specifically:

[0052] S101, providing a heterogeneous crystal circle.

[0053] Specifically, in this embodiment, the heterogeneous crystal wafer includes a stacked substrate, a gallium nitride layer, and a barrier layer.

[0054] S102, depositing a passivation layer on the surface of the heterogeneous crystal circle, and depositing a dielectric layer on the surface of the passivation layer.

[0055] Specifically, in this embodiment, the passivation layer may be a silicon nitride layer or an aluminum oxide layer, and the dielectric layer may be a silicon dioxide layer.

[0056] S103, photolithography of the dielectric layer and the passivation layer to form a gate groove,

[0057] Specifically, in this embodiment, photoresist is coated on the surface of the dielectric layer, a pattern of a gate groove is defined on the photoresist, and the dielectric layer and the passivation layer are etched to form a gate groove; at this time, the photoresist remaining on the surface of the dielectric layer is not removed.

[0058] S104, etching the dielectric layer forming the gate groove so that a partial area of ​​the gate groove is extended in the dielectric layer; the size of the gate groove in the dielectric layer is the length of the micro field plate.

[0059] S105, removing the photoresist on the surface of the dielectric layer.

[0060] S106, photolithography a gate region on the surface of the dielectric layer and in the gate groove, depositing a gate metal in the gate region, evaporating the gate metal and then peeling it off to form a gate.

[0061] S107, etching away the dielectric layer to form a micro field plate gate.

[0062] In an optional embodiment of the present invention, Figures 5a to 5g 1 is a schematic diagram of a method for preparing a semiconductor device of a micro-gate field plate for radio frequency provided by an embodiment of the present invention. The micro-gate Fin gate is prepared by the following steps, specifically:

[0063] S101, providing a heterogeneous crystal circle.

[0064] Specifically, in this embodiment, the heterogeneous crystal wafer includes a stacked substrate, a gallium nitride layer, and a barrier layer.

[0065] S102, depositing a passivation layer on the surface of the heterogeneous crystal circle, depositing a dielectric layer on the surface of the passivation layer, and depositing a hard mask layer on the surface of the dielectric layer.

[0066] Specifically, in this embodiment, a passivation layer, a dielectric layer and a hard mask layer are sequentially deposited on the surface of the AlGaN / GaN heterogeneous crystal circle. The hard mask layer can use one or more metals such as aluminum, nickel, titanium, tungsten, etc., the passivation layer can be a silicon nitride layer or an aluminum oxide layer, and the dielectric layer can be a silicon dioxide layer.

[0067] S103, etching the hard mask layer, the dielectric layer and the passivation layer to form a gate groove, such as Figure 5a shown.

[0068] Specifically, see Figure 5a In this embodiment, a gate groove is etched on the surface of the wafer using photolithography and etching technology.

[0069] An optional method is to coat a photoresist on the surface of the hard mask layer in consideration of the etching depth, and to sequentially etch the hard mask layer, the dielectric layer and the passivation layer using a photolithography and etching process to form a gate groove.

[0070] Another optional method is to coat a photoresist on the surface of the hard mask layer and etch the hard mask layer using a photolithography etching process;

[0071] The photoresist coated on the surface of the hard mask layer is removed, and a photolithography and etching process is used to etch the dielectric layer and the passivation layer using the hard mask layer to form a gate groove.

[0072] In an optional embodiment, F-based plasma is used to etch the dielectric layer and the passivation layer.

[0073] It should be noted that when the dielectric layer and the passivation layer are etched using F-based plasma, the barrier layer will not be etched.

[0074] S104, coating a photoresist on the surface of the hard mask layer and on a part of the bottom and side of the gate groove, etching a part of the barrier layer, and forming a Fin groove, such as Figure 5b shown.

[0075] S105, removing the photoresist, such as Figure 5c shown.

[0076] S106, etching the dielectric layer forming the gate groove so that a part of the gate groove is extended in the dielectric layer; the size of the gate groove in the dielectric layer is the length of the micro field plate, such as Figure 5d shown.

[0077] S107, etching away the hard mask layer, such as Figure 5e shown.

[0078] Specifically, see Figure 5eIn this embodiment, other etching solutions are used to etch away the hard mask layer, and the etching solution is selected according to the material of the hard mask layer; for example, if nickel metal is used as the hard mask layer, FeCl3 solution can be used as the etching solution.

[0079] S108, photolithography a gate region on the surface of the dielectric layer, in the gate groove, and in the Fin groove, depositing a gate metal in the gate region, evaporating the gate metal and then peeling it off to form a gate, such as Figure 5f shown.

[0080] Specifically, see Figure 5f In this embodiment, the gate is first photolithographically processed, and the gate metal is evaporated and then peeled off.

[0081] S109, etching away the dielectric layer to form a micro field plate gate, such as Figure 5g shown.

[0082] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant is intended to cover non-exclusive inclusion, so that the article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or device including the elements. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0083] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0084] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor device with a micro-gate field plate for radio frequency, characterized in that: include: Providing a heterogeneous crystal circle; Depositing a passivation layer on the surface of the heterogeneous crystal circle, depositing a dielectric layer on the surface of the passivation layer, and depositing a hard mask layer on the surface of the dielectric layer; Etching the hard mask layer, the dielectric layer and the passivation layer to form a gate groove; The dielectric layer forming the gate groove is corroded so that a partial area of ​​the gate groove is extended in the dielectric layer; the size of the gate groove in the dielectric layer is the length of the micro field plate; etching away the hard mask layer; Photolithography a gate region on the surface of the dielectric layer and in the gate groove, depositing a gate metal in the gate region, evaporating the gate metal and then peeling it off to form a gate; The dielectric layer is etched away to form a micro field plate gate.

2. The method for preparing a semiconductor device of a radio frequency micro-gate field plate according to claim 1, characterized in that: The heterogeneous crystal circle includes a substrate, a gallium nitride layer and a barrier layer which are stacked.

3. The method for preparing a semiconductor device of a radio frequency micro-gate field plate according to claim 1, characterized in that: The material of the hard mask layer includes one or more of aluminum, nickel, titanium, and tungsten.

4. The method for preparing a semiconductor device of a radio frequency micro-gate field plate according to claim 1, characterized in that: The etching of the hard mask layer, the dielectric layer and the passivation layer to form a gate groove includes: A photoresist is coated on the surface of the hard mask layer, and the hard mask layer, the dielectric layer and the passivation layer are sequentially etched using a photolithography and etching process to form the gate groove.

5. The method for preparing a semiconductor device of a radio frequency micro-gate field plate according to claim 1, characterized in that: The etching of the hard mask layer, the dielectric layer and the passivation layer to form a gate groove includes: Coating a photoresist on the surface of the hard mask layer, and etching the hard mask layer using a photolithography etching process; The photoresist coated on the surface of the hard mask layer is removed, and the dielectric layer and the passivation layer are etched using the hard mask layer by using a photolithography and etching process to form the gate groove.

6. The method for preparing a semiconductor device of a radio frequency micro-gate field plate according to claim 4 or 5, characterized in that: Etching the dielectric layer and the passivation layer, comprising: The dielectric layer and the passivation layer are etched using F-based plasma.

7. The method for preparing a semiconductor device of a radio frequency micro-gate field plate according to claim 1, characterized in that: The etching of the dielectric layer forming the gate groove so that a partial area of ​​the gate groove extends in the dielectric layer includes: The dielectric layer forming the gate groove is etched using a BOE etching solution, and the concentration of the BOE etching solution and the etching time are controlled to control the size of the gate groove extending in the dielectric layer.

8. The method for preparing a semiconductor device of a radio frequency micro-gate field plate according to claim 7, characterized in that: The etching time of the BOE etching solution is 5 to 30 seconds.

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