Plane gate silicon carbide VDMOS integrated with JBS and preparation method

Abstract

The invention provides a planar gate silicon carbide VDMOS integrated with JBS and a preparation method thereof, and the method comprises the steps: depositing a metal layer on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift region; performing ion implantation to form a current sharing layer, a first drift layer, a second drift layer, a second P-type well region, a Schottky region, a lug boss, a first P-type well region and an N-type source region; forming a barrier layer again, etching the barrier layer to form a through hole, and depositing to form an insulating dielectric layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, metal is deposited, and a gate metal layer is formed; and forming a barrier layer again, etching the barrier layer to form a through hole, depositing metal, forming a source metal layer, removing the barrier layer, and completing preparation. The follow current capability of the body diode is improved, the loss of the body diode is reduced, and the reliability of the device is improved.

Description

Technical Field

[0001] The invention relates to a JBS-integrated planar gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. For silicon carbide power VDMOS, the requirements for device performance in different fields have different focuses, but the overall requirements include higher voltage resistance, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short-circuit reliability, etc.), and lower body diode conduction loss.

[0003] Especially in the field of switching power supplies, as the switching speed increases, the body diode freewheeling time accounts for an increasingly higher proportion of the total device conduction time. Reducing the device body diode freewheeling loss and increasing the device's reverse recovery speed are increasingly important for reducing device losses, and there is an urgent need to optimize the design of the body diode. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a planar gate silicon carbide VDMOS with integrated JBS and a preparation method thereof, so as to improve the freewheeling capability of the body diode, reduce the body diode loss and improve the reliability of the device.

[0005] In a first aspect, the present invention provides a method for preparing a planar gate silicon carbide VDMOS integrated with a JBS, comprising the following steps: Step 1: depositing a metal layer on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing a drift region on the side of the silicon carbide substrate; Step 2: forming a current balancing layer, a first drift layer and a second drift layer by performing ion implantation into the drift region; Step 3, forming a barrier layer on the second drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the second drift layer to form a second P-type well region; Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the second drift layer to form a Schottky region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the second drift layer to form a protrusion; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the second drift layer to form a first P-type well region; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the first P-type well region to form an N-type source region; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form an insulating dielectric layer; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 10: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0006] In a second aspect, the present invention provides a JBS-integrated planar gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the method for preparing a JBS-integrated planar gate silicon carbide VDMOS according to the first aspect.

[0007] The advantages of the present invention are: 1. The Schottky region and the second P-type well region of the present invention cross and contact the source metal layer, which can realize the JBS structure of the device body diode having both Schottky junction and pn junction on the basis of ensuring the voltage resistance of the device. This method not only realizes the Schottky low-voltage freewheeling during the freewheeling of the body diode, but also ensures the body diode's ability to withstand large current freewheeling, reduces the conduction loss, and at the same time reduces the number of hole conduction during the freewheeling of the device body diode, which can suppress the bipolar degradation effect of the device caused by hole conduction; 2. The depth of the second P-type well region of the present invention is greater than the depth of the Schottky region, so as to ensure that when the device withstands reverse voltage, the second P-type well region can wrap the Schottky region, thereby ensuring the reverse voltage withstand capability of the device; 3. The current-balancing layer of the present invention is to distribute the electrons moving from the JFET region of the device horizontally, reduce the on-resistance of the device and shield the capacitance from the gate to the drain of the device, reduce the Maitreya capacitance, reduce the device driving loss, and increase the switching speed of the device; the convex part is to reduce the on-resistance of the JFET region of the device; Fourth, the convex portion, the first P-type well region and the second P-type well region of the present invention cooperate to effectively suppress the voltage impact when the drain is connected to a high voltage, thereby improving the reliability of the device, based on the fact that the convex portion reduces the on-resistance of the device. 5. In the present invention, there is a second drift layer of 500nm-1μm between the N-type current balancing layer and the first P-type well region, which is to achieve decoupling of the device gate structure and the current balancing layer and ensure the high reliability characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0009] Figure 1 The schematic diagram of a JBS-integrated planar gate silicon carbide VDMOS of the present invention is shown in FIG.

[0010] Figure 2 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with integrated JBS according to the present invention Figure 1 .

[0011] Figure 3 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with integrated JBS according to the present invention Figure 2 .

[0012] Figure 4 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with integrated JBS according to the present invention Figure 3 .

[0013] Figure 5 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with integrated JBS according to the present invention Figure 4 .

[0014] Figure 6 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with integrated JBS according to the present invention Figure 5 .

[0015] Figure 7 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with integrated JBS according to the present invention Figure 6 .

[0016] Figure 8 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with integrated JBS according to the present invention Figure 7 .

[0017] Fig. 9 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with integrated JBS according to the present invention Figure 8 .

[0018] Fig.10 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with integrated JBS according to the present invention Figure 9 .

[0019] Fig.11 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with integrated JBS according to the present invention Figure 10 . DETAILED DESCRIPTION

[0020] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0022] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0023] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0024] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0025] like Figures 1 to 11 As shown, the embodiment of the present application provides a method for preparing a planar gate silicon carbide VDMOS integrated with a JBS, comprising the following steps: Step 1: depositing a metal layer on the lower side of the silicon carbide substrate 101 to form a drain metal layer 110; epitaxially growing a drift region 111 on the upper side of the silicon carbide substrate 101; Step 2: forming a current-balancing layer 103, a first drift layer 102 and a second drift layer 104 by performing ion implantation on the drift region 111; Step 3: forming a barrier layer 112 on the second drift layer 104, etching the barrier layer 112 to form a through hole, and performing ion implantation into the second drift layer 104 to form a second P-type well region 1061; Step 4: remove the original barrier layer 112, re-form the barrier layer 112, etch the barrier layer 112 to form a through hole, and perform ion implantation into the second drift layer 104 to form a Schottky region 106; Step 5, removing the original barrier layer 112, re-forming the barrier layer 112, etching the barrier layer 112 to form a through hole, and performing ion implantation into the second drift layer 104 to form a protrusion 1031; Step 6: remove the original barrier layer 112, re-form the barrier layer 112, etch the barrier layer 112 to form a through hole, and perform ion implantation into the second drift layer 104 to form a first P-type well region 105; Step 7, removing the original barrier layer 112, re-forming the barrier layer 112, etching the barrier layer 112 to form a through hole, and performing ion implantation into the first P-type well region 105 to form an N-type source region 1051; Step 8, removing the original barrier layer 112, re-forming the barrier layer 112, etching the barrier layer 112 to form a through hole, and depositing to form an insulating dielectric layer 107; Step 9, removing the original barrier layer 112, re-forming the barrier layer 112, etching the barrier layer 112 to form a through hole, depositing metal, and forming a gate metal layer 109; Step 10: remove the original barrier layer 112, re-form the barrier layer 112, etch the barrier layer 112 to form a through hole, deposit metal to form a source metal layer 108, remove the barrier layer 112, and complete the preparation.

[0026] In this embodiment, preferably, the doping concentration of the current equalizing layer 103 is greater than the doping concentrations of the first drift layer 102 and the second drift layer 104 .

[0027] In this embodiment, preferably, the doping concentration of the second P-type well region 1061 is greater than the doping concentration of the first P-type well region 105 .

[0028] In this embodiment, preferably, the thickness of the Schottky region 106 is smaller than the thickness of the second P-type well region 1061 , a plurality of grooves (not shown) are provided on the second drift layer 104 , and the lower part of the second P-type well region 1061 is provided in the grooves.

[0029] In this embodiment, preferably, the thickness of the second drift layer 104 is 500 nm-1 μm.

[0030] In this embodiment, preferably, the silicon carbide substrate 101 , the first drift layer 102 , the second drift layer 104 , the current balancing layer 103 and the Schottky region 106 are all of N type.

[0031] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes: Silicon carbide substrate 101, A first drift layer 102, wherein a lower side of the first drift layer 102 is connected to an upper side of the silicon carbide substrate 101; A current balancing layer 103, wherein the lower side of the current balancing layer 103 is connected to the first drift layer 102, and a protrusion 1031 is provided on the current balancing layer 103; A second drift layer 104, wherein a lower side of the second drift layer 104 is connected to an upper side of the current balancing layer 103, and an inner side of the second drift layer 104 is connected to an outer side of the protrusion 1031; A first P-type well region 105, wherein the lower side of the first P-type well region 105 is connected to the upper side of the second drift layer 104, and the inner side of the first P-type well region 105 is connected to the outer side of the protrusion 1031; an N-type source region 1051 is disposed on the first P-type well region 105; A Schottky region 106, wherein the lower side of the Schottky region 106 is connected to the upper side of the second drift layer 104, a plurality of second P-type well regions 1061 are evenly spaced in the Schottky region 106, and the lower side of the second P-type well region 1061 is connected to the upper side of the second drift layer 104; An insulating dielectric layer 107, wherein the lower side of the insulating dielectric layer 107 is connected to the upper side of the first P-type well region 105 and the upper side of the protrusion 1031; A source metal layer 108 , wherein the source metal layer 108 is respectively connected to the Schottky region 106 , the second P-type well region 1061 , the first P-type well region 105 , and the N-type source region 1051 ; A gate metal layer 109, wherein the lower side of the gate metal layer 109 is connected to the upper side of the insulating dielectric layer 107; and a drain metal layer 110 , wherein the drain metal layer 110 is connected to the lower side of the silicon carbide substrate 101 .

[0032] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 101 is 2-8e18cm -3 The doping concentrations of the first drift layer 102 and the second drift layer 104 are both 1-5e16cm -3 The doping concentration of the N-type current balancing layer 103 is 1-5e17cm -3 , the doping concentration of the second P-type well region 1061 is 1-2e19cm -3 , the doping concentration of the first P-type well region 105 is 1-5e17cm -3 , the doping concentration of the N-type Schottky region 106 is 1-5e17cm -3 The material of the insulating dielectric layer 107 can be silicon dioxide, and the doping concentration of the N-type source region 1051 is 2-8e18cm -3 ; The doping concentration of the N-type silicon carbide substrate 101 is to ensure that a low-resistance ohmic contact is formed with the drain metal layer 110, thereby reducing the overall on-resistance of the device; the doping concentration of the first drift layer 102 and the second drift layer 104 is a compromise between the reverse withstand voltage and the on-resistance of the device; the doping concentration of the N-type current-balancing layer 103 is designed with two considerations: one is to achieve current balancing in the device and reduce the on-resistance of the device, which requires ensuring that its doping concentration is high; the other is to ensure that the reverse resistance of the device is not affected when a pn junction is formed with the first P-type well region 105. The second P-type well region 1061 can effectively realize the pn junction withstand voltage of the device when the drain of the device is subjected to a large voltage. The second P-type well region 1061 and the N-type Schottky region 106 jointly construct the device body JBS diode, which can improve the body diode freewheeling capability of the device, reduce the conduction loss of the device, reduce the reverse recovery loss, and inhibit the bipolar degradation effect of the device. The relatively low doping of the first P-type well region 105 can reduce the gate inversion voltage of the device, thereby reducing the driving loss of the device.

[0033] The thickness of the N-type silicon carbide substrate 101 is 1 μm, the thickness of the first drift layer 102 is 30-100 μm, which can be adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The thickness of the N-type current balancing layer 103 is 500-1000 nm, the thickness of the protrusion 1031 is 2-3 μm, the thickness of the first P-type well region 105 in the contact area with the insulating dielectric layer 107 and the source metal layer 108 is 1 μm, the thickness of the contact area with the N-type source region 1051 is 800 nm, and the thickness of the N-type source region 1051 is 200 nm; the thickness of the N-type Schottky region 106 is 600 nm, the thickness of the second P-type well region 1061 is 1 μm, and the insulating dielectric layer 1 The thickness of 07 is 50nm, the thickness of the gate metal layer 109 is 200nm, the thickness of the source metal layer 108 is 200-300nm, the width of the N-type source region 1051 is 50-70% of the width of the first P-type well region 105, the total width of the first P-type well region 105 and the second P-type well region 1061 accounts for 50-60% of the device cell, and the width ratio of the second P-type well region 1061 to the N-type Schottky region 106 is 1:2 to 2:2. This width range is designed to compromise between the withstand voltage of the device and the voltage drop of the body diode. When the proportion of the Schottky diode is large, the voltage drop of the body diode is low; when the proportion of the second P-type well region 1061 is large, the withstand voltage capability of the device can be guaranteed; The N-type Schottky region 106 and the second P-type well region 1061 of the present invention cross and contact the source metal layer 108, which can realize the JBS structure of the device body diode having both Schottky junction and pn junction on the basis of ensuring the withstand voltage capability of the device, and reduce the number of holes conducting during the freewheeling of the device body diode, which can inhibit the bipolar degradation effect of the device caused by hole conduction, and can also increase the freewheeling capability of the device body diode, and can also reduce the freewheeling loss of the device body diode; The N-type current-balancing layer 103 is used to distribute the electrons moving from the JFET region of the device horizontally, reduce the device on-resistance and shield the capacitance from the gate to the drain of the device, reduce the Maitreya capacitance, reduce the device driving loss, and improve the device switching speed; the raised portion 1031 is used to reduce the on-resistance of the JFET region of the device; the raised portion 1031 cooperates with the first P-type well region 105 and the second P-type well region 1061 to reduce the device on-resistance at the raised portion 1031, and can effectively suppress the voltage shock when the drain is connected to a high voltage, thereby improving the reliability of the device; A second drift layer 104 is provided between the N-type current balancing layer 103 and the first P-type well region 105 and the second P-type well region 1061. The thickness of the second drift layer 104 is 500nm-1μm, which realizes the decoupling of the device gate structure and the N-type current balancing layer 103, ensuring the high reliability characteristics of the device.

[0034] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a planar gate silicon carbide VDMOS integrated with a JBS, characterized in that: The steps include: Step 1: depositing a metal layer on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing a drift region on the side of the silicon carbide substrate; Step 2: forming a current balancing layer, a first drift layer and a second drift layer by performing ion implantation into the drift region; Step 3, forming a barrier layer on the second drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the second drift layer to form a second P-type well region; Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the second drift layer to form a Schottky region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the second drift layer to form a protrusion; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the second drift layer to form a first P-type well region; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the first P-type well region to form an N-type source region; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form an insulating dielectric layer; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 10: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a planar gate silicon carbide VDMOS integrated with a JBS according to claim 1, characterized in that: The doping concentration of the current balancing layer is greater than the doping concentrations of the first drift layer and the second drift layer.

3. The method for preparing a planar gate silicon carbide VDMOS integrated with a JBS according to claim 1, characterized in that: The doping concentration of the second P-type well region is greater than the doping concentration of the first P-type well region.

4. The method for preparing a planar gate silicon carbide VDMOS integrated with a JBS according to claim 1, characterized in that: The thickness of the Schottky region is smaller than that of the second P-type well region. The second drift layer is provided with a plurality of grooves, and the lower portion of the second P-type well region is provided in the grooves.

5. The method for preparing a planar gate silicon carbide VDMOS integrated with a JBS according to claim 1, characterized in that: The thickness of the second drift layer is 500 nm-1 μm.

6. The method for preparing a planar gate silicon carbide VDMOS integrated with a JBS according to claim 1, characterized in that: The silicon carbide substrate, the first drift layer, the second drift layer, the current balancing layer and the Schottky region are all of N type.

7. A planar gate silicon carbide VDMOS with integrated JBS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 6.

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