High-voltage SiC MOSFET cellular structure and preparation method thereof

Abstract

The invention discloses a high-voltage SiC MOSFET cellular structure. The high-voltage SiC MOSFET cellular structure comprises an N + type silicon carbide power substrate, an N type drift region and a current expansion layer which are stacked in sequence, the electric field modulation regions are arranged on the left side and the right side of the current expansion layer, the P-body region is arranged above the current expansion layer, and the N + type source region and the P + type source region are arranged above the P-body region; the gate trench is arranged in the middle of the current expansion layer, a P + type shielding region is arranged at the bottom of the gate trench, a gate is arranged in the gate trench, and the gate is located above the P + type shielding region; and the gate oxide layer covers the upper surfaces of the gate, the N + type source region and the P + type source region. According to the structure, the electric field modulation areas are arranged on the two sides of the current expansion layer, the peak electric field intensity of the bottom of the groove of the UMOSFET device is reduced, the reverse breakdown voltage of the device is greatly improved, and meanwhile, the N-type areas in the electric field modulation areas also effectively reduce the characteristic on-resistance when the power device is conducted.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a high-voltage SiC MOSFET cell structure and a preparation method thereof. Background Art

[0002] The electric field concentration problem at the bottom corner of the gate of the SiC power UMOSFET device has always been a key difficulty that limits the improvement of the reverse breakdown voltage of the SiC power UMOSFET device. Therefore, how to reduce the maximum peak electric field at the bottom of the gate trench of the SiC power UMOSFET device and improve the reverse breakdown voltage of the SiC power UMOSFET device under the premise of ensuring that the on-resistance of the SiC power UMOSFET device is not affected is the direction that technicians in this field are committed to studying. Summary of the invention

[0003] The object of the present invention is to provide a high-voltage SiC MOSFET cell structure, which can effectively reduce the peak electric field strength at the bottom of the trench of a silicon carbide power UMOSFET device, so that the reverse breakdown voltage of the device is greatly improved.

[0004] To achieve this purpose, the present invention adopts the following technical solution: a high-voltage SiC MOSFET cell structure, the structure comprising: An N+ type silicon carbide power substrate, an N type drift region and a current spreading layer stacked in sequence; An electric field modulation region is arranged on the left and right sides of the current spreading layer, and the electric field modulation region is composed of an N-type region and a P-type region within the N-type region; A P-body region is disposed above the current spreading layer, and the left and right sides of the P-body region extend to above the electric field modulation regions on both sides; An N+ type source region and a P+ type source region are arranged above the P-body region, and the P+ type source region is located outside the N+ type source region; A gate trench is arranged in the middle of the current extension layer, the lower part of the gate trench extends into the N-type drift region, the gate trench passes through the P-body region and the N+ type source region upward along the current extension layer, a P+ type shielding region is arranged at the bottom of the gate trench, a gate is arranged in the gate trench, and the gate is located above the P+ type shielding region; and a gate oxide layer, wherein the gate oxide layer covers the upper surfaces of the gate, the N+ type source region and the P+ type source region.

[0005] As a specific implementation, the N+ type silicon carbide power substrate is doped with arsenic at a doping concentration of 1×10 19 ~1.5×10 19 cm -3.

[0006] As a specific implementation, the thickness of the electric field modulation region is greater than the thickness of the current spreading layer.

[0007] As a specific implementation, the thickness of the current spreading layer is 0.4±0.05 μm, and the current spreading layer is doped with phosphorus at a doping concentration of 1×10 16 ~1.5×10 16 cm -3 .

[0008] As a specific implementation, the thickness of the N-type drift region is 33±0.5 μm, and the N-type drift region is doped with arsenic at a doping concentration of 2.5×10 15 ~2.8×10 15 cm -3 .

[0009] As a specific implementation, the P-type region is smaller than the N-type region in width and height, and the surface where the bottom of the gate trench is located is higher than the surface where the bottom of the electric field modulation region is located.

[0010] As a specific implementation, the height of the N-type region is 1.6±0.05 μm, the width is 2.3±0.1 μm, the doping element is phosphorus, and the doping concentration is 5×10 16 ~5.3×10 16 cm -3 The height of the P-type region is 1.3±0.05μm, the width is 1.2±0.05μm, the doping element is boron, and the doping concentration is 4.5×10 17 ~4.8×10 17 cm -3 .

[0011] As a specific implementation manner, the thickness of the P-body region is 0.8±0.05 μm.

[0012] Another object of the present invention is to provide a method for preparing the above-mentioned high voltage SiC MOSFET cell structure, comprising the following steps: 1) Growing an N-type drift region on an N-type silicon carbide power substrate, and then growing a current spreading layer on the N-type drift region; 2) Forming an N-type region in the electric field modulation region in the device by ion implantation, and the electric field modulation region is located on the left and right sides of the current spreading layer; 3) Forming a P-type region in the electric field modulation region in the device by ion implantation; 4) A P-body region is formed above the current spreading layer by epitaxial growth, and an N+ source region and a P+ source region are formed above the P-body region by ion implantation, with the P-source region being located on the left and right sides of the N+ source region; 5) First, a gate trench is formed by extending downward from the middle of the N+ source region to the N-type drift region by dry oxygen etching, and then a P+ shielding region is formed at the bottom of the gate trench by ion implantation; 6) A gate oxide layer is formed on the upper surface of the N+ source region, the P+ source region, and the inside and upper surface of the gate trench through a thermal oxidation process, and finally the gate of the device is formed in the gate trench by depositing polysilicon.

[0013] Compared with the prior art, the technical solution of the present invention has the following advantages: The high-voltage SiC MOSFET cell structure of the present invention sets electric field modulation regions on both sides of the current spreading layer, which reduces the peak electric field strength at the bottom of the UMOSFET device trench, so that the reverse breakdown voltage of the device is greatly improved by about 25%. At the same time, the N-type region in the electric field modulation region also effectively reduces the characteristic on-resistance of the power device when it is turned on (decreased by about 28%). Compared with the traditional silicon carbide power UMOSFET device structure, the figure of merit of the silicon carbide power UMOSFET device structure with an electric field modulation region under the P-body region is improved by 120%, and the device performance is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematic diagram of the structure of the high-voltage SiC MOSFET cell structure of the present invention; Figure 2 The figure is a flow chart of the preparation of the high voltage SiC MOSFET cell structure according to the present invention; Among them: 1. N+ type silicon carbide power substrate; 2. N type drift region; 3. current spreading layer; 4. N type region; 5. P type region; 6. P-body region; 7. N+ type source region; 8. P+ type source region; 9. gate trench; 10. P+ type shielding region; 11. gate oxide layer; 12. gate. DETAILED DESCRIPTION

[0015] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific embodiments.

[0016] A high voltage SiC MOSFET cell structure, see Figure 1 As shown, it includes: an N+ type silicon carbide power substrate 1, an N type drift region 2 and a current spreading layer 3 stacked in sequence; An electric field modulation region is arranged on the left and right sides of the current spreading layer 3, and the electric field modulation region is composed of an N-type region 4 and a P-type region 5 within the N-type region 4; A P-body region 6 is disposed above the current spreading layer 3, and the left and right sides of the P-body region 6 extend to above the electric field modulation regions on both sides; An N+ type source region 7 and a P+ type source region 8 are arranged above the P-body region 6, and the P+ type source region 8 is located outside the N+ type source region 7; A gate trench 9 is provided in the middle of the current extension layer 3, the lower part of the gate trench 9 extends into the N-type drift region 2, the gate trench 9 passes through the P-body region 6 and the N+ type source region 7 upward along the current extension layer 3, a P+ type shielding region 10 is provided at the bottom of the gate trench 9, a gate 12 is provided in the gate trench 9, and the gate 12 is located above the P+ type shielding region 10; And a gate oxide layer 11 , wherein the gate oxide layer 11 covers the upper surfaces of the gate 12 , the N+ type source region 7 and the P+ type source region 8 .

[0017] The preparation method of the above-mentioned high-voltage SiC MOSFET cell structure is shown in Figure 2 As shown, the following steps are included: 1) When the doping element is arsenic and the doping concentration is 1×10 19 cm -3 A 32.9 μm thick N-type drift region is grown on the N+ type silicon carbide power substrate 1, and then a 0.4 μm thick current spreading layer 3 is grown on the N-type drift region. The current spreading layer is doped with phosphorus at a doping concentration of 1×10 16 cm -3 ; 2) An N-type region 4 in the electric field modulation region is formed in the device by ion implantation. The electric field modulation region is located on the left and right sides of the current spreading layer 3. Here, the N-type region 4 has a height of 1.6 μm and a width of 2.3 μm. It is doped with phosphorus at a doping concentration of 5×10 16 cm -3 ; 3) A P-type region 5 in the electric field modulation region is formed in the device by ion implantation. Here, the P-type region 5 has a height of 1.3 μm and a width of 1.2 μm and is doped with boron at a doping concentration of 4.5×10 17 cm -3 ; 4) forming a P-body region 6 with a thickness of 0.8 μm on the current spreading layer 3 by epitaxial growth, and forming an N+ type source region 7 and a P+ type source region 8 on the P-body region 6 by ion implantation, wherein the P-type source region is located on the left and right sides of the N+ type source region 7; 5) First, a gate trench 9 is formed by extending downward from the middle of the N+ type source region 7 to the N type drift region by dry oxygen etching, and then a P+ type shielding region 10 is formed at the bottom of the gate trench 9 by ion implantation; 6) A gate oxide layer 11 is formed on the upper surfaces of the N+ source region 7 and the P+ source region 8 and inside and on the upper surface of the gate trench 9 by a thermal oxidation process, and finally a gate 12 of the device is formed in the gate trench 9 by depositing polysilicon.

[0018] The device prepared by the above method reduces the peak electric field strength at the bottom of the UMOSFET device groove compared with the UMOSFET device without the electric field modulation region in the prior art, so that the reverse breakdown voltage of the device is greatly improved by about 25%. At the same time, the N-type region in the electric field modulation region of the present invention also effectively reduces the characteristic on-resistance of the power device when it is turned on, which is reduced by about 28%.

[0019] The above contents are only preferred embodiments of the present invention. For ordinary technicians in this field, according to the concept of the present invention, there will be changes in the specific implementation methods and application scopes. The content of this specification should not be understood as limiting the present invention.

Claims

1. A high voltage SiC MOSFET cell structure, characterized in that: The structure comprises: An N+ type silicon carbide power substrate, an N type drift region and a current spreading layer stacked in sequence; An electric field modulation region is arranged on the left and right sides of the current spreading layer, and the electric field modulation region is composed of an N-type region and a P-type region within the N-type region; A P-body region is disposed above the current spreading layer, and the left and right sides of the P-body region extend to above the electric field modulation regions on both sides; An N+ type source region and a P+ type source region are arranged above the P-body region, and the P+ type source region is located outside the N+ type source region; A gate trench is arranged in the middle of the current extension layer, the lower part of the gate trench extends into the N-type drift region, the gate trench passes through the P-body region and the N+ type source region upward along the current extension layer, a P+ type shielding region is arranged at the bottom of the gate trench, a gate is arranged in the gate trench, and the gate is located above the P+ type shielding region; and a gate oxide layer, wherein the gate oxide layer covers the upper surfaces of the gate, the N+ type source region and the P+ type source region.

2. A high voltage SiC MOSFET cell structure according to claim 1, characterized in that: The N+ type silicon carbide power substrate is doped with arsenic at a doping concentration of 1×10 19 ~1.5×10 19 cm -3 .

3. A high voltage SiC MOSFET cell structure according to claim 1, characterized in that: The thickness of the electric field modulation region is greater than the thickness of the current spreading layer.

4. A high voltage SiC MOSFET cell structure according to claim 1, characterized in that: The thickness of the current spreading layer is 0.4±0.05 μm, and the current spreading layer is doped with phosphorus at a doping concentration of 1×10 16 ~1.5×10 16 cm -3 .

5. A high voltage SiC MOSFET cell structure according to claim 1, characterized in that: The thickness of the N-type drift region is 33±0.5μm, and the N-type drift region is doped with arsenic at a doping concentration of 2.5×10 15 ~2.8×10 15 cm -3 .

6. A high voltage SiC MOSFET cell structure according to claim 1, characterized in that: The P-type region is smaller than the N-type region in width and height, and the surface where the bottom of the gate trench is located is higher than the surface where the bottom of the electric field modulation region is located.

7. A high voltage SiC MOSFET cell structure according to claim 6, characterized in that: The N-type region has a height of 1.6±0.05 μm, a width of 2.3±0.1 μm, a doping element of phosphorus, and a doping concentration of 5×10 16 ~5.3×10 16 cm -3 The height of the P-type region is 1.3±0.05μm, the width is 1.2±0.05μm, the doping element is boron, and the doping concentration is 4.5×10 17 ~4.8×10 17 cm -3 .

8. The high voltage SiC MOSFET cell structure according to claim 1, characterized in that: The thickness of the P-body region is 0.8±0.05 μm.

9. A method for preparing a high voltage SiC MOSFET cell structure according to any one of claims 1 to 8, characterized in that: The following steps are involved: 1) Growing an N-type drift region on an N-type silicon carbide power substrate, and then growing a current spreading layer on the N-type drift region; 2) Forming an N-type region in the electric field modulation region in the device by ion implantation, and the electric field modulation region is located on the left and right sides of the current spreading layer; 3) Forming a P-type region in the electric field modulation region in the device by ion implantation; 4) A P-body region is formed above the current spreading layer by epitaxial growth, and an N+ source region and a P+ source region are formed above the P-body region by ion implantation, with the P-source region being located on the left and right sides of the N+ source region; 5) First, a gate trench is formed by extending downward from the middle of the N+ source region to the N-type drift region by dry oxygen etching, and then a P+ shielding region is formed at the bottom of the gate trench by ion implantation; 6) A gate oxide layer is formed on the upper surface of the N+ source region, the P+ source region, and the inside and upper surface of the gate trench through a thermal oxidation process, and finally the gate of the device is formed in the gate trench by depositing polysilicon.

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