Field effect transistor and manufacturing method thereof
By continuously forming SiO2 and Si3N4 layers on the silicon carbide epitaxial layer in the silicon carbide field effect transistor, the interface trap problem caused by traditional high-temperature oxidation processes is solved, and the performance and production efficiency of the device are improved.
Patent Information
- Application Number
- CN202411755874.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-02
- Publication Date
- 2025-03-25
AI Technical Summary
The high-density interface traps formed by traditional silicon carbide field effect transistors during high-temperature oxidation lead to poor device quality and performance, while the high-temperature process costs and low production efficiency.
A silicon carbide epitaxial layer is formed on a silicon carbide substrate, and a SiO2 layer and a Si3N4 layer are continuously formed on its surface, replacing the traditional gate oxygen dielectric layer, thereby reducing interface defects and improving the quality of the polysilicon gate.
By reducing the interface defects between the silicon carbide epitaxial layer and the SiO2 layer, the quality of the polysilicon gate is improved, so that the gate can apply higher voltage, thereby improving the performance and production efficiency of the device.
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Figure CN119698045A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to semiconductor technology, and in particular to a field effect transistor and a method for manufacturing the same. Background Art
[0002] Silicon carbide (SiC) is the best material to replace silicon in power electronics applications. In particular, its high critical electric field and wide bandgap can work at high current levels and breakdown voltages up to 10KV, with excellent high-frequency performance. The fact that silicon carbide can form silicon dioxide at a certain temperature is also an important advantage. Taking the junction field-effect transistor (JFET) as an example, silicon dioxide is formed on the surface of the silicon carbide material as a gate oxide dielectric layer, and then polysilicon can be deposited on the gate oxide dielectric layer as a gate.
[0003] The traditional solution uses a high-temperature oxidation furnace to oxidize silicon carbide at a temperature above 1100°C to form a gate oxide dielectric layer. When silicon carbide is oxidized in a high-temperature environment, its surface will have high-density interface traps, resulting in poor quality at the interface between silicon carbide and silicon dioxide, which seriously affects the subsequent gate voltage resistance and poor device quality and performance.
[0004] In addition, due to the high temperature of the gate oxide process, the temperature and precision requirements in the manufacturing process are high, and thus the capacity requirements of the machine are high, resulting in a small number of products that can be produced in a single process, thereby causing a sharp increase in production costs.
[0005] Furthermore, since the conduction channel of the JFET device is located inside the device and it is a normally-on device, the gate is usually in the on state when no negative voltage is applied. At the same time, since the gate and the channel are a PN junction structure, a voltage greater than 3V cannot usually be applied to the gate, otherwise the device will be turned on, which in turn limits its application in power devices. Summary of the invention
[0006] In order to solve one of the above technical defects, a field effect transistor and a method for manufacturing the same are provided in an embodiment of the present application.
[0007] According to a first aspect of an embodiment of the present application, there is provided a field effect transistor, comprising:
[0008] Silicon carbide substrate;
[0009] A silicon carbide epitaxial layer formed on the upper surface of the silicon carbide substrate;
[0010] A SiO2 layer formed on the upper surface of the silicon carbide epitaxial layer;
[0011] A Si3N4 layer formed on the upper surface of the SiO2 layer;
[0012] A polysilicon layer is formed on the upper surface of the Si3N4 layer.
[0013] According to a second aspect of an embodiment of the present application, a method for manufacturing a field effect transistor is provided, comprising:
[0014] forming a silicon carbide epitaxial layer on a silicon carbide substrate;
[0015] A SiO2 layer and a Si3N4 layer are successively formed on the silicon carbide epitaxial layer;
[0016] A polysilicon layer is formed on the upper surface of the Si3N4 layer.
[0017] The technical solution provided in the embodiment of the present application is that a silicon carbide epitaxial layer is formed on a silicon carbide substrate; a SiO2 layer is formed on the upper surface of the silicon carbide epitaxial layer, and a Si3N4 layer is formed on the upper surface of the SiO2 layer; a polysilicon layer is formed on the upper surface of the Si3N4 layer, and the gate oxide dielectric layer in the traditional solution is replaced by the SiO2 layer and the Si3N4 layer continuously formed on the upper surface of the silicon carbide epitaxial layer, thereby reducing defects at the interface between the silicon carbide epitaxial layer and the SiO2 layer, and improving the quality of the polysilicon gate, so that a higher voltage can be applied to the gate, thereby improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0019] Figure 1 A schematic diagram of the structure of a field effect transistor provided in an embodiment of the present application;
[0020] Figure 2 A flow chart of a method for manufacturing a field effect transistor provided in an embodiment of the present application;
[0021] Figure 3 A schematic diagram of a method for manufacturing a field effect transistor provided in an embodiment of the present application;
[0022] Figure 4 A schematic diagram of a conventional method for manufacturing a field effect transistor;
[0023] Figure 5 This is the measured curve of the field effect transistor in the traditional solution;
[0024] Figure 6 This is a measured curve diagram of the field effect transistor provided in the embodiment of the present application.
[0025] Reference numerals:
[0026] 1-silicon carbide substrate; 2-silicon carbide epitaxial layer; 3-SiO2 layer; 4-Si3N4 layer; 5-polysilicon layer; 6-first well region; 7-second well region; 8-gate buried layer; 9-source region; 10-source metal; 11-drain metal. DETAILED DESCRIPTION
[0027] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.
[0028] like Figure 1 As shown, this embodiment provides a field effect transistor, including a silicon carbide substrate 1, a silicon carbide epitaxial layer 2, a SiO2 layer 3, a Si3N4 layer 4 and a polysilicon layer 5.
[0029] SiO2 layer 3 and Si3N4 layer 4 are continuously formed on silicon carbide epitaxial layer 2, wherein SiO2 layer 3 is formed on the upper surface of silicon carbide epitaxial layer 2, and Si3N4 layer 4 is formed on the upper surface of SiO2 layer 3. Polysilicon layer 5 is formed on the upper surface of Si3N4 layer 4 as the gate of the device.
[0030] The technical solution provided in this embodiment is that a silicon carbide epitaxial layer is formed on a silicon carbide substrate; a SiO2 layer is continuously formed on the upper surface of the silicon carbide epitaxial layer, a Si3N4 layer is formed on the upper surface of the SiO2 layer, and a polysilicon layer is formed on the upper surface of the Si3N4 layer. The SiO2 layer and the Si3N4 layer continuously formed on the upper surface of the silicon carbide epitaxial layer replace the gate oxide dielectric layer in the traditional solution, thereby reducing defects at the interface between the silicon carbide epitaxial layer and the SiO2 layer, and improving the quality of the polysilicon gate, so that a higher voltage can be applied to the gate, thereby improving the performance of the device.
[0031] This embodiment provides an implementation of a field effect transistor, wherein a first well region 6, a second well region 7, a gate buried layer 8 and a source region 9 are also formed in the silicon carbide epitaxial layer 2, all of which are formed in the silicon carbide epitaxial layer 2 and located at the upper part of the silicon carbide epitaxial layer 2. Among them, the second well region 7 is formed on both sides of the silicon carbide epitaxial layer 2, and the doping type of the second well region 7 is P type. The first well region 6 is located on the inner side of the second well region 7 and extends inwardly from the inner side of the second well region 7 in the lateral direction, and there is a gap between the two parts of the first well region 6, and the doping type of the first well region 6 is P type.
[0032] A source region 9 is also provided inside the second well region 7. The source region 9 and the first well region 6 are both located inside the second well region 7, and the source region 9 is located above the first well region 6. The doping type of the source region 9 is N-type. A source terminal metal 10 is also provided on the upper surfaces of the second well region 7 and the source region 9.
[0033] A gate buried layer 8 is formed between the two source regions 9, and the doping type of the gate buried layer 8 is P type. The SiO2 layer 3 is formed on the upper surface of the gate buried layer 8. A drain metal 11 is also provided on the lower surface of the silicon carbide substrate 1. The gate buried layer 8 and the source region 9 form a PN junction.
[0034] Furthermore, the depth of the source region 9 is greater than the depth of the gate buried layer 8 , so that a channel is formed between the gate buried layer 8 and the first well region 6 .
[0035] The widths of the SiO2 layer 3, Si3N4 layer 4, polysilicon layer 5 and gate buried layer 8 are equal.
[0036] As a junction field effect transistor (JFET), the device uses gate voltage to control the reverse bias of the PN junction with the channel to achieve the shutoff of the drain and source. When the gate is not voltaged, it is usually a normally open device, and its conduction channel is in the device body. It has the advantages of low noise, small size and high frequency response, and can be used in switching devices, power amplifier devices and digital electronic circuits to meet the requirements of different electronic devices.
[0037] In the above scheme, a SiO2 layer and a Si3N4 layer can be continuously formed on the silicon carbide epitaxial layer by chemical vapor deposition (CVD) or low pressure chemical vapor deposition (LPCVD). This step can be achieved by using a semiconductor furnace tube device, and multiple gas inlets are set on the semiconductor furnace tube device to introduce corresponding gases at different stages.
[0038] The above transistors are formed on a wafer, and a plurality of transistors are formed on one wafer at the same time.
[0039] One implementation method is: the SiO2 layer 3 is formed on the upper surface of the gate buried layer 8 at a first preset temperature. Specifically, the first preset temperature is 750°C-800°C, and the wafer is placed in a reaction chamber. First, the reaction chamber temperature of the furnace tube is controlled at 750°C-800°C, and N2O gas and SiH2Cl2 gas are introduced into the reaction chamber to form the SiO2 layer 3 on the silicon carbide epitaxial layer in the wafer.
[0040] The Si3N4 layer 4 is formed on the upper surface of the SiO2 layer 3 at the second preset temperature. The second preset temperature is 650°C-760°C. After the SiO2 layer 3 is formed, the temperature of the reaction chamber is then controlled at 650°C-760°C, and NH3 gas and SiH2Cl2 gas are introduced into the reaction chamber to form the Si3N4 layer 4 on the SiO2 layer 3.
[0041] The SiO2 layer 3 and the Si3N4 layer 4 are continuously formed in the furnace tube, which is equivalent to continuously forming the SiO2 layer 3 and the Si3N4 layer 4 on the surface of the wafer through one furnace tube, thereby reducing the number of furnace tubes and thus reducing production costs. It also avoids the wafer from being transported between furnace tubes, reducing the probability of wafer damage, thereby improving the yield rate.
[0042] The thickness of the formed SiO2 layer 3 is 40nm-50nm, and the thickness of the Si3N4 layer 4 is 45nm-50nm.
[0043] The polysilicon layer 5 can also be formed in the same furnace tube by depositing the polysilicon layer 5 on the surface of the Si3N4 layer 4 through a CVD or LPCVD process. The deposition temperature is 560°C-590°C, and the thickness of the polysilicon layer 5 is 30nm-50nm.
[0044] In the above scheme, the SiO2 layer 3 and the Si3N4 layer 4 are formed at a lower temperature, which can reduce the process difficulty and process cost, and can improve the production capacity. In addition, the formed Si3N4 layer 4 has a larger dielectric constant and a larger capacitance at the same thickness, which increases the gate capacitance to a certain extent, so that a larger voltage can be applied to the gate of the JFET device on the silicon carbide substrate, thereby improving the device performance.
[0045] On the basis of the above technical solution, this embodiment also provides a method for manufacturing a field effect transistor, such as Figures 2 to 4 As shown, the method includes:
[0046] Step 101: forming a silicon carbide epitaxial layer on a silicon carbide substrate.
[0047] Specifically, a silicon carbide epitaxial layer 2 is formed on a silicon carbide substrate 1. Afterwards, a first well region 6, a second well region 7, a gate buried layer 8 and a source region 9 are formed in the silicon carbide epitaxial layer 2, all of which are formed on the upper part of the silicon carbide epitaxial layer 2. Among them, the second well region 7 is formed on both sides of the silicon carbide epitaxial layer 2, and the doping type of the second well region 7 is P type. The first well region 6 extends inward from the inner side of the second well region 7, and there is a gap between the two parts of the first well region 6, and the doping type of the first well region 6 is P type. A source region 9 is also provided on the inner side of the second well region 7, and the source region 9 is located above the first well region 6, and the doping type of the source region 9 is N type. A gate buried layer 8 is formed between the two source regions 9, and the doping type of the gate buried layer 8 is P type. The SiO2 layer 3 is formed on the upper surface of the gate buried layer 8. A drain metal 11 is also provided on the lower surface of the silicon carbide substrate 1. The gate buried layer 8 and the source region 9 form a PN junction.
[0048] Step 102: continuously forming a SiO2 layer and a Si3N4 layer on the silicon carbide epitaxial layer.
[0049] One implementation mode is: SiO2 layer 3 and Si3N4 layer 4 are continuously formed on silicon carbide epitaxial layer 2, wherein SiO2 layer 3 is formed on silicon carbide epitaxial layer 2 at a first preset temperature, specifically located on the upper surface of gate buried layer 8, and the first preset temperature is less than 850°C. Si3N4 layer 4 is formed on the upper surface of SiO2 layer 3 at a second preset temperature, and the second preset temperature is less than 800°C. Polysilicon layer 5 is formed on the upper surface of Si3N4 layer 4 as the gate of the device.
[0050] Step 103: forming a polysilicon layer on the upper surface of the Si3N4 layer.
[0051] Specifically, silicon is deposited on the upper surface of the Si3N4 layer 4 to form a polysilicon layer 5.
[0052] The technical solution provided in this embodiment first forms a silicon carbide epitaxial layer on a silicon carbide substrate; then continuously forms a SiO2 layer and a Si3N4 layer on the silicon carbide epitaxial layer, and forms a polysilicon layer on the Si3N4 layer. The continuously formed SiO2 layer and Si3N4 layer replace the gate oxide dielectric layer in the traditional solution, thereby reducing defects at the interface between the silicon carbide epitaxial layer and the SiO2 layer, and improving the quality of the polysilicon gate, so that a higher voltage can be applied to the gate, thereby improving the performance of the device.
[0053] The device formed by the above steps is a junction field effect transistor JFET, which uses gate voltage to control the reverse bias of the PN junction with the channel to achieve the shutoff of the drain and source. When the gate is not voltaged, it is usually a normally open device, and its conducting channel is in the device body. It has the advantages of low noise, small size and high frequency response, and can be used in switching devices, power amplifier devices and digital electronic circuits to meet the requirements of different electronic devices.
[0054] On the basis of the above technical solution, a SiO2 layer and a Si3N4 layer can be continuously formed on the silicon carbide epitaxial layer by chemical vapor deposition (CVD) or low pressure chemical vapor deposition (LPCVD). This step can be implemented using a semiconductor furnace tube device, on which multiple gas inlets are set to introduce corresponding gases at different stages. The above steps are implemented for wafers, and multiple transistors are formed on one wafer at the same time.
[0055] The above step 102 continuously forms a SiO2 layer and a Si3N4 layer on the silicon carbide epitaxial layer. One implementation method is: the first preset temperature is 750°C-800°C, and the wafer is placed in the reaction chamber. First, the reaction chamber temperature of the furnace tube is controlled at 750°C-800°C, and N2O gas and SiH2Cl2 gas are introduced into the reaction chamber to form a SiO2 layer 3 on the silicon carbide epitaxial layer in the wafer. The second preset temperature is 650°C-760°C, and then the reaction chamber temperature is controlled at 650°C-760°C, and NH3 gas and SiH2Cl2 gas are introduced into the reaction chamber to form a Si3N4 layer 4 on the SiO2 layer 3.
[0056] The SiO2 layer 3 and the Si3N4 layer 4 are continuously formed in the furnace tube, which is equivalent to continuously forming the SiO2 layer 3 and the Si3N4 layer 4 on the surface of the wafer through one furnace tube, thereby reducing the number of furnace tubes and thus reducing production costs. It also avoids the wafer from being transported between furnace tubes, reducing the probability of wafer damage, thereby improving the yield rate.
[0057] The thickness of the formed SiO2 layer 3 is 40nm-50nm, and the thickness of the Si3N4 layer 4 is 45nm-50nm.
[0058] The polysilicon layer 5 can also be formed in the same furnace tube by depositing the polysilicon layer 5 on the surface of the Si3N4 layer 4 through a CVD or LPCVD process. The deposition temperature is 560°C-590°C, and the thickness of the polysilicon layer 5 is 30nm-50nm.
[0059] In the above scheme, the SiO2 layer 3 and the Si3N4 layer 4 are formed at a lower temperature, which can reduce the process difficulty and process cost, and can improve the production capacity. In addition, the formed Si3N4 layer 4 has a larger dielectric constant and a larger capacitance at the same thickness, which increases the gate capacitance to a certain extent, so that a larger voltage can be applied to the gate of the JFET device on the silicon carbide substrate, thereby improving the device performance.
[0060] On the basis of the above technical solution, before the SiO2 layer and the Si3N4 layer are continuously formed on the silicon carbide epitaxial layer 2, the method further includes:
[0061] A first well region 6 is formed in the upper part of the silicon carbide epitaxial layer 2, and the first well region 6 extends in the lateral direction; there is a gap between the two first well regions 6. Then a second well region 7 is formed in the upper part of the silicon carbide epitaxial layer 2, and the second well region 7 is located outside the first well region 6. A source region 9 is formed in the upper part of the silicon carbide epitaxial layer 2, and the source region 9 is located above the first well region 6 and inside the second well region 6. A gate buried layer 8 is formed in the upper part of the silicon carbide epitaxial layer 2, and the gate buried layer 8 is located between the two source regions 9; the SiO2 layer 3 is formed on the upper surface of the gate buried layer 8.
[0062] Several field effect transistors at different positions in the wafer obtained by the traditional solution are tested, and the Vgs-Igs curves obtained are as follows: Figure 5 As shown, it can be seen that the breakdown voltage of all tested field effect transistors is less than 20V. Figure 5 The multiple curves in correspond to multiple field effect transistors respectively.
[0063] Several field effect transistors at different positions of the wafer obtained in the embodiment of the present application are tested, and the obtained Vgs-Igs curves are as follows: Figure 6 As shown, it can be seen that the breakdown voltage of all tested field effect transistors is greater than 40V. Figure 6 The multiple curves in correspond to multiple field effect transistors respectively.
[0064] from Figure 5 and Figure 6 It can be seen from the measured curve that the embodiment of the present application can significantly improve the breakdown voltage of the field effect transistor.
[0065] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.
[0066] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0067] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0068] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.
[0069] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A field effect transistor, characterized in that: include: Silicon carbide substrate; A silicon carbide epitaxial layer formed on the upper surface of the silicon carbide substrate; A SiO2 layer formed on the upper surface of the silicon carbide epitaxial layer; A Si3N4 layer formed on the upper surface of the SiO2 layer; A polysilicon layer is formed on the upper surface of the Si3N4 layer.
2. The field effect transistor according to claim 1, characterized in that Field effect transistors also include: A gate buried layer is formed in the silicon carbide epitaxial layer and is located on the upper layer of the silicon carbide epitaxial layer; a SiO2 layer is formed on the upper surface of the gate buried layer; A source region is formed in the silicon carbide epitaxial layer and is located on an upper layer of the silicon carbide epitaxial layer; the source region is located on both sides of the gate buried layer; A first well region is formed in the silicon carbide epitaxial layer and is located in an upper layer of the silicon carbide epitaxial layer; the first well region is located below the source region, and the well region extends laterally from below the source region to below the gate buried layer; first well regions are provided below the two source regions, and a gap is left between the first well regions; The second well region is formed in the silicon carbide epitaxial layer and is located at the upper layer of the silicon carbide epitaxial layer; the second well region is located outside the source region and the first well region.
3. The field effect transistor according to claim 2, characterized in that: The depth of the source region is greater than the depth of the gate buried layer, and a channel is formed between the gate buried layer and the first well region.
4. The field effect transistor according to claim 2, characterized in that: The widths of the SiO2 layer, the Si3N4 layer and the gate buried layer are equal.
5. The field effect transistor according to claim 1, characterized in that: The thickness of the SiO2 layer is 40nm-50nm.
6. The field effect transistor according to claim 1, characterized in that: The thickness of the Si3N4 layer is 45nm-50nm.
7. A method for manufacturing a field effect transistor, characterized in that: include: forming a silicon carbide epitaxial layer on a silicon carbide substrate; successively forming a SiO2 layer and a Si3N4 layer on the silicon carbide epitaxial layer; A polysilicon layer is formed on the upper surface of the Si3N4 layer.
8. The manufacturing method according to claim 7, characterized in that: A SiO2 layer and a Si3N4 layer are successively formed on the silicon carbide epitaxial layer, including: Introducing N2O gas and SiH2Cl2 gas into the reaction chamber to form a SiO2 layer on the silicon carbide epitaxial layer; Then, NH3 gas and SiH2Cl2 gas are introduced into the reaction chamber to form a Si3N4 layer on the SiO2 layer.
9. The manufacturing method according to claim 7, characterized in that: The thickness of the SiO2 layer is 40nm-50nm.
10. The manufacturing method according to claim 7, characterized in that: Before the SiO2 layer and the Si3N4 layer are successively formed on the silicon carbide epitaxial layer, the method further includes: A first well region is formed at an upper portion of the silicon carbide epitaxial layer, the first well region extending in a lateral direction; and a gap is provided between two first well regions; forming a second well region at an upper portion of the silicon carbide epitaxial layer, wherein the second well region is located outside the first well region; forming a source region at an upper portion of the silicon carbide epitaxial layer, the source region being located above the first well region and inside the second well region; A gate buried layer is formed in the upper part of the silicon carbide epitaxial layer, and the gate buried layer is located between the two source regions; and a SiO2 layer is formed on the upper surface of the gate buried layer.