Manufacturing method of semiconductor device and semiconductor device

Abstract

The invention discloses a manufacturing method of a semiconductor device and the semiconductor device, and the method comprises the steps: providing a semiconductor substrate which comprises a substrate, an oxide layer and a dummy gate material layer, and forming an isolation structure in the substrate; a groove is formed, a side wall structure is formed in the groove, the groove is located in the area where the isolation structure is located, and the dummy gate material layer is divided through the side wall structure in the groove; forming a first gate structure, removing the pseudo gate material layer on one side of the side wall structure and the side wall structure, and forming the first gate structure; and forming a second gate structure, removing the residual pseudo gate material layer, and forming the second gate structure. According to the manufacturing method, before the first gate structure and the second gate structure are formed, the dummy gate material layer is separated by the side wall structure, and then the dummy gate on one side is removed, the first gate structure is formed, the dummy gate on the other side is removed, and the second gate structure is formed, so that the yield of the semiconductor device is improved, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] In semiconductor technology, logic chip devices are widely used. In the existing logic (LOGIC) chip metal gate (Metal Gate, MG) process, polycrystalline material (poly) is usually used as a hard mask (HM) for subsequent operations.

[0003] The researchers of the present application discovered that, due to the removal of polycrystalline material (poly) in the PMOS region, the gate boundaries of NMOS and PMOS have no sidewall distinction, which inevitably forms undercuts or footings, and causes subsequent metal gate film deposition (MG film dep) to appear open, thereby affecting the yield of semiconductor devices and affecting the performance of semiconductor devices. Summary of the invention

[0004] The main technical problem solved by the present invention is: to provide a method for manufacturing a semiconductor device and a semiconductor device, to open a groove on an isolation structure of a substrate, and to form a sidewall structure in the groove to isolate the pseudo gate material layers of NMOS and PMOS, so that in the process of removing the pseudo gate material layer, the retained pseudo gate material layer will not have biting edges and protrusions, thereby forming a first gate structure with a complete structure, and then removing the remaining pseudo gate material layer to form a second gate structure with a complete structure, thereby reducing the occurrence of the gate boundary area failing to form or incompletely forming, improving the yield of the semiconductor device, and then improving the performance of the semiconductor device.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: providing a method for manufacturing a semiconductor device, comprising: providing a semiconductor base, wherein the semiconductor base includes a substrate, an oxide layer and a pseudo gate material layer covered in sequence, and an isolation structure is formed in the substrate; forming a groove, and forming a sidewall structure in the groove, wherein the groove is located in the area where the isolation structure is located, and the pseudo gate material layer is divided by the sidewall structure in the groove; forming a first gate structure, wherein the pseudo gate material layer and the sidewall structure on one side of the sidewall structure are removed, and the first gate structure is formed; forming a second gate structure, wherein the remaining pseudo gate material layer is removed, and the second gate structure is formed.

[0006] In one embodiment of the present application, the forming of a groove and the forming of a sidewall structure in the groove include: removing a portion of the pseudo gate material layer and the oxide layer from the pseudo gate material layer toward the substrate to form the groove, wherein the substrate is exposed from the groove; and the sidewall structure, wherein a sacrificial material is filled in the groove and serves as the sidewall structure.

[0007] In one embodiment of the present application, forming the sidewall structure includes: forming a sacrificial material on the pseudo gate material layer and filling the groove; removing the sacrificial material on the pseudo gate material layer, and using the sacrificial material retained in the groove as the sidewall structure.

[0008] In one embodiment of the present application, the sacrificial material is one or a combination of silicon dioxide, silicon carbon nitride, silicon oxynitride, and silicon carbide.

[0009] In an embodiment of the present application, the method further includes: using a logical operation method to open a boundary area of ​​the dummy gate material layer to form the groove, wherein the boundary area is the area where the isolation structure is located.

[0010] In an embodiment of the present application, the method further includes: the sidewall structure is located in the groove above the isolation structure, and the sidewall structure is in contact with the isolation structure to separate the dummy gate material layer and the oxide layer.

[0011] In one embodiment of the present application, the forming of the first gate structure includes: removing the dummy gate material layer in the first area, wherein the first area is the area on one side of the sidewall structure; forming the first gate structure in the first area, wherein the first gate structure is a metal gate structure.

[0012] In one embodiment of the present application, before forming the first gate structure, the method further includes: removing the sidewall structure, and repairing the oxide layer in the area where the sidewall structure is located to form a complete oxide layer.

[0013] In one embodiment of the present application, the forming of the second gate structure includes: removing the dummy gate material layer in the second region, wherein the second region is the region on the other side of the sidewall structure; forming the second gate structure in the second region, wherein the second gate structure is a metal gate structure.

[0014] In an embodiment of the present application, the method further includes: forming an interlayer dielectric layer to cover the first gate structure and the second gate structure.

[0015] In one embodiment of the present application, providing the semiconductor base includes: providing the substrate, wherein an isolation structure is formed in the substrate; forming the oxide layer, wherein the oxide layer covers the substrate; and forming the dummy gate material layer, wherein the dummy gate material layer covers the oxide layer.

[0016] In order to solve the above technical problem, another technical solution adopted by the present application is: to provide a semiconductor device, which is manufactured using the above manufacturing method.

[0017] Different from the current technology, the manufacturing method of the semiconductor device provided by the present application provides a semiconductor base, wherein the semiconductor base includes a substrate, an oxide layer and a pseudo gate material layer covered in sequence, and an isolation structure is formed in the substrate; a groove is formed, and a sidewall structure is formed in the groove, wherein the groove is located in the area where the isolation structure is located, and the pseudo gate material layer is divided by the sidewall structure in the groove; a first gate structure is formed, wherein the pseudo gate material layer and the sidewall structure on one side of the sidewall structure are removed, and a first gate structure is formed; a second gate structure is formed, wherein the remaining pseudo gate material layer is removed, and a second gate structure is formed. That is, in the present application, a groove is opened on the isolation structure of the substrate, and a sidewall structure is formed in the groove to isolate the pseudo gate material layers of NMOS and PMOS, so that in the process of removing the pseudo gate material layer on one side, the pseudo gate material layer retained on the other side will not have biting edges and protrusions, thereby forming a first gate structure, so that the structure of the formed first gate structure is complete, and then the pseudo gate material layer on the other side is removed to form a second gate structure, and the structure of the second gate structure is complete, which reduces the occurrence of the gate boundary area failing to form or incompletely forming, improves the yield of the semiconductor device, and thus improves the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0019] Figure 1 It is a schematic flow chart of an embodiment of a method for manufacturing a semiconductor device in the present application;

[0020] Figure 2 It is a structural schematic diagram of an embodiment of a semiconductor substrate in the present application;

[0021] Figure 3 This application Figure 2 A top view of

[0022] Figure 4 It is a structural schematic diagram of an embodiment of forming a groove in the present application;

[0023] Figure 5 This application Figure 4 A top view of

[0024] Figure 6 It is a structural schematic diagram of an embodiment of forming a side wall structure in the present application;

[0025] Figure 7 This application Figure 6 A top view of

[0026] Figure 8 is a structural schematic diagram of an embodiment of forming a first gate structure in the present application;

[0027] Fig. 9 This application Figure 8 A top view of

[0028] Fig.10 is a structural schematic diagram of an embodiment of forming a second gate structure in the present application;

[0029] Fig.11 This application Fig.10 A top view of

[0030] Fig.12 It is a structural schematic diagram of an embodiment of forming an interlayer dielectric layer in the present application.

[0031] In the drawings, there are a substrate 100, a groove 101, an isolation structure 110, an oxide layer 200, a dummy gate material layer 300, a spacer structure 400, a first gate structure 510, a second gate structure 520, an interlayer dielectric layer 600, a first active area AA1, and a second active area AA2. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0033] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0034] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0035] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0036] In current semiconductor devices, especially in the metal gate (MG) process of logic (LOGIC) chips, polycrystalline material (poly) is usually used as a hard mask (HM) for subsequent operations. Since the gate boundary (Gate boundary) of NMOS and PMOS is not distinguished by the sidewall during the removal of polycrystalline material (poly) in the PMOS region, defects such as undercut or footing will inevitably be formed, and the subsequent metal gate film deposition (MGfilm dep) will have an open phenomenon, that is, during the metal gate film deposition process, the metal gate film fails to form or is incompletely formed in the gate boundary region, resulting in the gate boundary region being unable to play the expected protective or conductive role, thereby affecting the yield of semiconductor devices and affecting the performance of semiconductor devices.

[0037] Therefore, a method for manufacturing a semiconductor device is provided, wherein a groove is opened on an isolation structure of a substrate, and a sidewall structure is formed in the groove to isolate the pseudo gate material layers of NMOS and PMOS, and then in the process of removing the pseudo gate material layer on one side of the sidewall structure, the pseudo gate material layer on the other side of the sidewall structure will not have undercuts and protrusions, thereby forming a first gate structure, so that the structure of the formed first gate structure is complete, and then the pseudo gate material layer on the other side is removed to form a second gate structure, and the structure of the second gate structure is complete, thereby reducing the occurrence of a gate boundary area that fails to form or is incompletely formed, improving the yield of the semiconductor device, and thereby improving the performance of the semiconductor device.

[0038] See also Figure 1 , Figure 1 It is a flow chart of an embodiment of a method for manufacturing a semiconductor device in the present application.

[0039] like Figure 1 As shown, the method for manufacturing a semiconductor device in the present application may include the following operations.

[0040] S10, providing a semiconductor body, wherein the semiconductor body comprises a substrate, an oxide layer and a dummy gate material layer covered in sequence, and an isolation structure is formed in the substrate.

[0041] Among them, the substrate can be any suitable base material known in the art, the oxide layer can be any suitable oxide material known in the art, the dummy gate material layer can be any suitable dummy gate material known in the art, and the dummy gate material needs to be removed in the subsequent manufacturing process, and the isolation structure can be any suitable isolation material known in the art.

[0042] Specifically, a substrate is provided, an oxide layer is formed on the substrate, and at least a pseudo gate material layer is formed on the oxide layer to form a semiconductor body, wherein an isolation structure is formed in the substrate, and the isolation structure may be a shallow trench isolation structure.

[0043] S20, forming a groove and forming a sidewall structure in the groove, wherein the groove is located in the area where the isolation structure is located, and the pseudo gate material layer is separated by the sidewall structure in the groove.

[0044] Among them, the sidewall structure can be an isolation material, which is used to separate the pseudo gate material layers on both sides of the isolation structure. The sidewall structure is also a sacrificial material and needs to be removed later.

[0045] Specifically, in the area where the isolation structure is located, part of the pseudo gate material layer and part of the oxide layer are removed from the pseudo gate material layer toward the substrate, so that the isolation structure in the substrate is exposed from the groove; then a sidewall structure is formed in the groove, and the sidewall structure is in contact with the isolation structure, so that the pseudo gate material layers on both sides of the isolation structure are separated by the sidewall structure.

[0046] S30, forming a first gate structure, wherein the dummy gate material layer and the spacer structure on one side of the spacer structure are removed to form the first gate structure.

[0047] The first gate structure may be a metal gate structure.

[0048] Specifically, after the sidewall structure is formed in the groove, the dummy gate material layer on one side of the sidewall structure is removed, and the dummy gate material layer on the other side of the sidewall structure is retained. Because of the protection of the sidewall structure, the dummy gate material layer retained on the other side of the sidewall structure is complete in structure without defects such as undercuts and protrusions. Then, the gate material is deposited on the side of the sidewall structure where the dummy gate material layer is removed to form a complete and defect-free first gate structure.

[0049] It can be understood that the pseudo gate material layer extends along a first direction, and the side wall structure extends along a second direction, and the first direction is perpendicular to the second direction, so that the side wall structure can separate the pseudo gate material layer, and a part of the separated pseudo gate material layer belongs to NMOS and the other part belongs to PMOS. For example, the retained pseudo gate material layer belongs to the pseudo gate material layer of NMOS, and the removed pseudo gate material layer belongs to the pseudo gate material layer of PMOS.

[0050] S40, forming a second gate structure, wherein the remaining dummy gate material layer is removed and a second gate structure is formed.

[0051] Wherein, the second gate structure is a metal gate structure.

[0052] Specifically, after forming the first gate structure, the remaining dummy gate material layer on the other side is removed, and then a gate material is deposited in the area of ​​the dummy gate material layer where the material is removed, ie, on the other side of the spacer structure, to form a second gate structure.

[0053] It can be understood that in the process of removing the residual dummy gate material layer, the first gate structure can be protected by controlling the etching rate of the etching method so that the first gate structure remains intact. For example, the etching rate of the dummy gate material layer by the etching method is much greater than the etching rate of the first gate structure.

[0054] In the present embodiment, a groove is opened on the isolation structure of the substrate, and a sidewall structure is formed in the groove to isolate the pseudo gate material layers on both sides of the isolation structure. In the process of removing the pseudo gate material layer on one side, the pseudo gate material layer retained on the other side will not have biting edges and protrusions, thereby forming a first gate structure, so that the structure of the formed first gate structure is complete, and then the pseudo gate material layer on the other side is removed to form a second gate structure. The structure of the second gate structure is complete, which reduces the occurrence of the gate boundary area failing to form or incompletely forming, improves the yield of the semiconductor device, and thus improves the performance of the semiconductor device.

[0055] The following is combined with Figure 2 To illustrate, the operation flow of step S10 is as follows:

[0056] A substrate 100 is provided, and an oxide layer 200 is formed on the substrate 100, and a dummy gate material layer 300 is formed on the oxide layer 200, that is, the oxide layer 200 is in contact with the substrate 100, and the oxide layer 200 is in contact with the dummy gate material layer 300; wherein an isolation structure 110 is also formed in the substrate 100, and the isolation structure 110 can be a shallow trench isolation structure.

[0057] In some embodiments, the dummy gate material layer 300 extends along a first direction, the isolation structure 110 in the substrate 100 divides the substrate into multiple active areas (AA), and the active areas extend along a second direction, and the dummy gate material layer 300 spans across the multiple active areas.

[0058] See also Figure 2 , Figure 2 It is a schematic structural diagram of an embodiment of a semiconductor substrate in the present application.

[0059] like Figure 2 As shown, a substrate 100 is provided, an oxide layer 200 is formed on the substrate 100 , and a dummy gate material layer 300 is formed on the oxide layer 200 .

[0060] The substrate may be any suitable base material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI).

[0061] In order to more intuitively represent the semiconductor substrate, Figure 2 Top view of the .

[0062] See also Figure 3 , Figure 3 This application Figure 2 Top view of the .

[0063] like Figure 3 As shown, it is assumed that the active area includes a first active area AA1 and a second active area AA2, then the first active area AA1 and the second active area AA2 in the substrate 100 extend along the second direction, and the first active area AA1 and the second active area AA2 are spaced apart in the first direction, and the dummy gate material layer 300 is disposed on the substrate 100, and the dummy gate material layer 300 extends along the first direction, at least bridging the first active area AA1 and the second active area AA2.

[0064] It can be understood that the first direction can be the X direction, and the second direction can be the Y direction, that is, the dummy gate material layer 300 extends along the first direction (X direction), and the first active area AA1 and the second active area AA2 extend along the second direction; further, an isolation structure 110 is arranged between the first active area AA1 and the second active area AA2, and the first active area AA1 and the second active area AA2 are spaced apart in the first direction by the isolation structure 110, and the dummy gate material layer 300 bridges the first active area AA1, the isolation structure 110 and the second active area AA2.

[0065] In some embodiments, the first active area AA1 and the second active area AA2 may be isolated by an isolation structure 110 .

[0066] Next, the operation of step S20 is performed, and the operation flow of step S20 is as follows:

[0067] Part of the dummy gate material layer 300 and part of the oxide layer 200 are removed from the dummy gate material layer 300 toward the substrate 100 to form a groove 101 , wherein the substrate 100 is exposed from the groove 101 .

[0068] See also Figure 4 , Figure 4 It is a structural schematic diagram of an embodiment of forming a groove in the present application.

[0069] like Figure 4 As shown, in Figure 2 On the basis of this, part of the dummy gate material layer 300 is removed, and then part of the oxide layer 200 is further removed to expose the substrate 100 to form a groove 101. Because the groove 101 is located in the area where the isolation structure is located, the isolation structure 110 is exposed by the groove 101.

[0070] In some embodiments, a logic operation method may be used to open the boundary region of the dummy gate material layer to form a groove 101 so that the isolation structure 110 is exposed from the groove 101 ; wherein the boundary region is the region where the isolation structure 110 is located.

[0071] That is, the poly boundary between NMOS and PMOS is determined by logic operation, and then the poly boundary between NMOS and PMOS is opened, so that the isolation structure 110 in the substrate 100 is exposed to form a groove 101 to divide NMOS and PMOS.

[0072] See also Figure 5 , Figure 5 This application Figure 4 Top view of the .

[0073] like Figure 5 As shown, in Figure 3 On the basis of this, part of the dummy gate material layer 300 and part of the oxide layer (not marked) between the first active area AA1 and the second active area AA2 are removed to form a groove 101, so that the isolation structure 110 in the substrate 100 is exposed, that is, the groove 101 divides the dummy gate material layer 300 into two parts.

[0074] In some embodiments, part of the dummy gate material layer 300 divided by the groove 101 may belong to NMOS, and the other part may belong to PMOS. For example, the dummy gate material layer 300 on the first active area AA1 belongs to PMOS, and the dummy gate material layer 300 on the second active area AA2 belongs to NMOS.

[0075] Then, a spacer structure is formed, and a sacrificial material is filled in the groove to form a spacer structure 400 in the groove 101 , wherein the spacer structure 400 is in contact with the isolation structure 110 in the substrate 100 .

[0076] See also Figure 6 , Figure 6 It is a structural schematic diagram of an embodiment of forming a side wall structure in the present application.

[0077] like Figure 6 As shown, in Figure 4 On the basis of the above, a sacrificial material is filled in the groove 101 to form a spacer structure 400 in the groove 101 , and the spacer structure 400 is in contact with the isolation structure 110 in the substrate 100 .

[0078] In some embodiments, the spacer structure 400 is located in the groove 101 above the isolation structure 110 , and the spacer structure 400 is in contact with the isolation structure 110 , so as to separate the dummy gate material layer 300 and the oxide layer 200 .

[0079] In some embodiments, when a sacrificial material is formed in the groove 101, a sacrificial material is also formed on the pseudo gate material layer 300 and fills the groove 101; that is, the sacrificial material can also cover the pseudo gate material layer 300, and then the sacrificial material on the pseudo gate material layer 300 needs to be removed, and the sacrificial material retained in the groove 101 is used as the sidewall structure 400.

[0080] In some embodiments, the sacrificial material may be one of silicon dioxide (SiO 2 ), silicon carbon nitride (SiCN), silicon oxynitride (SiON), and silicon carbide (SiC); or a combination of multiple materials thereof.

[0081] It can be understood that the sacrificial material serves as a protective structure, which can effectively prevent the pseudo gate material layer 300 on the other side of the sidewall structure 400 from being etched when the pseudo gate material layer 300 on one side of the sidewall structure 400 is removed, that is, the sacrificial material can protect the pseudo gate material layer 300 on the other side of the sidewall structure 400.

[0082] In some embodiments, the first width of the groove 101 in the horizontal direction is not greater than the second width of the spacer structure 400 in the horizontal direction; that is, the first width of the groove 101 in the horizontal direction may be equal to the second width of the spacer structure 400 in the horizontal direction formed in the groove 101; and when forming the spacer structure 400, the exposed portion of the substrate 100 of the groove 101 may also form a portion of the spacer structure 400, that is, the second width of the spacer structure 400 in the horizontal direction may be greater than the first width of the groove 101 in the horizontal direction. For example, if the first width of the groove 101 in the horizontal direction is one unit size, the second width of the spacer structure 400 in the horizontal direction may be 1.0 to 1.8 unit sizes.

[0083] See also Figure 7 , Figure 7 This application Figure 6 Top view of the .

[0084] like Figure 7 As shown, in Figure 5 On the basis of, a sacrificial material is filled in the groove 101 to serve as a sidewall structure 400; that is, the sidewall structure 400 contacts the isolation structure (not shown) in the substrate 100, thereby separating the pseudo gate material layer 300, which belongs to NMOS and PMOS respectively.

[0085] Next, the operation of step S30 is performed, and the operation flow of step S30 is as follows:

[0086] The first gate structure is formed, that is, the dummy gate material layer 300 on one side of the spacer structure 400 is removed, and the spacer structure 400 is removed, thereby forming the first gate structure 510 .

[0087] See also Figure 8 , Figure 8 It is a structural schematic diagram of an embodiment of forming a first gate structure in the present application.

[0088] like Figure 8 As shown, in Figure 6 On the basis of this, the dummy gate material layer 300 on one side of the spacer structure 400 is removed, while the dummy gate material layer 300 on the other side of the spacer structure 400 is retained, and then a first gate structure 510 is formed in the area where the dummy gate material layer 300 on one side of the spacer structure 400 is removed; wherein the first gate structure 510 can have the same thickness as the remaining dummy gate material layer 300, that is, the thickness in the vertical direction.

[0089] It can be understood that the area on one side of the sidewall structure 400 is the first area, and the area on the other side of the sidewall structure 400 is the second area, that is, the area where the dummy gate material layer 300 on one side of the sidewall structure 400 is removed is the first area, that is, the area where the first gate structure 510 is formed is the first area; and the area where the remaining dummy gate material layer 300 on the other side of the sidewall structure 400 is located is the second area, that is, the area where the second gate structure is subsequently formed is the second area.

[0090] In some embodiments, the dummy gate material layer 300 that needs to be retained can be covered by a hard mask deposition method, and then the dummy gate material layer 300 not covered by the hard mask can be removed, and the corresponding oxide layer 200 can be exposed; due to the introduction of the hard mask deposition method, the difficulty of the dummy gate material layer 300 removal process can be effectively reduced, as well as the difficulty of the thin film deposition process, thereby effectively reducing the process cost.

[0091] In some embodiments, before forming the first gate structure 510 , it is also necessary to remove the spacer structure 400 and repair the oxide layer in the area where the spacer structure 400 is located to form a complete oxide layer 200 covering the substrate 100 .

[0092] When removing the pseudo gate material layer 300 on one side of the sidewall structure 400, because the sidewall structure 400 protects the pseudo gate material layer 300 on the other side of the sidewall structure 400, the retained pseudo gate material layer 300 will not have edge biting or protrusions, thereby forming a first gate structure, making the structure of the formed first gate structure complete, thereby protecting the integrity of the first gate structure and improving the performance of subsequent semiconductor devices.

[0093] It can be understood that in some embodiments, isolation sidewalls of the gate structure can be formed on the active areas on both sides of the gate structure in the second direction, and source / drain regions can be formed in the active areas on both sides of the gate structure to form corresponding source / drain electrodes.

[0094] See also Fig. 9 , Fig. 9 This application Figure 8 Top view of the .

[0095] like Fig. 9 As shown, in Figure 7 On this basis, the dummy gate material layer 300 on one side of the spacer structure 400 is removed, while the dummy gate material layer 300 on the other side of the spacer structure 400 is retained, that is, the dummy gate material layer 300 on the second active area AA2 is removed, while the dummy gate material layer 300 on the first active area AA1 is retained, thereby forming a first gate structure 510 on the second active area AA2.

[0096] Next, the operation of step S40 is performed, and the operation flow of step S40 is as follows:

[0097] The second gate structure is formed, that is, the remaining dummy gate material layer is removed and the second gate structure is formed.

[0098] See also Fig.10 , Fig.10 It is a structural schematic diagram of an embodiment of forming a second gate structure in the present application.

[0099] like Fig.10 As shown, in Figure 8 On the basis of this, the remaining dummy gate material layer 300 is removed, and the gate material is filled in the area where the remaining dummy gate material layer 300 is removed to form a second gate structure 520; wherein the second gate structure 520 can have the same thickness as the first gate structure 510, that is, the thickness in the vertical direction.

[0100] In some embodiments, the first gate structure 510 and the second gate structure 520 may be in contact.

[0101] It can be understood that because the structure of the first gate structure 510 is complete, in the process of removing the residual dummy gate material layer, the first gate structure can be protected by controlling the etching rate of the etching method, so that the first gate structure remains intact. For example, the etching rate of the residual dummy gate material layer by the etching method is much greater than the etching rate of the first gate structure, and then the gate material is deposited to form a second gate structure 520 with a complete structure, thereby reducing the occurrence of the gate boundary area failing to form or incompletely forming, improving the yield of the semiconductor device, and then improving the performance of the semiconductor device.

[0102] See also Fig.11, Fig.11 yes Fig.10 Top view of the .

[0103] like Fig.11 As shown, in Fig. 9 On the basis of this, the dummy gate material layer 300 on the other side of the spacer structure 400 is removed to form a second gate structure 520, that is, the dummy gate material layer 300 on the first active area AA1 is removed to form a second gate structure 520 on the first active area AA1.

[0104] In some embodiments, an interlayer dielectric layer 600 may also be formed.

[0105] See also Fig.12 , Fig.12 It is a structural schematic diagram of an embodiment of forming an interlayer dielectric layer in the present application.

[0106] like Fig.12 As shown, in Fig.11 On this basis, an interlayer dielectric layer 600 is formed to cover the semiconductor device, specifically to cover the first gate structure 510 and the second gate structure 520 .

[0107] In the present embodiment, a groove is opened on the isolation structure of the substrate, and a sidewall structure is formed in the groove to isolate the pseudo gate material layers on both sides of the isolation structure. In the process of removing the pseudo gate material layer on one side, the pseudo gate material layer retained on the other side will not have biting edges and protrusions, thereby forming a first gate structure, so that the structure of the formed first gate structure is complete, and then the pseudo gate material layer on the other side is removed to form a second gate structure. The structure of the second gate structure is complete, which reduces the occurrence of the gate boundary area failing to form or incompletely forming, improves the yield of the semiconductor device, and thus improves the performance of the semiconductor device.

[0108] The present application also provides a semiconductor device, see Figure 2-10 .

[0109] The semiconductor device includes a substrate 100, an oxide layer 200, a first gate structure 510 and a second gate structure 520; wherein an isolation structure 110 is formed in the substrate 100, and gate boundaries of the first gate structure 510 and the second gate structure 520 are located in the region where the isolation structure 110 is located.

[0110] Among them, the semiconductor device is obtained by forming a groove in the area where the isolation structure 110 is located in the substrate when a dummy gate material layer is formed on the substrate 100, and forming a sidewall structure 400 in the groove, and then removing the dummy gate material layer 300 and the sidewall structure 400 on one side of the sidewall structure 400 in turn to form a first gate structure 510, and then removing the remaining dummy gate material layer 300 to form a second gate structure 520.

[0111] In the present embodiment, a method for manufacturing a semiconductor device is provided, wherein a groove is opened on an isolation structure of a substrate, and a sidewall structure is formed in the groove to isolate the pseudo gate material layers on both sides of the isolation structure, so that in the process of removing the pseudo gate material layer on one side, the pseudo gate material layer retained on the other side will not have biting edges and protrusions, thereby forming a first gate structure, so that the structure of the formed first gate structure is complete, and then the pseudo gate material layer on the other side is removed to form a second gate structure, and the structure of the second gate structure is complete, thereby reducing the occurrence of the gate boundary area failing to form or incompletely forming, improving the yield of the semiconductor device, reducing the process cost, and thus improving the performance of the semiconductor device.

[0112] The above description is only an implementation mode of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate, an oxide layer and a dummy gate material layer covered in sequence, and an isolation structure is formed in the substrate; Forming a groove and forming a sidewall structure in the groove, wherein the groove is located in the region where the isolation structure is located, and the pseudo gate material layer is divided by the sidewall structure in the groove; Forming a first gate structure, wherein the dummy gate material layer and the spacer structure on one side of the spacer structure are removed, and the first gate structure is formed; A second gate structure is formed, wherein the remaining dummy gate material layer is removed and the second gate structure is formed.

2. The manufacturing method according to claim 1, characterized in that: The forming of the groove and forming a sidewall structure in the groove includes: removing a portion of the dummy gate material layer and the oxide layer from the dummy gate material layer toward the substrate to form the groove, wherein the substrate is exposed from the groove; The sidewall structure is formed, wherein a sacrificial material is filled in the groove and serves as the sidewall structure.

3. The manufacturing method according to claim 2, characterized in that: The forming of the sidewall structure comprises: forming the sacrificial material on the dummy gate material layer and filling the groove; The sacrificial material on the dummy gate material layer is removed, and the sacrificial material retained in the groove is used as the sidewall structure.

4. The manufacturing method according to claim 2, characterized in that: The sacrificial material is one or a combination of silicon dioxide, silicon carbon nitride, silicon oxynitride, and silicon carbide.

5. The manufacturing method according to claim 2, characterized in that: Also includes: The boundary area of ​​the dummy gate material layer is opened by means of a logic operation to form the groove, wherein the boundary area is the area where the isolation structure is located.

6. The manufacturing method according to claim 2, characterized in that: Also includes: The spacer structure is located on the isolation structure, and the spacer structure is in contact with the isolation structure to separate the dummy gate material layer from the oxide layer.

7. The manufacturing method according to claim 1, characterized in that: The forming of the first gate structure comprises: removing the dummy gate material layer in a first region, wherein the first region is a region on one side of the spacer structure; The first gate structure is formed in the first region, wherein the first gate structure is a metal gate structure.

8. The manufacturing method according to claim 7, characterized in that: Before forming the first gate structure, the method further includes: The sidewall structure is removed, and the oxide layer is repaired in the area where the sidewall structure is located.

9. The manufacturing method according to claim 1, characterized in that: The forming of the second gate structure comprises: removing the dummy gate material layer in the second region, wherein the second region is the region on the other side of the spacer structure; The second gate structure is formed in the second region, wherein the second gate structure is a metal gate structure.

10. The manufacturing method according to claim 7, characterized in that: An interlayer dielectric layer is formed to cover the first gate structure and the second gate structure.

11. The manufacturing method according to claim 1, characterized in that: The semiconductor substrate is provided, comprising: providing the substrate, wherein the isolation structure is formed in the substrate; forming the oxide layer, wherein the oxide layer covers the substrate; The dummy gate material layer is formed, and the dummy gate material layer covers the oxide layer.

12. A semiconductor device, characterized in that: The semiconductor device is manufactured by using the manufacturing method described in any one of claims 1 to 11.

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