Thin film transistor substrate and display device using the same

Abstract

Disclosed are a thin film transistor substrate and a display device using the same. The thin film transistor substrate includes: a substrate; an active layer disposed on the substrate; a gate electrode disposed on the active layer; a source electrode connected to one side of the active layer; and a drain electrode connected to the other side of the active layer, in which the gate electrode includes a first side disposed protruding in a direction of any one of the source electrode and the drain electrode, the active layer includes a plurality of first active holes overlapping the first side, and a plurality of second active holes overlapping the second side. And the plurality of first active holes are arranged in a direction perpendicular to a direction in which the source electrode and the drain electrode face each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2023-0128053, filed on September 25, 2023, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a thin film transistor substrate and a display device using the same. Background Art

[0004] Since a thin film transistor can be manufactured on a glass or plastic substrate, the thin film transistor is widely used as a switch or a driving element of a display device such as a liquid crystal display device or an organic light emitting device.

[0005] Various types of thin film transistors, such as a display area thin film transistor that emits each pixel, a logic-GIP thin film transistor for controlling the display area thin film transistor, and a buffer-GIP thin film transistor that controls the overall power supply, can be used in a display panel for driving an organic light emitting device (OLED).

[0006] In order to realize a device with high mobility, in a thin film transistor having a top gate structure, a process of making an oxide semiconductor layer conductive may be performed by using a gate electrode as a mask. However, in the process of making the oxide semiconductor layer conductive, the region to be conductive may be excessively penetrated, and thus the channel region may be formed to be smaller than the setting region, and thus the channel length may be reduced and the threshold voltage Vth may be shifted in the negative (-) direction. In particular, when the width of the oxide semiconductor layer is large, the degree of penetration of the region to be conductive may increase, and thus the channel length may be further shortened.

[0007] When the threshold voltage Vth is shifted in the negative (-) direction, leakage current may occur in the initial image. Therefore, a display panel including a thin film transistor may be poorly driven due to the leakage current, and a problem of increased panel power consumption may occur. Summary of the invention

[0008] The present disclosure is made in view of the above problems, and an object of the present disclosure is to provide a thin film transistor substrate and a display device including the thin film transistor substrate, on which, since the gate electrode includes a side that protrudes in the direction of either the source electrode or the drain electrode and has a certain curvature, the channel portion of the active layer can ensure the same effective channel length in the width direction.

[0009] According to one aspect of the present disclosure, the above and other purposes can be achieved by providing a thin film transistor substrate and a display device including the thin film transistor substrate. The thin film transistor substrate includes: a substrate; an active layer disposed on the substrate; a gate electrode disposed on the active layer; a source electrode connected to one side of the active layer; and a drain electrode connected to the other side of the active layer, wherein the gate electrode includes a first side protruding in the direction of either the source electrode or the drain electrode, the active layer includes a plurality of first active holes overlapping the first side, and the plurality of first active holes are arranged in a direction perpendicular to the direction in which the source electrode and the drain electrode face each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1A is a plan view of a thin film transistor substrate according to an embodiment of the present disclosure.

[0012] Figure 1B is a plan view showing an active layer of a thin film transistor substrate according to an embodiment of the present disclosure.

[0013] Figure 2A is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present disclosure. In this case, Figure 2A The cross-sectional view corresponds to the Figure 1A A cross section taken along line II'.

[0014] Figure 2B is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present disclosure. In this case, Figure 2B The cross-sectional view corresponds to the Figure 1A A cross section taken along line II-II'.

[0015] Figure 3 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0016] Figure 4A is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present disclosure. In this case, Figure 4A The cross-sectional view corresponds to the Figure 3 A cross section taken along line III-III'.

[0017] Figure 4B is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present disclosure. In this case, Figure 4B The cross-sectional view corresponds to the Figure 3 A cross section taken along line IV-IV'.

[0018] Figure 5A is a graph showing the channel length Leff according to the position of the thin film transistor substrate according to the comparative example, Figure 5B is a graph showing a channel portion length Leff depending on a position of a thin film transistor substrate according to another embodiment of the present disclosure.

[0019] Figure 6 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0020] Figure 7 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0021] Figure 8 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0022] Fig.9A is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig.9A The cross-sectional view corresponds to the Figure 8 The cross section is taken along the line V-V'.

[0023] Fig. 9B is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig. 9B The cross-sectional view corresponds to the Figure 8 A cross section taken along line VI-VI'.

[0024] Fig.10 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig.10 The cross-sectional view corresponds to the Figure 8 The cross section is taken along the line V-V'.

[0025] Fig.11 is a cross-sectional view of a display device including a thin film transistor substrate according to an embodiment of the present disclosure.

[0026] Fig.12 is a schematic diagram of a display device according to an embodiment of the present disclosure.

[0027] Fig.13 is a circuit diagram of a pixel included in a display device according to an embodiment of the present disclosure.

[0028] Fig.14 is a circuit diagram of a pixel included in a display device according to another embodiment of the present disclosure.

[0029] Fig.15is a circuit diagram of a pixel included in a display device according to another embodiment of the present disclosure.

[0030] Fig.16 is a schematic diagram of a shift register according to an embodiment of the present disclosure.

[0031] Fig.17 is a circuit diagram of a shift register according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] The advantages and features of the present disclosure and its implementation methods will be explained by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments set forth herein. Rather, these embodiments are provided to make the present disclosure thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0033] The shapes, sizes, proportions, angles, and numbers disclosed in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and the present disclosure is therefore not limited to the details shown. Like reference numerals refer to like elements throughout. In the following description, when a detailed description of a related known function or configuration is determined to unnecessarily obscure the focus of the present disclosure, the detailed description will be omitted.

[0034] In the case where “including,” “having,” and “comprising” described in the present specification are used, other parts may also be present unless “only” is used. Terms in the singular form may include plural forms unless described otherwise.

[0035] When explaining an element, although the error region is not explicitly described, the element is interpreted as including the error region.

[0036] When describing a positional relationship, for example, when the positional order is described as "on", "above", "below", "under", and "immediately adjacent to", unless "just" or "directly" is used, the case where there is no contact between them can be included.

[0037] If a first element is mentioned as being "on" a second element, this does not mean that the first element is substantially above the second element in the drawings. The upper and lower parts of the objects concerned may change depending on the orientation of the objects. Therefore, the case where a first element is "on" a second element includes the case where the first element is "below" the second element as well as the case where the first element is "above" the second element in the drawings or in the actual configuration.

[0038] When describing a time relationship, for example, when a time sequence is described as “after,” “subsequently,” “next,” and “before,” discontinuous cases may be included unless “immediately” or “directly” is used.

[0039] It should be understood that although the terms "first", "second", etc. may be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0040] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of a first element, a second element, and a third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each element of the first element, the second element, and the third element.

[0041] The features of various embodiments of the present disclosure may be coupled or combined with each other in part or in whole, and may interoperate with each other in various ways and be driven technically. The embodiments of the present disclosure may be performed independently of each other, or may be performed together in a mutually dependent relationship.

[0042] In the drawings, the same or similar elements are denoted by the same reference numerals even though they are depicted in different drawings.

[0043] In the embodiments of the present disclosure, for ease of explanation, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode can be used interchangeably. Therefore, the source electrode can be a drain electrode, and the drain electrode can be a source electrode. In addition, the source electrode in any embodiment of the present disclosure can be a drain electrode in another embodiment of the present disclosure, and the drain electrode in any embodiment of the present disclosure can be a source electrode in another embodiment of the present disclosure.

[0044] In one or more embodiments of the present disclosure, for ease of description, the source region is distinguished from the source electrode, and the drain region is distinguished from the drain electrode. However, the embodiments of the present disclosure are not limited to this structure. For example, the source region may be a source electrode, and the drain region may be a drain electrode. In addition, the source region may be a drain electrode, and the drain region may be a source electrode.

[0045] Figure 1A is a plan view of a thin film transistor substrate according to an embodiment of the present disclosure.

[0046] like Figure 1AAs shown, the thin film transistor substrate according to an embodiment of the present disclosure may include an active layer 120 , a gate electrode 140 , a source electrode 161 , and a drain electrode 162 .

[0047] The active layer 120 may extend in a first direction X, for example, a horizontal direction. In this case, the first direction X may be defined as a direction in which the source electrode 161 and the drain electrode 162 face each other.

[0048] A first contact hole CH1 may be provided at one side, for example, the left side, of the active layer 120, and a second contact hole CH2 may be provided at the other side, for example, the right side, of the active layer 120. In this case, one side of the active layer 120 may be electrically connected to the source electrode 161 through the first contact hole CH1, and the other side of the active layer 120 may be electrically connected to the drain electrode 162 through the second contact hole CH2.

[0049] The gate electrode 140 may extend in a second direction Y, for example, a vertical direction. In this case, the second direction Y may be defined as a direction orthogonal to the first direction X.

[0050] According to an embodiment of the present disclosure, the gate electrode 140 may have a convex shape. Specifically, the gate electrode 140 may be configured to protrude in the first direction X. For example, the gate electrode 140 may include a first side 141a protruding in the direction of the source electrode 161 and a second side 141b protruding in the direction of the drain electrode 162 while overlapping the active layer 120. In this case, the first side 141a and the second side 141b may be an arc with a constant curvature, but are not limited thereto.

[0051] Since the first side 141a of the gate electrode 140 is formed to protrude from the gate electrode 140, the distance between the first side 141a and the source electrode 161 may increase from the central portion of the active layer 120 toward the edge portion of the active layer 120 along the second direction Y. Specifically, the distance between the first side 141a and the source electrode 161 may be smallest at the central portion of the active layer 120, and the distance between the first side 141a and the source electrode 161 may be largest at a portion overlapping one side (e.g., the upper side) of the active layer 120. Likewise, the distance between the first side 141a and the source electrode 161 may be largest at a portion overlapping the other side (e.g., the lower side) of the active layer 120.

[0052] Since the second side 141b of the gate electrode 140 is formed to protrude from the gate electrode 140, the distance between the second side 141b and the drain electrode 162 may increase from the central portion of the active layer 120 toward the edge portion of the active layer 120 in the second direction Y. Specifically, the distance between the second side 141b and the drain electrode 162 may be smallest in the central portion of the active layer 120, and the distance between the second side 141b and the drain electrode 162 may be largest at a portion overlapping one side (e.g., the upper side) of the active layer 120. Likewise, the distance between the second side 141b and the drain electrode 162 may be largest at a portion overlapping the other side (e.g., the lower side) of the active layer 120.

[0053] According to an embodiment of the present disclosure, the first side 141a and the second side 141b of the gate electrode 140 are respectively formed to protrude in the direction of the source electrode 161 or the drain electrode 162, so that the gate electrode 140 may have different widths along the second direction Y. For example, the gate electrode 140 may have a first width W1 in the central portion of the active layer 120, and the gate electrode 140 may have a second width W2 in a region between the central portion of the active layer 120 and the upper side of the active layer 120. In this case, the first width W1 may be greater than the second width W2.

[0054] According to an embodiment of the present disclosure, the gate electrode 140 includes a first side 141a and a second side 141b that are protruded in the direction of the source electrode 161 or the drain electrode 162. Therefore, even if a conductive process is performed on the active layer 120 using the gate electrode 140 as a mask, the problem that the length of the channel portion in the active layer 120 is formed shorter than the designed length can be eliminated or minimized. Meanwhile, this will be referred to in detail later. Figure 1B Describe in more detail.

[0055] Figure 1B is a plan view showing an active layer of a thin film transistor substrate according to an embodiment of the present disclosure. Figure 1A The active layer of the thin film transistor substrate of the embodiment, Figure 1B This is a diagram without gate electrodes. Figure 1A The configuration of the implementation scheme is the same, so the repeated description will be omitted below.

[0056] like Figure 1B As shown, the active layer 120 may include a channel portion 121 , a first connection portion 122 a , a second connection portion 122 b , a first middle portion 123 a , and a second middle portion 123 b .

[0057] By using a gate electrode (see Figure 1AThe active layer 120 may include a channel portion 121, a first connection portion 122a, a second connection portion 122b, a first intermediate portion 123a, and a second intermediate portion 123b.

[0058] The conductive process refers to a process of increasing the electron concentration in a partial region of the active layer 120 made of an oxide semiconductor, for example, a process of performing plasma treatment in a process of etching a gate insulating layer, or a process of doping dopant ions. When the conductive process is performed, the electron concentration is increased in a partial region of the active layer 120 to have conductive properties, thereby having the same properties as a conductor. When the conductive process is performed as a process of doping dopant ions, the dopant ions may be boron B, phosphorus P, fluorine F, and hydrogen H.

[0059] According to an embodiment of the present disclosure, a conductive process such as a process of doping dopant ions may be performed using the gate electrode 140 as a mask. In this case, in the active layer 120, a region such as the channel portion 121 in which a dopant is not doped while overlapping the gate electrode 140, and a region such as the first connection portion 122a and the second connection portion 122b in which a dopant is doped while not overlapping the gate electrode 140, and further, a region such as the first middle portion 123a and the second middle portion 123b in which a dopant doped in the first connection portion 122a or the second connection portion 122b is diffused while overlapping the gate electrode may be formed. At the same time, the conductive process is not limited to the dopant doping process, but may include a conductive process by plasma treatment.

[0060] If the gate electrode does not have the protruding first and second sides and the width of the gate electrode is constant along the second direction Y, there may be a difference between the diffusion rate of dopant ions at the central portion of the active layer and the diffusion rate of dopant ions at the edge portion of the active layer.

[0061] Specifically, since the diffusion rate of the dopant ions in the central portion of the active layer is faster than the diffusion rate of the dopant ions in the edge portion of the active layer, the length of the channel portion formed in the central portion of the active layer is formed to be shorter than the length of the channel portion formed at the edge portion of the active layer. In other words, the channel portion of the active layer may be formed to be concave in the direction of the source electrode or the drain electrode in a plan view. In this case, since the length of the channel portion as designed may not be guaranteed, the characteristics of the thin film transistor substrate may be formed to be different from the designed characteristics, and the length of the entire channel portion may be shortened, resulting in leakage current.

[0062] According to one embodiment of the present disclosure, the gate electrode 140 is formed to be convex and the first width W1 at the center of the active layer 120 is formed to be maximum so that the amount of dopant ions excessively diffused to the channel portion 121 during a conduction process at the center of the active layer 120 can be reduced.

[0063] The channel portion 121 may have a first channel length L in the first direction X. CHa According to an embodiment of the present disclosure, since the gate electrode (see Figure 1A The gate electrode 140 is protrudingly disposed in the direction of the source electrode 161 or the drain electrode 162, so even if a conductive process is performed on a partial area of ​​the active layer 120 by using the gate electrode 140 as a mask, the channel portion 121 can be formed to have the same first channel length L in the second direction Y. CHa , without a separate curvature.

[0064] The first connection portion 122a and the second connection portion 122b may be formed on one side and the other side of the channel portion 121, respectively. Specifically, the first connection portion 122a may be spaced apart from the channel portion 121, and the first middle portion 123a may be interposed therebetween. Similarly, the second connection portion 122b may be spaced apart from the channel portion 121, and the second middle portion 123b may be interposed therebetween.

[0065] One side of the first connection portion 122 a may be electrically connected to the source electrode 161 through the first contact hole CH1 , and the other side of the second connection portion 122 b may be electrically connected to the drain electrode 162 through the second contact hole CH2 .

[0066] The first middle portion 123a and the second middle portion 123b may be respectively formed on one side and the other side of the channel portion 121. Specifically, the first middle portion 123a may be disposed on one side of the channel portion 121, for example, the left side, and disposed between the channel portion 121 and the first connection portion 122a, and the second middle portion 123b may be disposed on the other side of the channel portion 121, for example, the right side, and disposed between the channel portion 121 and the second connection portion 122b.

[0067] The first middle portion 123a and the second middle portion 123b may be formed along the gate electrode (see Figure 1A 140) protrudes in the direction of the source electrode 161 or the drain electrode 162.

[0068] According to an embodiment of the present disclosure, the first intermediate portion 123a and the second intermediate portion 123b are connected by gate electrodes (see Figure 1A140), but some conductive properties are provided by dopant ions or plasma diffused from the first connection portion 122a or the second connection portion 122b, and the concentration of dopant ions diffused into the first intermediate portion 123a and the second intermediate portion 123b can be relatively lower than the concentration of dopant ions doped into the first connection portion 122a and the second connection portion 122b, and can be relatively higher than the concentration of dopant ions in the channel portion 121.

[0069] Figure 2A is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present disclosure. In this case, Figure 2A The cross-sectional view corresponds to the Figure 1A A cross section taken along line II'.

[0070] like Figure 2A As shown, the thin film transistor substrate according to an embodiment of the present disclosure may include a substrate 100 , a buffer layer 110 , an active layer 120 , a gate insulating layer 130 , a gate electrode 140 , an interlayer insulating layer 150 , a source electrode 161 , and a drain electrode 162 .

[0071] The substrate 100 may be made of glass or plastic. In particular, the substrate 100 may be made of a transparent plastic having a flexible property, such as polyimide. When polyimide is used as the substrate 100, considering that a high temperature deposition process is performed on the substrate 100, a heat-resistant polyimide capable of withstanding high temperatures may be used.

[0072] The buffer layer 110 may be formed on the substrate 100. The buffer layer 110 may protect the active layer 120 by blocking air and moisture. The buffer layer 110 may be formed of an inorganic insulating material such as silicon oxide, silicon nitride, or metal oxide, but is not limited thereto and may be formed of an organic insulating material. The buffer layer 110 may be formed of a single layer, a plurality of layers, or may be omitted.

[0073] Meanwhile, although not shown in detail, a light blocking layer may be disposed between the substrate 100 and the buffer layer 110. In this case, the light blocking layer may be disposed in a larger area than the active layer 120 to prevent light introduced from the outside from traveling to the active layer 120.

[0074] The active layer 120 may be disposed on the buffer layer 110 .

[0075] The active layer 120 may include a semiconductor material, such as an oxide semiconductor material. The oxide semiconductor material may include, for example, at least one of an IZO (InZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an ITO (InSnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, and a FIZO (FeInZnO)-based oxide semiconductor material.

[0076] The active layer 120 may include a channel portion 121 , a first connection portion 122 a , a second connection portion 122 b , a first middle portion 123 a , and a second middle portion 123 b .

[0077] The channel portion 121 corresponds to a region where a separate conductive process is not performed due to the overlap of the gate electrode 140, and thus semiconductor characteristics are maintained. In this case, the channel portion 121 may have a first channel length L in the first direction X. CHa .

[0078] The first connection portion 122a and the second connection portion 122b may be respectively disposed on both sides of the channel portion 121. Specifically, the first connection portion 122a may be disposed on one side of the channel portion 121, such as the left side, and the second connection portion 122b may be disposed on the other side of the channel portion 121, such as the right side.

[0079] By performing a conductive process of ion doping or plasma treatment on a semiconductor material using the gate electrode 140 as a mask, the first connection portion 122a and the second connection portion 122b may have conductive properties. Therefore, the first connection portion 122a and the second connection portion 122b may have better conductivity than the channel portion 121, and each of them may be used as a wiring or a source / drain electrode.

[0080] The first middle portion 123a and the second middle portion 123b may be disposed between the channel portion 121, the first connection portion 122a and the second connection portion 122b, respectively. Specifically, the first middle portion 123a may be disposed between the channel portion 121 and the first connection portion 122a, and the second middle portion 123b may be disposed between the channel portion 121 and the second connection portion 122b.

[0081] Since the first middle portion 123a and the second middle portion 123b correspond to the portions overlapping with the gate electrode 140, one side (e.g., the left side) of the first middle portion 123a can be protruded in the direction of the source electrode 161 to have the same curvature as the first side 141a of the gate electrode 140, and one side (e.g., the right side) of the second middle portion 123b can be protruded in the direction of the drain electrode 162 to have the same curvature as the second side 141b of the gate electrode 140.

[0082] The first intermediate portion 123a and the second intermediate portion 123b overlap the gate electrode 140, but since the dopant ions or plasma doped into the first connection portion 122a or the second connection portion 122b diffuse during the conduction process, the conductive property may be provided to the first intermediate portion 123a and the second intermediate portion 123b by the diffused dopant ions or the diffused plasma. In this case, the conductivity of the first intermediate portion 123a and the second intermediate portion 123b may be lower than that of the first connection portion 122a and the second connection portion 122b.

[0083] According to an embodiment of the present disclosure, one end (e.g., the left end) of the first middle portion 123a may correspond to one end (e.g., the left end) of the gate electrode 140, and one end (e.g., the right end) of the second middle portion 123b may correspond to the other end (e.g., the right end) of the gate electrode 140.

[0084] The gate insulating layer 130 may be disposed on the active layer 120. In detail, the gate insulating layer 130 may be disposed on the entire surface of the substrate 100, and may be disposed on the active layer 120 and the buffer layer 110. Therefore, the active layer 120 may be surrounded by the buffer layer 110 and the gate insulating layer 130.

[0085] The gate insulating layer 130 may include a silicon nitride layer SiNx or a silicon oxide layer SiOx, but is not limited thereto. The gate insulating layer 130 may be formed of a single layer or a plurality of layers including an inorganic insulating material and / or an organic insulating material. Meanwhile, although not shown, the gate insulating layer 130 is not limited to being disposed on the entire surface of the substrate 100, and may be disposed to overlap one end and the other end of the gate electrode 140.

[0086] The gate electrode 140 may be formed on the gate insulating layer 130 .

[0087] The gate electrode 140 may have a first width W1 in the first direction X. In this case, the first width W1 may be greater than a first channel length L of the channel portion 121 . CHa .

[0088] The gate electrode 140 may include at least one of an aluminum-based metal such as aluminum Al or an aluminum alloy, a silver-based metal such as silver Ag or a silver alloy, a copper-based metal such as copper Cu or a copper alloy, a molybdenum-based metal such as molybdenum Mo or a molybdenum alloy, chromium Cr, tantalum Ta, neodymium Nd, and titanium Ti. The gate electrode 140 may have a structure including one metal layer, or a multilayer structure including at least two metal layers each having different physical properties.

[0089] The interlayer insulating layer 150 insulates between the gate electrode 140 and the source electrode 161, and also insulates between the gate electrode 140 and the drain electrode 162. The interlayer insulating layer 150 may be formed of a single layer or a plurality of layers including an inorganic insulating material and / or an organic insulating material.

[0090] A first contact hole CH1 and a second contact hole CH2 may be provided in the interlayer insulating layer 150. Therefore, a portion of an upper surface of the first connection portion 122a of the active layer 120 may be exposed by the first contact hole CH1, and further, a portion of an upper surface of the second connection portion 122b of the active layer 120 may be exposed by the second contact hole CH2.

[0091] The source electrode 161 and the drain electrode 162 may be disposed on the interlayer insulating layer 150 .

[0092] The source electrode 161 may be electrically connected to the first connection portion 122 a of the active layer 120 through the first contact hole CH1 , and the drain electrode 162 may be electrically connected to the second connection portion 122 b of the active layer 120 through the second contact hole CH2 .

[0093] The source electrode 161 and the drain electrode 162 may be formed of the same material as the gate electrode 140 , but are not limited thereto and may be formed of a material according to knowledge in the art.

[0094] Meanwhile, although not shown in detail, the source electrode 161 and the drain electrode 162 may not be disposed on the interlayer insulating layer 150, but may be formed on the same layer as the gate electrode 140 on the gate insulating layer 130. In this case, the gate electrode 140, the source electrode 161, and the drain electrode 162 may be patterned using the same material and by the same process on the same layer. Fig.9A and Fig. 9B A form in which the gate electrode 140 , the source electrode 161 , and the drain electrode 162 are formed on the same layer is described in more detail.

[0095] Figure 2B is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present disclosure. In this case, Figure 2B The cross-sectional view corresponds to the Figure 1A At the same time, in addition to the active layer and the gate electrode, Figure 2BThe implementation method and Figure 2A The implementation methods are the same, so the following will mainly describe different configurations.

[0096] like Figure 2B As shown, according to an embodiment of the present disclosure, the gate electrode 140 may be formed to have a second width W2 in the first direction X, and the second width W2 may be less than Figure 2A The gate electrode 140 has a first width W1.

[0097] Meanwhile, although the second width W2 of the gate electrode 140 is formed to be smaller than the first width W1, the length of the channel portion 121 may be the same as the length of the channel portion 121 at the central portion. That is, the channel portion 121 may have a first channel length L CHa .

[0098] In addition, Figure 2A The lengths of the first middle portion 123a and the second middle portion 123b may also be formed to be narrower than Figure 2A For example, Figure 2B The length of the first middle portion 123a and the second middle portion 123b in the first direction X may be shorter than Figure 2A The lengths of the first middle portion 123a and the second middle portion 123b.

[0099] The second width W2 of the gate electrode 140 may be formed to be narrower than Figure 2A The first width W1 of the gate electrode 140 is denoted as follows.

[0100] Figure 3 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure. Meanwhile, in addition to the configuration of the active hole provided in the active layer, Figure 3 The implementation method and Figure 1A The implementation methods are the same, so the following will mainly describe different configurations.

[0101] like Figure 3 As shown, a thin film transistor substrate according to another embodiment of the present disclosure may include an active layer 120, a gate electrode 140, a source electrode 161 and a drain electrode 162, and in this case, the active layer 120 may include a plurality of first active holes AH1 arranged adjacent to the source electrode 161 and a plurality of second active holes AH2 arranged adjacent to the drain electrode 162.

[0102] The plurality of first active holes AH1 and the plurality of second active holes AH2 may overlap the gate electrode 140. Specifically, the plurality of first active holes AH1 may be arranged along the second direction Y while overlapping the first side 141a of the gate electrode 140, and the plurality of second active holes AH2 may be arranged along the second direction Y while overlapping the second side 141b of the gate electrode 140.

[0103] One end of each of the plurality of first active holes AH1 may overlap with the gate electrode 140, and the other end of each of the plurality of first active holes AH1 may be disposed to be adjacent to the source electrode 161 without overlapping with the gate electrode 140, one end (e.g., the left end) of each of the plurality of second active holes AH2 may overlap with the gate electrode 140, and the other end of each of the plurality of second active holes AH2 may be disposed to be adjacent to the drain electrode 162 without overlapping with the gate electrode 140.

[0104] According to another embodiment of the present disclosure, a plurality of first active holes AH1 and a plurality of second active holes AH2 may be formed along the first side 141a and the second side 141b of the gate electrode 140. For example, a plurality of first active holes AH1 may be formed along the first side 141a of the gate electrode 140, and a plurality of second active holes AH2 may be formed along the second side 141b of the gate electrode 140.

[0105] like Figure 3 As shown in the enlarged view of , the plurality of first active holes AH1 may include, for example, a first hole AH1a disposed adjacent to a central portion of the active layer 120, a third hole AH1c disposed adjacent to an edge portion of the active layer 120, and a second hole AH1b disposed between the first hole AH1a and the third hole AH1c.

[0106] In this case, one end of the first hole AH1a (e.g., the right end overlapping the gate electrode 140), one end of the second active hole AH2a (e.g., the right end overlapping the gate electrode 140), and one end of the third active hole AH3a (e.g., the right end overlapping the gate electrode 140) may be spaced apart from the first side 141a of the gate electrode 140 by the same distance. By forming in this manner, a virtual curve connecting the centers of the first hole AH1a to the third hole AH1c may have the same curvature as the first side 141a of the gate electrode 140. At the same time, in Figure 3 , only the case where a virtual curve connecting the centers of one ends of the plurality of first active holes AH1 has the same curvature as the first side 141a is shown, but the present disclosure is not limited thereto, and a virtual curve connecting the centers of one ends of the plurality of first active holes AH1 may have a curvature different from that of the first side 141a.

[0107] According to another embodiment of the present disclosure, the length of a portion where each of the plurality of first active holes AH1 overlaps the gate electrode 140 may be 0.1 μm or more and 1.5 μm or less. Specifically, the minimum length from the center of one end of the plurality of first active holes AH1 to the first side 141a of the gate electrode 140 may be 0.1 μm or more and 1.5 μm or less.

[0108] When the length of the overlapping portion of the plurality of first active holes AH1 and the gate electrode 140 is less than 0.1 μm, the gate electrode 140 and the plurality of first active holes AH1 or the plurality of second active holes AH2 may not overlap each other during an actual process, and thus the channel portion (see Figure 1B The first length L of 121) CHa It may be different due to the plurality of first active holes AH1.

[0109] In addition, when the length of the overlapping portion of the plurality of first active holes AH1 and the gate electrode 140 exceeds 1.5 μm, when the thin film transistor substrate according to an embodiment of the present disclosure is turned on, the resistance of the active layer 120 may become too large, resulting in lower charge mobility and lower device characteristics of the thin film transistor substrate.

[0110] According to another embodiment of the present disclosure, the length of each of the plurality of first active holes AH1 and the plurality of second active holes AH2 may gradually increase from the edge portion of the active layer 120 toward the center portion of the active layer 120. More specifically, as Figure 3 As shown in the enlarged view of FIG. 1 , the first hole AH1a may have a first length d1, the second hole AH1b may have a second length d2, and the third hole AH1c may have a third length d3. In this case, the first length d1 may be greater than the second length d2, and the second length d2 may be greater than the third length d3.

[0111] By forming in this way, even if a conductive process is performed on a partial region of the active layer 120 by using the gate electrode 140 as a mask, a phenomenon in which the length of the channel portion in the central portion of the active layer 120 is excessively shortened can be suppressed. Therefore, in the thin film transistor substrate according to an embodiment of the present disclosure, in the first direction X, Figure 1B The lengths of the channel portions 121 in the second direction Y may be the same.

[0112] According to another embodiment of the present disclosure, since each of the plurality of first active holes AH1 has the same length at a portion overlapping the gate electrode 140, and each of the plurality of first active holes AH1 has a different length, the curvature of a virtual curve connecting the centers of one ends of the plurality of first active holes AH1 adjacent to the gate electrode 140 may be different from the curvature of a virtual curve connecting the centers of the other ends of the plurality of first active holes AH1 adjacent to the source electrode 161 (e.g., the centers of the left ends). In this case, the curvature of the virtual curve formed by the left ends of the plurality of first active holes AH1 may be smaller than the curvature of the virtual curve formed by the right ends of the plurality of first active holes AH1. Meanwhile, since the plurality of second active holes AH2 are the same as the plurality of first active holes AH1, repeated description thereof will be omitted.

[0113] According to another embodiment of the present disclosure, the first side 141a and the second side 141b of the gate electrode 140 are set to a convex curved shape, and the lengths of the plurality of first active holes AH1 and the plurality of second active holes AH2 gradually decrease from the center of the active layer 120 to the edge of the active layer 120 while overlapping with the convex gate electrode 140. Even if a conductive process for forming a thin film transistor substrate according to another embodiment of the present disclosure is performed, excessive diffusion of dopant ions or plasma into the channel portion can be prevented, thereby ensuring that the length of the channel portion is as designed.

[0114] Figure 4A is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present disclosure. In this case, Figure 4A The cross-sectional view corresponds to the Figure 3 At the same time, in addition to the configuration of the active hole, Figure 4A The implementation method and Figure 2A The implementation methods are the same, so the following will mainly describe different configurations.

[0115] like Figure 4A As shown, the active layer 120 may include a channel portion 121, a first connection portion 122a, a second connection portion 122b, a first middle portion 123a, and a second middle portion 123b. Figure 2A In different embodiments, a first hole AH1a of the plurality of first active holes AH1 may be provided on one side of the channel portion 121, such as the left side, and any one of the plurality of second active holes AH2 may be provided on the other side of the channel portion 121, such as the right side.

[0116] The first hole AH1a of the plurality of first active holes AH1 may overlap one end (eg, left end) of the gate electrode 140. By forming in this manner, one end (eg, left end) of the first middle portion 123a and one end of the gate electrode 140 may not correspond to each other.

[0117] According to another embodiment of the present disclosure, since the gate electrode 140 is provided in a convex shape and the active layer 120 is provided with a plurality of first active holes AH1 and a plurality of second active holes AH2, the channel portion 121 may have a second channel length L CHb .

[0118] According to another embodiment of the present disclosure, a first hole AH1a among the plurality of first active holes AH1 may have a first length d1 in the first direction X.

[0119] According to another embodiment of the present disclosure, by forming a plurality of first active holes AH1 and a plurality of second active holes AH2, the first middle portion 123a and the second middle portion 123b may be located inside the gate electrode 140. For example, Figure 2A Differently, one end (e.g., the right end) of the first middle portion 123a corresponds to one end (e.g., the left end) of the channel portion 121, and the other end (e.g., the left end) of the first middle portion 123a overlaps with the gate electrode 140 and may not correspond to one end (e.g., the left end) of the gate electrode 140. Similarly, one end (e.g., the left end) of the second middle portion 123b corresponds to the other end (e.g., the right end) of the channel portion 121, and the other end of the second middle portion 123b overlaps with the gate electrode 140 and may not correspond to the other end (e.g., the right end) of the gate electrode 140.

[0120] By forming in this way, Figure 2A Compared with the length of the first middle portion 123 a and the second middle portion 123 b in the first direction X, the lengths are reduced, and thus the degree to which dopant ions or plasma diffuse into the channel portion 121 may be reduced.

[0121] Figure 4B is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present disclosure. In this case, Figure 4B The cross-sectional view corresponds to the Figure 3 At the same time, in addition to the configuration of the active hole, Figure 4B The implementation method and Figure 2B The implementation methods are the same, so the following will mainly describe different configurations.

[0122] like Figure 4B As shown, the active layer 120 may include a channel portion 121, a first connection portion 122a, a second connection portion 122b, a first middle portion 123a, and a second middle portion 123b. Figure 2BIn different embodiments, the third hole AH1c of the plurality of first active holes AH1 may be provided on one side of the channel portion 121, such as the left side thereof, and any one of the plurality of second active holes AH2 may be provided on the other side of the channel portion 121, such as the right side.

[0123] The third hole AH1c of the plurality of first active holes AH1 may overlap one end (eg, left end) of the gate electrode 140. By forming in this manner, one end (eg, left end) of the first middle portion 123a and one end of the gate electrode 140 may not correspond to each other.

[0124] According to another embodiment of the present disclosure, since the gate electrode 140 is provided in a convex shape and the active layer 120 is provided with a plurality of first active holes AH1 and a plurality of second active holes AH2, the channel portion 121 may have a second channel length L CHb .in this case, Figure 4B The second channel length L of the channel portion 121 is shown CHb Can be used with Figure 4A The second channel length L of the channel portion 121 is shown CHb same.

[0125] According to another embodiment of the present disclosure, a third hole AH1c among the plurality of first active holes AH1 may have a third length d3 in the first direction X, and the third length d3 may be less than Figure 4A A first hole AH1a among the plurality of first active holes AH1 is shown to have a first length d1.

[0126] According to another embodiment of the present disclosure, by forming a plurality of first active holes AH1 and a plurality of second active holes AH2, the first middle portion 123a and the second middle portion 123b may be located inside the gate electrode 140. For example, Figure 2B Differently, one end (e.g., the right end) of the first middle portion 123a corresponds to one end (e.g., the left end) of the channel portion 121, and the other end (e.g., the left end) of the first middle portion 123a overlaps with the gate electrode 140 and may not correspond to one end (e.g., the left end) of the gate electrode 140. Similarly, one end (e.g., the left end) of the second middle portion 123b corresponds to the other end (e.g., the right end) of the channel portion 121, and the other end of the second middle portion 123b overlaps with the gate electrode 140 and may not correspond to the other end (e.g., the right end) of the gate electrode 140.

[0127] By forming in this way, Figure 2B Compared with the length of the first middle portion 123 a and the second middle portion 123 b in the first direction X, the lengths are reduced, and thus the degree to which dopant ions or plasma diffuse into the channel portion 121 may be reduced.

[0128] Figure 5A is a graph showing the channel portion length Leff depending on the position of the thin film transistor substrate according to the comparative example, and Figure 5B is a graph showing a channel portion length Leff depending on a position of a thin film transistor substrate according to another embodiment of the present disclosure.

[0129] First, according to Figure 5A The thin film transistor substrate of the comparative example corresponds to the case where the gate electrode does not have a protruding first side or a protruding second side and is not provided with a plurality of active holes, and according to Figure 5B The thin film transistor substrate of the embodiment corresponds to Figure 3 The gate electrode includes a protruding first side and a second side and a plurality of first active holes and a plurality of second active holes are arranged along the first side and the second side. In this case, Figure 5B The central portion C of the active layer and the edge portions Ea and Eb of the active layer shown correspond to Figure 3 The central portion C of the active layer and the edge portions Ea and Eb of the active layer are shown. For example, Figure 5B The lengths Leff of the channel portions at positions Ea and Eb of the active layer correspond to Figure 3 The length of the channel portion in the edge portion Ea of the active layer and the edge portion Eb of the active layer in the first direction X, and Figure 5B The length Leff of the channel portion at position C corresponds to Figure 3 The length of the channel portion in the central portion C of the active layer in the first direction X.

[0130] like Figure 5A As shown in FIG. 1 , when the protruding first side or the protruding second side is not provided, the length Leff of the channel portion formed in the central portion C of the active layer is smaller than the length Leff of the channel portion formed in the edge portions Ea and Eb of the active layer. This is because in the central portion C of the active layer 120, the diffusion rate of the dopant ions or plasma during the conductive process performed on the active layer is faster than the diffusion rate of the dopant ions or plasma in the edge portions Ea and Eb of the active layer 120.

[0131] At the same time, according to an embodiment of the present disclosure, the gate electrode 140 includes a protruding first side 141a and a protruding second side 141b, and includes a plurality of first active holes AH1 overlapping the first side 141a and a plurality of second active holes AH2 overlapping the second side 141b, so that the length Leff of the channel portion 121 formed at the central portion C of the active layer 120 and the length Leff of the channel portion 121 formed at the edge portions Ea and Eb of the active layer 120 have almost the same value.

[0132] Therefore, according to one embodiment of the present disclosure, by making the gate electrode 140 include a protruding first side 141a and a protruding second side 141b, a plurality of first active holes AH1 and a plurality of second active holes AH2 respectively overlapping each of the first side 141a and the second side 141b, although the diffusion rate of the dopant ions or plasma in the central portion C of the active layer 120 is relatively faster than the diffusion rate of the dopant ions or plasma in the edge portions Ea and Eb of the active layer 120, the length Leff of the channel portion 121 formed in the central portion C of the active layer 120 and the edge portions Ea and Eb of the active layer 120 can be formed to be the same.

[0133] Figure 6 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure. Meanwhile, in addition to the configuration of the plurality of first active holes and the plurality of second active holes, according to Figure 6 Implementation and basis Figure 3 The implementation methods are the same, so the following will mainly describe different configurations.

[0134] like Figure 6 As shown, a thin film transistor substrate according to another embodiment of the present disclosure may include an active layer 120 , a gate electrode 140 , a source electrode 161 , and a drain electrode 162 .

[0135] According to another configuration of the present disclosure, one ends of the plurality of first active holes AH1 (e.g., each of the right ends overlapping the gate electrode 140) may be connected to form a virtual straight line. One ends of the plurality of second active holes AH2 (e.g., each of the left ends overlapping the gate electrode 140) may be connected to form a virtual straight line.

[0136] The other ends of the plurality of first active holes AH1 (e.g., the center of each of the left ends adjacent to the source electrode 161) may form a virtual curve. In this case, the virtual curve formed by connecting the centers of the left ends of the plurality of first active holes AH1 may be aligned with the center of the gate electrode 140. Figure 1A Similarly, the other ends of the plurality of second active holes AH2 (e.g., the center of each of the right ends adjacent to the drain electrode 162) may form a virtual curve. In this case, the virtual curve formed by connecting the centers of the right ends of the plurality of second active holes AH2 may be aligned with the curvature of the gate electrode 140. Figure 1A The curvature of the second side 141b is the same.

[0137] According to another embodiment of the present disclosure, since the width of the gate electrode 140 decreases from the center of the active layer 120 to the edge of the active layer 120, and the lengths of the plurality of first active holes AH1 and the plurality of second active holes AH2 decrease, when a conductive process is performed on the active layer 120, the degree of diffusion of dopant ions or plasma at the center of the active layer 120 and the degree of diffusion of dopant ions or plasma at the edge of the active layer 120 are reduced, and furthermore, the length of the channel portion 121 at the center portion according to another embodiment of the present disclosure and the length of the channel portion 121 at the edge portion according to another embodiment of the present disclosure can be formed to be the same.

[0138] Figure 7 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure. Meanwhile, in addition to the configuration of the plurality of first active holes and the plurality of second active holes, Figure 7 The implementation method and Figure 3 The implementation methods are the same, so the following will mainly describe different configurations.

[0139] like Figure 7 As shown, a thin film transistor substrate according to another embodiment of the present disclosure may include an active layer 120 , a gate electrode 140 , a source electrode 161 , and a drain electrode 162 .

[0140] According to another embodiment of the present disclosure, each of the plurality of first active holes AH1 may be formed to have the same length, and each of the plurality of second active holes AH2 may be formed to have the same length.

[0141] According to another embodiment of the present disclosure, since each of the plurality of first active holes AH1 is formed with the same length, and one end of each of the plurality of first active holes AH1 (for example, the center of the right end overlapping the gate electrode 140) is connected to form a virtual curve, the degree to which the dopant ions or plasma diffuse in the central portion of the active layer 120 is lower than the degree to which the dopant ions or plasma diffuse in the edge portion of the active layer 120, so that the length of the channel portion 121 at the central portion according to another embodiment of the present disclosure and the length of the channel portion 121 at the edge portion according to another embodiment of the present disclosure can be formed to be the same.

[0142] Since each of the plurality of second active holes AH2 is formed to have the same length, and one end of each of the plurality of second active holes AH2 (for example, the center of the left end overlapping the gate electrode 140) is connected to form a virtual curve, the degree to which the dopant ions or plasma diffuse in the central portion of the active layer 120 is lower than the degree to which the dopant ions or plasma diffuse in the edge portion of the active layer 120, so that the length of the channel portion 121 at the central portion according to another embodiment of the present disclosure and the length of the channel portion 121 at the edge portion according to another embodiment of the present disclosure can be formed to be the same.

[0143] Figure 8 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure. Meanwhile, in addition to the configuration of the source electrode, the drain electrode and the conductive material layer, according to Figure 8 Implementation and basis Figure 3 The implementation methods are the same, so the following will mainly describe different configurations.

[0144] like Figure 8 As shown, a thin film transistor substrate according to another embodiment of the present disclosure may include an active layer 120 , a gate electrode 140 , a source electrode 161 , a drain electrode 162 , a first conductive material layer 200 a , and a second conductive material layer 200 b .

[0145] According to another embodiment of the present disclosure, the source electrode 161 and the drain electrode 162 include one side that is recessed in the direction of the gate electrode 140. By doing so, the area to be conducted in the active layer 120 is reduced by the source electrode 161 and the drain electrode 162, and thus the diffusion degree of dopant ions or plasma in the direction of the channel portion 121 during the conduction process performed on the active layer 120 can be reduced.

[0146] A thin film transistor substrate according to another embodiment of the present disclosure may further include a first conductive material layer 200 a and a second conductive material layer 200 b .

[0147] The first conductive material layer 200a may be disposed on one side, for example, the left side, of the active layer 120, and the second conductive material layer 200b may be disposed on the other side, for example, the right side, of the active layer 120. In this case, the first conductive material layer 200a may overlap the source electrode 161 and one side of the active layer 120, and the second conductive material layer 200b may overlap the drain electrode 162 and the other side of the active layer 120.

[0148] According to another embodiment of the present disclosure, the first conductive material layer 200a and the second conductive material layer 200b may be respectively provided in the same shape as the source electrode 161 and the drain electrode 162. Specifically, the first conductive material layer 200a includes one side that is concavely provided with a certain curvature in the direction of the gate electrode 140 similarly to the source electrode 161, and the second conductive material layer 200b includes one side that is concavely provided with a certain curvature in the direction of the gate electrode 140 similarly to the drain electrode 162.

[0149] Fig.9A is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig.9A The cross-sectional view corresponds to the Figure 8 Meanwhile, in addition to the configuration of the active layer, the source electrode, the drain electrode and the conductive material layer, Fig.9A The implementation method and Figure 4A The implementation methods are the same, so the following will mainly describe different configurations.

[0150] like Fig.9A As shown, a thin film transistor substrate according to another embodiment of the present disclosure may include a substrate 100, a buffer layer 110, an active layer 120, a gate insulating layer 130, a gate electrode 140, an interlayer insulating layer 150, a source electrode 161, a drain electrode 162, a first conductive material layer 200a and a second conductive material layer 200b.

[0151] According to Figure 4A Unlike the embodiment of the present invention, the source electrode 161 and the drain electrode 162 are disposed on the gate insulating layer 130 and may be formed of the same material and in the same layer as the gate electrode 140. In addition, the source electrode 161 and the drain electrode 162 may be patterned in the same process as the gate electrode 140.

[0152] Therefore, a separate contact hole for connecting the active layer 120 with the source electrode 161 or the drain electrode 162 may not be provided in the interlayer insulating layer 150 .

[0153] In a thin film transistor substrate according to another embodiment of the present disclosure, since the gate electrode 140, the source electrode 161 and the drain electrode 162 are formed on the same layer and in the same process, not only the gate electrode 140 but also the source electrode 161 and the drain electrode 162 are used as masks to give conductive properties to some areas of the active layer 120.

[0154] Specifically, the active layer 120 includes a channel portion 121, a first connection portion 122a, a second connection portion 122b, a first middle portion 123a, and a second middle portion 123b. In this case, since the channel portion 121, the first middle portion 123a, and the second middle portion 123b are connected to the above Figure 4A , and thus repeated description thereof will be omitted.

[0155] According to another embodiment of the present disclosure, the first connection portion 122a includes a first region 122a1 that does not overlap with the source electrode 161 and a second region 122a2 that overlaps with the source electrode 161. In this case, the first region 122a1 is not covered by the source electrode 161, and thus may have a conductive property by dopant ions or plasma when a conductive process is performed, and since the second region 122a2 is covered by the source electrode 161, a separate conductive property may not be provided when a conductive process is performed.

[0156] Likewise, the second connection portion 122b includes a first region 122b1 that does not overlap the drain electrode 162 and a second region 122b2 that overlaps the drain electrode 162. In this case, the first region 122b1 is not covered by the drain electrode 162 and thus may have conductive properties by dopant ions or plasma when a conductive process is performed, while the second region 122b2 may not have a separate conductive property during the conductive process.

[0157] The first conductive material layer 200a may be disposed on the first connection portion 122a. Specifically, the first conductive material layer 200a may be disposed in contact with the upper surface of the second region 122a2 of the first connection portion 122a. Similarly, the second conductive material layer 200b may be disposed on the second connection portion 122b. Specifically, the second conductive material layer 200b may be disposed in contact with the upper surface of the second region 122b2 of the second connection portion 122b. By forming as described above, the active layer 120 and the source electrode 161 may be electrically connected to each other through the first conductive material layer 200a, and the active layer 120 and the drain electrode 162 may be electrically connected to each other through the second conductive material layer 200b.

[0158] The source electrode 161 or the drain electrode 162 may have a first length L1 in the first direction X. Figure 8 , since the source electrode 161 or the drain electrode 162 of the thin film transistor substrate according to another embodiment of the present disclosure has a concave side toward the gate electrode 140, the first length L1 of the source electrode 161 or the drain electrode 162 disposed in the middle region of the active layer 120 may be formed to be shorter than the second length L1 of the source electrode 161 or the drain electrode 162 disposed at the edge portion of the active layer 120 (see Fig. 9B of L2).

[0159] Fig. 9B is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig. 9B The cross-sectional view corresponds to the Figure 8Meanwhile, in addition to the configuration of the active layer, the gate electrode, the source electrode, the drain electrode, the first conductive material layer and the second conductive material layer, Fig. 9B The implementation method and Fig.9A The implementation methods are the same, so the following will mainly describe different configurations.

[0160] like Fig. 9B As shown, the first connection portion 122a and the second connection portion 122b of the active layer 120 may be formed to be longer than Fig.9A The first connection portion 122a and the second connection portion 122b of the thin film transistor substrate of the embodiment.

[0161] Combination Figure 8 Since the source electrode 161 or the drain electrode 162 of the thin film transistor substrate according to another embodiment of the present disclosure has a concave side toward the gate electrode 140, the second length L2 of the source electrode 161 or the drain electrode 162 disposed in the edge portion of the active layer 120 may be formed to be longer than the first length of the source electrode 161 or the drain electrode 162 disposed in the central portion of the above-mentioned active layer 120 (see Fig.9A of L1).

[0162] By forming in this manner, the area of ​​the active layer 120 to be conducted is reduced by the source electrode 161 and the drain electrode 162 , so that the diffusion degree of dopant ions or plasma during the conduction process performed on the active layer 120 can be reduced.

[0163] Fig.10 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig.10 The cross-sectional view corresponds to the Figure 8 In addition to the configuration of the gate insulating layer, Fig.10 The implementation method and Fig.9A The implementation methods are the same, so the following will mainly describe different configurations.

[0164] like Fig.10 As shown, a thin film transistor substrate according to another embodiment of the present disclosure may be formed by an etching structure in which a partial region of the gate insulating layer 130 is etched.

[0165] Specifically, the etching structure refers to a structure in which one end and the other end of the gate insulating layer 130 are formed to overlap with one end and the other end of the gate electrode 140 by dry etching a partial region of the gate insulating layer 130 using the gate electrode 140 as a mask.

[0166] In this case, the gate insulating layer 130 may be formed on the substrate 100 to correspond to the gate electrode 140 , rather than being formed on the entire surface of the substrate 100 .

[0167] According to Fig.9A In different embodiments, the source electrode 161 and the drain electrode 162 may be arranged to directly contact the upper surface of the first conductive material layer 200a and the second conductive material layer 200b. Specifically, the source electrode 161 may be arranged to contact the upper surface of the first conductive material layer 200a, and the drain electrode 162 may be arranged to contact the upper surface of the second conductive material layer 200b.

[0168] According to another embodiment of the present disclosure, a portion of the gate insulating layer 130 may be disposed inside the plurality of first active holes AH1 and the plurality of second active holes AH2 , and a portion of the interlayer insulating layer 150 may be disposed inside the plurality of first active holes AH1 and the plurality of second active holes AH2 .

[0169] Fig.11 is a cross-sectional view of a display device including a thin film transistor substrate according to an embodiment of the present disclosure.

[0170] like Fig.11 As shown, the display device according to an embodiment of the present disclosure includes a substrate 100, a buffer layer 110, an active layer 120, a gate insulating layer 130, a gate electrode 140, an interlayer insulating layer 150, a source electrode 161, a drain electrode 162, a planarization layer 170, a first electrode 300, a dam layer 310, a light-emitting layer 320 and a second electrode 330.

[0171] Since the substrate 100 , the buffer layer 110 , the active layer 120 , the gate insulating layer 130 , the gate electrode 140 , the interlayer insulating layer 150 , the source electrode 161 , and the drain electrode 162 are the same as those in the above embodiment, only different configurations will be described below.

[0172] A planarization layer 170 may be disposed on the source electrode 161 and the drain electrode 162 .

[0173] The third contact hole CH3 may be provided in the planarization layer 170 so that the source electrode 161 may be exposed by the third contact hole CH3. However, in some cases, the drain electrode 162 may be exposed by the third contact hole CH3.

[0174] The first electrode 300 may be formed on the planarization layer 170, and may be connected to the source electrode 161 or the drain electrode 162 through a contact hole. The first electrode 300 may function as an anode.

[0175] The bank layer 310 may be provided to cover the edge of the first electrode 300 to define a light emitting region. Therefore, an upper surface region of the first electrode 300 that is not covered by the bank layer 310 and exposed becomes a light emitting region.

[0176] The light emitting layer 320 may be disposed on the first electrode 300. The light emitting layer 320 may include red, green, and blue light emitting layers patterned for each pixel, or may include a white light emitting layer connected from all pixels. When the light emitting layer 320 is formed of a white light emitting layer, the light emitting layer 320 may include, for example, a first stack including a blue light emitting layer, a second stack including a yellow-green light emitting layer, and a charge generation layer disposed between the first stack and the second stack, but is not limited thereto.

[0177] The second electrode 330 may be disposed on the light emitting layer 320. The second electrode 330 may function as a cathode.

[0178] Although not shown, an encapsulation layer for preventing penetration of moisture or oxygen may be additionally formed on the second electrode 330 .

[0179] Fig.12 is a schematic diagram of a display device according to an embodiment of the present disclosure.

[0180] like Fig.12 As shown, the display device according to an embodiment of the present disclosure may include a display panel 410 , a gate driver 420 , a data driver 430 , and a controller 440 .

[0181] The display panel 410 includes gate lines GL and data lines DL, and pixels P are disposed in respective crossing regions of the gate lines GL and the data lines DL. An image is displayed by driving the pixels P. The gate lines GL, the data lines DL, and the pixels P may be disposed on the substrate 100 .

[0182] The controller 440 controls the gate driver 420 and the data driver 430. The controller 440 outputs a gate control signal GCS for controlling the gate driver 420 and a data control signal DCS for controlling the data driver 430 by using a signal provided from an external system (not shown). In addition, the controller 440 samples input video data input from the external system and rearranges the sampled input video data, and provides the rearranged digital video data RGB to the data driver 430.

[0183] The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. In addition, a control signal for controlling a shift register may be included in the gate control signal GCS.

[0184] The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

[0185] The data driver 430 supplies data voltages to the data lines DL of the display panel 410. Specifically, the data driver 430 converts the video data RGB input from the controller 440 into analog data voltages and supplies the data voltages to the data lines DL.

[0186] The gate driver 420 may be mounted on the display panel 410. As described above, the structure in which the gate driver 420 is directly mounted on the display panel 410 is referred to as a gate-in-panel (GIP) structure. Specifically, in the gate-in-panel (GIP) structure, the gate driver 420 may be disposed on the substrate 100.

[0187] The gate driver 420 may include a shift register 450 .

[0188] The shift register 450 sequentially supplies gate pulses to the gate lines GL during one frame by using a start signal and a gate clock transmitted from the controller 440. Herein, one frame refers to a period during which one image is output through the display panel 410. The gate pulse has a turn-on voltage capable of turning on a switching device (thin film transistor) provided in the pixel P.

[0189] In addition, during the remaining period of one frame in which no gate pulse is supplied, the shift register 450 supplies a gate-off signal to the gate line GL that enables the switching device to be turned off. Hereinafter, the gate pulse and the gate-off signal are collectively referred to as a scan signal GS.

[0190] Fig.13 is a circuit diagram of a pixel included in a display device according to an embodiment of the present disclosure.

[0191] like Fig.13 As shown, the display device according to the embodiment of the present disclosure includes first to second thin film transistors T1 to T2 and a capacitor Cst.

[0192] The first thin film transistor T1 is a driving thin film transistor, and the second thin film transistor T2 is a switching thin film transistor. At least one of the first thin film transistor T1 and the second thin film transistor T2 may be formed by the various thin film transistors described above.

[0193] The first thin film transistor T1 is switched according to the data voltage Vdata supplied from the second thin film transistor T2 , generates a data current according to the driving voltage VDD supplied from the power line PL, and supplies it to the organic light emitting diode OLED.

[0194] The second thin film transistor T2 is switched according to the gate signal GS supplied to the gate line GL, and supplies the data voltage Vdata supplied from the data line DL to the first thin film transistor T1 .

[0195] According to the embodiments of the present disclosure, according to the above Figures 1A to 10 The thin film transistor of the embodiment may be used as any one of the first thin film transistor T1 and the second thin film transistor T2.

[0196] The capacitor Cst serves to maintain a data voltage supplied to the first thin film transistor T1 within one frame, and is provided between a gate electrode and a source electrode of the first thin film transistor T1.

[0197] The organic light emitting diode OLED emits predetermined light according to the data current supplied from the first thin film transistor T1.

[0198] Fig.14 is a circuit diagram of a pixel included in a display device according to another embodiment of the present disclosure.

[0199] like Fig.14 As shown, a display device according to another embodiment of the present disclosure includes first to third thin film transistors T1 , T2 , and T3 and a capacitor Cst.

[0200] The first thin film transistor T1 is a driving thin film transistor, and the second to third thin film transistors T2 to T3 are switching thin film transistors.

[0201] The first thin film transistor T1 is switched according to the data voltage Vdata supplied from the second thin film transistor T2 , generates a data current according to the driving voltage VDD supplied from the power line PL, and supplies it to the organic light emitting diode OLED.

[0202] The second thin film transistor T2 is switched according to the gate signal GS supplied to the gate line GL, and supplies the data voltage Vdata supplied from the data line DL to the first thin film transistor T1 .

[0203] The third thin film transistor T3 supplies the current of the first thin film transistor T1 to the reference line RL in response to the sensing control signal SENSE supplied from the scan line SCL. A reference voltage Vref is supplied to the reference line RL.

[0204] According to the embodiments of the present disclosure, according to the above Figures 1A to 10 The thin film transistor of the embodiment may be used as any one of the first to third thin film transistors T1 to T3 .

[0205] The capacitor Cst serves to maintain a data voltage supplied to the first thin film transistor T1 within one frame, and is provided between a gate electrode and a source electrode of the first thin film transistor T1.

[0206] The organic light emitting diode OLED emits predetermined light according to the data current supplied from the first thin film transistor T1.

[0207] Fig.15 is a circuit diagram of a pixel included in a display device according to another embodiment of the present disclosure.

[0208] like Fig.15 As shown, a display device according to another embodiment of the present disclosure includes first to fourth thin film transistors T1 , T2 , T3 , and T4 and a capacitor Cst.

[0209] The first thin film transistor T1 is a driving thin film transistor, and the second to fourth thin film transistors T2 to T4 are switching thin film transistors.

[0210] The first thin film transistor T1 is switched according to the data voltage Vdata supplied from the second thin film transistor T2 , generates a data current according to the driving voltage VDD supplied from the power line PL, and supplies it to the organic light emitting diode OLED.

[0211] The second thin film transistor T2 is switched according to the gate signal GS supplied to the gate line GL, and supplies the data voltage Vdata supplied from the data line DL to the first thin film transistor T1 .

[0212] The third thin film transistor T3 supplies the current of the first thin film transistor T1 to the reference line RL in response to the sensing control signal SENSE supplied from the scan line SCL. A reference voltage Vref is supplied to the reference line RL.

[0213] The fourth thin film transistor T4 is switched according to the light emission control signal EM supplied to the light emission control line EML, and supplies the driving voltage VDD supplied from the power line PL to the first thin film transistor T1 .

[0214] According to the embodiments of the present disclosure, according to the above Figures 1A to 10 The thin film transistor of the embodiment may be used as any one of the first to fourth thin film transistors T1 to T4 .

[0215] The capacitor Cst serves to maintain a data voltage supplied to the first thin film transistor T1 within one frame, and is provided between a gate electrode and a source electrode of the first thin film transistor T1.

[0216] The organic light emitting diode OLED emits predetermined light according to the data current supplied from the first thin film transistor T1.

[0217] Fig.16 is a schematic diagram of a shift register according to an embodiment of the present disclosure.

[0218] like Fig.16 As shown, each of the plurality of GIP circuits GIP1 , GIP2 , GIP3 , and GIP4 outputs gate signals Vout1 , Vout2 , Vout3 , and Vout4 for one frame and supplies them to gate wirings.

[0219] Specifically, the first stage Stage 1 of the first GIP circuit GIP1 is activated by a separate start signal Vst, outputs a first gate signal Vout1 using a first clock signal CLK1, and is provided to a first gate wiring.

[0220] The second stage Stage 2 to the fourth stage Stage 4 of each of the second to fourth GIP circuits GIP2, GIP3 and GIP4 are started by the signal Vst, and the second to fourth gate signals Vout2, Vout3 and Vout4 are output using the second to fourth clock signals CLK2, CLK3 and CLK4, and are provided to the second to fourth gate wirings.

[0221] On the other hand, although not shown, when the last gate signal Vout is output at the stage of the last GIP circuit at the end of one frame, the stage of the last GIP circuit is initialized by receiving the reset signal Vreset, and then the first gate signal Vout1 is output at the first stage Stage 1 of the first GIP circuit GIP1 at the beginning of the next frame, and the above is repeated.

[0222] Fig.17 is a circuit diagram of a shift register according to an embodiment of the present disclosure.

[0223] like Fig.17 As shown, the GIP circuit includes a pull-up node Q, a pull-down node QB, a node controller NC and a buffer unit Buffer.

[0224] The buffer unit Buffer is connected to the output terminal, and includes a pull-up transistor Tu, a pull-down transistor Td, and a capacitor C.

[0225] When the pull-up node Q is charged with a gate high voltage, the pull-up transistor Tu is turned on to output a gate-on signal.

[0226] When the pull-down node QB is charged with the gate low voltage, the pull-down transistor Td is turned on to output a gate-off signal.

[0227] The capacitor C is used to maintain a gate high voltage supplied to the pull-up transistor Tu within one frame, and is provided between the gate terminal and the source terminal of the pull-up transistor Tu.

[0228] The node controller NC controls the charging and discharging between the pull-up node Q and the pull-down node QB. The node controller NC may include a pull-up node controller NC_Q for controlling the charging and discharging of the pull-up node Q and a pull-down node controller NC_QB for controlling the charging and discharging of the pull-down node QB. The pull-up node controller NC_Q includes at least one transistor T for controlling the pull-up node Q. Q , and the pull-down node controller NC_QB includes at least one transistor T for controlling the pull-down node QB QB .

[0229] The output of the gate signal Vout can be stably controlled by the node controller NC. Specifically, when the pull-up node Q is charged with the gate high voltage, the node controller NC discharges the pull-down node QB to the gate low voltage, and when the pull-down node QB is charged with the gate high voltage, the node controller NC discharges the pull-up node Q to the gate low voltage.

[0230] Therefore, when the start signal Vst is applied, the plurality of transistors T1 and T2 provided in the node controller NC are connected. Q and T QB The operation of the gate high voltage charges the pull-up node Q and discharges the pull-down node QB with the gate low voltage, thereby outputting the high power voltage VDD as the gate signal Vout. In addition, when the discharge signal V QB When multiple transistors T are set in the node controller NC Q and T QB The operation of the gate MOSFET charges the pull-up node Q with a gate low voltage and charges the pull-down node QB with a gate high voltage to output the low power voltage VSS as the gate signal Vout.

[0231] According to the embodiments of the present disclosure, according to the above Figures 1A to 10 The thin film transistor of the embodiment of the present invention may be used as a pull-up transistor Tu, a pull-down transistor Td, and a plurality of transistors T provided in a node controller NC. Q and T QB Therefore, the present disclosure may have the following advantages.

[0232] According to one embodiment of the present disclosure, the gate electrode is provided in a convex shape, and the width of the gate electrode increases from the edge of the active layer to the center of the active layer. Even if a conductive process is performed using the gate electrode as a mask to make a partial area of ​​the active layer conductive, the diffusion degree of the dopant ions or plasma in the center of the active layer can be controlled so that the length of the channel portion in the central portion of the active layer is the same as the length of the channel portion in the edge portion of the active layer.

[0233] According to an embodiment of the present disclosure, a plurality of active holes may be disposed along one side of a gate electrode disposed in a convex shape, and the plurality of active holes may gradually become longer from an edge of the active layer toward a center of the active layer.

[0234] According to an embodiment of the present disclosure, a gate electrode having a convex shape and a plurality of active holes formed along the convex side of the gate electrode may be formed to have channel portions of the same length at a central portion of an active layer and an edge portion of the active layer, thereby achieving designed device characteristics.

[0235] According to an embodiment of the present disclosure, when the source electrode and the drain electrode include a side having a certain curvature like the gate electrode, and thus the conductive process uses the source electrode, the drain electrode and the gate electrode as a mask to give conductive properties to a partial area of ​​the active layer, the conductive area of ​​the active layer can be reduced by the curved shape of the source electrode and the drain electrode, and the total amount of dopants or plasma diffused into the active layer can be reduced, thereby eliminating or minimizing the excessive reduction in the length of the channel portion in the central portion of the active layer.

[0236] It is obvious to those skilled in the art that various substitutions, modifications and variations can be made within the scope of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the scope of the present disclosure is represented by the appended claims, and all changes or modifications derived from the meaning, scope and equivalent concepts of the claims should be interpreted as included within the scope of the present disclosure.

Claims

1. A thin film transistor substrate, comprising: substrate; an active layer disposed on the substrate; a gate electrode disposed on the active layer; a source electrode connected to one side of the active layer; as well as a drain electrode connected to the other side of the active layer, wherein the gate electrode comprises a first side protruding in a direction of either the source electrode or the drain electrode, The active layer includes a plurality of first active holes overlapping the first side, and The plurality of first active holes are arranged in a direction perpendicular to a direction in which the source electrode and the drain electrode face each other.

2. The thin film transistor substrate according to claim 1, in, The first side, which is convexly disposed in a direction of any one of the source electrode and the drain electrode, is disposed in an arc shape having a certain curvature.

3. The thin film transistor substrate according to claim 1, in, The active layer includes a channel portion, a first connection portion disposed on one side of the channel portion, and a first intermediate portion disposed between the channel portion and the first connection portion. wherein the first connecting portion does not overlap with the gate electrode, The first intermediate portion overlaps the gate electrode, and An end side of the first intermediate portion is convexly disposed to correspond to the first side of the gate electrode.

4. The thin film transistor substrate according to claim 1, in, The active layer includes a channel portion, a first connection portion disposed on one side of the channel portion, and a first intermediate portion disposed between the channel portion and the first connection portion. wherein the first connecting portion does not overlap with the gate electrode, The first intermediate portion is disposed inside the gate electrode, and An end side of the first intermediate portion does not correspond to the first side of the gate electrode.

5. The thin film transistor substrate according to claim 1, in, A length of any one of the plurality of first active holes closest to an upper side of the active layer is shorter than a length of another first active hole of the plurality of first active holes closest to a center of the active layer.

6. The thin film transistor substrate according to claim 1, in, Another first active hole among the plurality of first active holes is disposed between any one of the plurality of first active holes closest to the upper side of the active layer and another first active hole among the plurality of first active holes closest to the center of the active layer, and The length of the further first active hole is longer than the length of any one of the first active holes, and shorter than the length of the further first active hole.

7. The thin film transistor substrate according to claim 5, in, A length of a portion where any one of the plurality of first active holes overlaps the gate electrode and a length of a portion where another one of the plurality of first active holes overlaps the gate electrode are identical to each other.

8. The thin film transistor substrate according to claim 1, in, A length of a portion of each of the plurality of first active holes overlapping the gate electrode is equal to or greater than 0.1 μm and equal to or less than 1.5 μm.

9. The thin film transistor substrate according to claim 1, in, One ends of the plurality of first active holes are disposed along the first side of the gate electrode with a predetermined curvature.

10. The thin film transistor substrate according to claim 9, in, A curvature formed by the one end of the plurality of first active holes is smaller than a curvature formed by the other end of the plurality of first active holes, The one end of each of the plurality of first active holes is disposed adjacent to any one of the source electrode and the drain electrode, and The other end of each of the plurality of first active holes is disposed adjacent to the gate electrode.

11. The thin film transistor substrate according to claim 9, in, The other ends of the plurality of first active holes form a virtual straight line, The one end of each of the plurality of first active holes is disposed adjacent to any one of the source electrode and the drain electrode, and The other end of each of the plurality of first active holes is disposed adjacent to the gate electrode.

12. The thin film transistor substrate according to claim 9, in, Each of the plurality of first active holes has the same length.

13. The thin film transistor substrate according to claim 1, in, Either one of the source electrode and the drain electrode includes a second side that is disposed concavely in a direction of the gate electrode.

14. The thin film transistor substrate according to claim 13, in, The second side concave in the direction of the gate electrode is provided in an arc shape having a certain curvature.

15. The thin film transistor substrate according to claim 13, further comprising: a first conductive material layer disposed on the active layer, The first conductive material layer includes a third side that is recessed in the direction of the gate electrode.

16. The thin film transistor substrate according to claim 1, in, The gate electrode includes a fourth side disposed protruding in a direction of the other of the source electrode and the drain electrode.

17. The thin film transistor substrate according to claim 16, in, The active layer further includes a plurality of second active holes overlapping the fourth side, and The plurality of second active holes are arranged in a direction perpendicular to a direction in which the source electrode and the drain electrode face each other.

18. The thin film transistor substrate according to claim 17, in, Each of the plurality of second active holes has a different length, and A length of any one of the plurality of second active holes closest to the upper side of the active layer is shorter than a length of another second active hole of the plurality of second active holes closest to the center of the active layer.

19. The thin film transistor substrate according to claim 17, in, One ends of the plurality of second active holes are disposed along the fourth side of the gate electrode with a predetermined curvature.

20. A display device comprising a thin film transistor substrate, the thin film transistor substrate comprising: substrate; an active layer disposed on the substrate; a gate electrode disposed on the active layer; a source electrode connected to one side of the active layer; as well as a drain electrode connected to the other side of the active layer, wherein the gate electrode comprises a first side protruding in a direction of either the source electrode or the drain electrode, The active layer includes a plurality of first active holes overlapping the first side, and The plurality of first active holes are arranged in a direction perpendicular to a direction in which the source electrode and the drain electrode face each other.

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