Layout structure of a power MOSFET gate driver chip

Abstract

A layout structure of a power MOSFET gate driver chip, which relates to the field of integrated circuit design. It includes a power supply module, a current mirror module, a logic control module, a bias module, a turn-on module, and a turn-off module. The turn-on module includes a charging NMOS group, and the turn-off module includes a discharging NMOS group. Each module is interconnected through a third metal conductive layer M3, a fourth metal conductive layer M4, and a top metal conductive layer TM1. The top metal conductive layer TM1 and the fourth metal conductive layer M4 interconnected with the port VDD1 and the port GND in the layout surround the layout, providing good stability. The top metal TM1 interconnected with the port Vout and the port GND2 in the layout structure completes the electrical connection in a short distance, reduces the parasitic inductance and parasitic resistance on the basis of realizing the function, realizes the high current-carrying capacity while reducing the area required for the layout, and meets the high power density requirements of industry manufacturers for power electronic devices.

Description

Technical Field

[0001] This invention patent relates to the field of integrated circuit design, and particularly to a layout structure of a power MOSFET gate driver chip. Background Art

[0002] Power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is an essential key power device in power electronic devices. It is the core of power conversion and circuit control in electronic devices and is used to drive various types of motor loads and electronic loads. The power MOSFET gate driver chip integrates circuit modules such as a power supply module, a current mirror module, a logic control module, a bias module, a turn-on module, and a turn-off module. Among them, the turn-on module and the turn-off module have a relatively large current, so the module occupies a large area. The layout of the driver chip is particularly crucial for improving power density. Therefore, to meet the high power density requirements of the industry for power electronic devices, it is necessary to design a new layout scheme to reduce the area required for the layout while achieving high current-carrying capacity. Summary of the Invention

[0003] The present invention aims to meet the high power density requirements of the industry for power electronic devices and also to meet the need for designing a new layout scheme to reduce the area required for the layout while achieving high current-carrying capacity. A layout structure of a power MOSFET gate driver chip is provided.

[0004] The technical solution adopted by the present invention is as follows:

[0005] A layout structure of a power MOSFET gate driver chip, which includes a power supply module (1), a logic control module (2), a current mirror module (3), a bias module (4), a turn-on module (5), a turn-off module (6), an input port Vin (10), an input port VDD1 (11), an input port VDD2 (12), an output port Vout (13), a port GND (14), a port PARA (15), and a port GND2 (16).

[0006] The input end of the power supply module (1) is connected to the input port VDD1 (11), and its output end is connected to the input ends of the logic control module (2), the current mirror module (3), and the bias module (4) and the port GND (14).

[0007] The input end of the logic control module (2) is connected to the input port Vin (10), and its output end is connected to the input ends of the turn-on module (5) and the turn-off module (6) and the port GND (14).

[0008] The input end of the current mirror module (3) is connected to the output end of the power supply module (1), and its output end is connected to the input ends of the turn-on module (5) and the turn-off module (6) and the port GND (14);

[0009] The input end of the bias module (4) is connected to the output end of the power supply module (1) and the port PARA (15), and its output end is connected to the input ends of the turn-on module (5) and the turn-off module (6) and the port GND (14);

[0010] The turn-on module (5) includes a charge NMOS group (NLDMOS1). The input end of the turn-on module (5) is connected to the output end of the logic control module (2), the output end of the bias module (4), and the input port VDD2 (12). The output end of the turn-on module (5) is connected to the output port Vout (13) and the port GND (14);

[0011] The turn-off module (6) includes a discharge NMOS group (NLDMOS2), and its input end is connected to the output end of the logic control module (2), the output end of the bias module (4), and the port GND2 (16).

[0012] Further, it further includes a fourth metal conductive layer (M4) and a top metal conductive layer (TM1);

[0013] The input port Vin (10) is used to connect a switched PWM signal. The input port Vin (10) is connected to the logic control module (2) through the fourth metal conductive layer (M4);

[0014] The input port VDD1 (11) is used to connect the supply voltage VDD1. The input port VDD1 (11) is connected to the top metal conductive layer (TM1) and is arranged in a surrounding manner on the inner side, and is used to avoid the top metal conductive layer (TM1) above the turn-on module (5) and the turn-off module (6) through the fourth metal conductive layer (M4); The input port VDD1 (11) is connected to the power supply module (1) through the top metal conductive layer (TM1);

[0015] The input port VDD2 (12) is used to connect the supply voltage VDD2. The input port VDD2 (12) is connected to the turn-on module (5) through the top metal conductive layer (TM1);

[0016] The port PARA (15) is used to connect an externally input bias voltage. The port PARA (15) is connected to the bias module (4) through the fourth metal conductive layer (M4);

[0017] The output port Vout (13) is used to connect to the gate of an external power MOSFET. The output port Vout (13) is connected to the turn-on module (5) and the turn-off module (6) through the top metal conductive layer (TM1).

[0018] The port GND (14) is used to connect to the digital ground. The port GND (14) is connected to the top metal conductive layer (TM1) and is arranged in a surrounding manner on the outside. The port GND (14) is connected to the power supply module (1), the logic control module (2), the current mirror module (3), the bias module (4), and the turn-on module (5) through the top metal conductive layer (TM1).

[0019] The port GND2 (16) is used to connect to the analog ground. The port GND2 (16) is connected to the top metal conductive layer (TM1) and is connected to the turn-off module (6) through the top metal conductive layer.

[0020] Furthermore, it further includes a second metal conductive layer (M2) and a third metal conductive layer (M3).

[0021] The power supply module (1) is connected to the input port VDD1 (11) through the top metal conductive layer (TM1) above the power supply module (1). The power supply module (1) is connected to the logic control module (2), the current mirror module (3), and the bias module (4) through the fourth metal conductive layer (M4). The power supply module (1) is connected to the port GND (14) through the top metal conductive layer (TM1).

[0022] The logic control module (2) is connected to the power supply module (1) through the fourth metal conductive layer (M4) above the logic control module (2), connected to the input port Vin (10) through the fourth metal conductive layer, connected to the turn-on module (5) and the turn-off module (6) respectively through the third metal conductive layer (M3), and connected to the port GND (14) through the top metal conductive layer (TM1).

[0023] The current mirror module (3) is connected to the power supply module (1) through the fourth metal conductive layer (M4) above the current mirror module (3), connected to the bias module (4) through the second metal conductive layer (M2), and connected to the port GND (14) through the top metal conductive layer (TM1).

[0024] The bias module (4) is connected to the power supply module (1) through the fourth metal conductive layer (M4) above the bias module (4), connected to the current mirror module (3) through the second metal conductive layer (M2), and connected to the port GND (14) through the top metal conductive layer (TM1).

[0025] The enabling module (5) has its upper part connected to the input port VDD2 (12) through the top metal conductive layer (TM1), connected to the logic control module (2) through the third metal conductive layer (M3), connected to the bias module (4) through the third metal conductive layer (M3), connected to the port GND (14) through the top metal conductive layer (TM1), and connected to the output port Vout (13) through the top metal conductive layer (TM1).

[0026] The disabling module (6) has its upper part extending above the enabling module (5) through the top metal conductive layer (TM1), and using the top metal conductive layer (TM1) to connect to the output port Vout (13); connected to the port GND2 (16) through the top metal conductive layer (TM1), connected to the logic control module (2) through the third metal conductive layer (M3), and connected to the bias module (4) through the third metal conductive layer (M3).

[0027] Furthermore, it also includes a via (M4-TM1). The energizing NMOS group (NLDMOS1) in the enabling module (5) contains multiple energizing NMOSs. The drain of the energizing NMOSs extends through the fourth metal conductive layer (M4) to the lower part of the top metal conductive layer (TM1) that connects to the input port VDD2 (12) above, and the metal interconnection between the drain of the energizing NMOS group and the input port VDD2 (12) is completed through the via (M4-TM1).

[0028] Furthermore, the discharging NMOS group (NLDMOS2) in the disabling module (6) contains multiple discharging NMOSs. The drain of the discharging NMOSs extends through the fourth metal conductive layer (M4) to the lower part of the top metal conductive layer (TM1) that connects to the output port Vout (13) above, and the metal interconnection between the drain of the discharging NMOS group and the output port Vout (13) is completed through the via (M4-TM1).

[0029] Furthermore, the input port VDD1 (11) is not only arranged around the inner side through the top metal conductive layer (TM1), but also longitudinally extends above the power supply module (1) through the top metal conductive layer (TM1);

[0030] The input port VDD2 (12) longitudinally extends above the enabling module (5) through the top metal conductive layer (TM1), and the fourth metal conductive layer (M4) below it forms an interconnection with the top metal conductive layer (TM1) connecting to the port VDD1 through the via (M4-TM1);

[0031] The output port Vout (13) laterally extends above the energizing NMOS group (NLDMOS1) in the enabling module (5) through the top metal conductive layer (TM1), and then longitudinally extends above the disabling module (6);

[0032] The port GND (14) is not only arranged around the outside through the top metal conductive layer (TM1), but also longitudinally extends above the current mirror module (3) and the power supply module (1) through the top metal conductive layer (TM1);

[0033] The port GND2 (16) laterally extends through the top metal conductive layer (TM1) above the discharge NMOS group (NLDMOS2) in the turn-off module (6);

[0034] Above the power supply module (1), it laterally extends through the fourth metal conductive layer (M4) past the current mirror module (3) and the logic control module (2), and longitudinally extends above the bias module (4); it is longitudinally connected to the input port VDD1 (11) through the top metal conductive layer (TM1);

[0035] Above the logic control module (2), it longitudinally extends through the third metal conductive layer (M3) to be close to the bias module (4), then laterally extends above the turn-off module (6), and longitudinally extends again to the turn-on module (5);

[0036] Above the current mirror module (3), it laterally extends through the fourth metal conductive layer (M4) above the power supply module (1); it longitudinally extends above the bias module (4) through the second metal conductive layer (M2); it laterally forms an interconnection with the top metal conductive layer longitudinally extending from the port GND (14) through the top metal conductive layer (TM1);

[0037] Above the bias module (4), it longitudinally extends through the fourth metal conductive layer (M4) above the power supply module (1); it longitudinally extends to the current mirror module (3) through the second metal conductive layer (M2); it laterally extends above the turn-off module (6) through the third metal conductive layer (M3), and longitudinally extends again above the turn-on module (5); it laterally forms an interconnection with the top metal conductive layer (TM1) longitudinally extending from the port GND (14) through the top metal conductive layer (TM1);

[0038] Above the turn-on module (5), it is longitudinally connected to the input port VDD2 (12) through the top metal conductive layer (TM1); it is laterally connected to the output port Vout (13) through the top metal conductive layer (TM1); it forms an interconnection with the top metal conductive layer of the output port Vout (13) and longitudinally extends above the turn-off module (6); through multiple third metal conductive layers (M3), it first longitudinally extends above the turn-off module (6), and then laterally extends above the bias module (4) and the logic control module (2);

[0039] Above the turn-off module (6), the port GND2 (16) is horizontally connected through the top metal conductive layer (TM1), extends vertically through the top metal conductive layer (TM1) above the turn-on module (5), and forms an interconnection with the top metal conductive layer (TM1) extended from the output port Vout (13); it extends horizontally through multiple third metal conductive layers (M3) above the bias module (4) and the logic control module (2).

[0040] Further, the current mirror module (3) is in the middle of the power supply module (1) and the logic control module (2); the bias module (4) is above the power supply module, the current mirror module, and the logic control module; the turn-on module (5) is at the lower left of the layout, and the turn-off module is at the upper left of the layout; the turn-off module (6) is above the turn-on module (5).

[0041] Further, the input port VDD1 (11), the input port VDD2 (12), the port GND (14), the port GND2 (16), the output port Vout (13), the power supply module (1), the logic control module (2), the current mirror module (3), the bias module (4), the turn-on module (5), and the turn-off module (6) are connected to the top metal conductive layer (TM1) and the fourth metal conductive layer (M4).

[0042] Beneficial effects: The present invention discloses a layout structure of a power MOSFET gate drive chip, which includes a power supply module, a current mirror module, a logic control module, a bias module, a turn-on module, and a turn-off module. The turn-on module includes a charging NMOS group, and the turn-off module includes a discharging NMOS group; each module is interconnected through the third metal conductive layer M3, the fourth metal conductive layer M4, and the top metal conductive layer TM1; the top metal conductive layer TM1 and the fourth metal conductive layer M4 interconnected with the ports VDD1 and GND in the layout surround the layout, providing good stability. The top metal TM1 interconnected with the ports Vout and GND2 in the layout structure completes the electrical connection in a short distance, reduces the parasitic inductance and parasitic resistance while realizing the function, realizes the high current-carrying capacity while reducing the area required for the layout, and meets the high power density requirements of the industry manufacturers for power electronic devices. Description of the Drawings

[0043] Figure 1 It is a schematic diagram of the connection relationship of the layout structure of the power MOSFET gate drive chip according to the embodiment of the present invention;

[0044] Figure 2 It is a simplified schematic diagram of the layout structure of the power MOSFET gate drive chip according to the embodiment of the present invention;

[0045] Figure 3 Schematic diagram of port metal interconnection for the layout structure of the power MOSFET gate driver chip according to an embodiment of the present invention;

[0046] Figure 4 Schematic diagram of metal interconnection between the ports and each module for the layout structure of the power MOSFET gate driver chip according to an embodiment of the present invention;

[0047] Figure 5 Schematic diagram of the drain-source connection of NLDMOS1 in the turn-on module for the layout structure of the power MOSFET gate driver chip according to an embodiment of the present invention;

[0048] Figure 6 Schematic diagram of the drain-source connection of NLDMOS2 in the turn-off module for the layout structure of the power MOSFET gate driver chip according to an embodiment of the present invention. Detailed implementation manners

[0049] The technical solutions of the embodiments of the present invention will be further described below in conjunction with the attached Figures 1-6 drawings,

[0050] The main purpose of the present invention is to provide a layout of a power MOSFET gate driver chip, aiming to achieve a high current-carrying capacity while reducing the layout area through the layout, promoting the miniaturization development of the driver chip, and meeting the high power density requirements of modern power electronic devices. Embodiment

[0051] The present invention discloses a layout of a power MOSFET gate driver chip, including a power supply module, a logic control module, a current mirror module, a bias module, a turn-on module, and a turn-off module, as Figures 1-2 shown in the following figure, where:

[0052] The power supply module has its input terminal connected to port VDD1 and its output connected to the logic control module, the current mirror module, the bias module, and port GND;

[0053] The logic control module has its input terminal connected to port Vin and its output connected to the turn-on module, the turn-off module, and port GND;

[0054] The current mirror module has its input terminal connected to the output of the power supply module and its output connected to the turn-on module, the turn-off module, and port GND;

[0055] The bias module has its input connected to the output of the power supply module and port PARA, and its output connected to the turn-on module, the turn-off module, and port GND;

[0056] The enabling module includes a charging NMOS group NLDMOS1, with its input connected to the outputs of the logic control module, the bias module, and port VDD2, and its output connected to port Vout and port GND;

[0057] The disabling module includes a discharging NMOS group NLDMOS2, with its input connected to the outputs of the logic control module and the bias module, and its output connected to port GND2.

[0058] The layout of the power MOSFET gate driver chip includes input port VDD, input port Vin, input port PARA, output port Vout, output port GND, and output port GND2, where there are crisscrossing metal conductive layer connection relationships, as Figure 3 shown, specifically manifested as:

[0059] The port Vin inputs a PWM switching digital signal and is connected to the logic control module through the fourth metal conductive layer M4;

[0060] The port VDD1 inputs the supply voltage VDD1, is connected to the top metal conductive layer TM1 and surrounds the layout inside. Among them, above the enabling module and the disabling module, the top metal conductive layer TM1 is avoided through the fourth metal conductive layer; it is connected to the power module through the top metal conductive layer TM1. Specifically, the port VDD1 not only surrounds the layout inside through the top metal conductive layer (TM1), but also extends longitudinally through the top metal conductive layer above the power module;

[0061] The port VDD2 inputs the supply voltage VDD2 and is connected to the enabling module through the top metal conductive layer TM1. Specifically, the port VDD2 extends longitudinally through the top metal conductive layer (TM1) above the enabling module, and the fourth metal conductive layer (M4) below it forms an interconnection with the top metal conductive layer (TM1) connected to port VDD1 through a via (M4 - TM1);

[0062] The port PARA inputs a bias voltage and is connected to the bias module through the fourth metal conductive layer M4;

[0063] The port Vout outputs current to the gate of an external power MOSFET and is connected to the enabling module and the disabling module through the top metal conductive layer TM1. Specifically, the port Vout extends horizontally through the top metal conductive layer TM1 above the charging NMOS group NLDMOS1 in the enabling module, and then extends longitudinally above the disabling module;

[0064] The port GND is connected to the digital ground, connected to the top metal conductive layer TM1 and surrounds the layout on the outside; the port GND is connected to the power supply module, the logic control module, the current mirror module, the bias module, and the turn-on module through the top metal conductive layer TM1. Specifically, the port GND not only surrounds the layout on the outside through the top metal conductive layer TM1, but also longitudinally extends through the top metal conductive layer above the current mirror module and the power supply module.

[0065] The port GND2 is connected to the analog ground, connected to the top metal conductive layer TM1, and connected to the turn-off module through the top metal conductive layer. Specifically, the port GND2 laterally extends through the top metal conductive layer TM1 above the discharge NMOS group NLDMOS2 in the turn-off module.

[0066] In the layout of the power MOSFET gate driver chip, there are criss-cross metal conductive layer connection relationships between the modules, such as Figure 4 shown, specifically manifested as:

[0067] Above the power supply module, it is connected to the port VDD1 through the top metal conductive layer TM1; connected to the logic control module, the current mirror module, and the bias module through the fourth metal conductive layer M4; connected to the port GND through the top metal conductive layer TM1. Specifically, above the power supply module, it laterally extends through the fourth metal conductive layer M4 past the current mirror module and the logic control module, and longitudinally extends above the bias module; longitudinally connected to the port VDD1 through the top metal conductive layer TM1;

[0068] Above the logic control module, it is connected to the power supply module through the fourth metal conductive layer M4, connected to the port Vin through the fourth metal conductive layer, connected to the turn-on module and the turn-off module respectively through the third metal conductive layer M3, and connected to the port GND through the top metal conductive layer TM1. Specifically, above the logic control module, it longitudinally extends through the third metal conductive layer M3 close to the bias module, then laterally extends above the turn-off module, and longitudinally extends to the turn-on module again;

[0069] Above the current mirror module, it is connected to the power supply module through the fourth metal conductive layer M4, connected to the bias module through the second metal conductive layer, and connected to the port GND through the top metal conductive layer. Specifically, above the current mirror module, it laterally extends through the fourth metal conductive layer M4 above the power supply module; longitudinally extends through the second metal conductive layer M2 above the bias module; laterally forms an interconnection with the top metal conductive layer longitudinally extending from the port GND through the top metal conductive layer TM1;

[0070] Above the bias module, it is connected to the power supply module through the fourth metal conductive layer M4, to the current mirror module through the second metal conductive layer M2, and to the port GND through the top metal conductive layer. Specifically, above the bias module, it extends longitudinally to above the power supply module through the fourth metal conductive layer M4; extends longitudinally to the current mirror module through the second metal conductive layer M2; extends laterally to above the turn-off module through the third metal conductive layer M3 and then extends longitudinally to above the turn-on module; forms an interconnection with the top metal conductive layer of the port GND extending longitudinally through the top metal conductive layer TM1;

[0071] Above the turn-on module, it is connected to the port VDD2 through the top metal conductive layer TM1, to the logic control module through the third metal conductive layer M3, to the bias module through the third metal conductive layer, to the port GND through the top metal conductive layer TM1, and to the port Vout through the top metal conductive layer TM1. Specifically, above the turn-on module, it is connected longitudinally to the port VDD2 through the top metal conductive layer TM1; is connected laterally to the port Vout through the top metal conductive layer; extends longitudinally to above the turn-off module through the top metal conductive layer interconnected with the port Vout; extends longitudinally to above the turn-off module through multiple third metal conductive layers M3 first and then extends laterally to above the bias module and the logic control module;

[0072] Above the turn-off module, it extends to above the turn-on module through the top metal conductive layer TM1 and connects to the port Vout using the top metal conductive layer; is connected to the port GND2 through the top metal conductive layer TM1, to the logic control module through the third metal conductive layer M3, and to the bias module through the third metal conductive layer M3. Specifically, above the turn-off module, it is connected laterally to the port GND2 through the top metal conductive layer TM1, extends longitudinally to above the turn-on module through the top metal conductive layer TM1, and forms an interconnection with the top metal conductive layer extended from the port Vout; extends laterally to above the bias module and the logic control module through multiple third metal conductive layers M3.

[0073] In the layout of the power MOSFET gate drive chip, the charging NMOS group NLDMOS1 included in the turn-on module is composed of multiple charging NMOSs, and its drain extends through the fourth metal conductive layer M4 to be below the top metal conductive layer TM1 connected to the port VDD2 above, and the metal interconnection between the drain of the charging NMOS and the port VDD2 is completed through the via M4-TM1, as Figure 5 shown.

[0074] In the layout of the power MOSFET gate drive chip, the discharging NMOS group NLDMOS2 included in the turn-off module is composed of multiple discharging NMOSs. Its drain extends to the lower part of the top metal conductive layer TM1 of the upper connection port Vout through the fourth metal conductive layer M4, and the metal interconnection between the drain of the discharging NMOS and the port Vout is completed through the via M4-TM1, as Figure 6 shown.

[0075] The current mirror module 3 is in the middle of the power supply module 1 and the logic control module 2; the bias module 4 is above the power supply module, the current mirror module, and the logic control module; the turn-on module 5 is in the lower left of the layout, and the turn-off module is in the upper left of the layout; the turn-off module 6 is above the turn-on module 5.

[0076] The connection of the port VDD1 (11), port VDD2 (12), port GND (14), port GND2 (16), port Vout (13), power supply module (1), logic control module (2), current mirror module (3), bias module (4), turn-on module (5) and turn-off module (6) to the top metal conductive layer (TM1) and the fourth metal conductive layer (M4).

[0077] The described embodiments are only a part of the embodiments of the present invention, rather than representing all embodiments; all other embodiments obtained by those skilled in the art without creative efforts are covered by the protection scope of the embodiments of the present invention; but it is not limited thereto. Any modification or equivalent replacement of the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention shall be covered by the protection scope of the present invention.

[0078] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and is a simplified description, rather than indicating or implying that the device or component must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention.

[0079] In the description of the present invention, it should be noted that unless otherwise clearly specified and defined, the terms "installed", "provided with", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

Claims

1. A layout structure of a power MOSFET gate driver chip, the driver chip is used to drive an external power MOSFET, characterized in that: It includes a power module (1), a logic control module (2), a current mirror module (3), a bias module (4), an enable module (5), a shutdown module (6), an input port Vin (10), an input port VDD1 (11), an input port VDD2 (12), an output port Vout (13), a port GND (14), a port PARA (15) and a port GND2 (16). The input end of the power supply module (1) is connected to the input port VDD1 (11), and the output end thereof is connected to the input end of the logic control module (2), the current mirror module (3), the bias module (4) and the port GND (14); The input end of the logic control module (2) is connected to the input port Vin (10), and the output end thereof is connected to the input ends of the opening module (5), the closing module (6) and the port GND (14); The input end of the current mirror module (3) is connected to the output end of the power module (1), and the output end thereof is connected to the input ends of the opening module (5), the closing module (6) and the port GND (14); The input end of the bias module (4) is connected to the output end of the power module (1) and the port PARA (15), and the output end thereof is connected to the input ends of the opening module (5), the closing module (6) and the port GND (14); The opening module (5) comprises a charging NMOS group (NLDMOS1), the input end of the opening module (5) is connected to the output end of the logic control module (2), the output end of the bias module (4) and the input port VDD2 (12), and the output end of the opening module (5) is connected to the output port Vout (13) and the port GND (14); The shutdown module (6) comprises a discharge NMOS group (NLDMOS2), an input end of which is connected to the output end of the logic control module (2), the output end of the bias module (4) and the port GND2 (16).

2. The layout structure of a power MOSFET gate driver chip according to claim 1, characterized in that: It also includes a fourth metal conductive layer (M4) and a top metal conductive layer (TM1); The input port Vin (10) is used to connect a switch PWM signal, and the input port Vin (10) is connected to the logic control module (2) via a fourth metal conductive layer (M4); The input port VDD1 (11) is used to connect the power supply voltage VDD1, the input port VDD1 (11) is connected to the top metal conductive layer (TM1) and is arranged around the inside, and is used to avoid the top metal conductive layer (TM1) through the fourth metal conductive layer (M4) above the opening module (5) and the closing module (6); the input port VDD1 (11) is connected to the power module (1) through the top metal conductive layer (TM1); The input port VDD2 (12) is used to connect the power supply voltage VDD2, and the input port VDD2 (12) is connected to the activation module (5) through the top metal conductive layer (TM1); The port PARA (15) is used to connect an external input bias voltage, and the port PARA (15) is connected to the bias module (4) through a fourth metal conductive layer (M4); The output port Vout (13) is used to connect to the gate of an external power MOSFET, and the output port Vout (13) is connected to the turn-on module (5) and the turn-off module (6) through the top metal conductive layer (TM1); The port GND (14) is used to connect to the digital ground, and the port GND (14) is connected to the top metal conductive layer (TM1) and is arranged around the outside; the port GND (14) is connected to the power module (1), the logic control module (2), the current mirror module (3), the bias module (4) and the enable module (5) through the top metal conductive layer (TM1); The port GND2 (16) is used to connect to the analog ground. The port GND2 (16) is connected to the top metal conductive layer (TM1) and is connected to the shutdown module (6) through the top metal conductive layer.

3. The layout structure of a power MOSFET gate driver chip according to claim 2, characterized in that: It also includes a second metal conductive layer (M2) and a third metal conductive layer (M3), The power module (1) is connected to an input port VDD1 (11) via a top metal conductive layer (TM1) above the power module (1); the power module (1) is connected to a logic control module (2), a current mirror module (3), and a bias module (4) via a fourth metal conductive layer (M4); the power module (1) is connected to a port GND (14) via the top metal conductive layer (TM1); The logic control module (2) is connected to the power module (1) via a fourth metal conductive layer (M4) above the logic control module (2), connected to the input port Vin (10) via the fourth metal conductive layer, connected to the opening module (5) and the closing module (6) via the third metal conductive layer (M3), and connected to the port GND (14) via the top metal conductive layer (TM1); The current mirror module (3) is connected to the power module (1) via the fourth metal conductive layer (M4) above the current mirror module (3), connected to the bias module (4) via the second metal conductive layer (M2), and connected to the port GND (14) via the top metal conductive layer (TM1); The bias module (4), the bias module (4) is connected to the power module (1) via a fourth metal conductive layer (M4), connected to the current mirror module (3) via a second metal conductive layer (M2), and connected to the port GND (14) via a top metal conductive layer (TM1); The opening module (5) is connected to the input port VDD2 (12) through the top metal conductive layer (TM1) above the opening module (5), connected to the logic control module (2) through the third metal conductive layer (M3), connected to the bias module (4) through the third metal conductive layer (M3), connected to the port GND (14) through the top metal conductive layer (TM1), and connected to the output port Vout (13) through the top metal conductive layer (TM1); The shutdown module (6) extends from the top of the shutdown module (6) to the top of the opening module (5) through the top metal conductive layer (TM1), and is connected to the output port Vout (13) through the top metal conductive layer (TM1); is connected to the port GND2 (16) through the top metal conductive layer (TM1), is connected to the logic control module (2) through the third metal conductive layer (M3), and is connected to the bias module (4) through the third metal conductive layer (M3).

4. The layout structure of a power MOSFET gate driver chip according to claim 3, characterized in that: It also includes a hole (M4-TM1), and the charging NMOS group (NLDMOS1) in the opening module (5) includes a plurality of charging NMOS, whose drain extends through the fourth metal conductive layer (M4) to below the top metal conductive layer (TM1) connected to the input port VDD2 (12) above, and completes the metal interconnection between the drain of the charging NMOS group and the input port VDD2 (12) through the hole (M4-TM1).

5. The layout structure of a power MOSFET gate driver chip according to claim 3, characterized in that: The discharge NMOS group (NLDMOS2) in the shutdown module (6) comprises a plurality of discharge NMOSs, the drain of which extends through a fourth metal conductive layer (M4) to below a top metal conductive layer (TM1) connected to an output port Vout (13) above, and completes metal interconnection between the drain of the discharge NMOS group and the output port Vout (13) through a hole (M4-TM1).

6. The layout structure of a power MOSFET gate driver chip according to claim 2 or 3, characterized in that: The input port VDD1 (11) is not only arranged around the inner side by the top metal conductive layer (TM1), but also extends longitudinally to above the power module (1) through the top metal conductive layer (TM1); The input port VDD2 (12) extends longitudinally through the top metal conductive layer (TM1) to above the activation module (5), and the fourth metal conductive layer (M4) below it is interconnected with the top metal conductive layer (TM1) of the connection port VDD1 through a hole (M4-TM1); The output port Vout (13) extends laterally through the top metal conductive layer (TM1) to above the charging NMOS group (NLDMOS1) in the turn-on module (5), and then extends longitudinally to above the turn-off module (6); The port GND (14) is not only arranged around the outside through the top metal conductive layer (TM1), but also extends longitudinally through the top metal conductive layer (TM1) to above the current mirror module (3) and the power module (1); The port GND2 (16) extends laterally through the top metal conductive layer (TM1) to above the discharge NMOS group (NLDMOS2) in the shutdown module (6); The power module (1) is horizontally extended through the fourth metal conductive layer (M4) through the current mirror module (3) and the logic control module (2), and vertically extends to the top of the bias module (4); and is vertically connected to the input port VDD1 (11) through the top metal conductive layer (TM1); The logic control module (2) is vertically extended through the third metal conductive layer (M3) to approach the bias module (4), then horizontally extended to the top of the shutdown module (6), and then vertically extended to the opening module (5); The current mirror module (3) is horizontally extended to the power module (1) through the fourth metal conductive layer (M4); it is vertically extended to the bias module (4) through the second metal conductive layer (M2); and it is interconnected with the top metal conductive layer extending vertically from the port GND (14) through the top metal conductive layer (TM1); The bias module (4) is longitudinally extended through the fourth metal conductive layer (M4) to the power module (1); the second metal conductive layer (M2) is longitudinally extended to the current mirror module (3); the third metal conductive layer (M3) is transversely extended to the shutdown module (6), and the opening module (5) is further longitudinally extended; and the top metal conductive layer (TM1) is transversely connected to the top metal conductive layer (TM1) extending longitudinally from the port GND (14) through the top metal conductive layer (TM1); The top metal conductive layer (TM1) is connected vertically to the input port VDD2 (12) above the enable module (5); the top metal conductive layer (TM1) is connected horizontally to the output port Vout (13); the top metal conductive layer (TM1) is interconnected with the output port Vout (13) and vertically extends to the top of the shutdown module (6); a plurality of third metal conductive layers (M3) are firstly extended vertically to the top of the shutdown module (6), and then horizontally extends to the top of the bias module (4) and the logic control module (2); The shutdown module (6) is laterally connected to the port GND2 (16) through the top metal conductive layer (TM1), and is vertically extended to the top of the enable module (5) through the top metal conductive layer (TM1), and is interconnected with the top metal conductive layer (TM1) extending from the output port Vout (13); and is laterally extended to the top of the bias module (4) and the logic control module (2) through multiple third metal conductive layers (M3).

7. The layout structure of a power MOSFET gate driver chip according to claim 3, characterized in that: The current mirror module (3) is located between the power module (1) and the logic control module (2); the bias module (4) is located above the power module, the current mirror module and the logic control module; the on module (5) is located at the lower left of the layout, and the off module is located at the upper left of the layout; the off module (6) is located above the on module (5).

8. A layout structure of a power MOSFET gate driver chip according to any one of claims 1 to 3, characterized in that: The input port VDD1 (11), the input port VDD2 (12), the port GND (14), the port GND2 (16), the output port Vout (13), the power module (1), the logic control module (2), the current mirror module (3), the bias module (4), the turn-on module (5) and the turn-off module (6) are connected to the top metal conductive layer (TM1) and the fourth metal conductive layer (M4).

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