P-type BC battery and preparation method thereof

Abstract

The invention belongs to the technical field of photovoltaic cells, and provides a P-type BC cell and a preparation method thereof. The method comprises the following steps: depositing a first tunneling oxide layer, an intrinsic amorphous silicon layer, a second tunneling oxide layer, a phosphorus-doped amorphous silicon layer and a surface silicon oxide layer on the back surface of a P-type monocrystalline silicon wafer; carrying out local film opening treatment on silicon oxide on the outermost layer of the laminated silicon wafer, carrying out wet etching treatment on the silicon wafer after film opening by adopting alkali and an additive, printing patterned boron slurry on the surface of the etched silicon wafer, and then carrying out high-temperature oxygen annealing to form a P-I-N structure silicon wafer; removing the oxide layer on the front surface of the P-I-N structure silicon wafer, and then performing low-temperature alkali texturing; and sequentially depositing an aluminum oxide layer and a silicon nitride film on the front surface and the back surface of the textured silicon wafer. The BC battery back surface structure is prepared by adopting a tunneling + poly laminated structure and a mode of printing boron slurry after laser film opening, so that the process flow is simplified, the manufacturing cost is reduced, and the large-scale mass production of the battery is promoted.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic cells, and in particular to a P-type BC cell and a preparation method thereof. Background Art

[0002] The innovative design of the BC cell lies in its unobstructed front structure, which eliminates the light energy loss caused by traditional grid line obstruction, ensures the maximum utilization of incident photons, and makes the BC cell more efficient. At the same time, the unique design of the BC cell enables the electrodes of the emitter and base regions to be located on the back, thus achieving the effect of no grid line obstruction on the front. However, the production process of BC cells is relatively complicated, requiring multiple doping laser or mask processes, and the process is cumbersome and the manufacturing cost is high, so it has not yet been mass-produced.

[0003] Therefore, it is of great significance to study and obtain a preparation method of P-type BC battery with simple process flow and reduced cost. Summary of the invention

[0004] The purpose of the present invention is to provide a P-type BC battery and a preparation method thereof in order to overcome the shortcomings of the prior art, utilize the structure of stacked tunneling oxidation plus poly doping layer and laser film opening to form graphics, utilize printing boron paste to perform regional doping, and simplify the process flow.

[0005] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions:

[0006] The present invention provides a method for preparing a P-type BC battery, comprising the following steps:

[0007] 1) depositing a stack of layers on the back side of a P-type single crystal silicon wafer to obtain a stacked silicon wafer, wherein the stack of layers sequentially comprises a first tunneling oxide layer, an intrinsic amorphous silicon layer, a second tunneling oxide layer, a phosphorus-doped amorphous silicon layer, and a surface silicon oxide layer;

[0008] 2) Partially open the silicon oxide on the outermost layer of the stacked silicon wafer to form a patterned P region structure;

[0009] 3) The opened silicon wafer is wet-etched with an alkali solution to obtain an etched silicon wafer;

[0010] 4) Printing a patterned boron paste on the surface of the etched silicon wafer, wherein the width of the boron paste is smaller than the width of the film opening, and performing high-temperature oxygen annealing on the printed silicon wafer to form a PIN structure silicon wafer;

[0011] After high-temperature oxygen annealing, boron paste is doped into the intrinsic amorphous silicon to form a P+poly structure; the intrinsic amorphous silicon in the area without boron paste is crystallized at high temperature to form intrinsic polycrystalline silicon; the phosphorus in the phosphorus-doped amorphous silicon layer is activated to form a phosphorus-doped poly layer, and the phosphorus atoms diffuse into the intrinsic amorphous silicon to form an N+poly structure together;

[0012] 5) After removing the oxide layer on the front side of the PIN structure silicon wafer, low temperature alkali texturing is performed;

[0013] 6) Aluminum oxide layer and silicon nitride film are sequentially deposited on the front and back of the silicon wafer after texturing; the coated silicon wafer is screen printed and sintered to obtain P-region metal electrodes and N-region metal electrodes.

[0014] Preferably, the thickness of the first tunneling oxide layer is 1-2 nm, the thickness of the intrinsic amorphous silicon layer is 50-200 nm, the thickness of the second tunneling oxide layer is 1-2 nm, the thickness of the phosphorus-doped amorphous silicon layer is 30-200 nm, and the thickness of the surface silicon oxide layer is 5-15 nm.

[0015] Preferably, the film opening width of the film opening treatment is 50-400 μm, the laser power is 2-20 W, the frequency is 2000-6000 kHz, and the speed is 8000-50000 mm / min.

[0016] Preferably, in the alkaline solution of step 3), the mass fraction of the alkali is 1-5%, the mass fraction of the additive is 0.2-2%, the temperature of the wet etching treatment is 50-65° C., and the time of the wet etching treatment is 80-220 s.

[0017] Preferably, the printing method of the boron paste in step 4) includes screen printing, mask diffusion or ion implantation; the width of the boron paste printing is 50 to 200 μm.

[0018] Preferably, the temperature of the low-temperature alkali texturing in step 5) is 55-75°C.

[0019] Preferably, in step 6), the single layer thickness of the aluminum oxide layer is 3 to 10 nm; the single layer thickness of the silicon nitride film is 70 to 85 nm.

[0020] The present invention also provides a P-type BC battery prepared by the preparation method of the P-type BC battery.

[0021] The beneficial effects of the present invention include:

[0022] The present invention adopts a laminated structure, uses the second tunnel oxide layer as a barrier layer after laser film opening, forms phosphorus-doped amorphous silicon regions and intrinsic amorphous silicon regions respectively, and then forms a cross-shaped back emitter structure by screen printing boron paste and high-temperature oxygen annealing. The intrinsic amorphous silicon layer is crystallized and the printed boron source forms a P+poly layer. The phosphorus-doped amorphous silicon layer is annealed to form a phosphorus-doped poly layer, and the intrinsic amorphous silicon crystallization separating the N+poly and P+poly regions is formed into intrinsic poly. The present invention adopts a tunneling + poly laminated structure and a method of printing boron paste after laser film opening to prepare the back structure of the BC battery, which simplifies the process flow, reduces manufacturing costs, and promotes large-scale mass production of batteries. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the structure of the P-type BC battery of the present invention, wherein 1 is front silicon nitride, 2 is front aluminum oxide, 3 is silicon substrate, 4 is the first tunneling oxide layer, 5 is intrinsic amorphous silicon, 6 is the first N+poly layer, 7 is the second tunneling oxide layer, 8 is the second N+poly layer, 9 is P+poly, 10 is back aluminum oxide, 11 is back silicon nitride, 12 is P-region metal electrode, and 13 is N-region metal electrode. DETAILED DESCRIPTION

[0024] The present invention provides a method for preparing a P-type BC battery, comprising the following steps:

[0025] 1) depositing a stack of layers on the back side of a P-type single crystal silicon wafer to obtain a stacked silicon wafer, wherein the stack of layers sequentially comprises a first tunneling oxide layer, an intrinsic amorphous silicon layer, a second tunneling oxide layer, a phosphorus-doped amorphous silicon layer, and a surface silicon oxide layer;

[0026] 2) Partially open the silicon oxide on the outermost layer of the stacked silicon wafer to form a patterned P region structure;

[0027] 3) The opened silicon wafer is wet-etched with an alkali solution to obtain an etched silicon wafer;

[0028] 4) Printing a patterned boron paste on the surface of the etched silicon wafer, wherein the width of the boron paste is smaller than the width of the film opening, and performing high-temperature oxygen annealing on the printed silicon wafer to form a PIN structure silicon wafer;

[0029] After high-temperature oxygen annealing, boron paste is doped into the intrinsic amorphous silicon to form a P+poly structure; the intrinsic amorphous silicon in the area without boron paste is crystallized at high temperature to form intrinsic polycrystalline silicon; the phosphorus in the phosphorus-doped amorphous silicon layer is activated to form a phosphorus-doped poly layer, and the phosphorus atoms diffuse into the intrinsic amorphous silicon to form an N+poly structure together;

[0030] 5) After removing the oxide layer on the front side of the PIN structure silicon wafer, low temperature alkali texturing is performed;

[0031] 6) Aluminum oxide layer and silicon nitride film are sequentially deposited on the front and back of the silicon wafer after texturing; the coated silicon wafer is screen printed and sintered to obtain P-region metal electrodes and N-region metal electrodes.

[0032] In the present invention, the method of depositing the stack is preferably low pressure chemical vapor deposition (LPCVD), the temperature of the low pressure chemical vapor deposition is preferably 600-650°C, further preferably 610-640°C, more preferably 620-630°C, the time is preferably 7000-9000s, further preferably 7500-8500s, more preferably 8000s.

[0033] In the present invention, the thickness of the first tunneling oxide layer is preferably 1-2 nm, more preferably 1.2-1.8 nm, and more preferably 1.4-1.5 nm. The thickness of the intrinsic amorphous silicon layer is preferably 50-200 nm, more preferably 80-160 nm, and more preferably 100-150 nm. The thickness of the second tunneling oxide layer is preferably 1-2 nm, more preferably 1.2-1.8 nm, and more preferably 1.4-1.5 nm. The thickness of the phosphorus-doped amorphous silicon layer is preferably 30-200 nm, more preferably 50-160 nm, and more preferably 100-120 nm. The thickness of the surface silicon oxide layer is preferably 5-15 nm, more preferably 8-12 nm, and more preferably 10 nm.

[0034] In the present invention, before depositing the stacked layers on the P-type single crystal silicon wafer in step 1), the front and back sides of the silicon wafer are preferably double-sided polished by wet alkaline etching.

[0035] In the present invention, the film opening width of the film opening treatment is preferably 50 to 400 μm, more preferably 150 to 350 μm, and more preferably 200 to 300 μm. The laser power is preferably 2 to 20 W, more preferably 5 to 15 W, and more preferably 8 to 12 W. The frequency is preferably 2000 to 6000 kHz, more preferably 3000 to 5000 kHz, and more preferably 4000 kHz. The speed is preferably 8000 to 50000 mm / min, more preferably 10000 to 40000 mm / min, and more preferably 20000 to 30000 mm / min.

[0036] In the present invention, in the alkaline solution of step 3), the mass fraction of the alkali is preferably 1-5%, more preferably 2-4%, more preferably 3%, the mass fraction of the additive is preferably 0.2-2%, more preferably 0.5-1.5%, more preferably 0.8-1.2%; the temperature of the wet etching treatment is preferably 50-65°C, more preferably 55-60°C, and the time of the wet etching treatment is preferably 80-220s, more preferably 100-200s, more preferably 130-160s.

[0037] In the present invention, the additive is preferably a silicon wafer cleaning agent.

[0038] In the present invention, in the wet etching treatment of step 3), the outermost layer at the film opening of the silicon wafer is the second tunneling oxide layer superimposed on the phosphorus-doped amorphous silicon layer. The alkaline solution will corrode the amorphous silicon layer, but will not react with the second tunneling oxide layer. Therefore, the first tunneling oxide layer and the intrinsic amorphous silicon layer can be completely retained. The area that has not been film-opened is protected by the silicon oxide layer and will not participate in the reaction, thereby ensuring the integrity of the structure of the protected area.

[0039] In the present invention, the printing method of the boron paste in step 4) preferably includes screen printing, mask diffusion or ion implantation; the width of the boron paste printing is preferably 50 to 200 μm, more preferably 80 to 150 μm, and more preferably 100 to 130 μm.

[0040] In step 4) of the present invention, the width of the boron paste is smaller than the film opening width, so the intrinsic amorphous silicon structure will be retained on both sides of the printed boron paste in the film opening area, thereby preventing the back structure PN area from short-circuiting; the P+poly structure is a boron-doped polycrystalline poly layer.

[0041] In step 4) of the present invention, the temperature of high-temperature oxygen annealing is preferably 850-900°C, more preferably 860-890°C, more preferably 870-880°C, and the time is preferably 5000-6000s, more preferably 5200-5800s, more preferably 5500-5600s; phosphorus doping annealing and boron doping annealing are carried out in the same furnace tube; the etched silicon wafer is patterned by printing boron paste.

[0042] In the present invention, the reagent used in step 5) to remove the oxide layer on the front side of the PIN structure silicon wafer is preferably an HF solution, and the mass concentration of the HF solution is preferably 20-40%, more preferably 25-35%, and more preferably 30%.

[0043] In the present invention, the temperature of the low-temperature alkali texturing in step 5) is preferably 55-75°C, more preferably 60-70°C, and more preferably 65°C.

[0044] In the present invention, in the low-temperature texturing of step 5), the back side of the silicon wafer can withstand the low-temperature alkali texturing because it contains an oxide layer formed in the high-temperature process. After the low-temperature texturing is completed, hydrofluoric acid is used to clean off the silicon oxide and residual boron slurry on the surface; the low-temperature alkali texturing adopts an alkali solution, and the alkali solution is preferably a sodium hydroxide solution or a potassium hydroxide solution. The mass concentration of the alkali solution is preferably 1-4%, and more preferably 2-3%.

[0045] In the present invention, the single layer thickness of the aluminum oxide layer in step 6) is preferably 3-10 nm, more preferably 5-8 nm, and more preferably 6-7 nm; the single layer thickness of the silicon nitride film is preferably 70-85 nm, and more preferably 75-80 nm.

[0046] In the present invention, step 6) depositing an aluminum oxide layer is preferably atomic layer deposition (ALD deposition), the temperature of the atomic layer deposition is preferably 200-300°C, further preferably 220-280°C, more preferably 250-260°C, and the time is preferably 2000-2500s, further preferably 2100-2400s, more preferably 2200-2300s; depositing a silicon nitride film is preferably plasma enhanced chemical vapor deposition (PECVD deposition); the temperature of plasma enhanced chemical vapor deposition is preferably 400-600°C, further preferably 450-550°C, more preferably 500°C, and the time is preferably 2000-4000s, further preferably 2500-3500s, more preferably 3000s.

[0047] In the present invention, the screen printing spacing is preferably 1.6 to 2.2 mm, more preferably 1.7 to 2.1 mm, and more preferably 1.8 to 2.0 mm. The screen printing speed is preferably 200 to 500 mm / s, more preferably 300 to 400 mm / s, and more preferably 350 mm / s. The screen printing pressure is preferably 45 to 65 N, more preferably 50 to 60 N, and more preferably 55 N. The peak sintering temperature is preferably 720 to 750°C, and more preferably 730 to 740°C.

[0048] The present invention also provides a P-type BC battery prepared by the preparation method of the P-type BC battery.

[0049] The technical solutions provided by the present invention are described in detail below in conjunction with the embodiments, but they should not be construed as limiting the protection scope of the present invention.

[0050] Example 1

[0051] The front and back sides of the P-type single-crystal silicon wafer were double-sided polished using a trough alkali polishing machine; a stack of layers was deposited on the back side of the polished silicon wafer by LPCVD deposition (temperature of 630°C, time of 8000s), and the stack of layers was in the following order: a first tunneling oxide layer (thickness of 1.5nm), an intrinsic amorphous silicon layer (thickness of 150nm), a second tunneling oxide layer (thickness of 1.5nm), a phosphorus-doped amorphous silicon layer (thickness of 120nm), and a surface silicon oxide layer (thickness of 10nm), to obtain a stacked silicon wafer.

[0052] The outermost silicon oxide on the back of the stacked silicon wafer was partially opened by laser to form a patterned P region structure. The opening width was 200μm, the laser power was 10W, the frequency was 4000kHz, and the speed was 20000mm / min. The opened silicon wafer was wet-etched by an alkaline aqueous solution. In the alkaline aqueous solution, the mass fraction of sodium hydroxide was 3%, the mass fraction of the additive (silicon wafer cleaning agent PC-401) was 1%, the temperature of the wet etching was 60℃, and the time was 130s to obtain an etched silicon wafer.

[0053] A screen printer is used to print patterned boron paste on the surface of the etched silicon wafer. The width of the printed boron paste is 100μm. Therefore, the intrinsic amorphous silicon structure will be retained on both sides of the printed boron paste, thereby preventing the short circuit of the PN area of ​​the back structure. The printed silicon wafer is then subjected to high-temperature oxygen annealing (temperature is 880℃, time is 5500s). After annealing, the boron paste is doped into the intrinsic amorphous silicon to form a boron-doped polycrystalline poly layer (P+poly structure). The intrinsic amorphous silicon in the area where the boron paste is not printed will also be crystallized at high temperature to become intrinsic polycrystalline silicon. At the same time, the phosphorus in the second layer of phosphorus-doped amorphous silicon will be activated to form a phosphorus-doped poly layer, and the phosphorus atoms will continue to diffuse into the first layer of intrinsic amorphous silicon to form N+poly together, that is, high-temperature annealing forms a PIN structure silicon wafer.

[0054] Use a chain-type single-sided HF solution (mass concentration of 30%) to remove the oxide layer formed on the front side of the PIN structure silicon wafer during the high temperature process, and then use a slot-type machine for low-temperature texturing. The temperature of the low-temperature texturing is 65°C. Since the back side contains an oxide layer formed during the high-temperature process, it can withstand the low-temperature sodium hydroxide solution (mass concentration of 3%) for texturing. After the low-temperature texturing is completed, hydrofluoric acid is used to clean off the surface silicon oxide and residual boron slurry.

[0055] After the textured silicon wafer, aluminum oxide was deposited on both sides by ALD (temperature 250℃, time 2300s) to form a front aluminum oxide layer and a back aluminum oxide layer, and the thickness of the front and back aluminum oxide layers was 5nm; then silicon nitride film was deposited by PECVD (temperature 500℃, time 3000s) to form a front silicon nitride film and a back silicon nitride film, and the thickness of the front and back silicon nitride films was 80nm. The coated silicon wafer was processed by screen printing and sintering. The process parameters of screen printing were: spacing 2.0mm, speed 350mm / s, pressure 55N, and the peak temperature of sintering was 730℃ to prepare P-zone metal electrodes and N-zone metal electrodes.

[0056] Example 2

[0057] The front and back sides of the P-type single-crystal silicon wafer were double-sided polished using a trough alkali polishing machine; a stack of layers was deposited on the back side of the polished silicon wafer by LPCVD deposition (temperature of 610°C, time of 8500s), and the stack of layers was in the following order: a first tunneling oxide layer (thickness of 1.2nm), an intrinsic amorphous silicon layer (thickness of 160nm), a second tunneling oxide layer (thickness of 1.8nm), a phosphorus-doped amorphous silicon layer (thickness of 50nm), and a surface silicon oxide layer (thickness of 8nm), to obtain a stacked silicon wafer.

[0058] Laser was used to partially open the outermost silicon oxide on the back of the stacked silicon wafer to form a patterned P region structure. The opening width was 300μm, the laser power was 15W, the frequency was 5000kHz, and the speed was 40000mm / min. The silicon wafer after opening was wet-etched with an alkaline aqueous solution. In the alkaline aqueous solution, the mass fraction of sodium hydroxide was 4%, the mass fraction of the additive (silicon wafer cleaning agent PC-401) was 1.5%, the temperature of the wet etching was 55℃, and the time was 160s to obtain an etched silicon wafer.

[0059] A screen printer is used to print patterned boron paste on the surface of the etched silicon wafer. The width of the printed boron paste is 200μm. Therefore, the intrinsic amorphous silicon structure will be retained on both sides of the printed boron paste, thereby preventing the short circuit of the PN area of ​​the back structure. The printed silicon wafer is then subjected to high-temperature oxygen annealing (temperature is 850℃, time is 5800s). After annealing, the boron paste is doped into the intrinsic amorphous silicon to form a boron-doped polycrystalline poly layer (P+poly structure). The intrinsic amorphous silicon in the area where the boron paste is not printed will also be crystallized at high temperature to become intrinsic polycrystalline silicon. At the same time, the phosphorus in the second layer of phosphorus-doped amorphous silicon will be activated to form a phosphorus-doped poly layer, and the phosphorus atoms will continue to diffuse into the first layer of intrinsic amorphous silicon to form N+poly together, that is, high-temperature annealing forms a PIN structure silicon wafer.

[0060] Use a chain-type single-sided HF solution (mass concentration of 25%) to remove the oxide layer formed on the front side of the PIN structure silicon wafer during the high temperature process, and then use a slot-type machine for low-temperature texturing. The temperature of the low-temperature texturing is 60°C. Since the back side contains an oxide layer formed during the high-temperature process, it can withstand the low-temperature sodium hydroxide solution (mass concentration of 2%) for texturing. After the low-temperature texturing is completed, hydrofluoric acid is used to clean off the surface silicon oxide and residual boron slurry.

[0061] After the textured silicon wafer, aluminum oxide was deposited on both sides by ALD (temperature 220℃, time 2400s) to form a front aluminum oxide layer and a back aluminum oxide layer, the thickness of the front and back aluminum oxide layers were 5nm and 8nm respectively; then silicon nitride film was deposited by PECVD (temperature 450℃, time 3500s) to form a front silicon nitride film and a back silicon nitride film, the thickness of the front and back silicon nitride films were 75nm and 85nm respectively. The coated silicon wafer was processed by screen printing and sintering. The process parameters of screen printing were: spacing 1.7mm, speed 300mm / s, pressure 50N, and the peak temperature of sintering was 720℃ to prepare P-zone metal electrodes and N-zone metal electrodes.

[0062] Example 3

[0063] The front and back sides of the P-type single-crystal silicon wafer were double-sided polished using a trough alkali polishing machine; a stack of layers was deposited on the back side of the polished silicon wafer by LPCVD deposition (temperature of 640°C, time of 7500s), and the stack of layers was in the following order: a first tunneling oxide layer (thickness of 1.8nm), an intrinsic amorphous silicon layer (thickness of 80nm), a second tunneling oxide layer (thickness of 1.2nm), a phosphorus-doped amorphous silicon layer (thickness of 160nm), and a surface silicon oxide layer (thickness of 12nm), to obtain a stacked silicon wafer.

[0064] The outermost silicon oxide on the back of the stacked silicon wafer was partially opened by laser to form a patterned P region structure. The opening width was 150μm, the laser power was 8W, the frequency was 3000kHz, and the speed was 30000mm / min. The opened silicon wafer was wet-etched by an alkaline aqueous solution. In the alkaline aqueous solution, the mass fraction of sodium hydroxide was 2%, the mass fraction of the additive (silicon wafer cleaning agent PC-401) was 0.8%, the temperature of the wet etching was 65℃, and the time was 100s to obtain an etched silicon wafer.

[0065] A screen printer is used to print patterned boron paste on the surface of the etched silicon wafer. The width of the printed boron paste is 80μm. Therefore, the intrinsic amorphous silicon structure will be retained on both sides of the printed boron paste, thereby preventing the short circuit of the PN area of ​​the back structure. The printed silicon wafer is then subjected to high-temperature oxygen annealing (temperature is 900℃, time is 5200s). After annealing, the boron paste is doped into the intrinsic amorphous silicon to form a boron-doped polycrystalline poly layer (P+poly structure). The intrinsic amorphous silicon in the area where the boron paste is not printed will also be crystallized at high temperature to become intrinsic polycrystalline silicon. At the same time, the phosphorus in the second layer of phosphorus-doped amorphous silicon will be activated to form a phosphorus-doped poly layer, and the phosphorus atoms will continue to diffuse into the first layer of intrinsic amorphous silicon to form N+poly together, that is, high-temperature annealing forms a PIN structure silicon wafer.

[0066] Use a chain-type single-sided HF solution (mass concentration of 35%) to remove the oxide layer formed on the front side of the PIN structure silicon wafer during the high temperature process, and then use a slot-type machine for low-temperature texturing. The temperature of the low-temperature texturing is 70°C. Since the back side contains an oxide layer formed during the high-temperature process, it can withstand the low-temperature potassium hydroxide solution (mass concentration of 3%) for texturing. After the low-temperature texturing is completed, hydrofluoric acid is used to clean off the surface silicon oxide and residual boron slurry.

[0067] After the textured silicon wafer, aluminum oxide was deposited on both sides by ALD (temperature 280℃, time 2100s) to form a front aluminum oxide layer and a back aluminum oxide layer, and the thickness of the front and back aluminum oxide layers was 7nm; then silicon nitride film was deposited by PECVD (temperature 550℃, time 2500s) to form a front silicon nitride film and a back silicon nitride film, and the thickness of the front and back silicon nitride films was 75nm. The coated silicon wafer was processed by screen printing and sintering. The process parameters of screen printing were: spacing 2.2mm, speed 400mm / s, pressure 65N, and the peak temperature of sintering was 750℃ to prepare P-zone metal electrodes and N-zone metal electrodes.

[0068] The present invention provides a P-type BC battery and a preparation method thereof. The method of the present invention uses a P-type single crystal silicon wafer to undergo wet double-sided polishing, firstly uses LPCVD to prepare a first tunneling oxide layer and an intrinsic amorphous silicon layer on the back, then prepares a second tunneling oxide layer and a phosphorus-doped amorphous silicon layer and superimposes an oxide layer, then uses a laser to groove according to a fixed pattern to remove the P-type region oxide layer, then wet alkali etch away the phosphorus-doped amorphous silicon in the laser grooved region, and the reaction stops when the alkali etched to the second tunneling oxide layer, and then screen printing is used to pattern boron paste, the screen pattern is consistent with the laser pattern, the screen grid line width is smaller than the laser groove width, and then after high-temperature oxidation annealing, the intrinsic amorphous silicon layer is crystallized and the printed boron source forms a P+poly layer, and the phosphorus-doped amorphous silicon layer is annealed to form an N+poly layer (phosphorus-doped poly layer). The present invention uses a stacked tunneling layer plus poly doping structure and a method of laser film printing and patterning the boron source, which simplifies the process flow and reduces costs.

[0069] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for preparing a P-type BC battery, characterized in that: The following steps are included: 1) depositing a stack of layers on the back side of a P-type single crystal silicon wafer to obtain a stacked silicon wafer, wherein the stack of layers sequentially comprises a first tunneling oxide layer, an intrinsic amorphous silicon layer, a second tunneling oxide layer, a phosphorus-doped amorphous silicon layer, and a surface silicon oxide layer; 2) Partially open the silicon oxide on the outermost layer of the stacked silicon wafer to form a patterned P region structure; 3) The opened silicon wafer is wet-etched with an alkali solution to obtain an etched silicon wafer; 4) Printing a patterned boron paste on the surface of the etched silicon wafer, wherein the width of the boron paste is smaller than the width of the film opening, and performing high-temperature oxygen annealing on the printed silicon wafer to form a PIN structure silicon wafer; After high-temperature oxygen annealing, boron paste is doped into the intrinsic amorphous silicon to form a P+poly structure; the intrinsic amorphous silicon in the area without boron paste is crystallized at high temperature to form intrinsic polycrystalline silicon; the phosphorus in the phosphorus-doped amorphous silicon layer is activated to form a phosphorus-doped poly layer, and the phosphorus atoms diffuse into the intrinsic amorphous silicon to form an N+poly structure together; 5) After removing the oxide layer on the front side of the PIN structure silicon wafer, low temperature alkali texturing is performed; 6) Aluminum oxide layer and silicon nitride film are sequentially deposited on the front and back of the silicon wafer after texturing; the coated silicon wafer is screen printed and sintered to obtain P-region metal electrodes and N-region metal electrodes.

2. The method for preparing a P-type BC battery according to claim 1, characterized in that: The thickness of the first tunneling oxide layer is 1-2 nm, the thickness of the intrinsic amorphous silicon layer is 50-200 nm, the thickness of the second tunneling oxide layer is 1-2 nm, the thickness of the phosphorus-doped amorphous silicon layer is 30-200 nm, and the thickness of the surface silicon oxide layer is 5-15 nm.

3. The method for preparing a P-type BC battery according to claim 1 or 2, characterized in that: The film opening width of the film opening treatment is 50-400 μm, the laser power is 2-20 W, the frequency is 2000-6000 kHz, and the speed is 8000-50000 mm / min.

4. The method for preparing a P-type BC battery according to claim 3, characterized in that: In step 3), the mass fraction of the alkali in the alkali solution is 1-5%, the mass fraction of the additive is 0.2-2%, the temperature of the wet etching treatment is 50-65° C., and the time of the wet etching treatment is 80-220 s.

5. The method for preparing a P-type BC battery according to claim 3, characterized in that: Step 4) The printing method of the boron paste includes screen printing, mask diffusion or ion implantation; the width of the boron paste printing is 50 to 200 μm.

6. The method for preparing a P-type BC battery according to claim 4 or 5, characterized in that: Step 5) The temperature of the low-temperature alkali texturing is 55-75°C.

7. The method for preparing a P-type BC battery according to claim 6, characterized in that: Step 6) The single layer thickness of the aluminum oxide layer is 3 to 10 nm; the single layer thickness of the silicon nitride film is 70 to 85 nm.

8. A P-type BC battery prepared by the method for preparing a P-type BC battery according to any one of claims 1 to 7.

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