Method for establishing reconfigurable field effect transistor based on symmetric broken MXene and application thereof

Abstract

The invention discloses a method for establishing a reconfigurable field effect transistor based on symmetric broken MXene and application thereof, and the method comprises the steps: oxidizing an MXene film on the surface of a transistor substrate through employing a plasma etching technology, enabling the surface of the MXene film to generate anatase titanium dioxide particles, obtaining an MXene substrate with symmetric broken, and recording the MXene substrate as an OXene layer, then P3HT is coated on the OXene layer to form a P-N junction, electrons in a P-type semiconductor are promoted to be directionally transferred to an N-type semiconductor, the current switching ratio of the P-type transistor is improved, and the switching ratio of the transistor reaches the maximum and tends to be stable after oxidation treatment for 60 seconds; the transistor prepared by the invention can be applied to an inverter, a NAND gate circuit and a NOR gate circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic device manufacturing, and in particular relates to a method for establishing a reconfigurable field effect transistor substrate based on symmetry-broken MXene and its application. Background Art

[0002] Field-effect transistors (FETs) are key components in a wide range of electronic device manufacturing technologies, including digital circuits, power management systems, and communications devices. FETs are highly regarded for their ability to efficiently control current, making them an essential component in modern electronics. The ongoing demand for smaller, faster, and more energy-efficient devices has driven extensive research into advanced materials and novel transistor architectures. Two-dimensional (2D) materials, such as transition metal di-doped materials (TMDs) and MXenes, have emerged as promising candidates for next-generation field-effect transistors due to their unique electronic, optical, and mechanical properties. These materials offer advantages over conventional bulk materials, such as high carrier mobility, tunable band gaps, and low contact resistance. Recent advances in 2D materials have prompted the exploration of symmetry engineering to further improve the performance of field-effect transistors, particularly by addressing issues related to metal-induced gap states and Fermi-level pinning effects.

[0003] MXenes are a class of two-dimensional transition metal carbides and nitrides that show great potential in FET applications due to their excellent conductivity and surface chemistry. However, MXenes generally exhibit non-orientational behavior, resulting in inconsistent interactions with P-type and N-type semiconductors. This lack of orientation specificity limits their ability to precisely control charge carrier dynamics, which is critical to achieving high-performance transistor architectures.

[0004] The Chinese invention patent application with announcement number CN116322070A proposes a perovskite vertical field effect transistor and a preparation method thereof, wherein the source electrode adopts a continuous MXene film with a porous structure, and a perovskite semiconductor precursor liquid is spin-coated on the MXene film and annealed to form a perovskite semiconductor layer. However, the MXene film without further treatment is used as the source of the field effect transistor, and controllable directional migration of carriers cannot be formed. Therefore, specific carrier migration cannot be formed for different semiconductor types, and therefore key performance indicators such as the current switching ratio of the field effect transistor cannot be further improved. Summary of the invention

[0005] In order to overcome the defects of the above-mentioned prior art, the purpose of the present invention is to provide a method for establishing a reconfigurable field effect transistor based on symmetry-broken MXene and its application, by adopting a plasma etching process to oxidize the MXene film on the surface of the transistor substrate, so that anatase titanium dioxide particles are generated on the surface of the MXene film, and a MXene substrate with broken symmetry is obtained, which is recorded as an OXene layer, and then P3HT is coated on the OXene layer to form a PN junction, which promotes the directional transfer of electrons in the P-type semiconductor to the N-type semiconductor, thereby improving the current switching ratio of the P-type transistor; the transistor prepared by the present invention can be applied to inverters (Inverter), NAND gates (NAND) circuits, and NOR gates (NOR) circuits.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0007] A method for establishing a reconfigurable field effect transistor based on symmetry-broken MXene comprises the following steps:

[0008] Step 1: using a chemical vapor transport process to deposit on a single-side polished silicon substrate to obtain a Parylene C substrate with a thickness of 10 to 20 μm; then using a plasma etching process to perform surface functional modification on the Parylene C substrate to remove the surface hydrophobic groups to obtain a modified Parylene C substrate;

[0009] Step 2: Spin-coat a gelatin aqueous solution with a concentration of 3.5-5 mg / ml onto the modified Parylene C substrate obtained in step 1; then dry the Parylene C substrate coated with gelatin; then spin-coat a MXene aqueous solution with a concentration of 5-20 mg / ml onto the dried Parylene C substrate coated with gelatin, and then perform thermal curing to obtain a Parylene C substrate with a MXene film;

[0010] Step 3: Use a near-infrared laser to pattern the xylene C substrate with the MXene film in step 2 to carve out a MXene film with a logic circuit to form a transistor substrate;

[0011] Step 4: Oxygen plasma etching is performed on the transistor substrate in step 3 using a plasma etching process, so that anatase titanium dioxide particles are generated on the surface of the MXene film, and a MXene substrate with broken symmetry is obtained, which is recorded as an OXene layer;

[0012] Step 5: Spin-coating a P-type semiconductor solution onto the OXene layer obtained in step 4 to obtain a P-type semiconductor layer of the transistor; patterning the P-type semiconductor layer of the transistor using a shadow mask; and then performing an annealing treatment;

[0013] Step 6: Mix and stir PVDF-HFP, EMI-TFSA and acetone to obtain an ionic dielectric solution of a transistor; by weight ratio, the PVDF-HFP:EMI-TFSA:acetone=(1-2):(3-4):(4-7);

[0014] Step 7: Pour the ionic dielectric solution of the transistor obtained in step 6 onto a clean glass substrate, and after solidification, obtain an ionic gel with a thickness of 200 to 400 μm;

[0015] Step 8: Cut the ion gel obtained in step 7 into strips and laminate them as a dielectric layer on the P-type semiconductor layer of the transistor obtained in step 5, thereby finally obtaining a reconfigurable field effect transistor based on symmetry-broken MXene.

[0016] The conditions of the plasma etching process used in step 1 and step 4 are: oxygen plasma is introduced into the etching chamber at a pressure of 20 to 40 mmHg, the etching rate is 20 to 40 cc / min, the etching power is 160 to 200 W, and the etching frequency is 20 to 40 KHz; the etching time of step 1 is 30 to 300 s, and the etching time of step 4 is 10 to 120 s.

[0017] The spin coating speeds in step 2 and step 5 are both 1500-3000 rpm; the spin coating time in step 2 is 20-30 s, the spin coating time in step 2 is 20-30 s, the thickness of the spin-coated gelatin is 10-30 μm, the thickness of the spin-coated Mxene aqueous solution is 40-60 μm, the spin coating time in step 5 is 15-45 s, and the thickness of the spin-coated P-type semiconductor is 20-30 μm.

[0018] The temperature of the drying and heat curing operations in step 2 is 60-70° C., and the time is 10-20 minutes.

[0019] In step 2, the MXene aqueous solution is composed of Ti 3 C 2 T x The powder is mixed with deionized water.

[0020] In the step 3, the channel width / length (W / L) of the transistor substrate is in the micrometer range, and W / L is 250 / 50-500 / 50 μm; the line width of the near-infrared laser is 100-150 μm, and the laser height is 15-20 cm from the operating platform.

[0021] In step 5, the P-type semiconductor solution is poly 3-hexylthiophene (P3HT), the shadow mask is a polyimide film, the annealing temperature is 120-130° C., and the time is 20-30 minutes.

[0022] In step 6, PVDF-HFP is polyvinylidene fluoride-co-hexafluoropropylene, and its molecular weight is 400,000; EMI-TFSA is 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide salt, and its purity is greater than 98%.

[0023] In step 6, the stirring temperature is 60-80° C. and the time is 1-2 hours; in step 7, the solidification temperature is 60-80° C. and the time is 6-12 hours.

[0024] Furthermore, the present invention also provides a reconfigurable field effect transistor based on symmetry-broken MXene prepared by the method of establishing a reconfigurable field effect transistor based on symmetry-broken MXene as mentioned above, and the application of the transistor in an inverter, a NAND gate (NAND) circuit, and a NOR gate (NOR) circuit.

[0025] Compared with the prior art, the advantages of the present invention are:

[0026] 1. Compared with the common silicon-based substrate, the xylene C substrate used in the present invention has the characteristics of flexibility, bendability, environmental friendliness, etc., and is low-cost, non-toxic, and biodegradable.

[0027] 2. The present invention obtains a xylene C substrate through a chemical vapor transport process. Compared with directly spin coating a xylene C solution in a fume hood and curing it at high temperature to obtain a xylene C substrate, the chemical vapor transport process can be carried out at room temperature, and the obtained xylene C substrate has a uniform thickness, controllable size, and a high yield rate.

[0028] 3. The present invention uses a plasma etching process to process the xylene C substrate, thereby enhancing the surface hydrophilicity of the xylene C substrate and functionalizing its surface, thereby promoting the adhesion of subsequent layers; at the same time, this plasma etching process can strictly control process parameters, including etching rate, etching time, etc., and carry out batch and repeatable production of the xylene C substrate.

[0029] 4. The present invention uses a uniformly spin-coated gelatin aqueous solution as the intermediate adhesion layer of the xylene C substrate and the MXene film. Due to the adhesion effect of the gelatin layer, the MXene layer has better environmental stability and is not easily peeled off or damaged by external force; at the same time, the subsequent MXene aqueous solution can be evenly spin-coated on the xylene C substrate with controllable thickness.

[0030] 5. The present invention uses a plasma etching process to process the MXene film on the xylene C substrate to obtain an oxidized MXene layer, called an OXene layer. When the OXene layer contacts the P-type semiconductor, the P-type semiconductor can be further activated. This is because the oxidized rutile titanium dioxide particles are generated on the surface of the MXene film by plasma etching, so that the OXene layer has a symmetry-broken material structure. This structure can form a PN junction with the contacting P-type semiconductor, prompting the electrons in the P-type semiconductor to be directed to the N-type semiconductor. This is similar to hole doping in a hole-dominated P-type semiconductor, that is, P-type doping, which makes the hole concentration in the P-type semiconductor higher, thereby improving the semiconductor carrier mobility.

[0031] 6. The ionic dielectric solution of the transistor prepared by step 6 of the present invention has high ionic conductivity, which can not only improve the switching speed and overall performance of the transistor, but also better control the gate capacitance, thereby improving device efficiency and reducing power consumption.

[0032] In summary, the present invention uses a plasma etching process to oxidize the MXene film on the surface of the transistor substrate, so that anatase titanium dioxide particles are generated on the surface of the MXene film, and a MXene substrate with broken symmetry is obtained, which is recorded as an OXene layer, and then P3HT is coated on the OXene layer to form a PN junction, which promotes the directional transfer of electrons in the P-type semiconductor to the N-type semiconductor, thereby improving the current switching ratio of the P-type transistor; the transistor prepared by the present invention can be applied to an inverter, a NAND gate (NAND) circuit, and a NOR gate (NOR) circuit; the process of the present invention is compatible with existing manufacturing technology, does not need to add complex or expensive materials, has a low production process cost, and is easy to mass produce. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 The TEM image of the oxidized MXene (OXene) layer formed in step 4 of the present invention and the EDX surface scan of the corresponding elements, wherein: Figure 1 (a) is the TEM image, Figure 1 (b) is the EDX scan of Ti element. Figure 1 (c) is the EDX scan of O element. Figure 1 (d) is the EDX scan image of the C element.

[0034] Figure 2 TEM images of commercially available MXene and EDX surface scan images of corresponding elements, where: Figure 2 (a) is the TEM image, Figure 2 (b) is the EDX scan of Ti element. Figure 2 (c) is the EDX scan of O element. Figure 2(d) is the EDX surface scan of the C element.

[0035] Figure 3 This is a transfer characteristic curve diagram of the transistor provided by the present invention.

[0036] Figure 4 A graph showing the relationship between the switching ratio of the transistor provided by the present invention and the oxidation treatment time. DETAILED DESCRIPTION

[0037] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0038] A method for establishing a reconfigurable field effect transistor based on symmetry-broken MXene comprises the following steps:

[0039] Step 1: Deposit on a single-side polished 4-inch silicon substrate using a chemical vapor transport process to obtain a Parylene C substrate with a thickness of 10 to 20 μm; then use a plasma etching process to modify the surface of the Parylene C substrate to remove surface hydrophobic groups such as amino-NH 3 etc., to obtain a modified xylene C substrate;

[0040] The conditions of the chemical vapor transport process are as follows: first, a 4-inch silicon substrate is placed in a CVD chamber, and the pressure of the CVD chamber is evacuated to less than 10Pa, and 0.2-0.5g of precursor particles are respectively vaporized at 140-160°C, and the furnace tube is maintained at 680-720°C to pyrolyze the precursor to form a monomer; during the deposition of the precursor particles, the chamber pressure is maintained at about 10Pa; the substrate temperature during the deposition process is 20-30°C, and the deposition time is 4-5h; the precursor particles are Parylene C;

[0041] The conditions of the plasma etching process are: oxygen plasma is introduced into the etching chamber at a pressure of 20 to 40 mmHg, the etching rate is 20 to 40 cc / min, the etching power is 160 to 200 W, the etching frequency is 20 to 40 KHz, and the etching time is 30 to 300 s. The plasma etching process can enhance the surface hydrophilicity of the Parylene C substrate and functionalize its surface, thereby promoting the adhesion of subsequent layers;

[0042] Step 2: Spin-coat the gelatin aqueous solution on the modified xylene C substrate obtained in step 1 at a rotation speed of 1500-3000 rpm for 20-30 seconds and a spin-coating thickness of 10-30 μm; then dry the xylene C substrate coated with gelatin on a hot plate at 60-70°C for 10-20 minutes; then spin-coat the MXene aqueous solution with a concentration of 5-20 mg / ml on the dried xylene C substrate coated with gelatin at a rotation speed of 1500-3000 rpm for 20-30 seconds and a spin-coating thickness of 40-60 μm; then thermally cure at 60-70°C for 10-20 minutes to obtain a xylene C substrate with a MXene film; the concentration of the gelatin is 3.5-5 mg / ml;

[0043] The MXene aqueous solution is composed of Ti 3 C 2 T x The powder is mixed with deionized water;

[0044] The preparation process of the gelatin aqueous solution is as follows:

[0045] Gelatin powder and deionized water were dissolved by stirring at 120°C for 30 min, with the purpose of serving as an adhesion layer between the Parylene C substrate and the MXene film.

[0046] Step 3: Use a near-infrared laser to pattern the xylene C substrate with the MXene film in step 2, and etch out the MXene film with a logic circuit to form a transistor substrate. The channel width / length (W / L) of the transistor substrate is in the micrometer range, and W / L is 250 / 50-500 / 50 μm; the line width of the near-infrared laser is 100-150 μm, and the laser height is 15-20 cm from the operating platform; laser patterning using near-infrared laser technology can ensure the correct geometry, thereby achieving optimal transistor performance;

[0047] Step 4: Oxygen plasma etching is performed on the transistor substrate in step 3 using a plasma etching process, so that anatase titanium dioxide particles are generated on the surface of the MXene film, and a MXene substrate with broken symmetry is obtained, which is recorded as an OXene layer;

[0048] The plasma etching process conditions of this step are the same as those of step 3, except that: the etching time of step 4 is 10 to 120 seconds;

[0049] Step 5: Spin coating the P-type semiconductor solution onto the OXene layer obtained in step 4 at a rotation speed of 1500-3000 rpm for 15-45 seconds with a spin coating thickness of 20-30 μm to obtain a P-type semiconductor layer of the transistor; patterning the P-type semiconductor layer of the transistor using a shadow mask, wherein the shadow mask is a polyimide film (commonly known as Kapton); then annealing the P-type semiconductor layer at 120-130° C. for 20-30 minutes to remove dichloromethane; the P-type semiconductor solution is poly 3-hexylthiophene (P3HT);

[0050] The preparation process of P3HT in step 5 is as follows:

[0051] P3HT powder was dissolved in dichloromethane with a concentration of 2 mg / ml at 60°C, and then cooled to -20°C and kept for 30 minutes to obtain a P3HT nanofiber solution (P3HT-NFs); the P3HT nanofiber solution and the PDMS solution were mixed with dichloromethane to obtain P3HT; the PDMS solution was obtained by mixing a PDMS prepolymer and a curing agent in a weight ratio of 10:1; the weight ratio of the P3HT nanofiber solution to the PDMS solution was 2:8;

[0052] Step 6: Mix PVDF-HFP, EMI-TFSA and acetone at 60-80° C. for 1-2 hours to obtain an ionic dielectric solution of a transistor; by weight ratio, the PVDF-HFP:EMI-TFSA:acetone=(1-2):(3-4):(4-7);

[0053] The PVDF-HFP is polyvinylidene fluoride-co-hexafluoropropylene, and its molecular weight is 400,000; EMI-TFSA is 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide salt, and its purity is greater than 98%;

[0054] Step 7: Pour the ionic dielectric solution of the transistor in step 6 onto a clean glass substrate and place it in a vacuum oven at 60 to 80°C for 6 to 12 hours to solidify it, thereby obtaining an ionic gel with a thickness of 200 to 400 μm, which is easy to shape and operate;

[0055] Step 8: Cut the ion gel obtained in step 7 into strips and laminate them as a dielectric layer on the P-type semiconductor layer of the transistor obtained in step 5 to provide insulation and control the electric field in the active area, and finally obtain a reconfigurable field effect transistor based on symmetry-broken MXene;

[0056] After the ion gel is cut into strips, use dust-free paper to promptly absorb the participating ion solution attached to the gel to prevent it from conducting electricity and causing gate leakage of the transistor.

[0057] Furthermore, the present invention also provides a reconfigurable field effect transistor based on symmetry-broken MXene prepared by the method of establishing a reconfigurable field effect transistor based on symmetry-broken MXene as mentioned above, and the application of the transistor in an inverter, a NAND gate (NAND) circuit, and a NOR gate (NOR) circuit.

[0058] Example 1

[0059] A method for establishing a reconfigurable field effect transistor based on symmetry-broken MXene comprises the following steps:

[0060] Step 1: Depositing on a single-side polished 4-inch silicon substrate using a chemical vapor transport process to obtain a 10 μm thick Parylene C substrate; then performing surface functional modification on the Parylene C substrate using a plasma etching process to remove the surface hydrophobic groups to obtain a modified Parylene C substrate;

[0061] The conditions of the chemical vapor transport process are as follows: first, a 4-inch silicon substrate is placed in a CVD chamber, and the pressure of the CVD chamber is evacuated to less than 10Pa, 0.2g of precursor particles are respectively vaporized at 140°C, and the furnace tube is maintained at 680°C to pyrolyze the precursor to form a monomer; during the deposition of the precursor particles, the chamber pressure is maintained at about 10Pa; the substrate temperature during the deposition process is 20°C, and the deposition time is 5h; the precursor particles are Parylene C;

[0062] The conditions of the plasma etching process are as follows: oxygen plasma is introduced into the etching chamber at a pressure of 20 mmHg, the etching rate is 20 cc / min, the etching power is 160 W, the etching frequency is 20 KHz, and the etching time is 30 s;

[0063] Step 2: Spin-coat a gelatin aqueous solution with a concentration of 3.5 mg / ml onto the modified xylene C substrate at a speed of 1500 rpm for 30 seconds and a coating thickness of 10 μm; then dry the xylene C substrate coated with gelatin on a 60°C hot plate for 20 minutes; then spin-coat a MXene aqueous solution with a concentration of 5 mg / ml onto the dried xylene C substrate coated with gelatin at a speed of 1500 rpm for 30 seconds and a coating thickness of 40 μm; then thermally cure at 60°C for 20 minutes to obtain a xylene C substrate with a MXene film;

[0064] Step 3: Use a near-infrared laser to pattern the xylene C substrate with the MXene film, and etch out the MXene film with the logic circuit to form a transistor substrate, and the channel width / length (W / L) of the transistor substrate is 250 / 50 μm; the line width of the near-infrared laser is 100 μm, and the laser height is 15 cm from the operating platform; laser patterning using near-infrared laser technology can ensure the correct geometry, thereby achieving optimal transistor performance;

[0065] Step 4: Oxygen plasma etching is performed on the transistor substrate using a plasma etching process to generate anatase titanium dioxide particles on the surface of the MXene film, thereby obtaining a MXene substrate with broken symmetry, which is recorded as an OXene layer;

[0066] The plasma etching process conditions of this step are the same as those of step 3, except that: the etching time of step 4 is 10 s;

[0067] Step 5: P3HT was applied to the OXene layer at a rotation speed of 1500 rpm for 45 seconds with a spin coating thickness of 20 μm to obtain a P-type semiconductor layer of the transistor; the P-type semiconductor layer of the transistor was patterned using a Kapton film as a shadow mask, and then annealed at 120° C. for 30 minutes;

[0068] Step 6: Mix PVDF-HFP, EMI-TFSA and acetone at 60° C. and stir for 2 hours to obtain an ionic dielectric solution of a transistor; in terms of weight ratio, the PVDF-HFP:EMI-TFSA:acetone=1:3:4;

[0069] Step 7: Pour the ionic dielectric solution of the transistor obtained in step 6 onto a clean glass substrate, place it in a vacuum oven at 60° C. for 12 hours to solidify it, and obtain an ionic gel with a thickness of 200 μm;

[0070] Step 8: Cut the solidified ion gel into strips and laminate them as a dielectric layer on the P-type semiconductor layer of the transistor obtained in step 5 to provide insulation and control the electric field in the active area, ultimately obtaining a reconfigurable field effect transistor based on symmetry-broken MXene.

[0071] Example 2

[0072] A method for establishing a reconfigurable field effect transistor based on symmetry-broken MXene comprises the following steps:

[0073] Step 1: Depositing on a single-side polished 4-inch silicon substrate using a chemical vapor transport process to obtain a 15 μm thick Parylene C substrate; then performing surface functional modification on the Parylene C substrate using a plasma etching process to remove the surface hydrophobic groups to obtain a modified Parylene C substrate;

[0074] The conditions of the chemical vapor transport process are as follows: first, a 4-inch silicon substrate is placed in a CVD chamber, and the pressure of the CVD chamber is evacuated to less than 10Pa, 0.3g of precursor particles are respectively vaporized at 150°C, and the furnace tube is maintained at 700°C to pyrolyze the precursor to form a monomer; during the deposition of the precursor particles, the chamber pressure is maintained at about 10Pa; the substrate temperature during the deposition process is 25°C, and the deposition time is 4h; the precursor particles are Parylene C;

[0075] The conditions of the plasma etching process are as follows: oxygen plasma is introduced into the etching chamber at a pressure of 30 mmHg, the etching rate is 30 cc / min, the etching power is 180 W, the etching frequency is 30 KHz, and the etching time is 130 s;

[0076] Step 2: Spin-coat a 4 mg / ml gelatin aqueous solution onto the modified xylene C substrate at a speed of 2000 rpm for 25 seconds and a coating thickness of 20 μm; then dry the xylene C substrate coated with gelatin on a 65°C hot plate for 15 minutes; then spin-coat a 10 mg / ml MXene aqueous solution onto the dried xylene C substrate coated with gelatin at a speed of 2000 rpm for 25 seconds and a coating thickness of 50 μm; then thermally cure at 65°C for 15 minutes to obtain a xylene C substrate with a MXene film;

[0077] Step 3: Use a near-infrared laser to pattern the xylene C substrate with the MXene film, and etch out the MXene film with the logic circuit to form a transistor substrate, and the channel width / length (W / L) of the transistor substrate is 250 / 50 μm; the line width of the near-infrared laser is 130 μm, and the laser height is 15 cm from the operating platform; laser patterning using near-infrared laser technology can ensure the correct geometry, thereby achieving optimal transistor performance;

[0078] Step 4: Oxygen plasma etching is performed on the transistor substrate using a plasma etching process to generate anatase titanium dioxide particles on the surface of the MXene film, thereby obtaining a MXene substrate with broken symmetry, which is recorded as an OXene layer;

[0079] The plasma etching process conditions of this step are the same as those of step 3, except that: the etching time of step 4 is 20 s;

[0080] Step 5: P3HT was applied onto the OXene layer at a rotation speed of 2000 rpm for 30 seconds with a spin coating thickness of 25 μm to obtain a P-type semiconductor layer of the transistor; the P-type semiconductor layer of the transistor was patterned using a Kapton film as a shadow mask, and then annealed at 125° C. for 25 minutes;

[0081] Step 6: Mix PVDF-HFP, EMI-TFSA and acetone at 70° C. and stir for 1 hour to obtain an ionic dielectric solution of a transistor; in terms of weight ratio, the PVDF-HFP:EMI-TFSA:acetone=1:4:7;

[0082] Step 7: Pour the ionic dielectric solution of the transistor obtained in step 6 onto a clean glass substrate, place it in a vacuum oven at 70°C for 9 hours to solidify it, and obtain an ionic gel with a thickness of 300 μm;

[0083] Step 8: Cut the solidified ion gel into strips and laminate them as a dielectric layer on the P-type semiconductor layer of the transistor obtained in step 5 to provide insulation and control the electric field in the active area, ultimately obtaining a reconfigurable field effect transistor based on symmetry-broken MXene.

[0084] Example 3

[0085] A method for establishing a reconfigurable field effect transistor based on symmetry-broken MXene comprises the following steps:

[0086] Step 1: Depositing on a single-side polished 4-inch silicon substrate using a chemical vapor transport process to obtain a 20 μm thick Parylene C substrate; then performing surface functional modification on the Parylene C substrate using a plasma etching process to remove the surface hydrophobic groups to obtain a modified Parylene C substrate;

[0087] The conditions of the chemical vapor transport process are as follows: first, a 4-inch silicon substrate is placed in a CVD chamber, and the pressure of the CVD chamber is evacuated to less than 10Pa. 0.5g of precursor particles are respectively vaporized at 160°C, and the furnace tube is maintained at 720°C to pyrolyze the precursor to form a monomer. During the deposition of the precursor particles, the chamber pressure is maintained at about 10Pa. The substrate temperature during the deposition process is 30°C, and the deposition time is 4h. The precursor particles are Parylene C.

[0088] The conditions of the plasma etching process are as follows: oxygen plasma is introduced into the etching chamber at a pressure of 40 mmHg, the etching rate is 40 cc / min, the etching power is 200 W, the etching frequency is 40 KHz, and the etching time is 170 s;

[0089] Step 2: Spin-coat a 5 mg / ml gelatin aqueous solution onto the modified xylene C substrate at a speed of 3000 rpm for 20 seconds and a coating thickness of 30 μm; then dry the xylene C substrate coated with gelatin on a 70°C hot plate for 20 minutes; then spin-coat a 20 mg / ml MXene aqueous solution onto the dried xylene C substrate coated with gelatin at a speed of 3000 rpm for 20 seconds and a coating thickness of 60 μm; then thermally cure at 65°C for 15 minutes to obtain a xylene C substrate with a MXene film;

[0090] Step 3: Use a near-infrared laser to pattern the xylene C substrate with the MXene film, and etch out the MXene film with the logic circuit to form a transistor substrate, and the channel width / length (W / L) of the transistor substrate is 500 / 50 μm; the line width of the near-infrared laser is 130 μm, and the laser height is 20 cm from the operating platform; laser patterning using near-infrared laser technology can ensure the correct geometry, thereby achieving optimal transistor performance;

[0091] Step 4: Oxygen plasma etching is performed on the transistor substrate using a plasma etching process to generate anatase titanium dioxide particles on the surface of the MXene film, thereby obtaining a MXene substrate with broken symmetry, which is recorded as an OXene layer;

[0092] The plasma etching process conditions of this step are the same as those of step 3, except that: the etching time of step 4 is 30 s;

[0093] Step 5: P3HT was applied to the OXene layer at a rotation speed of 3000 rpm for 15 seconds with a spin coating thickness of 30 μm to obtain a P-type semiconductor layer of the transistor; the P-type semiconductor layer of the transistor was patterned using a Kapton film as a shadow mask, and then annealed at 130° C. for 20 minutes;

[0094] Step 6: Mix PVDF-HFP, EMI-TFSA and acetone at 80° C. and stir for 1 hour to obtain an ionic dielectric solution of a transistor; in terms of weight ratio, the PVDF-HFP:EMI-TFSA:acetone=2:4:7;

[0095] Step 7: Pour the ionic dielectric solution of the transistor obtained in step 6 onto a clean glass substrate, place it in a vacuum oven at 80°C for 6 hours to solidify it, and obtain an ionic gel with a thickness of 400 μm;

[0096] Step 8: Cut the solidified ion gel into strips and laminate them as a dielectric layer on the P-type semiconductor layer of the transistor obtained in step 5 to provide insulation and control the electric field in the active area, ultimately obtaining a reconfigurable field effect transistor based on symmetry-broken MXene.

[0097] Example 4

[0098] A method for establishing a reconfigurable field effect transistor based on symmetry-broken MXene comprises the following steps:

[0099] Step 1: Depositing on a single-side polished 4-inch silicon substrate using a chemical vapor transport process to obtain a 20 μm thick Parylene C substrate; then performing surface functional modification on the Parylene C substrate using a plasma etching process to remove the surface hydrophobic groups to obtain a modified Parylene C substrate;

[0100] The conditions of the chemical vapor transport process are as follows: first, a 4-inch silicon substrate is placed in a CVD chamber, and the pressure of the CVD chamber is evacuated to less than 10Pa. 0.5g of precursor particles are respectively vaporized at 150°C, and the furnace tube is maintained at 700°C to pyrolyze the precursor to form a monomer. During the deposition of the precursor particles, the chamber pressure is maintained at about 10Pa. The substrate temperature during the deposition process is 25°C, and the deposition time is 4h. The precursor particles are Parylene C.

[0101] The conditions of the plasma etching process are as follows: oxygen plasma is introduced into the etching chamber at a pressure of 30 mmHg, the etching rate is 30 cc / min, the etching power is 180 W, the etching frequency is 30 KHz, and the etching time is 230 s;

[0102] Step 2: Spin-coat a 5 mg / ml gelatin aqueous solution onto the modified xylene C substrate at a speed of 2000 rpm for 25 seconds and a coating thickness of 20 μm; then dry the xylene C substrate coated with gelatin on a 65°C hot plate for 15 minutes; then spin-coat a 10 mg / ml MXene aqueous solution onto the dried xylene C substrate coated with gelatin at a speed of 2000 rpm for 25 seconds and a coating thickness of 50 μm; then thermally cure at 70°C for 20 minutes to obtain a xylene C substrate with a MXene film;

[0103] Step 3: Use a near-infrared laser to pattern the xylene C substrate with the MXene film, and etch out the MXene film with the logic circuit to form a transistor substrate, and the channel width / length (W / L) of the transistor substrate is 500 / 50 μm; the line width of the near-infrared laser is 100 μm, and the laser height is 20 cm from the operating platform; laser patterning using near-infrared laser technology can ensure the correct geometry, thereby achieving optimal transistor performance;

[0104] Step 4: Oxygen plasma etching is performed on the transistor substrate using a plasma etching process to generate anatase titanium dioxide particles on the surface of the MXene film, thereby obtaining a MXene substrate with broken symmetry, which is recorded as an OXene layer;

[0105] The plasma etching process conditions of this step are the same as those of step 3, except that: the etching time of step 4 is 60s;

[0106] Step 5: P3HT was applied onto the OXene layer at a rotation speed of 2000 rpm for 30 seconds with a spin coating thickness of 25 μm to obtain a P-type semiconductor layer of the transistor; the P-type semiconductor layer of the transistor was patterned using a Kapton film as a shadow mask, and then annealed at 120° C. for 20 minutes;

[0107] Step 6: Mix PVDF-HFP, EMI-TFSA and acetone at 70° C. and stir for 1 hour to obtain an ionic dielectric solution of a transistor; in terms of weight ratio, the PVDF-HFP:EMI-TFSA:acetone=1:4:7;

[0108] Step 7: Pour the ionic dielectric solution of the transistor obtained in step 6 onto a clean glass substrate, place it in a vacuum oven at 70°C for 12 hours to solidify it, and obtain an ionic gel with a thickness of 300 μm;

[0109] Step 8: Cut the solidified ion gel into strips and laminate them as a dielectric layer on the P-type semiconductor layer of the transistor obtained in step 5 to provide insulation and control the electric field in the active area, ultimately obtaining a reconfigurable field effect transistor based on symmetry-broken MXene.

[0110] Example 5

[0111] A method for establishing a reconfigurable field effect transistor based on symmetry-broken MXene comprises the following steps:

[0112] Step 1: Depositing on a single-side polished 4-inch silicon substrate using a chemical vapor transport process to obtain a 20 μm thick Parylene C substrate; then performing surface functional modification on the Parylene C substrate using a plasma etching process to remove the surface hydrophobic groups to obtain a modified Parylene C substrate;

[0113] The conditions of the chemical vapor transport process are as follows: first, a 4-inch silicon substrate is placed in a CVD chamber, and the pressure of the CVD chamber is evacuated to less than 10Pa. 0.5g of precursor particles are respectively vaporized at 150°C, and the furnace tube is maintained at 700°C to pyrolyze the precursor to form a monomer. During the deposition of the precursor particles, the chamber pressure is maintained at about 10Pa. The substrate temperature during the deposition process is 25°C, and the deposition time is 4h. The precursor particles are Parylene C.

[0114] The conditions of the plasma etching process are as follows: oxygen plasma is introduced into the etching chamber at a pressure of 30 mmHg, the etching rate is 30 cc / min, the etching power is 180 W, the etching frequency is 30 KHz, and the etching time is 300 s;

[0115] Step 2: Spin-coat a 5 mg / ml gelatin aqueous solution onto the modified xylene C substrate at a speed of 2000 rpm for 25 seconds and a coating thickness of 20 μm; then dry the xylene C substrate coated with gelatin on a 65°C hot plate for 15 minutes; then spin-coat a 10 mg / ml MXene aqueous solution onto the dried xylene C substrate coated with gelatin at a speed of 2000 rpm for 25 seconds and a coating thickness of 50 μm; then thermally cure at 65°C for 15 minutes to obtain a xylene C substrate with a MXene film;

[0116] Step 3: Use a near-infrared laser to pattern the xylene C substrate with the MXene film, and etch out the MXene film with the logic circuit to form a transistor substrate, and the channel width / length (W / L) of the transistor substrate is 500 / 50 μm; the line width of the near-infrared laser is 100 μm, and the laser height is 20 cm from the operating platform; laser patterning using near-infrared laser technology can ensure the correct geometry, thereby achieving optimal transistor performance;

[0117] Step 4: Oxygen plasma etching is performed on the transistor substrate using a plasma etching process to generate anatase titanium dioxide particles on the surface of the MXene film, thereby obtaining a MXene substrate with broken symmetry, which is recorded as an OXene layer;

[0118] The plasma etching process conditions of this step are the same as those of step 3, except that: the etching time of step 4 is 120 s;

[0119] Step 5: P3HT was applied onto the OXene layer at a rotation speed of 2000 rpm for 30 seconds with a spin coating thickness of 25 μm to obtain a P-type semiconductor layer of the transistor; the P-type semiconductor layer of the transistor was patterned using a Kapton film as a shadow mask, and then annealed at 125° C. for 25 minutes;

[0120] Step 6: Mix PVDF-HFP, EMI-TFSA and acetone at 70° C. and stir for 1 hour to obtain an ionic dielectric solution of a transistor; in terms of weight ratio, the PVDF-HFP:EMI-TFSA:acetone=1:4:7;

[0121] Step 7: Pour the ionic dielectric solution of the transistor obtained in step 6 onto a clean glass substrate, place it in a vacuum oven at 70°C for 12 hours to solidify it, and obtain an ionic gel with a thickness of 300 μm;

[0122] Step 8: Cut the solidified ion gel into strips and laminate them as a dielectric layer on the P-type semiconductor layer of the transistor obtained in step 5 to provide insulation and control the electric field in the active area, ultimately obtaining a reconfigurable field effect transistor based on symmetry-broken MXene.

[0123] Figure 1 TEM image of the OXene layer formed in step 4 of the present invention and the EDX surface scan of the corresponding elements, compared with the original MXene ( Figure 2 ),Depend on Figure 1 As shown in the red box of (a), a spindle-shaped anatase titanium dioxide structure is clearly seen at the boundary of the OXene layer. Figure 1 (b) and (c), Ti and O elements are uniformly distributed at the boundary of the OXene layer, indicating that the present invention forms a titanium dioxide structure in situ after oxygen plasma treatment on the transistor substrate.

[0124] Figure 3 It is shown that due to the broken symmetry of the OXene layer, the material structure achieves more efficient carrier dynamics, so that when the OXene layer is connected to the P-type semiconductor layer, it produces a transistor behavior that is completely different from the original MXene. Figure 3 It can be seen that the drain-source voltage (V DS ) is -1 V, a gate-source voltage (V) ranging from 0 V to -3 V is applied to the original MXene layer and the oxidized MXene (OXene) layer. GS), the MXene layer and OXene layer in contact with the P-type semiconductor exhibited distinct drain-source currents (I DS ) switching ratio. Among them, after the OXene layer contacts the P3HT of the P-type semiconductor, its I DS The ratio of the maximum to the minimum is greater than 10 5 times, indicating that the OXene layer has an excitatory effect on the P3HT of the P-type semiconductor; on the contrary, after the MXene layer contacts the P3HT of the P-type semiconductor, its I DS The ratio is less than 10 times, indicating that the MXene layer has an inhibitory effect on the P-type semiconductor.

[0125] After the MXene film is subjected to plasma etching treatment, anatase titanium dioxide particles are oxidized on the surface of the MXene film to form an OXene layer with a symmetry-breaking structure. When the OXene layer contacts the P-type semiconductor, the P-type semiconductor is further activated. This is because this structure can form a PN junction with the contacted P-type semiconductor, prompting the electrons in the P-type semiconductor to be transferred to the N-type semiconductor in a directional manner. This is similar to hole doping in a hole-dominated P-type semiconductor, that is, P-type doping, which makes the hole concentration in the P-type semiconductor higher and enhances the semiconductor carrier migration effect. In contrast, the original MXene layer with a negatively charged surface will capture the positive holes in P3HT to form a depletion layer that hinders the movement of carriers, which is similar to electron doping in a hole-dominated P-type semiconductor, so that the MXene layer has an inhibitory effect on the P-type semiconductor after contacting it.

[0126] Figure 4 The on / off ratio (l on / l off ) can be highly tuned by varying the duration of the oxidation treatment, with a wide modulation range and eventually becoming stable; Figure 4 It can be seen that as the duration of oxygen treatment increases, the on-off ratio of the transistor prepared by the present invention increases. When the duration of oxygen treatment is 60 s, the on-off ratio of the transistor reaches 2×10 5 , and eventually stabilized; this is due to the relationship between the duration of oxygen treatment and the TiO derived from the oxidized MXene (OXene) surface. 2 The particles are positively correlated, with more TiO 2 The particles can generate more channels for directional electron migration, making the transistor have more superior transmission characteristics. 2 The particles are N-type semiconductors, and too much TiO 2 The particles reduce the conductivity of the OXene transistor itself, so the switching ratio of the transistor no longer increases after 60s of oxidation treatment and tends to be stable.

Claims

1. A method for establishing a reconfigurable field effect transistor based on symmetry-broken MXene, characterized in that: The steps include: Step 1: using a chemical vapor transport process to deposit on a single-side polished silicon substrate to obtain a Parylene C substrate with a thickness of 10 to 20 μm; then using a plasma etching process to perform surface functional modification on the Parylene C substrate to remove the surface hydrophobic groups to obtain a modified Parylene C substrate; Step 2: Spin-coat a gelatin aqueous solution with a concentration of 3.5-5 mg / ml onto the modified Parylene C substrate obtained in step 1; then dry the Parylene C substrate coated with gelatin; then spin-coat a MXene aqueous solution with a concentration of 5-20 mg / ml onto the dried Parylene C substrate coated with gelatin, and then perform thermal curing to obtain a Parylene C substrate with a MXene film; Step 3: Use a near-infrared laser to pattern the xylene C substrate with the MXene film in step 2 to carve out a MXene film with a logic circuit to form a transistor substrate; Step 4: Oxygen plasma etching is performed on the transistor substrate in step 3 using a plasma etching process, so that anatase titanium dioxide particles are generated on the surface of the MXene film, and a MXene substrate with broken symmetry is obtained, which is recorded as an OXene layer; Step 5: Spin-coating a P-type semiconductor solution onto the OXene layer obtained in step 4 to obtain a P-type semiconductor layer of the transistor; and patterning the P-type semiconductor layer of the transistor using a shadow mask; Then annealing treatment is performed; Step 6: Mix and stir PVDF-HFP, EMI-TFSA and acetone to obtain an ionic dielectric solution of a transistor; by weight ratio, the PVDF-HFP:EMI-TFSA:acetone=(1-2):(3-4):(4-7); Step 7: Pour the ionic dielectric solution of the transistor obtained in step 6 onto a clean glass substrate, and after solidification, obtain an ionic gel with a thickness of 200 to 400 μm; Step 8: Cut the ion gel obtained in step 7 into strips and laminate them as a dielectric layer on the P-type semiconductor layer of the transistor obtained in step 5, thereby finally obtaining a reconfigurable field effect transistor based on symmetry-broken MXene.

2. The method for establishing a reconfigurable field effect transistor based on symmetry-broken MXene according to claim 1, characterized in that: The conditions of the plasma etching process used in step 1 and step 4 are: oxygen plasma is introduced into the etching chamber at a pressure of 20 to 40 mmHg, the etching rate is 20 to 40 cc / min, the etching power is 160 to 200 W, and the etching frequency is 20 to 40 KHz; the etching time of step 1 is 30 to 300 s, and the etching time of step 4 is 10 to 120 s.

3. The method for establishing a reconfigurable field effect transistor based on symmetry-broken MXene according to claim 1, characterized in that: The spin coating speeds in step 2 and step 5 are both 1500-3000 rpm; the spin coating time in step 2 is 20-30 s, the thickness of the spin-coated gelatin is 10-30 μm, the thickness of the spin-coated Mxene aqueous solution is 40-60 μm, the spin coating time in step 5 is 15-45 s, and the thickness of the spin-coated P-type semiconductor is 20-30 μm.

4. The method for establishing a reconfigurable field effect transistor based on symmetry-broken MXene according to claim 1, characterized in that: The temperature of the drying and heat curing operations in step 2 is 60-70° C., and the time is 10-20 minutes.

5. The method for establishing a reconfigurable field effect transistor based on symmetry-broken MXene according to claim 1, characterized in that: In step 2, the MXene aqueous solution is composed of Ti3C2T x The powder is mixed with deionized water.

6. The method for establishing a reconfigurable field effect transistor based on symmetry-broken MXene according to claim 1, characterized in that: In the step 3, the channel width / length (W / L) of the transistor substrate is in the micrometer range, and W / L is 250 / 50-500 / 50 μm; the line width of the near-infrared laser is 100-150 μm, and the laser height is 15-20 cm from the operating platform.

7. The method for establishing a reconfigurable field effect transistor based on symmetry-broken MXene according to claim 1, characterized in that: In step 5, the P-type semiconductor solution is poly 3-hexylthiophene (P3HT), the shadow mask is a polyimide film, the annealing temperature is 120-130° C., and the time is 20-30 minutes.

8. The method for establishing a reconfigurable field effect transistor based on symmetry-broken MXene according to claim 1, characterized in that: In step 6, PVDF-HFP is polyvinylidene fluoride-co-hexafluoropropylene, and its molecular weight is 400,000; EMI-TFSA is 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide salt, and its purity is greater than 98%.

9. The method for establishing a reconfigurable field effect transistor based on symmetry-broken MXene according to claim 1, characterized in that: In step 6, the stirring temperature is 60-80° C. and the time is 1-2 hours; in step 7, the solidification temperature is 60-80° C. and the time is 6-12 hours.

10. A reconfigurable field effect transistor based on symmetry-broken MXene prepared by the method for establishing a reconfigurable field effect transistor based on symmetry-broken MXene as described in claim 1, and application of the transistor in an inverter, a NAND gate (NAND) circuit, and a NOR gate (NOR) circuit.

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