Display device

Abstract

A display device is provided. The display device includes a substrate defining a display area and a non-display area, a first bank layer disposed on the substrate and defining a plurality of openings in the display area, a second bank layer disposed on the first bank layer and including a side surface protruding from a side surface of the first bank layer, a plurality of light emitting elements disposed on the substrate and overlapping the plurality of openings, a first inorganic encapsulation layer disposed on the plurality of light emitting elements, an organic encapsulation layer disposed on the first inorganic encapsulation layer and the second bank layer, a second inorganic encapsulation layer disposed on the organic encapsulation layer, and a first dam disposed between the substrate and the second inorganic encapsulation layer in the non-display area, wherein a region of the first side of the first dam does not overlap the first inorganic encapsulation layer in a thickness direction of the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0127645, filed on September 25, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] With the development of the information age, the demand for display devices for displaying images has increased in various forms. The display device may be a flat panel display device, such as a liquid crystal display device, a field emission display device, or an organic light emitting display device. Among such flat panel display devices, a light emitting display device includes a light emitting element that can emit light by itself in each pixel of a display panel, thereby displaying an image without using a backlight unit that provides light to the display panel.

[0005] A display device generally includes a display area that displays an image and a non-display area near the display area (e.g., the non-display area is arranged to surround the display area). Recently, in order to increase the immersion of the display area and increase the aesthetic appeal of the display device, the width of the non-display area has gradually decreased. Summary of the invention

[0006] Embodiments of the present disclosure provide a display device having a narrow width of a non-display area and improved resistance to moisture permeation.

[0007] According to an embodiment of the present disclosure, a display device includes a substrate, a first embankment layer, a second embankment layer, a plurality of light-emitting elements, a first inorganic encapsulation layer, an organic encapsulation layer, a second inorganic encapsulation layer and a first dam, wherein a display area and a non-display area arranged near the display area are defined on the substrate, the first embankment layer is arranged on the substrate, wherein the first embankment layer defines a plurality of openings in the display area, the second embankment layer is arranged on the first embankment layer, wherein the second embankment layer includes a side protruding more than a side of the first embankment layer, a plurality of light-emitting elements are arranged on the substrate and overlap with the plurality of openings, the first inorganic encapsulation layer is arranged on the plurality of light-emitting elements, the organic encapsulation layer is arranged on the first inorganic encapsulation layer and the second embankment layer, the second inorganic encapsulation layer is arranged on the organic encapsulation layer, and the first dam is arranged between the substrate and the second inorganic encapsulation layer in the non-display area, wherein an area on a first side of the first dam does not overlap with the first inorganic encapsulation layer in a thickness direction of the substrate.

[0008] In an implementation, a first side of the first dam may be directed toward the display region, and the organic encapsulation layer may overlap the first side of the first dam in a thickness direction of the substrate.

[0009] In an embodiment, a first side of the first dam may be in contact with the organic encapsulating layer, and a second side of the first dam opposite to the first side of the first dam may be in contact with the second inorganic encapsulating layer.

[0010] In an embodiment, the first inorganic encapsulation layer may include a first inorganic layer disposed on the plurality of light emitting elements and a second inorganic layer disposed on the first dam and spaced apart from the first inorganic layer.

[0011] In an embodiment, the first inorganic layer may include a plurality of sub-inorganic layers disposed on each of the plurality of light emitting elements, and the plurality of sub-inorganic layers of the first inorganic layer may be spaced apart from each other.

[0012] In an embodiment, the second inorganic layer may include the same material as that of a corresponding one of the plurality of sub-inorganic layers of the first inorganic layer.

[0013] In an implementation, the second inorganic layer may include a plurality of sub-inorganic layers sequentially stacked on the first dam.

[0014] In an implementation, the display device may further include a second dam between the first dam and the plurality of light emitting elements.

[0015] In an embodiment, the second inorganic layer may include a first sub-inorganic layer disposed on the first dam and a second sub-inorganic layer disposed on the second dam, and the first sub-inorganic layer and the second sub-inorganic layer may be spaced apart from each other.

[0016] In an embodiment, the second inorganic layer may further include a third sub-inorganic layer disposed on the first sub-inorganic layer.

[0017] In an embodiment, each of the plurality of light emitting elements may include a pixel electrode arranged on a substrate and overlapping a corresponding opening among the plurality of openings, a light emitting layer arranged on the pixel electrode, and a common electrode arranged on the light emitting layer, and one end of the common electrode and the other end of the common electrode opposite to the one end of the common electrode overlap with the corresponding opening.

[0018] In an implementation, the common electrode may contact the first bank layer.

[0019] In an embodiment, the first inorganic encapsulation layer may include a plurality of sub-inorganic layers arranged on the plurality of light emitting elements overlapping the plurality of openings and on the second bank layer near the plurality of openings.

[0020] In an embodiment, the display device may further include a third inorganic encapsulating layer disposed between the first inorganic encapsulating layer and the organic encapsulating layer.

[0021] According to an embodiment of the present disclosure, a display device includes a substrate, a first bank layer, a second bank layer, a first light-emitting element, a second light-emitting element, a first dam, a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, wherein a display area and a non-display area arranged near the display area are defined on the substrate, the first bank layer is arranged on the substrate, wherein the first bank layer defines a plurality of openings in the display area, the second bank layer is arranged on the first bank layer, wherein the second bank layer includes a side protruding from a side of the first bank layer, the first light-emitting element is arranged on the substrate and overlaps with a first opening among the plurality of openings, the second light-emitting element is arranged on the substrate and overlaps with a second opening spaced apart from the first opening, the first dam is arranged on the substrate in the non-display area, the first inorganic encapsulation layer includes a first sub-inorganic layer arranged on the first light-emitting element, a second sub-inorganic layer arranged on the second light-emitting element, and a third sub-inorganic layer arranged on the first dam, the organic encapsulation layer is arranged on the first inorganic encapsulation layer, and the second inorganic encapsulation layer is arranged on the organic encapsulation layer, wherein the first sub-inorganic layer, the second sub-inorganic layer, and the third sub-inorganic layer of the first inorganic encapsulation layer may be spaced apart from each other.

[0022] In an embodiment, the first sub-inorganic layer and the second sub-inorganic layer may contact a lower surface of the second bank layer.

[0023] In an embodiment, a first side of the first dam may be in contact with the organic encapsulating layer, and a second side of the first dam opposite to the first side of the first dam may be in contact with the second inorganic encapsulating layer.

[0024] According to an embodiment of the present disclosure, a display device includes a substrate, a plurality of light-emitting elements, a first dam, a second dam, a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, wherein a display area and a non-display area arranged near the display area are defined on the substrate, a plurality of light-emitting elements are arranged on the substrate in the display area, a first dam is arranged on the substrate in the non-display area, a second dam is arranged on the substrate in the non-display area and is positioned between the plurality of light-emitting elements and the first dam, the first inorganic encapsulation layer includes a first sub-inorganic layer arranged on the first dam, a second sub-inorganic layer arranged on the first sub-inorganic layer, and a third sub-inorganic layer arranged on the second dam, the organic encapsulation layer is arranged on the plurality of light-emitting elements and the third sub-inorganic layer, and the second inorganic encapsulation layer is arranged on the organic encapsulation layer and the first dam, wherein the first sub-inorganic layer and the third sub-inorganic layer may be spaced apart from each other.

[0025] In an embodiment, the first inorganic encapsulation layer may include a fourth sub-inorganic layer arranged on a first light-emitting element among a plurality of light-emitting elements and a fifth sub-inorganic layer arranged on a second light-emitting element among the plurality of light-emitting elements and separated from the fourth sub-inorganic layer, the first sub-inorganic layer may include the same material as that of the fourth sub-inorganic layer, and the second sub-inorganic layer may include the same material as that of the fifth sub-inorganic layer.

[0026] In an embodiment, a first side of the first dam may overlap with the organic encapsulation layer, a second side of the first dam opposite to the first side of the first dam may not overlap with the organic encapsulation layer, and a first side of the second dam and a second side of the second dam opposite to the first side of the second dam may overlap with the organic encapsulation layer.

[0027] The display device according to the embodiment may have improved resistance to moisture penetration.

[0028] The display device according to the embodiment may have a non-display area with a narrow width.

[0029] The effects according to the embodiments of the present disclosure are not limited to the above-mentioned effects, and more various effects are included in the following description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other features of the embodiments of the present disclosure will become more apparent by describing in detail the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0031] Figure 1 is a perspective view showing a display device according to an embodiment;

[0032] Figure 2 is shown in a folded state when viewed on the front surface Figure 1 A plan view of a display device;

[0033] Figure 3 is shown in a folded state when viewed from the side Figure 1 A cross-sectional view of a display device;

[0034] Figure 4 is a plan view showing a display layer of a display device according to an embodiment;

[0035] Figure 5 is a plan view showing an arrangement of a light emitting region and a second bank layer in a display region of a display device according to an embodiment;

[0036] Figure 6 is a cross-sectional view showing a display area of ​​a display device (eg, a display panel) according to an embodiment;

[0037] Figure 7 It is shown Figure 6 An enlarged plan view of a first light emitting region;

[0038] Figures 8 to 10 is an enlarged cross-sectional view showing a first light emission region of a display device according to other embodiments;

[0039] Fig.11 It is shown Figure 2 An enlarged plan view of area A2;

[0040] Fig.12 is shown along Fig.11 A cross-sectional view of an example of a display device (eg, a display panel) taken along line II-II';

[0041] Fig.13 It is shown by Fig.12 A cross-sectional view of an example of a display panel enlarged in area A4; and

[0042] Fig.14 and Fig.15 is an enlarged cross-sectional view showing a boundary between a display area and a non-display area of ​​a display device according to another embodiment. DETAILED DESCRIPTION

[0043] Now the present invention will be described more fully below with reference to the accompanying drawings showing various embodiments of the present invention. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the specification, similar reference numerals refer to similar elements.

[0044] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0045] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present invention, the first element discussed below can be referred to as the second element. Similarly, the second element can also be referred to as the first element.

[0046] The terms used herein are only for the purpose of describing a specific embodiment, and are not intended to be limited. Unless the context clearly indicates otherwise, "a", "an", "the" and "at least one" as used herein do not foreshadow the limitation of quantity, and are intended to include both the singular and the plural. Therefore, the element mentioned in a claim that subsequently mentions "the" element includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one (at least one)" will not be interpreted as limiting "a" or "an". "Or (or)" means "and / or (and / or)". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will also be understood that the terms “comprises” and / or “comprising” or “includes” and / or “including”, when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or clusters thereof.

[0047] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, relative terms are intended to cover different orientations of the device. For example, if the device in one of the multiple figures is turned over, the element described as being on the "lower" side of the other elements will then be oriented on the "upper" side of the other elements. Therefore, depending on the specific orientation of the figure, the term "lower" can cover both the orientation of "lower" and "upper". Similarly, if the device in one of the multiple figures is turned over, the element described as being "below" or "beneath" of the other elements will then be oriented "above" the other elements. Therefore, the term "below" or "below" can cover both the orientation of the upper and lower sides.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0049] Embodiments are described herein with reference to schematically illustrated cross-sectional views of idealized embodiments. Thus, variations in the shapes of the illustrations resulting from, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the embodiments described herein should not be construed as being limited to the shapes of the specific zones as shown herein, but will include deviations in shapes resulting from, for example, manufacturing. For example, a zone shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the zones shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the zones, and are not intended to limit the scope of the claims.

[0050] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0051] Figure 1 is a perspective view showing a display device 10 according to an embodiment. Figure 2 is shown in a folded state when viewed on the front surface Figure 1 FIG. 1 is a plan view of the display device 10 .

[0052] Reference Figure 1 and Figure 2 According to the embodiment, the display device 10 is a device for displaying moving images or still images, and can be used as a display screen for various products (such as televisions, notebook computers, monitors, billboards, and devices for the Internet of Things (IoT)) and portable electronic devices (such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic diaries, electronic books, portable multimedia players (PMPs), navigators, and ultra mobile PCs (UMPCs)).

[0053] The display device 10 according to the embodiment may be a light-emitting display device, such as an organic light-emitting display device using an organic light-emitting diode (organic LED), a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro (or nano) light-emitting display device using a micro (or nano) light-emitting diode (micro LED or nano LED). Hereinafter, for the convenience of description, an embodiment in which the display device 10 is an organic light-emitting display device will be described, but the present disclosure is not limited thereto.

[0054] The display device 10 according to the embodiment may include a display panel 100 , a display driver 200 , and a circuit board 300 .

[0055] In an embodiment, for example, Figure 1As shown in , the display panel 100 may be formed as a rectangular plane having short sides in a first direction DR1 and long sides in a second direction DR2 crossing the first direction DR1. A corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be formed as a right angle or rounded to have a curvature. The plane shape of the display panel 100 is not limited to a rectangular shape, and may be formed in other polygonal shapes, a circular shape, or an elliptical shape.

[0056] The display panel 100 may be formed to be flat, but is not limited thereto. In an embodiment, for example, the display panel 100 may include curved surface portions having a constant curvature or a variable curvature formed at the left and right ends. In addition, the display panel 100 may be flexibly formed to be bent, curved, folded, or curled.

[0057] The display panel 100 may include a main area MA and a sub area SBA.

[0058] The main area MA may include a display area DA for displaying an image and a non-display area NDA where no image is displayed.

[0059] The display area DA may occupy most of the area of ​​the display panel 100. The display area DA may be disposed at the center of the display panel 100. Pixels each including a plurality of light emission areas may be disposed in the display area DA to display an image. Figure 2 The area A1 shown in FIG. 5 may be part of the display area DA.

[0060] The non-display area NDA may be disposed adjacent to the display area DA. The non-display area NDA may be an outer area of ​​the display area DA and may be disposed to surround the display area DA. The non-display area NDA may be an edge area of ​​the display panel 100. Figure 2 The area A2 shown in FIG. 1 may be an edge area of ​​the display device 10 , and may include a portion of the display area DA and a portion of the non-display area NDA.

[0061] The sub-region SBA may extend from one side of the main region MA. The sub-region SBA may include a flexible material that can withstand bending, folding, curling, or the like. In an embodiment, for example, in a state where the sub-region SBA is bent, the sub-region SBA may overlap with the main region MA in the thickness direction DR3 (third direction DR3). The sub-region SBA may include a display driver 200 and a pad portion connected to the circuit board 300. In another embodiment, the sub-region SBA may be omitted, and the display driver 200 and the pad portion may be arranged in the non-display area NDA.

[0062] Reference Figure 1 , the sub-area SBA may include a display pad DP (eg Figure 4), a display driver 200 and a circuit board 300.

[0063] The display pad DP may be disposed at one edge of the display panel 100. In an embodiment, for example, the display pad DP may be disposed at a lower edge of the display panel 100. The display pad DP may be connected to the display driver 200 and the circuit board 300.

[0064] The display driver 200 may generate and output signals and voltages for driving the display panel 100. In an embodiment, the display driver 200 may generate and output a data voltage, a power voltage, and a scan timing signal (e.g., a gate control signal (e.g., a scan control signal)). The display driver 200 may supply the power voltage to the power line and supply the gate control signal to the gate driver (e.g., a scan driver).

[0065] In the present embodiment, the display driver 200 may be arranged between the display pad DP and the non-display area NDA in the sub-area SBA. In another embodiment, the display driver 200 may be arranged between the display pad DP and the display area DA in the non-display area NDA. The display driver 200 may be attached to the non-display area NDA of the display panel 100 in a chip on glass (COG) scheme. Alternatively, the display driver 200 may be attached to the circuit board 300 in a chip on plastic (COP) scheme.

[0066] The circuit board 300 may be arranged at one edge of the display panel 100 and may be arranged on the display pad DP. The circuit board 300 may be attached to the display pad DP by using a conductive adhesive member such as an anisotropic conductive film and an anisotropic conductive adhesive. Therefore, the circuit board 300 may be electrically connected to the signal line of the display panel 100. The circuit board 300 may be a flexible printed circuit board or a flexible film such as a chip on film. In addition, components (e.g., Figure 3 Component 400 shown in FIG.

[0067] Figure 3 is shown in a folded state when viewed from the side Figure 1 That is, Figure 3 is shown folded and viewed from the side Figure 1 1 is a cross-sectional view of a display device 10.

[0068] Reference Figure 3 , an embodiment of the display panel 100 may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, a thin film encapsulation layer TFEL, and a color filter layer CFL.

[0069] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate capable of being bent, folded, curled, or the like. In an embodiment, for example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. In another embodiment, the substrate SUB may include a glass material or a metal material.

[0070] The thin film transistor layer TFTL may be arranged on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may also include a scan line, a data line, a power line, a scan control line, a fan-out line for connecting the display driver 200 with the data line, and a lead for connecting the display driver 200 with a pad portion. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. In an embodiment, for example, when a scan driver is formed on one side of the non-display area NDA of the display panel 100, the scan driver may include a thin film transistor.

[0071] The thin film transistor layer TFTL may be arranged in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistor, the scan line, the data line, and the power line of each of the pixels of the thin film transistor layer TFTL may be arranged in the display area DA. The scan control line and the fan-out line of the thin film transistor layer TFTL may be arranged in the non-display area NDA. The lead line of the thin film transistor layer TFTL may be arranged in the sub-area SBA.

[0072] The light emitting element layer EML may be arranged on the thin film transistor layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements including a first electrode (e.g., a pixel electrode), a second electrode (e.g., a common electrode) and a light emitting layer, and a pixel defining layer for defining pixels. The plurality of light emitting elements of the light emitting element layer EML may be arranged in the display area DA.

[0073] In an embodiment, the light emitting element layer EML may be an organic light emitting layer including an organic material. The light emitting layer may include a hole transport layer, an organic light emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin film transistor of the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may move to the organic light emitting layer through the hole transport layer and the electron transport layer, and may be combined with each other in the organic light emitting layer to emit light.

[0074] In another embodiment, the light emitting element may include a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, or a micro LED.

[0075] The thin film encapsulation layer TFEL may cover the upper surface and side surfaces of the light emitting element layer EML and may protect the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer to encapsulate the light emitting element layer EML.

[0076] The color filter layer CFL may be disposed on the thin film encapsulation layer TFEL. The color filter layer CFL may include a plurality of color filters (eg, Figure 6 CF shown in FIG. 1 ). Each of the color filters may selectively transmit light of a specific wavelength and may block or absorb light of another wavelength. The color filter layer CFL may absorb part of light incident from the outside of the display device 10 to reduce reflected light due to external light. Therefore, the color filter layer CFL may effectively prevent color distortion caused by external light reflection from occurring.

[0077] In an implementation, the color filter layer CFL is directly disposed on the thin film encapsulation layer TFEL, so that the display device 10 may not include a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively small.

[0078] In some embodiments, the display device 10 may further include an optical device (not shown). The optical device may emit or receive light in an infrared, ultraviolet, or visible wavelength band. In an embodiment, for example, the optical device may be an optical sensor for sensing light incident on the display device 10, such as a proximity sensor, an illumination sensor, a camera sensor, a fingerprint sensor, or an image sensor.

[0079] Figure 4 is a plan view showing a display layer of a display device according to an embodiment.

[0080] Reference Figure 4 In an embodiment, the display layer may include a display area DA and a non-display area NDA. In this document, the display layer may refer to Figure 1 The display panel 100 shown in FIG.

[0081] The display area DA may be disposed at the center of the display panel 100. A plurality of pixels PX, a plurality of scan lines SL, a plurality of data lines DL, and a plurality of power lines VL may be disposed in the display area DA. Each of the plurality of pixels PX may be defined as a minimum or basic unit for outputting light.

[0082] The plurality of scan lines SL may supply scan signals received from the scan driver 210 to the plurality of pixels PX. The plurality of scan lines SL may extend in a first direction DR1 and may be spaced apart from each other in a second direction DR2 crossing the first direction DR1.

[0083] The plurality of data lines DL may supply data voltages received from the display driver 200 to the plurality of pixels PX. The plurality of data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0084] The plurality of power lines VL may supply a power voltage received from the display driver 200 to the plurality of pixels PX. In this case, the power voltage may include at least one selected from a driving voltage, an initialization voltage, a reference voltage, and a low potential voltage. The plurality of power lines VL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0085] The non-display area NDA may surround the display area DA. The scan driver 210, the fan-out lines FOL, and the scan control lines SCL may be arranged in the non-display area NDA. The scan driver 210 may generate a plurality of scan signals based on the scan control signal, and may sequentially supply the plurality of scan signals to the plurality of scan lines SL according to a predetermined order.

[0086] The fan-out line FOL may extend to the display area DA from the display driver 200. The fan-out line FOL may supply a data voltage received from the display driver 200 to the plurality of data lines DL.

[0087] The scan control line SCL may extend from the display driver 200 to the scan driver 210. The scan control line SCL may supply a scan control signal received from the display driver 200 to the scan driver 210.

[0088] The sub-area SBA may include the display driver 200 , the pad area PA, and first and second touch pad areas TPA1 and TPA2 .

[0089] The display driver 200 may output signals and voltages for driving the display panel 100 to the fan-out lines FOL. The display driver 200 may supply data voltages to the data lines DL through the fan-out lines FOL. The data voltages may be supplied to a plurality of pixels PX, and the brightness of the plurality of pixels PX may be controlled. The display driver 200 may supply scan control signals to the scan driver 210 through the scan control lines SCL.

[0090] The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2 may be arranged at the edge of the sub-area SBA. The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2 may be electrically connected to the circuit board 300 by using a material such as an anisotropic conductive film or a self-assembled anisotropic conductive paste (SAP).

[0091] The pad area PA may include a plurality of display pads DP. The plurality of display pads DP may be connected to a graphics system through a circuit board 300. The plurality of display pads DP may be connected to the circuit board 300 to receive digital video data, and may supply the digital video data to the display driver 200. The first touch pads TP1 in the first touch pad area TPA1 and / or the second touch pads TP2 in the second touch pad area TPA2 may also be connected to the circuit board 300 or another component.

[0092] Figure 5 is a diagram showing a portion of a display device according to an embodiment (specifically, Figure 2 A plan view of area A1). Figure 5 is a diagram showing a display device 10 (for example, referring to Figure 2 ) is a plan view of the arrangement of the light emission areas EA1, EA2 and EA3 and the second bank layer BN2 in the display area DA of FIG.

[0093] Reference Figure 5 The second bank layer BN2 may expose a portion of the display area DA while covering the display area DA. An opening may be defined or formed in the exposed area not covered by the second bank layer BN2, and each of the light emission areas EA1, EA2, and EA3 may be defined by the opening.

[0094] exist Figure 5 In the figure, the area exposed and not covered by the second bank layer BN2 is shown as a circular shape, but may be a polygonal shape such as a triangle, a rectangle, or a hexagon. The plurality of light emission areas EA1, EA2, and EA3 may be arranged as follows: Type (e.g. diamond Type). In an embodiment, for example, the first light emission region EA1 and the third light emission region EA3 may be spaced apart from each other in the first direction DR1, and may be alternately arranged in the first direction DR1 and the second direction DR2. The second light emission region EA2 may be spaced apart from another adjacent second light emission region EA2 in the first direction DR1 and the second direction DR2. The second light emission region EA2 and the first light emission region EA1 or the second light emission region EA2 and the third light emission region EA3 may be alternately arranged in any one direction in a plane defined by the first direction DR1 and the second direction DR2. The shape and arrangement of the area exposed and not covered by the second bank layer BN2 and the plurality of light emission regions are not limited to Figure 5 .

[0095] Figure 6 is a diagram showing a display panel 100 according to an embodiment (for example, referring to Figure 1 ) of the display area DA (for example, referring to Figure 1 ) is a cross-sectional view of a portion of the Figure 6 is along Figure 5 A cross-sectional view taken along line II'. Figure 6 is a cross-sectional view showing a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, a thin film encapsulation layer TFEL, and a color filter layer CFL.

[0096] In an embodiment, the thin film transistor layer TFTL may include a first buffer layer BF1, a lower metal layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first through hole layer VIA1, a second connection electrode CNE2, and a second through hole layer VIA2.

[0097] In an embodiment, the first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic layer capable of preventing air or moisture from penetrating. In an embodiment, for example, the first buffer layer BF1 may include a plurality of inorganic layers alternately stacked.

[0098] The lower metal layer BML may be disposed on the first buffer layer BF1. For example, the lower metal layer BML may be formed of a single layer or a multilayer including at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, or made thereof.

[0099] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 may include an inorganic layer capable of preventing air or moisture from penetrating. In an embodiment, for example, the second buffer layer BF2 may include a plurality of inorganic layers alternately stacked.

[0100] The thin film transistor TFT may be arranged on the second buffer layer BF2, and may constitute a pixel circuit of each of the plurality of pixels (e.g., may be included in a pixel circuit of each of the plurality of pixels). In an embodiment, for example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0101] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap the lower metal layer BML and the gate electrode GE in the thickness direction DR3, and may be insulated from the gate electrode GE by the gate insulating layer GI. Portions of the semiconductor layer ACT may form a source electrode SE and a drain electrode DE by doping or conducting the material of the semiconductor layer ACT.

[0102] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT in the thickness direction DR3 with the gate insulating layer GI interposed therebetween.

[0103] The gate insulating layer GI may be disposed on the semiconductor layer ACT. In an embodiment, for example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2 and may insulate the semiconductor layer ACT from the gate electrode GE. The gate insulating layer GI may provide a contact hole through which the first connection electrode CNE1 passes.

[0104] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may provide a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0105] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE may overlap the gate electrode GE in the thickness direction DR3. The capacitor electrode CPE and the gate electrode GE may form a capacitance.

[0106] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may provide a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer ILD2 may be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0107] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole defined or formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0108] The first via layer VIA1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first via layer VIA1 may protect the thin film transistor TFT. The first via layer VIA1 may provide a contact hole through which the second connection electrode CNE2 passes.

[0109] The second connection electrode CNE2 may be disposed on the first via layer VIA1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 with the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED. The second connection electrode CNE2 may be inserted into a contact hole formed in the first via layer VIA1 to contact the first connection electrode CNE1.

[0110] The second via layer VIA2 may cover the second connection electrode CNE2 and the first via layer VIA1. The second via layer VIA2 may include contact holes through which the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED pass.

[0111] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a light emitting element ED, a pixel defining layer PDL, a capping layer CAP, and a bank structure BNS. The light emitting element ED may include pixel electrodes AE1, AE2, and AE3, light emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3.

[0112] Figure 7 It is shown Figure 6 The first light emitting area EA1 (specifically, Figure 6 An enlarged plan view of area A3).

[0113] Apart from Figure 6 In addition, refer to Figure 7 , the display device 10 (for example, referring to Figure 1 ) may include a plurality of light emission areas EA1, EA2, and EA3 arranged or defined in the display area DA. The light emission areas EA1, EA2, and EA3 may include areas where light is emitted from the light emitting elements ED1, ED2, and ED3 to pass through the color filter layer CFL in the third direction DR3, wherein the pixel electrodes AE1, AE2, and AE3, the light emitting layers EL1, EL2, and EL3, and the common electrodes CE1, CE2, and CE3 are sequentially stacked in the light emitting elements ED1, ED2, and ED3. The light emission areas EA1, EA2, and EA3 may include a first light emission area EA1, a second light emission area EA2, and a third light emission area EA3 that are spaced apart from each other and emit light of the same color or different colors.

[0114] In an embodiment, the areas or sizes of the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3 may be the same as each other. In an embodiment, for example, in the display device 10, the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3 may have the same size, but are not limited thereto. In the display device 10, the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3 may have sizes different from each other. In an embodiment, for example, the size of the second light emission area EA2 may be larger than (or smaller than) the size of each of the first light emission area EA1 and the third light emission area EA3, and the size of the third light emission area EA3 may be larger than the size of the first light emission area EA1. The intensity of light emitted from the corresponding first light emission area EA1, second light emission area EA2, and third light emission area EA3 can be changed according to the size of the first light emission area EA1, second light emission area EA2, and third light emission area EA3, and the size of the first light emission area EA1, second light emission area EA2, and third light emission area EA3 can be adjusted so that the color of the picture displayed on the display device 10 can be controlled. Figure 6 In the embodiment of FIG. 1 , sizes of the first light emission area EA1 , the second light emission area EA2 , and the third light emission area EA3 are shown to be the same as one another, but are not limited thereto.

[0115] In an embodiment of the display device 10, one first light emission area EA1, one second light emission area EA2, and one third light emission area EA3 arranged adjacent to each other may form a pixel group. One pixel group may include the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3 emitting light of different colors, thereby representing a white grayscale, but the present disclosure is not limited thereto. The combination of the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3 constituting one pixel group may be variously modified according to the arrangement of the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3 and the color of the light emitted from the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3.

[0116] A plurality of openings OP1, OP2, and OP3 formed in the embankment structure BNS of the light emitting element layer EML may be defined along a boundary of the first embankment layer BN1. The first embankment layer BN1 and the second embankment layer BN2 of the embankment structure BNS may surround the first light emission region EA1, the second light emission region EA2, and the third light emission region EA3. Each of the openings OP1, OP2, and OP3 may correspond to one of the first light emission region EA1, the second light emission region EA2, and the third light emission region EA3.

[0117] The display device 10 may include a plurality of light emitting elements ED1, ED2, and ED3 respectively arranged in different first light emission areas EA1, second light emission areas EA2, and third light emission areas EA3. The light emitting elements ED1, ED2, and ED3 may include a first light emitting element ED1 arranged in the first light emission area EA1, a second light emitting element ED2 arranged in the second light emission area EA2, and a third light emitting element ED3 arranged in the third light emission area EA3.

[0118] The first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 may include pixel electrodes AE1, AE2, and AE3, respectively, light emitting layers EL1, EL2, and EL3, respectively, and common electrodes CE1, CE2, and CE3, respectively, and the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3, respectively arranged in different first light emission areas EA1, the second light emission areas EA2, and the third light emission areas EA3, may emit light of different colors according to the materials of the light emitting layers EL1, EL2, and EL3. In an embodiment, for example, the first light emitting element ED1 arranged in the first light emission area EA1 may emit a red first light having a peak wavelength in the range of 610 nanometers (nm) to 650 nm, the second light emitting element ED2 arranged in the second light emission area EA2 may emit a green second light having a peak wavelength in the range of 510 nm to 550 nm, and the third light emitting element ED3 arranged in the third light emission area EA3 may emit a blue third light having a peak wavelength in the range of 440 nm to 480 nm. The first light emission region EA1, the second light emission region EA2, and the third light emission region EA3 constituting one pixel group may include a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3 for emitting light of different colors to represent a white grayscale. Alternatively, since the light emitting layers EL1, EL2, and EL3 may include two or more materials for emitting light of different colors, one light emitting layer may emit mixed light. In an embodiment, for example, the light emitting layers EL1, EL2, and EL3 may include a material for emitting red light and a material for emitting green light together to emit yellow light, or may include all of a material for emitting red light, a material for emitting green light, and a material for emitting blue light to emit white light.

[0119] The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be arranged on the second through hole layer VIA2. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be arranged in a plurality of light emission areas EA1, EA2, and EA3, respectively. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may include a first pixel electrode AE1 arranged in the first light emission area EA1, a second pixel electrode AE2 arranged in the second light emission area EA2, and a third pixel electrode AE3 arranged in the third light emission area EA3. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be spaced apart from each other on the second through hole layer VIA2, respectively.

[0120] The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2. The edges of the separated first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be covered by the pixel defining layer PDL so that the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be insulated from each other. Each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 overlaps one of the openings OP1, OP2, and OP3.

[0121] The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may include a transparent electrode material and / or a conductive metal material. The conductive metal material may include at least one selected from silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), lanthanum (La), titanium (Ti), and titanium nitride (TiN). The transparent electrode material may include at least one selected from indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may have a multilayer structure of a transparent electrode material and a conductive metal material.

[0122] The pixel defining layer PDL may be disposed on the second through hole layer VIA2, the residual pattern RP, and the first, second, and third pixel electrodes AE1, AE2, and AE3. The pixel defining layer PDL may be completely disposed on the second through hole layer VIA2, and may cover the sides of the first, second, and third pixel electrodes AE1, AE2, and AE3, and the residual pattern RP to expose portions of the upper surfaces of the first, second, and third pixel electrodes AE1, AE2, and AE3. In an embodiment, for example, the pixel defining layer PDL may expose the first pixel electrode AE1 in the first light emission area EA1, and the first light emitting layer EL1 may be disposed directly on the first pixel electrode AE1.

[0123] The pixel defining layer PDL may include an inorganic insulating material. The pixel defining layer PDL may include at least one selected from silicon nitride layer, silicon oxynitride layer, silicon oxide layer, titanium oxide layer, aluminum oxide layer, tantalum oxide layer, hafnium oxide layer, zinc oxide layer and amorphous silicon layer, but is not limited thereto.

[0124] According to an embodiment, the pixel defining layer PDL is arranged on the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3, and may be spaced apart from the upper surfaces of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. The pixel defining layer PDL may not directly contact the upper surfaces of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3, while partially overlapping the upper surfaces of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 in the thickness direction DR3 of the substrate SUB, and the residual pattern RP may be arranged between the pixel defining layer PDL and the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. However, the pixel defining layer PDL may directly contact the side surfaces of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. The side surfaces of the pixel defining layer PDL may protrude toward the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3 than the side surfaces of the second bank layer BN2.

[0125] The residual pattern RP may be arranged on the edge of each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. Due to the residual pattern RP, the pixel defining layer PDL may not directly contact the upper surface of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. In the manufacturing process of the display device 10, a portion of the sacrificial layer arranged on the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be removed so that the residual pattern RP may be formed. The residual pattern RP may include a metal or oxide semiconductor material. In the accompanying drawings, the side of the residual pattern RP pointing to the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3 is only shown as being recessed than the side of the pixel defining layer PDL, but the present disclosure is not limited thereto. The side of the residual pattern RP may protrude toward the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3 than the side of the pixel defining layer PDL, or may be aligned with the side of the pixel defining layer PDL.

[0126] The light-emitting layers EL1, EL2, and EL3 may be arranged on the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. The light-emitting layers EL1, EL2, and EL3 may be organic light-emitting layers including or made of organic materials, and may be formed on the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 by a deposition process. The light-emitting layers EL1, EL2, and EL3 may have a multilayer structure, and each of a hole injection material, a hole transport material, a light-emitting material, an electron transport material, and / or an electron injection material may constitute a layer. When the thin film transistor TFT applies a predetermined voltage to the first pixel electrode AE1 of the first light-emitting element ED1, the second pixel electrode AE2 of the second light-emitting element ED2, and the third pixel electrode AE3 of the third light-emitting element ED3, and the common electrodes CE1, CE2, and CE3 of the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 receive a common voltage or a cathode voltage, holes and electrons may be injected and transported, and may be combined with each other in the light-emitting layers EL1, EL2, and EL3 to emit light.

[0127] The light-emitting layers EL1, EL2, and EL3 may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3, which are respectively arranged in different first light-emitting regions EA1, second light-emitting regions EA2, and third light-emitting regions EA3. The first light-emitting layer EL1 may be arranged on the first pixel electrode AE1 in the first light-emitting region EA1, the second light-emitting layer EL2 may be arranged on the second pixel electrode AE2 in the second light-emitting region EA2, and the third light-emitting layer EL3 may be arranged on the third pixel electrode AE3 in the third light-emitting region EA3. The plurality of light-emitting layers EL1, EL2, and EL3 may emit light of different colors, respectively, or one of the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 may emit mixed light. In an embodiment, the first light-emitting layer EL1 may emit red light, the second light-emitting layer EL2 may emit green light, and the third light-emitting layer EL3 may emit blue light. In another embodiment, the first light-emitting layer EL1 may emit yellow light, which is a mixed light of red light and green light, and the second light-emitting layer EL2 may emit blue light. In another embodiment, the first light emitting layer EL1 may emit white light which is a mixture of red light, green light, and blue light.

[0128] The first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 may be arranged on the upper surface of the pixel defining layer PDL. In an embodiment, the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 may be arranged in a space between the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 and the pixel defining layer PDL. In an embodiment, the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 may contact the pixel defining layer PDL, the residual pattern RP, and the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3.

[0129] The common electrodes CE1, CE2, and CE3 may be arranged on the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3. The common electrodes CE1, CE2, and CE3 may include a transparent conductive material so that light generated from the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 may be emitted. The common electrodes CE1, CE2, and CE3 may receive a common voltage or a low potential voltage. When the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 receive a voltage corresponding to the data voltage and the common electrodes CE1, CE2, and CE3 receive a low potential voltage, a potential difference may be formed between the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 and the common electrodes CE1, CE2, and CE3, whereby the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 may emit light.

[0130] The common electrodes CE1, CE2, and CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3 respectively arranged in different first light emission areas EA1, second light emission areas EA2, and third light emission areas EA3. The first common electrode CE1 may be arranged on the first light emitting layer EL1 in the first light emission area EA1, the second common electrode CE2 may be arranged on the second light emitting layer EL2 in the second light emission area EA2, and the third common electrode CE3 may be arranged on the third light emitting layer EL3 in the third light emission area EA3. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be spaced apart from each other. One end and the other end of the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may overlap with the openings OP1, OP2, and OP3.

[0131] The cover layers CAP1, CAP2, and CAP3 may be arranged on the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3. The cover layers CAP1, CAP2, and CAP3 may include an organic material or an inorganic insulating material to cover the pattern arranged in the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3. The cover layers CAP1, CAP2, and CAP3 may prevent the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 from being damaged by external air. In an embodiment, the cover layers CAP1, CAP2, and CAP3 may include an organic material or an inorganic insulating material such as a-NPD, NPB, TPD, m-MTDATA, Alq 3 and / or CuPc, or an inorganic material such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, LiF and / or silicon oxynitride.

[0132] The capping layers CAP1, CAP2, and CAP3 may include first, second, and third capping layers CAP1, CAP2, and CAP3 disposed in different first, second, and third light emission areas EA1, EA2, and EA3, respectively. The first, second, and third capping layers CAP1, CAP2, and CAP3 may be spaced apart from each other.

[0133] The display device 10 may include a plurality of embankment structures BNS arranged on the pixel defining layer PDL. The embankment structure BNS may have a structure in which embankment layers BN1 and BN2 including their respective materials different from each other are sequentially stacked, may include a plurality of openings OP1, OP2, and OP3 including a first light emission area EA1, a second light emission area EA2, and a third light emission area EA3, and may be arranged to overlap with a light blocking layer BM to be described later. The first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 of the display device 10 may be arranged to overlap with the openings OP1, OP2, and OP3 of the embankment structure BNS.

[0134] The bank structure BNS may include a first bank layer BN1 and a second bank layer BN2 sequentially stacked on the pixel defining layer PDL.

[0135] The first bank layer BN1 may be arranged on the pixel defining layer PDL. The side of the first bank layer BN1 may be recessed in a direction opposite to the direction pointing to the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3 than the side of the pixel defining layer PDL. The side of the first bank layer BN1 may be recessed in a direction opposite to the direction pointing to the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3 than the side of the second bank layer BN2 to be described later.

[0136] According to an embodiment, the first bank layer BN1 may include a metal material. In an embodiment, the first bank layer BN1 may include aluminum (Al) or an alloy of aluminum (Al).

[0137] According to an embodiment, the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be in direct contact with the side of the first bank layer BN1. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 of the different first light emitting elements ED1, the second light emitting elements ED2, and the third light emitting elements ED3 may be in direct contact with the first bank layer BN1, and the first bank layer BN1 may include a metal material so that the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be electrically connected to each other through the first bank layer BN1.

[0138] The first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 may be in direct contact with the side surface of the first bank layer BN1. The area in which the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 contact the side surface of the first bank layer BN1 may be larger than the area in which the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 contact the side surface of the first bank layer BN1. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be arranged on the side surface of the first bank layer BN1 to reach an area larger than the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 or at a higher position on the side surface of the first bank layer BN1. Since the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 of different first light emitting elements ED1, the second light emitting element ED2, and the third light emitting element ED3 are electrically connected to each other through the first bank layer BN1, it is expected that the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 contact the first bank layer BN1 with a larger area.

[0139] The second bank layer BN2 may be disposed on the first bank layer BN1. The second bank layer BN2 may include a tip that is a region protruding from the first bank layer BN1. A side of the second bank layer BN2 may protrude toward the first light emission region EA1, the second light emission region EA2, and the third light emission region EA3 from a side of the first bank layer BN1.

[0140] Since the side surface of the second bank layer BN2 has a shape protruding toward the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3 than the side surface of the first bank layer BN1, an undercut structure of the first bank layer BN1 can be formed under the tip of the second bank layer BN2.

[0141] In the display device 10 according to an embodiment, the embankment structure BNS may include a tip protruding toward the first light emission region EA1, the second light emission region EA2, and the third light emission region EA3, so that the first light emission layer EL1, the second light emission layer EL2, and the third light emission layer EL3, which are spaced apart from each other, and the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be formed by a deposition and etching process instead of a mask process. In an embodiment, for example, although the first light emission layer EL1 and the first common electrode CE1 of the first light emitting element ED1, the second light emission layer EL2 and the second common electrode CE2 of the second light emitting element ED2, and the third light emission layer EL3 and the third common electrode CE3 of the third light emitting element ED3 are formed by a deposition process without using a mask, the deposited material may be disconnected by the tip of the second embankment layer BN2 with the embankment structure BNS interposed therebetween, and is not connected between the first light emission region EA1, the second light emission region EA2, and the third light emission region EA3. After forming a material for forming a specific layer on the entire surface of the display device 10, different layers can be separately formed in different first light emission areas EA1, second light emission areas EA2, and third light emission areas EA3 by etching away the layer formed in the undesired area. In an embodiment of the display device 10, different first light emitting elements ED1, second light emitting elements ED2, and third light emitting elements ED3 can be formed for the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3, respectively, by deposition and etching processes without using a mask process, elements provided for the mask process in the display device 10 can be omitted, and the size of the non-display area NDA can be minimized. For example, in an embodiment, a spacer provided for the mask process can be omitted.

[0142] Since the first bank layer BN1 and the second bank layer BN2 include respective materials different from each other, the side shape of the bank structure BNS may have a structure formed due to a difference in etching rates in an etching process. According to an embodiment, the second bank layer BN2 may include a material having an etching rate slower than that of the first bank layer BN1, and the first bank layer BN1 may be further etched during the etching process so that the lower surface of the tip of the second bank layer BN2 may be exposed and an undercut may be formed under the second bank layer BN2. In an embodiment, the first bank layer BN1 may include aluminum (Al) or an alloy of aluminum (Al), and the second bank layer BN2 may include titanium (Ti) or an alloy of titanium (Ti).

[0143] The tip of the second bank layer BN2 may overlap the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3, the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3, or the pixel defining layer PDL in a thickness direction DR3 perpendicular to the substrate SUB. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be formed below the lower surface of the tip of the second bank layer BN2. One end and the other end of each of the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may overlap the second bank layer BN2 in the thickness direction DR3 of the substrate SUB. The maximum vertical distance from the substrate SUB to the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be shorter than the maximum vertical distance from the substrate SUB to the second bank layer BN2.

[0144] The display device 10 may include trace patterns TRP1, TRP2, and TRP3 that are traces of a deposition process on the bank structure BNS. The trace patterns TRP1, TRP2, and TRP3 may include organic patterns ELP1, ELP2, and ELP3, electrode patterns CEP1, CEP2, and CEP3, and cover patterns CPP1, CPP2, and CPP3, and may surround outer edges of the first, second, and third light emission areas EA1, EA2, and EA3 on the second bank layer BN2.

[0145] The trace patterns TRP1, TRP2, and TRP3 may be traces formed as the corresponding material layers are disconnected from the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3, the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3, and the cover layers CAP1, CAP2, and CAP3 in the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3 through the tip included in the embankment structure BNS. The first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3, the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3, and the cover layers CAP1, CAP2, and CAP3 may be formed in the openings OP1, OP2, and OP3, and the organic patterns ELP1, ELP2, and ELP3 may be disconnected from the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 through the tip of the embankment structure BNS. The electrode patterns CEP1, CEP2, and CEP3 may be disconnected from the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 through the tip of the embankment structure BNS. Likewise, the capping patterns CPP1, CPP2, and CPP3 may be disconnected from the capping layers CAP1, CAP2, and CAP3 by the tip of the bank structure BNS. The trace patterns TRP1, TRP2, and TRP3 may be formed by patterning near each of the first, second, and third light emission regions EA1, EA2, and EA3.

[0146] The display device 10 may include a plurality of organic patterns ELP1, ELP2, and ELP3 including the same material as the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3, arranged on the bank structure BNS. The first organic pattern ELP1 may include the same material as the first light emitting layer EL1 of the first light emitting element ED1. The second organic pattern ELP2 may include the same material as the second light emitting layer EL2 of the second light emitting element ED2, and the third organic pattern ELP3 may include the same material as the third light emitting layer EL3 of the third light emitting element ED3. Each of the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 may be formed in a process of forming the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 including the same material. The first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 may be arranged adjacent to the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3, where the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 are arranged, respectively.

[0147] The display device 10 according to the embodiment may include a plurality of electrode patterns CEP1, CEP2, and CEP3 including the same material as the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 and arranged on the embankment structure BNS. The first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be directly arranged on the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, respectively. The arrangement relationship of the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 to the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 may be the same as the arrangement relationship of the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 of the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 to the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3.

[0148] The display device 10 may include cover patterns CPP1, CPP2, and CPP3 disposed above the embankment structure BNS. The cover patterns CPP1, CPP2, and CPP3 may be disposed directly on the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3, respectively. The arrangement relationship of the cover patterns CPP1, CPP2, and CPP3 to the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be the same as the arrangement relationship of the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 to the cover layers CAP1, CAP2, and CAP3.

[0149] The thin film encapsulation layer TFEL may be arranged on the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 and the embankment structure BNS, and may cover the plurality of light emitting elements ED1, ED2, and ED3 and the embankment structure BNS. In addition, the thin film encapsulation layer TFEL may be arranged in the non-display area NDA (for example, referring to Figure 1 ) and the display area DA (for example, referring to Figure 1 ). The thin film encapsulation layer TFEL may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one organic film to protect the light emitting element layer EML from particles such as dust.

[0150] In an implementation, the thin film encapsulation layer TFEL may include a first inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and a second inorganic encapsulation layer TFE3, which are sequentially stacked.

[0151] Each of the first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 may include one or more inorganic insulating materials. The inorganic insulating material may include at least one selected from silicon oxide, silicon nitride and silicon oxynitride, and for example, may be aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride. Each of the first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 may be a single layer, or may have a multilayer structure in which two or more of the aforementioned inorganic materials are stacked.

[0152] The organic encapsulation layer TFE2 may include a polymer material. The polymer material may include an acrylic resin, an epoxy resin, a polyimide, or polyethylene. In an embodiment, for example, the organic encapsulation layer TFE2 may include an acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.). The organic encapsulation layer TFE2 may be formed by curing a monomer or coating a polymer.

[0153] The first inorganic encapsulation layer TFE1 may include a first inorganic layer arranged in the display area DA, and the first inorganic layer may be arranged on the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 and the embankment structure BNS. The first inorganic encapsulation layer TFE1 may include a plurality of sub-inorganic layers TL1, TL2, and TL3 arranged to correspond to different first light emission areas EA1, second light emission areas EA2, and third light emission areas EA3, respectively. The sub-inorganic layers TL1, TL2, and TL3 may include an inorganic insulating material covering the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3. The first sub-inorganic layer TL1, the second sub-inorganic layer TL2, and the third sub-inorganic layer TL3 may prevent the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 from being damaged by external air.

[0154] The first inorganic encapsulation layer TFE1 may be formed by a chemical vapor deposition (CVD) method, and thus may be formed along a step difference of a deposition layer. In an embodiment, for example, the first sub-inorganic layer TL1, the second sub-inorganic layer TL2, and the third sub-inorganic layer TL3 may form a thin film even under the tip of the bank structure BNS. The first sub-inorganic layer TL1, the second sub-inorganic layer TL2, and the third sub-inorganic layer TL3 may be arranged along the upper surface, the side surface, and the lower surface of the second bank layer BN2, the side surface of the first bank layer BN1, and the upper surface of the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3. The first sub-inorganic layer TL1, the second sub-inorganic layer TL2, and the third sub-inorganic layer TL3 may be in contact with the lower surface of the second bank layer BN2 to prevent moisture penetration from the external air.

[0155] The first sub-inorganic layer TL1 does not overlap with the second light emission region EA2 and the third light emission region EA3, and may be arranged only on the first light emission region EA1 and the dike structure BNS near the first light emission region EA1. The second sub-inorganic layer TL2 does not overlap with the first light emission region EA1 and the third light emission region EA3, and may be arranged only on the dike structure BNS near the second light emission region EA2 and the second light emission region EA2. The third sub-inorganic layer TL3 does not overlap with the first light emission region EA1 and the second light emission region EA2, and may be arranged only on the third light emission region EA3 and the dike structure BNS near the third light emission region EA3.

[0156] The first sub-inorganic layer TL1 may be formed after forming the first common electrode CE1, the second sub-inorganic layer TL2 may be formed after forming the second common electrode CE2, and the third sub-inorganic layer TL3 may be formed after forming the third common electrode CE3. The first sub-inorganic layer TL1, the second sub-inorganic layer TL2, and the third sub-inorganic layer TL3 may be arranged to be spaced apart from each other on the bank structure BNS. The first sub-inorganic layer TL1, the second sub-inorganic layer TL2, and the third sub-inorganic layer TL3 may include the same material or different materials.

[0157] The organic encapsulating layer TFE2 is disposed on the second bank layer BN2 and the first inorganic encapsulating layer TFE1. Portions of the organic encapsulating layer TFE2 may contact the second bank layer BN2 between separate sub-inorganic layers of the first inorganic layer of the first inorganic encapsulating layer TFE1.

[0158] The second inorganic encapsulation layer TFE 3 may be disposed on the organic encapsulation layer TFE 2. The second inorganic encapsulation layer TFE 3 may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0159] Figures 8 to 10 is an enlarged cross-sectional view illustrating a first light emission area EA1 of a display device according to other embodiments.

[0160] In addition to the absence of the trace patterns TRP1, TRP2 and TRP3 on the second bank layer BN2, Figure 8 The area A3a of the display device shown in FIG. Figure 7 The area A3 of the display device shown in FIG. 1 is substantially the same. In an embodiment, as shown in FIG. Figure 8 As shown in FIG, after forming the first inorganic sublayer TL1 on the first light emission area EA1, the trace pattern TRP1 between the first inorganic sublayer TL1 and the second bank layer BN2 may be removed by an etching process. An organic encapsulation layer TFE2a may be disposed in the space between the first inorganic sublayer TL1 and the second bank layer BN2.

[0161] In addition to the third inorganic encapsulation layer TFE4 being arranged between the first sub-inorganic layer TL1 and the organic encapsulation layer TFE2b, and the first filling material FIL1 being arranged between the first sub-inorganic layer TL1 and the third inorganic encapsulation layer TFE4, Fig. 9 The area A3b of the display device shown in FIG. Figure 7 The area A3 of the display device shown in FIG. 1 is substantially the same. In an embodiment, as shown in FIG. Fig. 9 As shown in , the third inorganic encapsulation layer TFE4 can prevent the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 from being damaged due to the penetration of particles such as etchants into the first sub-inorganic layer TL1, the second sub-inorganic layer TL2, and the third sub-inorganic layer TL3 separated by the first inorganic encapsulation layer TFE1. The third inorganic encapsulation layer TFE4 may be arranged on the entire surface of the substrate SUB. The third inorganic encapsulation layer TFE4 may include an inorganic material, such as the same material as the first inorganic encapsulation layer TFE1 or the second inorganic encapsulation layer TFE3.

[0162] The first filling material FIL1, the second filling material and the third filling material may be arranged between the first sub-inorganic layer TL1, the second sub-inorganic layer TL2 and the third sub-inorganic layer TL3 and the third inorganic encapsulation layer TFE4 on the first light-emitting element ED1, the second light-emitting element ED2 and the third light-emitting element ED3. The first filling material FIL1, the second filling material and the third filling material may be sealed by the first sub-inorganic layer TL1, the second sub-inorganic layer TL2 and the third sub-inorganic layer TL3 of the first inorganic encapsulation layer TFE1 and the third inorganic encapsulation layer TFE4. The first filling material FIL1, the second filling material and the third filling material may correspond to the first light emission area EA1, the second light emission area EA2 and the third light emission area EA3, respectively, and may be spaced apart from each other. The first filling material FIL1, the second filling material and the third filling material may include an organic material, and the organic material may be a photoresist used in a photolithography process.

[0163] Except that there are no trace patterns TRP1, TRP2, and TRP3 on the second bank layer BN2 and the third inorganic encapsulation layer TFE4a is disposed between the first sub-inorganic layer TL1 and the organic encapsulation layer TFE2c, Fig.10 The area A3c of the display device shown in FIG. Figure 7 The area A3 of the display device shown in FIG. 1 is substantially the same. In an embodiment, as shown in FIG. Fig. 9 The third inorganic encapsulation layer TFE4a may prevent the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 from being damaged, and may include an inorganic material. In an embodiment, the third inorganic encapsulation layer TFE4a may be arranged in a space between the first sub-inorganic layer TL1 and the second bank layer BN2, and may be arranged on the entire surface of the substrate SUB.

[0164] Return to reference Figure 6 , the light blocking layer BM may be arranged on the thin film encapsulation layer TFEL. The light blocking layer BM may include a plurality of holes OPT1, OPT2, and OPT3 arranged to overlap with the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3. In an embodiment, for example, the first hole OPT1 may be arranged to overlap with the first light emission area EA1. The second hole OPT2 may be arranged to overlap with the second light emission area EA2, and the third hole OPT3 may be arranged to overlap with the third light emission area EA3. The area or size of each of the first to third holes OPT1 to OPT3 may be greater than the area or size of a corresponding one of the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3. Since the first hole OPT1, the second hole OPT2 and the third hole OPT3 of the light blocking layer BM are formed to be larger than the first light emission area EA1, the second light emission area EA2 and the third light emission area EA3, the light emitted from the first light emission area EA1, the second light emission area EA2 and the third light emission area EA3 may be visible to the user and the front surface of the display device 10.

[0165] The light blocking layer BM may include a light absorbing material. In an embodiment, for example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one selected from lactam black, perylene black, and aniline black, but is not limited thereto. The light blocking layer BM may prevent visible light from penetrating between the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3, thereby improving the color reproduction rate of the display device 10.

[0166] The display device 10 may include a plurality of color filters CF1, CF2, and CF3 arranged on the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3. The plurality of color filters CF1, CF2, and CF3 may be arranged to correspond to the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3, respectively. In an embodiment, for example, the color filters CF1, CF2, and CF3 may be arranged on a light blocking layer BM including a plurality of holes OPT1, OPT2, and OPT3 arranged to correspond to the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3. The holes OPT1, OPT2, and OPT3 of the light blocking layer BM may be formed to overlap with the openings OP1, OP2, and OP3 of the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3 or the embankment structure BNS, and may form a light output area where light emitted from the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3 is output. Each of the color filters CF1 , CF2 , and CF3 may have an area greater than that of the corresponding hole of the light blocking layer BM, and each of the color filters CF1 , CF2 , and CF3 may completely cover the light output region formed by the hole.

[0167] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 arranged to correspond to different first light emission areas EA1, second light emission areas EA2, and third light emission areas EA3, respectively. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a colorant (such as a dye or a pigment) for absorbing light of another wavelength band other than the light of a specific wavelength band, and may be arranged to correspond to the color of the light emitted from the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3. In an embodiment, for example, the first color filter CF1 may be a red color filter arranged to overlap with the first light emission area EA1, wherein the red color filter transmits only the red first light. The second color filter CF2 may be a green color filter arranged to overlap with the second light emission area EA2, wherein the green color filter transmits only the green second light. The third color filter CF3 may be a blue color filter arranged to overlap with the third light emission area EA3, wherein the blue color filter transmits only the blue third light.

[0168] A plurality of color filters CF1, CF2, and CF3 may be spaced apart from other adjacent first color filters CF1, second color filters CF2, and third color filters CF3 on the light-blocking layer BM (e.g., each of the plurality of color filters CF1, CF2, and CF3 may be spaced apart from other adjacent color filters on the light-blocking layer BM). Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 covers a corresponding one of the first hole OPT1, the second hole OPT2, and the third hole OPT3 of the light-blocking layer BM, and has an area larger than the area of ​​the hole. Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may have an area spaced apart from other color filters on the light-blocking layer BM, but the present disclosure is not limited thereto. A plurality of color filters CF1, CF2, and CF3 may be arranged to partially overlap with other adjacent color filters CF1, CF2, and CF3 (e.g., each of the plurality of color filters CF1, CF2, and CF3 may be arranged to partially overlap with other adjacent color filters). Different first color filters CF1, second color filters CF2, and third color filters CF3 may include portions that do not overlap with the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3, and may overlap with each other on the light blocking layer BM, which will be described later. When the first color filter CF1, the second color filter CF2, and the third color filter CF3 overlap with each other, the display device 10 can reduce the intensity of reflected light due to external light. In addition, the display device 10 can control the color perception of reflected light due to external light by adjusting the layout, shape, area, and similar features of the first color filter CF1, the second color filter CF2, and the third color filter CF3 in a plan view.

[0169] An overcoat layer OC may be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3 to flatten the upper ends of the first color filter CF1, the second color filter CF2, and the third color filter CF3. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. In an embodiment, for example, the overcoat layer OC may include a colorless light-transmitting organic material such as an acrylic resin.

[0170] Will refer to Figures 11 to 13 The non-display area NDA is described in detail.

[0171] Fig.11 is shown as a display device 10 (for example, referring to Figure 2 ) is an enlarged view of an edge area of ​​the display device 10, which is a boundary between the display area DA and the non-display area NDA. Fig.11 It is shown Figure 2 is an enlarged plan view of area A2, and Fig.12 is shown along Fig.11 A cross-sectional view of an example of a display device taken along line II-II'. Fig.13 It is shown Fig.12 An enlarged cross-sectional view of area A4.

[0172] Reference Figures 11 to 13 In an embodiment of the display device 10, the light emitting element ED (for example, referring to Figure 6 ) may be arranged in the first light emission area EA1, the second light emission area EA2, and the third light emission area EA3 of the display area DA, and the non-display area NDA may be arranged near the display area DA. A second dam DAM2 surrounding the display area DA may be arranged in the non-display area NDA, a first dam DAM1 surrounding the outer side of the second dam DAM2 may be arranged, and a crack dam CRD may be arranged outside the first dam DAM1.

[0173] In an embodiment, if Fig.12 As shown in FIG, the thin film encapsulation layer TFEL may overlap the light emitting element layer EML, the second dam DAM2 and the first dam DAM1 in the thickness direction DR3 of the substrate SUB. Although not shown in the drawings, in another embodiment, the thin film encapsulation layer TFEL may also overlap the crack dam CRD.

[0174] The first dam DAM1 may be formed to prevent the organic material from overflowing into the non-display area NDA (eg, an area between the first dam DAM1 and the edge EG in the non-display area NDA) during a manufacturing process of the organic material. Fig.13 As shown in FIG. 1 , due to the first dam DAM1 in the non-display area NDA, the organic encapsulation layer TFE2 may not flow to the edge EG.

[0175] The first dam DAM1 may overlap the non-display area NDA and may be positioned to surround the display area DA. The first dam DAM1 may be disposed between the second interlayer insulating layer ILD2 and the second inorganic encapsulation layer TFE3.

[0176] The first dam DAM1 may include a first sub-dam SD11 disposed on the second interlayer insulating layer ILD2 and a second sub-dam SD12 disposed on the first sub-dam SD11. In an embodiment, the first dam DAM1 may further include a third sub-dam SD13 disposed on the second sub-dam SD12. In an embodiment, the third sub-dam SD13 may be omitted. The first sub-dam SD11 may include a material that is the same as a material of a corresponding one of the first through-hole layer VIA1, the second through-hole layer VIA2, and the pixel defining layer PDL. The second sub-dam SD12 may include a material that is the same as a material of a corresponding one of the first through-hole layer VIA1, the second through-hole layer VIA2, and the pixel defining layer PDL. The third sub-dam SD13 may include a material that is the same as a material of a corresponding one of the first through-hole layer VIA1, the second through-hole layer VIA2, and the pixel defining layer PDL. In an embodiment, for example, the first sub-dam SD11 may include a material that is the same as a material of the first through-hole layer VIA1, the second sub-dam SD12 may include a material that is the same as a material of the second through-hole layer VIA2, and the third sub-dam SD13 may include a material that is the same as a material of the pixel defining layer PDL.

[0177] The second dam DAM2 may be positioned at an inner side relative to the first dam DAM1, and thus positioned between the first dam DAM1 and the first, second, and third light emitting elements ED1, ED2, and ED3. The second dam DAM2 may include a first sub-dam SD21 disposed on the second interlayer insulating layer ILD2 and a second sub-dam SD22 disposed on the first sub-dam SD21. The first sub-dam SD21 may include a material that is the same as a material of a corresponding one of the first through-hole layer VIA1, the second through-hole layer VIA2, and the pixel defining layer PDL. The second sub-dam SD22 may include a material that is the same as a material of a corresponding one of the first through-hole layer VIA1, the second through-hole layer VIA2, and the pixel defining layer PDL. In an embodiment, for example, the first sub-dam SD21 may include a material that is the same as a material of the first through-hole layer VIA1 or the second through-hole layer VIA2, and the second sub-dam SD22 may include a material that is the same as a material of the pixel defining layer PDL. The total thickness of the second dam DAM2 may be the same as or different from the total thickness of the first dam DAM1.

[0178] The first inorganic encapsulation layer TFE1 (for example, see Figure 6 ) may include a first inorganic layer arranged in the display area DA and a second inorganic layer arranged in the non-display area NDA. The first inorganic layer and the second inorganic layer may be spaced apart from each other. The second inorganic layer may be formed of a single or multiple sub-inorganic layers arranged on the first dam DAM1 and / or the second dam DAM2.

[0179] Reference Fig.13, the second inorganic layer of the first inorganic encapsulation layer TFE1 may include a fourth sub-inorganic layer TL4, and the fourth sub-inorganic layer TL4 may be disposed on the first dam DAM1. The fourth sub-inorganic layer TL4 may be disposed between the first dam DAM1 and the second inorganic encapsulation layer TFE3. The fourth sub-inorganic layer TL4 may be formed on the first sub-inorganic layer TL1 (for example, referring to Figure 6 ), the second inorganic sub-layer TL2 (for example, refer to Figure 6 ) and the third inorganic sub-layer TL3 (for example, refer to Figure 6 ) is formed synchronously with one of the first sub-inorganic layer TL1, the second sub-inorganic layer TL2, and the third sub-inorganic layer TL3. That is, the fourth sub-inorganic layer TL4 may include the same material as one of the first sub-inorganic layer TL1, the second sub-inorganic layer TL2, and the third sub-inorganic layer TL3, and may be spaced apart from the first sub-inorganic layer TL1, the second sub-inorganic layer TL2, and the third sub-inorganic layer TL3.

[0180] The first dam DAM1 may include a first side directed toward the display area DA and a second side opposite to the first side. The first side of the first dam DAM1 may have an area that does not overlap with the fourth sub-inorganic layer TL4 of the first inorganic encapsulation layer TFE1 in the thickness direction DR3 of the substrate SUB. In the case where the first inorganic encapsulation layer TFE1 (the fourth sub-inorganic layer TL4) spaced apart from the display area DA and the second dam DAM2 is arranged on the first dam DAM1, the filling amount of the organic encapsulation layer TFE2 may be much increased than the case where the first inorganic encapsulation layer TFE1 is formed on the entire surface of the substrate SUB, and the overflow of the organic encapsulation layer TFE2 may be more effectively prevented.

[0181] The first side of the first dam DAM1 may overlap with the organic encapsulation layer TFE2 in the thickness direction DR3 of the substrate SUB. In an embodiment, the first side of the first dam DAM1 may contact the organic encapsulation layer TFE2. The second side of the first dam DAM1 may not overlap with the organic encapsulation layer TFE2 in the thickness direction DR3 of the substrate SUB. In an embodiment, the second side of the first dam DAM1 may contact the second inorganic encapsulation layer TFE3. The first side and the second side of the first sub-dam SD11 of the first dam DAM1 may not overlap with the first inorganic encapsulation layer TFE1.

[0182] The second dam DAM2 may include a first side directed toward the display area DA and a second side opposite to the first side. The first and second sides of the second dam DAM2 may overlap with the organic encapsulation layer TFE2 in the thickness direction DR3 of the substrate SUB. In an embodiment, the first and second sides of the second dam DAM2 may contact with the organic encapsulation layer TFE2.

[0183] The second inorganic layer of the first inorganic encapsulation layer TFE1 may include a plurality of sub-inorganic layers (eg, Fig.14 The inorganic sub-layers TL4a, TL5a and TL6a or Fig.15 The thicknesses of the sub-inorganic layers may be the same as or different from each other. In an embodiment, a plurality of sub-inorganic layers may be sequentially stacked on the first dam DAM1. In another embodiment, the sub-inorganic layers may be respectively arranged in the first dam DAM1 and the second dam DAM2, and may be spaced apart from each other.

[0184] Fig.14 and Fig.15 is an enlarged cross-sectional view showing a boundary (specifically, areas A4a and A4b) between a display area and a non-display area of ​​a display device according to another embodiment.

[0185] Reference Fig.14 In an embodiment, the second inorganic layer of the first inorganic encapsulation layer TFE1 may include a fourth sub-inorganic layer TL4a and a fifth sub-inorganic layer TL5a disposed on the first dam DAM1 and a sixth sub-inorganic layer TL6a disposed on the second dam DAM2. The number of sub-inorganic layers disposed on the first dam DAM1 may be different from the number of sub-inorganic layers disposed on the second dam DAM2. The fourth sub-inorganic layer TL4a and the sixth sub-inorganic layer TL6a may be spaced apart from each other.

[0186] The fifth sub-inorganic layer TL5a may be disposed on the fourth sub-inorganic layer TL4a. Each of the fourth sub-inorganic layer TL4a and the fifth sub-inorganic layer TL5a may include a material that is the same as a material of a corresponding one of the first sub-inorganic layer TL1, the second sub-inorganic layer TL2, and the third sub-inorganic layer TL3 of the display area DA. In an embodiment, for example, the fourth sub-inorganic layer TL4a may include a material that is the same as a material of the first sub-inorganic layer TL1, and the fifth sub-inorganic layer TL5a may include a material that is the same as a material of the second sub-inorganic layer TL2. The sixth sub-inorganic layer TL6a may include a material that is the same as a material of any one of the first sub-inorganic layer TL1, the second sub-inorganic layer TL2, and the third sub-inorganic layer TL3.

[0187] The first and second sides of the second dam DAM2 may have a region not overlapping the sixth sub-inorganic layer TL6a in the thickness direction DR3 of the substrate SUB. The first and second sides of the first sub-dam SD21 of the second dam DAM2 may not overlap the sixth sub-inorganic layer TL6a.

[0188] Except that the second dam DAM2 is omitted and three sub-inorganic layers TL4b, TL5b and TL6b are sequentially stacked on the first dam DAM1, Fig.15 The embodiment shown in Fig.13 The number and total thickness of the sub-inorganic layers of the first inorganic encapsulation layer TFE1 disposed on the dam may be increased, and at the same time, the non-display area NDA may be reduced.

[0189] In an embodiment, if Fig.15 As shown in , the sub-inorganic layers TL4b, TL5b, and TL6b sequentially stacked on the first dam DAM1 may each include a material that is the same as a material of a corresponding one of the first sub-inorganic layer TL1, the second sub-inorganic layer TL2, and the third sub-inorganic layer TL3 of the display area DA. In an embodiment, for example, the fourth sub-inorganic layer TL4b may include a material that is the same as a material of the first sub-inorganic layer TL1, the fifth sub-inorganic layer TL5b may include a material that is the same as a material of the second sub-inorganic layer TL2, and the sixth sub-inorganic layer TL6b may include a material that is the same as a material of the third sub-inorganic layer TL3.

[0190] The crack dam CRD may be arranged outside the first dam DAM1. The crack dam CRD may be arranged close to the display panel 100 (eg, referring to Figure 1 ) edge EG. The crack dam CRD may be used to prevent the display device 10 (for example, referring to Figure 1 The crack dam CRD may be disposed along the left edge, the upper edge, and the right edge of the display panel 100. The crack dam CRD may not be disposed at the lower edge of the display panel 100. The crack dam CRD may be an outermost structure disposed at the outermost portion of the left side, the upper side, and the right side of the display panel 100.

[0191] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the content of the present invention to those skilled in the art.

[0192] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined in the following claims.

Claims

1. A display device, comprising: A substrate, wherein a display area and a non-display area arranged near the display area are defined on the substrate; a first bank layer, the first bank layer being arranged on the substrate, wherein the first bank layer defines a plurality of openings in the display area; a second bank layer, the second bank layer being disposed on the first bank layer, wherein the second bank layer includes a side surface protruding from a side surface of the first bank layer; a plurality of light emitting elements arranged on the substrate and overlapping the plurality of openings; a first inorganic encapsulation layer, the first inorganic encapsulation layer being arranged on the plurality of light emitting elements; an organic encapsulation layer, the organic encapsulation layer being arranged on the first inorganic encapsulation layer and the second bank layer; a second inorganic encapsulation layer, the second inorganic encapsulation layer being arranged on the organic encapsulation layer; as well as a first dam, the first dam being arranged between the substrate and the second inorganic encapsulation layer in the non-display area, Wherein, a region of the first side of the first dam does not overlap with the first inorganic encapsulation layer in a thickness direction of the substrate.

2. The display device according to claim 1, wherein: The first side of the first dam is directed toward the display area, and The organic encapsulating layer overlaps the first side of the first dam in the thickness direction of the substrate.

3. The display device according to claim 1, wherein: The first side of the first dam contacts the organic encapsulation layer, and A second side of the first dam opposite to the first side of the first dam contacts the second inorganic encapsulating layer.

4. The display device according to claim 1, wherein: The first inorganic encapsulating layer includes a first inorganic layer disposed on the plurality of light emitting elements and a second inorganic layer disposed on the first dam and spaced apart from the first inorganic layer.

5. The display device according to claim 4, wherein: The first inorganic layer includes a plurality of sub-inorganic layers arranged on each of the plurality of light emitting elements, and The plurality of sub-inorganic layers of the first inorganic layer are spaced apart from each other.

6. The display device according to claim 5, wherein: The second inorganic layer includes a material that is the same as a material of a corresponding one of the plurality of sub-inorganic layers of the first inorganic layer.

7. The display device according to claim 4, wherein: The second inorganic layer includes a plurality of sub-inorganic layers sequentially stacked on the first dam.

8. The display device according to claim 4, further comprising: A second dam is provided between the first dam and the plurality of light emitting elements.

9. The display device according to claim 8, wherein: The second inorganic layer includes a first sub-inorganic layer disposed on the first dam and a second sub-inorganic layer disposed on the second dam, and The first sub-inorganic layer and the second sub-inorganic layer are spaced apart from each other.

10. The display device according to claim 9, wherein: The second inorganic layer further includes a third sub-inorganic layer disposed on the first sub-inorganic layer.

11. The display device according to claim 1, wherein: Each of the plurality of light emitting elements comprises: a pixel electrode disposed on the substrate and overlapping a corresponding opening among the plurality of openings; a light-emitting layer, the light-emitting layer being arranged on the pixel electrode; and a common electrode disposed on the light emitting layer, and One end of the common electrode and the other end of the common electrode opposite to the one end of the common electrode overlap with the corresponding opening.

12. The display device according to claim 11, wherein: The common electrode contacts the first bank layer.

13. The display device according to claim 11, wherein: The first inorganic encapsulation layer includes a plurality of sub-inorganic layers arranged on the plurality of light emitting elements overlapping the plurality of openings and on the second bank layer near the plurality of openings.

14. The display device according to claim 1, further comprising: A third inorganic encapsulation layer is disposed between the first inorganic encapsulation layer and the organic encapsulation layer.

15. A display device, comprising: A substrate, wherein a display area and a non-display area arranged near the display area are defined on the substrate; a first bank layer, the first bank layer being arranged on the substrate, wherein the first bank layer defines a plurality of openings in the display area; a second bank layer, the second bank layer being disposed on the first bank layer, wherein the second bank layer includes a side surface protruding from a side surface of the first bank layer; a first light emitting element disposed on the substrate and overlapping a first opening of the plurality of openings; a second light emitting element disposed on the substrate and overlapping a second opening of the plurality of openings, the second opening being spaced apart from the first opening; a first dam, the first dam being arranged on the substrate in the non-display area; a first inorganic encapsulation layer, the first inorganic encapsulation layer comprising a first sub-inorganic layer disposed on the first light-emitting element, a second sub-inorganic layer disposed on the second light-emitting element, and a third sub-inorganic layer disposed on the first dam; an organic encapsulation layer, the organic encapsulation layer being arranged on the first inorganic encapsulation layer; as well as a second inorganic encapsulation layer, the second inorganic encapsulation layer being arranged on the organic encapsulation layer, The first sub-inorganic layer, the second sub-inorganic layer, and the third sub-inorganic layer of the first inorganic encapsulation layer are spaced apart from each other.

16. The display device according to claim 15, wherein: The first sub-inorganic layer and the second sub-inorganic layer are in contact with a lower surface of the second bank layer.

17. The display device according to claim 15, wherein: A first side of the first dam contacts the organic encapsulation layer, and A second side of the first dam opposite to the first side of the first dam contacts the second inorganic encapsulating layer.

18. A display device comprising: A substrate, wherein a display area and a non-display area arranged near the display area are defined on the substrate; a plurality of light emitting elements, the plurality of light emitting elements being arranged on the substrate in the display area; a first dam, the first dam being arranged on the substrate in the non-display area; a second dam disposed on the substrate in the non-display area and positioned between the plurality of light emitting elements and the first dam; a first inorganic encapsulation layer, the first inorganic encapsulation layer comprising a first sub-inorganic layer disposed on the first dam, a second sub-inorganic layer disposed on the first sub-inorganic layer, and a third sub-inorganic layer disposed on the second dam; an organic encapsulation layer, the organic encapsulation layer being arranged on the plurality of light emitting elements and the third inorganic sub-layer; as well as a second inorganic encapsulation layer, the second inorganic encapsulation layer being arranged on the organic encapsulation layer and the first dam, The first inorganic sub-layer and the third inorganic sub-layer are spaced apart from each other.

19. The display device according to claim 18, wherein: The first inorganic encapsulation layer includes a fourth sub-inorganic layer disposed on a first light-emitting element among the plurality of light-emitting elements, and a fifth sub-inorganic layer disposed on a second light-emitting element among the plurality of light-emitting elements and spaced apart from the fourth sub-inorganic layer, The first sub-inorganic layer includes the same material as that of the fourth sub-inorganic layer, and The second sub-inorganic layer includes the same material as that of the fifth sub-inorganic layer.

20. The display device according to claim 18, wherein: A first side of the first dam overlaps with the organic encapsulation layer, A second side of the first dam opposite to the first side of the first dam does not overlap with the organic encapsulation layer, and A first side of the second dam and a second side of the second dam opposite to the first side of the second dam overlap the organic encapsulating layer.

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