Array substrate, display panel and display device

Abstract

The embodiment of the invention provides an array substrate, a display panel and a display device, is applied to the field of display and is used for improving the light transmittance of the display device. The array substrate comprises a plurality of sub-pixel areas, and pixel driving circuits are arranged in the sub-pixel areas. The array substrate comprises a substrate, a second gate metal layer and a first source-drain metal layer. The second gate metal layer is arranged on one side of the substrate, the second gate metal layer comprises a plurality of conductive connecting lines, and each conductive connecting line comprises a plurality of first conductive patterns and a plurality of second conductive patterns which are alternately connected in the first direction. The first source-drain metal layer is arranged on the side, away from the substrate, of the second gate metal layer, the first source-drain metal layer comprises a plurality of first voltage signal lines, and each first voltage signal line comprises a plurality of first parts and a plurality of second parts which are alternately connected in the first direction. The second conductive pattern is overlapped with the first part, and the conductive connecting line and the first voltage signal line transmit the same voltage signal.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] At present, OLED (Organic Light-Emitting Diode) display devices are widely used because of their self-luminescence, fast response, wide viewing angle and the ability to be manufactured on flexible substrates. OLED display devices include multiple sub-pixels, each of which includes a pixel driving circuit and a light-emitting device. The light-emitting device is driven by the pixel driving circuit to emit light, thereby achieving display. Summary of the invention

[0003] The purpose of the embodiments of the present disclosure is to provide an array substrate, a display panel and a display device, which can increase the light transmittance used for the display panel and improve the image quality of the display product.

[0004] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0005] The first aspect of the present disclosure provides an array substrate. The array substrate includes a plurality of sub-pixel regions arranged in an array, a row of sub-pixel regions are arranged along a first direction, a column of sub-pixel regions are arranged along a second direction, and the first direction and the second direction intersect; a pixel driving circuit is arranged in the sub-pixel region, and the pixel driving circuit includes a capacitor. The array substrate includes a substrate substrate, a second gate metal layer and a first source-drain metal layer. Wherein, the second gate metal layer is arranged on one side of the substrate substrate, the second gate metal layer includes a plurality of conductive connection lines extending along the first direction, the conductive connection lines include a plurality of first conductive patterns and a plurality of second conductive patterns alternately connected along the first direction, and the first conductive pattern is the first electrode plate of the capacitor. The first source-drain metal layer is arranged on the side of the second gate metal layer away from the substrate substrate, the first source-drain metal layer includes a plurality of first voltage signal lines extending along the first direction, and the first voltage signal line includes a plurality of first parts and a plurality of second parts alternately connected along the first direction. Wherein, the second conductive pattern overlaps with the first part, and the conductive connection line is connected to the first voltage signal line.

[0006] In the array substrate provided by some embodiments of the present disclosure, since the second conductive pattern is located in the second gate metal layer and the first part is located in the first source and drain metal layer, by arranging the second conductive pattern to overlap with the first part, the space utilization rate of the array substrate can be improved, thereby increasing the transmittance of light and enhancing the display effect.

[0007] In some embodiments, the first portion includes a first sub-portion and a second sub-portion, the first sub-portion has no overlap with the orthographic projection of the first conductive pattern on the base substrate, the orthographic projection of the second sub-portion on the base substrate is located within the orthographic projection of the first conductive pattern on the base substrate; the orthographic projection of the first sub-portion on the base substrate coincides with the orthographic projection of the second conductive pattern on the base substrate.

[0008] In some embodiments, the second portion overlaps with the first conductive pattern, and the second portion is electrically connected to the first conductive pattern through at least two first vias.

[0009] In some embodiments, the array substrate also includes: a light-shielding layer arranged between the base substrate and the second gate metal layer, the light-shielding layer including a plurality of light-shielding metal traces extending along the first direction; the light-shielding metal traces including a plurality of light-shielding patterns and a plurality of first connection patterns alternately connected along the first direction, the first connection patterns overlapping with the orthographic projection of the second conductive pattern on the base substrate.

[0010] In some embodiments, the first connection pattern includes a first sub-connection pattern, and the first sub-connection pattern has no overlap with the orthographic projection of the first conductive pattern on the base substrate; the orthographic projection of the first connection pattern on the base substrate coincides with the orthographic projection of the second conductive pattern on the base substrate.

[0011] In some embodiments, the pixel driving circuit includes a driving transistor, a writing transistor, a first reset transistor and a compensation transistor; the array substrate further includes: a first active film layer disposed between the light shielding layer and the second gate metal layer; the first active film layer includes an active layer pattern of the driving transistor and an active layer pattern of the fourth transistor;

[0012] A second active film layer is arranged between the second gate metal layer and the first source-drain metal layer; the first active film layer includes an active layer pattern of a first reset transistor and an active layer pattern of a compensation transistor, and the active layer pattern of the first reset transistor and the active layer pattern of the compensation transistor are connected to a first connection point; a second source-drain metal layer is arranged on the side of the first source-drain metal layer away from the base substrate; the second source-drain metal layer includes a plurality of data signal lines; the connecting end of the data signal line is connected to the active layer pattern of the write transistor through a third via hole; the first source-drain metal layer also includes a first connecting portion, the first end of the first connecting portion is connected to the active layer pattern of the drive transistor through a second via hole, and the second end of the first connecting portion is connected to the first connection point through a fourth via hole; the first source-drain metal layer also includes an isolation pattern, the orthographic projection of the isolation pattern on the base substrate is located between the orthographic projection of the first connecting portion on the base substrate and the orthographic projection of the connecting end of the data signal line on the base substrate, and the isolation pattern transmits a voltage-stabilized signal.

[0013] In some embodiments, the isolation pattern is connected to the second portion.

[0014] In some embodiments, the pixel driving circuit also includes a first light-emitting control transistor, and the first active film layer also includes an active layer pattern of the first light-emitting control transistor; the active layer pattern of the driving transistor, the active layer pattern of the writing transistor and the active layer pattern of the first light-emitting control transistor are connected to a second connection point; the second connection point overlaps with the orthographic projection of the data signal line on the base substrate, and the second connection point overlaps with the orthographic projection of the second part on the base substrate.

[0015] In some embodiments, the second connection point overlaps with an orthographic projection of the first conductive pattern on the base substrate.

[0016] In some embodiments, the second source-drain metal layer further includes a plurality of second voltage signal lines extending along the second direction, and in the sub-pixel region, one of the second voltage signal lines is connected to one of the first voltage signal lines through a fifth via hole.

[0017] A second aspect of the present disclosure provides a display panel, comprising: an array substrate as described in any one of the above embodiments.

[0018] The beneficial effects of the above-mentioned display panel are the same as the beneficial effects of the array substrate provided in the first aspect of the present disclosure, and will not be described in detail here.

[0019] In some embodiments, the display panel also includes: an anode layer arranged on the array substrate, the anode layer including multiple anodes; each anode is connected to a pixel driving circuit; the display panel includes multiple pixel areas, the pixel area includes three sub-pixel areas arranged in sequence along the row direction, the three sub-pixel areas are respectively a first sub-pixel area, a second sub-pixel area and a third sub-pixel area, the anode includes a first anode, a second anode and a third anode; the array substrate also includes a second source-drain metal layer, the second source-drain metal layer includes multiple second voltage signal lines extending along the second direction; the orthographic projections of the first anode and the second anode on the base substrate overlap with the second voltage signal line located in the first sub-pixel area.

[0020] In some embodiments, within the first sub-pixel region, the second voltage signal line includes a first voltage pattern and a second voltage pattern, the ratio of an overlapping area between the first anode and the first voltage pattern to an area of ​​the first anode is greater than 90%, and the ratio of an overlapping area between the second anode and the second voltage pattern to an area of ​​the second anode is greater than 90%.

[0021] In some embodiments, the second source-drain metal layer includes a plurality of data signal lines extending along a second direction; the third anode overlaps with the data signal line located in the second sub-pixel region, the second voltage signal line located in the second sub-pixel region, and the second voltage signal line located in the third sub-pixel region.

[0022] In some embodiments, the display panel also includes: a second flat layer arranged on the array substrate and between the anode layer; a pixel defining layer arranged on the side of the anode layer away from the base substrate, a plurality of pixel openings being arranged on the pixel defining layer, and the pixel openings exposing a portion of the corresponding anode; the second source-drain metal layer of the third sub-pixel area includes a bridging pattern, and the third anode includes an anode connecting portion, and the anode connecting portion is connected to the bridging pattern through a sixth via hole penetrating the second flat layer; the second flat layer has a climbing area around the sixth via hole, and there is an angle between the surface of the portion of the second flat layer located in the climbing area and the base substrate; the distance in a set direction between the orthographic projection of the pixel opening corresponding to the third anode on the base substrate and the orthographic projection of the anode connecting portion on the base substrate is greater than the size of the orthographic projection of the climbing area on the base substrate in the set direction, and the set direction is parallel to the base substrate.

[0023] A third aspect of the present disclosure provides a display device, wherein the display device comprises a plurality of display panels as described in any of the above embodiments.

[0024] The beneficial effects of the above-mentioned display device are the same as the beneficial effects of the display panel provided by any embodiment of the second aspect of the present disclosure, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0026] Figure 1 is a planar structural diagram of a display device according to some embodiments of the present disclosure;

[0027] Figure 2 is a planar structural diagram of a display panel according to some embodiments of the present disclosure;

[0028] Figure 3 A planar structural diagram of an array substrate provided in some embodiments of the present disclosure;

[0029] Figure 4A An equivalent circuit diagram of a pixel driving circuit provided by some embodiments of the present disclosure;

[0030] Figure 4B A timing signal control diagram of a pixel driving circuit provided in some embodiments of the present disclosure;

[0031] Figure 5A A cross-sectional structural diagram of a display panel provided in some embodiments of the present disclosure;

[0032] Figure 5B Another cross-sectional structural diagram of a display panel provided in some embodiments of the present disclosure;

[0033] Fig. 6A A film layer structure diagram of a light shielding layer of an array substrate provided in some embodiments of the present disclosure;

[0034] Figure 6B A film layer structure diagram of a first active film layer of an array substrate provided in some embodiments of the present disclosure;

[0035] Figure 6C A film layer structure diagram of a first gate metal layer of an array substrate provided in some embodiments of the present disclosure;

[0036] Fig.6D A film layer structure diagram of a second gate metal layer of an array substrate provided in some embodiments of the present disclosure;

[0037] Fig. 6E A film layer structure diagram of a second active film layer of an array substrate provided in some embodiments of the present disclosure;

[0038] Fig. 6F A film layer structure diagram of a third gate metal layer of an array substrate provided in some embodiments of the present disclosure;

[0039] Figure 6G A structural diagram of a first type of via hole group of an array substrate provided in some embodiments of the present disclosure;

[0040] Figure 6H A structural diagram of a first type of via hole group of an array substrate provided in some embodiments of the present disclosure;

[0041] Fig.6I A film layer structure diagram of a first source-drain metal layer of an array substrate provided in some embodiments of the present disclosure;

[0042] Figure 6J A film layer structure diagram of a passivation layer of an array substrate provided in some embodiments of the present disclosure;

[0043] Figure 6K A film layer structure diagram of a first flat layer of an array substrate provided in some embodiments of the present disclosure;

[0044] Figure 6L A film layer structure diagram of a second source-drain metal layer of an array substrate provided in some embodiments of the present disclosure;

[0045] Figure 6M A film layer structure diagram of a second flat layer of an array substrate provided in some embodiments of the present disclosure;

[0046] Figure 6N A film layer structure diagram of an anode layer of a display panel provided in some embodiments of the present disclosure;

[0047] Fig.6O A structural diagram of a pixel definition layer of a display panel provided in some embodiments of the present disclosure;

[0048] Fig. 7A A partially overlapping structural diagram of a first source-drain metal layer and a second gate metal layer of an array substrate provided in some embodiments of the present disclosure;

[0049] Figure 7B A partially overlapping structural diagram of a first source-drain metal layer and a light shielding layer of an array substrate provided in some embodiments of the present disclosure;

[0050] Figure 7CA connection structure diagram of a second portion of a first source-drain metal layer and a first conductive pattern of a second gate metal layer of an array substrate provided in some embodiments of the present disclosure;

[0051] Fig.7D A diagram of a connection structure between a first source-drain metal layer and a first active film layer and a second active film layer of an array substrate provided in some embodiments of the present disclosure;

[0052] Fig. 7E A diagram of a connection structure between a first source-drain metal layer and a second source-drain metal layer of an array substrate provided in some embodiments of the present disclosure;

[0053] Figure 7F A stacking structure diagram of a first source-drain metal layer, a second gate metal layer, and a second source-drain metal layer of an array substrate provided in some embodiments of the present disclosure;

[0054] Figure 7G A diagram showing a stacking structure of film layers of a display panel provided in some embodiments of the present disclosure;

[0055] Fig. 8A A diagram of a connection structure between an anode layer and a second source-drain metal layer of a display panel provided in some embodiments of the present disclosure;

[0056] Figure 8B A structural diagram of the partial overlapping relationship between the anode layer and the second source-drain metal layer of the display panel provided in some embodiments of the present disclosure;

[0057] Fig. 9 A position structure diagram of a pixel opening of a pixel defining layer of a display panel and a bridge pattern of a second source-drain metal layer provided according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0058] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0059] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0060] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0061] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0062] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0063] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0064] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0065] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0066] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0067] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0068] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0069] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0070] like Figure 1As shown, some embodiments of the present disclosure provide a display device 1000. The display device provided by the embodiments of the present disclosure can be any device that displays whether it is moving (e.g., video) or fixed (e.g., still image) and whether it is text or image. More specifically, it is expected that the embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, cameras, game consoles, watches, clocks, calculators, TV monitors, flat panel displays, computer monitors, car displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0071] Specifically, Figure 1 As shown, in the embodiment of the present disclosure, the display device 1000 is exemplified as a mobile phone.

[0072] like Figure 1 and Figure 2 As shown, the display device 1000 includes a display panel 100, and the display panel 100 includes a display area AA and a peripheral area BB located on at least one side of the display area AA, wherein a plurality of sub-pixels 21 and a plurality of signal lines are arranged in the display area AA according to a specified rule, and the area where each sub-pixel 21 is located is a sub-pixel area A1, wherein the sub-pixel 21 is the smallest unit for displaying a picture in the display panel 100, and each sub-pixel 21 can display a single color, such as red, green or blue, and by adjusting the brightness of different sub-pixels 21, color superposition can realize the display of multiple colors. Figure 3 As shown, each sub-pixel 21 includes a light-emitting device OLED and a pixel driving circuit 200 for driving the light-emitting device OLED to emit light.

[0073] For example, the display panel 100 is an OLED (Organic Light-Emitting Diode) display panel, and the display panel 100 includes an array substrate 10, a light-emitting device layer, and a packaging layer stacked in sequence, wherein the array substrate 10 is provided with a plurality of transistors and capacitors included in a pixel driving circuit, and the light-emitting device layer includes a plurality of light-emitting devices OLED. Figure 3 and Figure 5AAs shown, the array substrate 10 includes: a base substrate 101 and a plurality of functional layers sequentially stacked on the base substrate 101, and an insulating layer located between adjacent functional layers, wherein the functional layer may include an active film layer, a gate metal layer and a source-drain metal layer, and the active film layer, the gate metal layer and the source-drain metal layer are used to form a plurality of pixel driving circuits 200 in the display panel 100, and the plurality of pixel driving circuits 200 may be formed in the display area AA of the display panel 100. The light emitting device OLED is arranged on a side of the pixel driving circuit 200 away from the base substrate 101.

[0074] Wherein, the pixel driving circuit 200 includes a plurality of transistors, the active layers of the plurality of transistors are located in the active film layer, the active layer of each transistor includes a first polar region, a second polar region and a channel region for connecting the first polar region and the second polar region, and the gates of the plurality of transistors are located in the gate metal layer, wherein the gate metal layer includes, for example, a plurality of signal lines, and the portion of a signal line passing through the active layer of a certain transistor can be used as the gate of the transistor, and the "passing through" here refers to the portion where the orthographic projections of the two on the substrate overlap. Wherein, when manufacturing a transistor, an active film layer can be first formed on the substrate 101 to obtain the active layer of the transistor, and then a gate metal layer can be formed on the side of the active film layer away from the substrate, and the position where the gate metal layer overlaps with the active film layer is the position where the gate metal layer "passes through" the active layer, for example, the gate of the transistor is arranged to overlap with the channel region of the transistor.

[0075] In some embodiments, the display device 1000 also includes components such as a camera, various sensors, and a speaker.

[0076] In order to realize full-screen display, it is necessary to integrate the photosensitive component under the display panel 100, and the photosensitive component collects light from the front of the display panel 100. The photosensitive component is, for example, a camera, and accordingly, this technology is the under-screen camera technology; the photosensitive component is, for example, a fingerprint sensor, and accordingly, this technology is the under-screen fingerprint recognition technology. To realize the under-screen camera technology and the under-screen fingerprint recognition technology, there are certain requirements for the light transmittance of the display screen. However, in the display screen, the setting of each film layer used to form the pixel driving circuit 200 affects the light transmittance of the screen, thereby affecting the shooting effect and fingerprint recognition effect of the display screen.

[0077] A plurality of signal lines are arranged in the pixel driving circuit 200, and the plurality of signal lines are distributed in a plurality of film layers. The size of the orthographic projection area of ​​the plurality of signal lines on the substrate can determine the size of the orthographic projection area of ​​the pixel driving circuit 200 on the substrate, thereby affecting the light transmittance of the display panel. For example, in a direction perpendicular to the plane where the substrate 101 is located, the smaller the orthographic projection area of ​​the signal line corresponding to the pixel opening position of the sub-pixel region on the substrate, the higher the light transmittance. The inventor of the present disclosure has found that in the related art, the wiring method of the signal line in the pixel driving circuit 200 can change the size of its orthographic projection area on the substrate. The smaller the orthographic projection area of ​​the signal line on the substrate, the more conducive it is to the transmission of light, thereby improving the display effect of the display panel.

[0078] Based on this, some embodiments of the present disclosure provide an array substrate 10, which includes: a plurality of pixel driving circuits 200 and a plurality of signal lines, such as Figure 3 As shown, a plurality of pixel driving circuits 200 are arranged in an array, and a plurality of signal lines include data signal lines Dt and gate lines, initialization signal lines Vin, voltage signal lines, etc. The gate lines and initialization signal lines Vin extend along a first direction X, and the data signal lines Dt and power signal lines extend along a second direction Y. Each data signal line Dt is electrically connected to a column of pixel driving circuits 200, and at least one gate line is electrically connected to a row of pixel driving circuits 200. According to the functional division of at least one gate line electrically connected to a row of pixel driving circuits 200, the at least one gate line may include a scanning signal line, a reset signal line Rst, a light emitting control signal line EM, etc. The following is a detailed introduction to the scheme of the present disclosure.

[0079] In some embodiments, the pixel driving circuit 200 in some embodiments of the present disclosure may be a 7T1C, 8T1C or 9T1C circuit, wherein T represents a transistor, and the number before T represents the number of transistors, C represents a capacitor, and the number before C represents the number of capacitors. By way of example, 7T1C represents 7 transistors and 1 capacitor. The following is an introduction to a pixel driving circuit in a 7T1C mode.

[0080] For example, Figure 4A and Figure 4BThe pixel driving circuit 200 may specifically include a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a write transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second reset transistor T7 and a capacitor Cst, and the signal lines electrically connected to the pixel driving circuit 200 include a data signal line Dt, a first power signal line VDD, a second power signal line VSS, a first scan signal line GP, a second scan signal line GN, a first initialization signal line Vin1, a second initialization signal line Vin2, a first reset signal line Rst-N, a second reset signal line Rst-P and a light emission control signal line EM.

[0081] Among them, combined Fig. 6F , the gate of the first reset transistor T1 is electrically connected to the first reset signal line Rst-N, the first electrode of the first reset transistor T1 is electrically connected to the first node N1, and the second electrode of the first reset transistor T1 is electrically connected to the first initialization signal line Vin1; the gate of the compensation transistor T2 is electrically connected to the second scanning signal line GN, the first electrode of the compensation transistor T2 is electrically connected to the second electrode of the driving transistor T3, and the second electrode of the compensation transistor T2 is electrically connected to the first node N1; the gate of the driving transistor T3 is electrically connected to the first node N1; the gate of the write transistor T4 is electrically connected to the first scanning signal line GP, the first electrode of the write transistor T4 is electrically connected to the data signal line Dt, and the second electrode of the write transistor T4 is electrically connected to the first electrode of the driving transistor T3; the gate of the first light emitting control transistor T5 is electrically connected to the first scanning signal line GP, the first electrode of the write transistor T4 is electrically connected to the data signal line Dt, and the second electrode of the write transistor T4 is electrically connected to the first electrode of the driving transistor T3; The gate G6 of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal line EM, the first electrode of the first light-emitting control transistor T5 is electrically connected to the first power signal line VDD, the second electrode of the first light-emitting control transistor T5 is electrically connected to the first electrode of the driving transistor T3, the first electrode of the second light-emitting control transistor T6 is electrically connected to the second electrode of the driving transistor T3, and the second electrode of the second light-emitting control transistor T6 is electrically connected to the anode of the light-emitting device OLED; the gate of the second reset transistor T7 is electrically connected to the second reset signal line Rst-P, the first electrode of the second reset transistor T7 is electrically connected to the second initialization signal line Vin2, the second electrode of the second reset transistor T7 is electrically connected to the anode of the light-emitting device OLED, and the cathode of the light-emitting device OLED is electrically connected to the second power signal line VSS.

[0082] A first plate Cst1 of the capacitor Cst is electrically connected to the first power signal line VDD, and a second plate Cst2 of the capacitor Cst is electrically connected to the first node N1.

[0083] Among them, the first scanning signal line GP is used to transmit the first scanning signal gP, the second scanning signal line GN is used to transmit the second scanning signal gN, the first reset signal line Rst-N is used to transmit the first reset timing signal rst-N, the second reset signal line Rst-P is used to transmit the second reset timing signal rst-P, and the first power signal line VDD is used to transmit the first voltage signal vdd, for example, a high-voltage DC signal; the first initialization signal line Vin1 and the second initialization signal line Vin2 are respectively used to transmit initialization signals to the first reset transistor T1 and the light-emitting device OLED, the data signal line Dt is used to transmit the data signal dt, the light-emitting control signal line EM is used to transmit the light-emitting control timing signal em, and the second power signal line VSS is used to transmit the second power signal, for example, a low-voltage DC signal.

[0084] like Figure 4B As shown, the driving process of the driving circuit 200 is as follows: one frame period includes a reset phase t1, a data refresh and compensation phase t2, and a light-emitting phase t3. In the reset phase t1, the first reset transistor T1 is turned on under the control of the first reset timing signal rst-N, so that the initialization signal is written to the first node N1, thereby resetting the first node N1. At this time, the driving transistor T3 is turned on, while the compensation transistor T2, the write transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second reset transistor T7 are all in a disconnected state, and the light-emitting device OLED does not emit light.

[0085] In the data refresh and compensation stage t2, the first reset transistor T1 is turned off, and the second reset transistor T7 is turned on under the control of the second reset timing signal rst-P, so that the initialization signal is written into the anode of the OLED, and the anode of the light-emitting device OLED is reset. The write transistor T4 is turned on under the control of the first scan signal gP, the compensation transistor T2 is turned on under the control of the second scan signal gN, and the drive transistor T3 maintains the on state of the reset stage t1, so the data signal dt can be transmitted to the first node N1 through the write transistor T4, the drive transistor T3 and the compensation transistor T2 in sequence, so that the voltage of the first node N1 changes until the voltage of the first node N1 reaches the sum of the threshold voltage of the drive transistor T3 and the voltage of the data signal dt, so that the drive transistor T3 is turned off. In the data refresh and compensation stage t2, the threshold voltage of the drive transistor T3 can be written to the first node N1 to compensate for the threshold voltage drift of the drive transistor T3, avoid the change of the drive signal generated by the drive transistor, and avoid the influence on the luminous intensity of the light-emitting device OLED. In this stage, the first light emission control transistor T5 and the second light emission control transistor T6 are in a disconnected state under the control of the light emission control timing signal em.

[0086] In the light-emitting stage t3, the first reset transistor T1 is disconnected under the control of the first reset timing signal rst-N, the compensation transistor T2 is disconnected under the control of the second scanning signal gN, the write transistor T4 and the second reset transistor T7 are disconnected under the control of the second reset timing signal rst-P, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on under the control of the light-emitting control timing em, so that the voltage signal of the first power signal line VDD is written to the first electrode of the driving transistor T3, and the anode voltage of the light-emitting device OLED can be written to the second electrode of the driving transistor T3, so that the driving transistor T3 is turned on, thereby forming a path between the first power signal line VDD and the light-emitting device OLED, so that the light-emitting device OLED emits light.

[0087] It should be noted that the first pole of the transistor disclosed in the present invention is one of the source and drain of the transistor, and the second pole is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first pole and the second pole of the transistor in the embodiment of the present invention can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first pole of the transistor is the source, and the second pole is the drain; Exemplarily, in the case where the transistor is an N-type transistor, the first pole of the transistor is the drain, and the second pole is the source.

[0088] In the circuit provided in the embodiment of the present disclosure, the nodes do not represent actual existing components, but represent the junction points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by the junction points of related electrical connections in the circuit diagram being equivalent.

[0089] The above-mentioned pixel driving circuit 200 adopts an LTPO (Low Temperature Polycrystalline Oxide) circuit, that is, a pixel driving circuit 200 includes a low-temperature polycrystalline silicon (Low Temperature Poly-Silicon, abbreviated as LTPS) thin film transistor and an oxide (Oxide) thin film transistor. The low-temperature polycrystalline silicon thin film transistor has a strong load capacity, and the oxide (Oxide) thin film transistor has a small off-state current and a stronger charge retention ability than the low-temperature polycrystalline silicon thin film transistor. In this way, the pixel driving circuit 200 can achieve a higher charge mobility and better stability.

[0090] In some examples, the oxide transistor is an N-type transistor and the LTPS transistor is a P-type transistor, wherein the N-type transistor is turned on when the gate receives a high voltage signal, and the P-type transistor is turned on when the gate receives a low voltage signal. Figure 4AAs shown, the first reset transistor T1 and the compensation transistor T2 can be oxide thin film transistors, and are N-type transistors, that is, they are turned on at a high level. The driving transistor T3, the writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6 and the second reset transistor T7 are all P-type transistors of low-temperature polysilicon thin film transistors (LowTemperature Poly-silicon Thin Film Transistor), and are turned on at a low level. Among them, the first reset transistor T1 and the compensation transistor T2 are set as oxide thin film transistors, which can effectively prevent the first node N1 from leaking.

[0091] It should be noted that the “high voltage signal” and “low voltage signal” mentioned above are popular terms. Generally speaking, the turn-on condition of an N-type transistor is that the gate-source voltage difference is greater than its threshold voltage, that is, the gate voltage of the N-type transistor is greater than the sum of its source voltage and its threshold voltage, and the threshold voltage of the N-type transistor is a positive value. In this case, the gate voltage signal that turns on the N-type transistor is called a high voltage signal. The turn-on condition of a P-type transistor is that the absolute value of the gate-source voltage difference is greater than its threshold voltage, and the threshold voltage of the P-type transistor is a negative value, that is, the gate voltage of the P-type transistor is less than the sum of its source voltage and its threshold voltage, and the gate voltage signal that turns on the P-type transistor is called a low voltage signal. The high and low in “high voltage signal” and “low voltage signal” are relative to a reference voltage (for example, 0V).

[0092] The following describes the film layer structures included in the array substrate and the arrangement of the transistors in the pixel driving circuit.

[0093] For example, Figure 5A As shown, the array substrate 10 includes: a base substrate 101 and a pixel driving circuit stack 20 , and the pixel driving circuit stack 20 is disposed on the base substrate 101 .

[0094] In some examples, the base substrate 101 may be a single-layer structure or a stacked structure, and may be rigid or flexible. Exemplarily, the material of the base substrate 101 may include any one of glass, metal or flexible material.

[0095] The pixel driving circuit stack 20 forms a plurality of pixel driving circuits 200. For example, the pixel driving circuit stack 20 includes: a light shielding layer 102, a first buffer layer 121, a first active film layer 103, a first gate insulating layer 122, a first gate metal layer 104, a second gate insulating layer 123, a second gate metal layer 105, a second buffer layer 124, a second active film layer 106, a third gate insulating layer 125, a third gate metal layer 107, an interlayer dielectric layer 108, a first source-drain metal layer 109, a passivation layer 110, a first planarizing layer 111, a second source-drain metal layer 112, and a second planarizing layer 113, which are stacked in sequence.

[0096] Exemplarily, the first buffer layer 121, the first gate insulating layer 122, the second gate insulating layer 123, the second buffer layer 124, the third gate insulating layer 125 and the interlayer dielectric layer 108 can be made of silicon nitride, silicon oxide or silicon oxynitride, or a combination of any two of these materials, and have the function of blocking water and oxygen and blocking alkaline ions.

[0097] Exemplarily, the material of the first active film layer 103 may be low-temperature polysilicon; the material of the second active film layer 106 may be any one of indium gallium zinc oxide or low-temperature polycrystalline oxide, for example, IGZO (Indium gallium zinc oxide) and IGZTO (Indium gallium zinc tin oxide).

[0098] Exemplarily, the material of the first planar layer 111 and the second planar layer 113 may be PI (Polyimide), or may be any one of silicon nitride and silicon oxide.

[0099] In some embodiments, Figure 2 , Figure 3 As shown, the array substrate 10 includes a plurality of sub-pixel regions A1, a row of sub-pixel regions A1 is arranged along a first direction X, and a column of sub-pixel regions A1 is arranged along a second direction Y. The first direction X and the second direction Y intersect; a pixel driving circuit 200 is disposed in the sub-pixel region A1, and the pixel driving circuit 200 includes a capacitor Cst.

[0100] It can be understood that the multiple sub-pixel regions A1 are arranged in multiple rows and columns, the first direction X is the row direction of the multiple sub-pixel regions A1, and the second direction Y is the column direction of the multiple sub-pixel regions A1.

[0101] Exemplarily, the first direction X is perpendicular to the second direction Y.

[0102] In some embodiments, Figure 5A and Fig. 7EAs shown, the array substrate 10 includes a base substrate 101, a first source-drain metal layer 109 disposed on one side of the base substrate 101, and a second source-drain metal layer 112 disposed on a side of the first source-drain metal layer 109 away from the base substrate 101, wherein the first source-drain metal layer 109 includes a plurality of first voltage signal lines 12 extending along a first direction X, and the second source-drain metal layer 112 also includes a plurality of second voltage signal lines 14 extending along a second direction Y. Each second voltage signal line 14 is located in a column of sub-pixel regions A1, and each first voltage signal line 12 is located in a row of sub-pixel regions A1, and a plurality of first voltage signal lines 12 and a plurality of second voltage signal lines 14 are connected to form a grid structure.

[0103] The first power signal line VDD includes multiple first voltage signal lines 12 and multiple second voltage signal lines 14, and the multiple first voltage signal lines 12 and the multiple second voltage signal lines 14 all transmit a first voltage signal vdd, such as a high-voltage DC signal.

[0104] In some embodiments, reference Figure 6J , Figure 6K , Figure 6L and Fig. 7E In the sub-pixel area A1, a second voltage signal line 14 is connected to a first voltage signal line 12 through a fifth via hole K5.

[0105] For example, refer to Figure 4A , Figure 5A , Figure 6J , Figure 6K , Figure 6L and Fig. 7E A passivation layer 110 and a first flat layer 111 are arranged between the first source-drain metal layer 109 and the second source-drain metal layer 112, and the fifth via K5 penetrates the first flat layer 111 and the passivation layer 110, wherein a lower-layer fifth via K52 is arranged on the passivation layer 110, and an upper-layer fifth via K51 is arranged on the first flat layer 111, and the lower-layer fifth via K52 is connected to the upper-layer fifth via K51 to form the fifth via K5. A second voltage signal line 14 is connected to a first voltage signal line 12 located on the first source-drain metal layer 109 through an upper fifth via K51 penetrating the first flat layer 111 and a lower fifth via K52 on the passivation layer 110. Exemplarily, a fifth via K5 is provided at a position where the second voltage signal line 14 and the first voltage signal line 12 overlap, so that a second voltage signal line 14 is connected to multiple first voltage signal lines 12 through multiple fifth vias K5, and a first voltage signal line 12 is connected to multiple second voltage signal lines 14 through multiple fifth vias K5.

[0106] The first power signal line VDD is divided into a plurality of first voltage signal lines 12 and a plurality of second voltage signal lines 14, and are arranged in the first source-drain metal layer 109 and the second source-drain metal layer 112, respectively. Since the plurality of first voltage signal lines 12 extend along the first direction X, the plurality of second voltage signal lines 14 extend along the second direction Y, and both the first voltage signal lines 12 and the second voltage signal lines 14 transmit the first power signal, that is, the plurality of first voltage signal lines 12 and the plurality of second voltage signal lines 14 can form a horizontal and vertical grid wiring method, which can greatly reduce the load of the transmitted voltage signal, reduce the voltage drop, and reduce the signal transmission loss, so that the signals transmitted by the plurality of first voltage signal lines 12 and the plurality of second voltage signal lines 14 are consistent. Furthermore, the voltage of the first voltage signal vdd received by the pixel driving circuits in the plurality of sub-pixel areas A1 can be consistent, so that the driving current provided to the light-emitting device is consistent, thereby improving the brightness uniformity of the display panel.

[0107] Exemplarily, the second voltage signal line 14 extends to the peripheral area, and the first power signal is connected to the display area from the peripheral area through the second voltage signal line. For example, the peripheral area is also provided with a first voltage signal bus, and the first voltage signal bus is connected to the second voltage signal line. The second voltage signal line 14 transmits the first power signal to the first voltage signal line 12, forming a networked transmission of the first power signal, and then providing the first power signal to each pixel driving circuit.

[0108] In some embodiments, reference Figure 5A , Fig.6D , Fig.6I and Fig. 7A As shown, the second gate metal layer 105 includes a plurality of conductive connection lines 11 extending along the first direction X, the conductive connection lines 11 include a plurality of first conductive patterns 11a and a plurality of second conductive patterns 11b alternately connected along the first direction X, the first conductive pattern 11a is the first electrode Cst1 of the capacitor Cst; illustratively, a first conductive pattern 11a is arranged in each sub-pixel area A1.

[0109] The first voltage signal line 12 located in the first source-drain metal layer 109 includes a plurality of first parts 12a and a plurality of second parts 12b alternately connected along a first direction X; wherein the second conductive pattern 11b overlaps with the first part 12a, and the conductive connecting line 11 and the first voltage signal line 12 transmit the same voltage signal, that is, the conductive connecting line 11 is connected to the first voltage signal line 12.

[0110] For example, refer to Fig.6D , Fig.6I and Fig. 7AThe conductive connection line 11 includes a plurality of first conductive patterns 11a and a plurality of second conductive patterns 11b alternately connected along the first direction X, and the size d1 of the first conductive pattern 11a in the second direction Y is greater than the size d2 of the second conductive pattern 11b in the second direction Y. Fig.6I As shown, the first voltage signal line 12 includes a plurality of first portions 12a and a plurality of second portions 12b alternately connected along a first direction X, wherein the first portions 12a extend along the first direction X, and the second portions 12b extend along the second direction Y. An average dimension d3' of the first portions 12a in the second direction Y is greater than a dimension d4' of the second portions 12b in the second direction Y.

[0111] Since the plurality of conductive connection lines 11 are located in the second gate metal layer 105, and the plurality of first voltage signal lines 12 are located in the first source-drain metal layer 109, that is, the plurality of conductive connection lines 11 and the plurality of first voltage signal lines 12 are located in different film layers, and the second conductive pattern 11b is arranged to overlap with the first portion 12a, it can be understood that the orthographic projection of the second conductive pattern 11b on the substrate 101 partially overlaps with the orthographic projection of the first portion 12a on the substrate 101, or the orthographic projection of the second conductive pattern 11b on the substrate 101 is located within the orthographic projection of the first portion 12a on the substrate 101, or the orthographic projection boundary of the second conductive pattern 11b on the substrate 101 completely overlaps with the orthographic projection boundary of the first portion 12a on the substrate 101. In the above cases, the overlapping design of the conductive connection lines 11 and the first voltage signal lines 12 can reduce the sum of the positive projection areas of the multiple conductive connection lines 11 and the multiple first voltage signal lines 12 on the base substrate 101, and further improve the light transmittance of the array substrate 10 and enhance the display effect of the display panel.

[0112] It should be noted that the conductive connection line 11 includes a plurality of first conductive patterns 11a and a plurality of second conductive patterns 11b alternately connected along the first direction X, the first conductive pattern 11a is the first plate Cst1 of the capacitor Cst, and the conductive connection line 11 transmits the same voltage signal as the first voltage signal line 12, that is, the first plate Cst1 of the capacitor Cst also receives the voltage signal. The setting of the conductive connection line 11 can connect the plurality of first plates Cst1 of the plurality of capacitors Cst through the second conductive pattern 11b, and can improve the uniformity of the voltage of the first plate Cst1 of the capacitor Cst in each pixel driving circuit, thereby improving the working stability of each pixel driving circuit.

[0113] Multiple conductive connecting lines 11 and multiple first voltage signal lines 12 extend along the first direction X and are connected to each other. Multiple second voltage signal lines 14 extend along the second direction Y and are connected to the multiple first voltage signal lines 12. Multiple conductive connecting lines 11, multiple first voltage signal lines 12 and multiple second voltage signal lines 14 are located in different film layers and are connected through vias. They all transmit the first voltage signal vdd. In this way, the signal lines of the three film layers form a voltage signal transmission network, which can further reduce the voltage drop of the first voltage signal vdd during the transmission process and improve the brightness uniformity of the display panel.

[0114] In some embodiments, Fig.6I and Fig. 7A As shown, the positional relationship between the conductive connection line 11 and the first voltage signal line 12 includes: the first portion 12a includes a first sub-portion 12a1 and a second sub-portion 12a2, and the first sub-portion 12a1 does not overlap with the orthographic projection of the first conductive pattern 11a on the base substrate 101; the orthographic projection of the second sub-portion 12a2 on the base substrate 101 is located within the orthographic projection of the first conductive pattern 11a on the base substrate 101. The orthographic projection of the first sub-portion 12a1 on the base substrate 101 coincides with the orthographic projection of the second conductive pattern 11b on the base substrate 101.

[0115] For example, continue to refer to Fig. 7A , the orthographic projection of the first sub-portion 12a1 of the first portion 12a on the base substrate 101 is a rectangle, while the orthographic projection boundary of the second sub-portion 12a2 of the first portion 12a on the base substrate 101 is bent, that is, the sizes in the second direction Y are different. Fig. 7A It can be seen that the orthographic projections of the first sub-portion 12a1 and the first conductive pattern 11a on the substrate 101 do not overlap, and the orthographic projection of the first sub-portion 12a1 on the substrate 101 coincides with the orthographic projection of the second conductive pattern 11b on the substrate 101, that is, the first sub-portion 12a1 and the second conductive pattern 11b have the same area and corresponding positions, and the dimension d3 of the first sub-portion 12a1 in the second direction Y is equal to the dimension d2 of the second conductive pattern 11b in the second direction Y. Therefore, the orthographic projection of the first sub-portion 12a1 on the substrate 101 is set to coincide with the orthographic projection of the second conductive pattern 11b on the substrate 101, which reduces the orthographic projection area of ​​the conductive connection line 11 and the first voltage signal line 12 on the substrate 101, thereby improving the light transmittance and enhancing the display effect of the display panel.

[0116] In some embodiments, reference Figure 7C The positional relationship between the conductive connection line 11 and the first voltage signal line 12 also includes: the second portion 12b overlaps with the first conductive pattern 11a, and the second portion 12b is electrically connected to the first conductive pattern 11a through at least two first vias K1.

[0117] For example, refer to Figure 7C , the second part 12b partially overlaps with the first conductive pattern 11a, wherein in the overlapping partial area, the second part 12b is electrically connected to the first conductive pattern 11a through two first vias K1. It can be seen from the aforementioned content that the second part 12b transmits the first voltage signal vdd, and the first conductive pattern 11a serves as the first plate Cst1 of the capacitor Cst, and is electrically connected to the second part 12b by passing through the first via K1. It should be noted that by providing two first vias K1, the contact area between the first plate Cst1 and the second part 12b can be increased, thereby reducing the contact resistance between the two, further reducing the sensitivity of process fluctuations to the contact resistance, and having the effect of stabilizing the voltage. Specifically, since the voltage stability of the first plate Cst1 of the capacitor Cst is improved, referring to Figure 4A and Figure 6C Due to the coupling effect of the capacitor, the stability of the voltage of the corresponding second electrode plate Cst2 is also improved, that is, the voltage stability of the first node N1 is improved, thereby controlling the driving current generated by the driving transistor T3 to be more stable.

[0118] In some embodiments, reference Fig. 6A The array substrate 10 further includes a light shielding layer 102 disposed between the base substrate 101 and the second gate metal layer 105. The light shielding layer 102 includes a plurality of light shielding metal traces 13 extending along the first direction X. The light shielding metal traces 13 include a plurality of light shielding patterns 13a and a plurality of first connection patterns 13b alternately connected along the first direction X.

[0119] The above-mentioned light shielding layer 102 can prevent the light on the side of the base substrate 101 away from the light shielding layer 102 from affecting the pixel driving circuit. Fig. 6A and Figure 6B The shading pattern 13a overlaps with the active layer pattern of the driving transistor T3. The shading pattern 13a can prevent the light on the side of the substrate 101 away from the shading pattern 13a from affecting the driving transistor T3, and can ensure that the driving current generated by the driving transistor is not affected by external light.

[0120] In some examples, the light shielding layer 102 further includes a plurality of second connection patterns 13 c extending along the second direction Y, and the plurality of second connection patterns 13 c connect two adjacent light shielding patterns 13 a .

[0121] It should be noted that the light shielding layer 102 is connected to the first voltage signal bus located in the peripheral area through the second connection pattern 13 c, thereby transmitting the same first voltage signal vdd.

[0122] like Figure 7BAs shown, the orthographic projections of the first connection pattern 13 b and the second conductive pattern 11 b on the base substrate 101 overlap.

[0123] For example, refer to Figure 7B , the orthographic projections of the first connection pattern 13b and the second conductive pattern 11b on the substrate 101 are overlapped, which can be understood as that the orthographic projection of the second conductive pattern 11b on the substrate 101 partially overlaps with the orthographic projection of the first connection pattern 13b on the substrate 101, or the orthographic projection of the second conductive pattern 11b on the substrate 101 is located within the orthographic projection of the first connection pattern 13b on the substrate 101, or the orthographic projection boundary of the second conductive pattern 11b on the substrate 101 completely overlaps with the orthographic projection boundary of the first connection pattern 13b on the substrate 101. In the above multiple cases, the sum of the orthographic projection areas of the multiple light-shielding metal traces 13 and the multiple first voltage signal lines 12 on the substrate 101 can be reduced, and further, the light transmittance of the array substrate 10 can be improved, and the display effect of the display panel can be enhanced.

[0124] In some embodiments, reference Fig. 7A and Figure 7B , the first connection pattern 13b includes a first sub-connection pattern 13b1 and a second sub-connection pattern 13b2, the first sub-connection pattern 13b has no overlap with the orthographic projection of the first conductive pattern 11a on the base substrate 101; the orthographic projection of the second sub-connection pattern 13b2 on the base substrate 101 is located within the orthographic projection of the first conductive pattern 11a on the base substrate 101. The orthographic projection of the first connection pattern 13b on the base substrate 101 coincides with the orthographic projection of the second conductive pattern 11b on the base substrate 101.

[0125] For example, refer to Figure 7B , the orthographic projection of the first sub-connection pattern 13b1 of the first connection pattern 13b on the substrate 101 is a rectangle, and the orthographic projection of the first sub-connection pattern 13b1 on the substrate 101 coincides with the orthographic projection of the second conductive pattern 11b on the substrate 101, that is, the first sub-connection pattern 13b1 and the second conductive pattern 11b are equal in area and position, and the dimension d4 of the first sub-connection pattern 13b in the second direction Y is equal to the dimension d2 of the second conductive pattern 11b in the second direction Y. Therefore, the orthographic projection of the first sub-portion 12a1 on the substrate 101 is arranged to coincide with the orthographic projection of the second conductive pattern 11b on the substrate 101, thereby reducing the orthographic projection area of ​​the light-shielding metal trace 13 and the first voltage signal line 12 on the substrate 101, thereby improving the light transmittance and enhancing the display effect of the display panel.

[0126] It should be noted that, since the orthographic projection of the first sub-connection pattern 13b1 on the base substrate 101 completely overlaps with the orthographic projection of the second conductive pattern 11b on the base substrate 101, Figure 7B A pattern (indicated by the arrow) represents the first sub-portion 12a1, the second conductive pattern 11b, and the first sub-connection pattern 13b1. The pattern sizes of the first sub-portion 12a1, the second conductive pattern 11b, and the first sub-connection pattern 13b1 are set to be consistent, so that their areas are equal and their positions correspond, which can further improve the light transmittance of the display panel and improve the display effect.

[0127] In some embodiments, Figure 4A and Figure 5A As shown, the pixel driving circuit 200 includes a driving transistor T3, a writing transistor T4, a first reset transistor T1 and a compensation transistor T2; the pixel driving circuit 200 also includes a low-temperature polysilicon thin film transistor and an oxide thin film transistor, so the multiple transistors are divided into two parts, and the active layer patterns of the two parts of the transistors are respectively located in different active film layers.

[0128] like Figure 6B As shown, the array substrate 10 further includes: a first active film layer 103 disposed between the light shielding layer 102 and the second gate metal layer 105; the first active film layer 103 includes an active layer pattern of the driving transistor T3 and an active layer pattern of the writing transistor T4. Exemplarily, the first active film layer 103 is a low temperature polysilicon layer.

[0129] like Fig. 6E As shown, the array substrate 10 further includes a second active film layer 106 disposed between the second gate metal layer 105 and the first source-drain metal layer 109; the first active film layer 103 includes an active layer pattern of the first reset transistor T1 and an active layer pattern of the compensation transistor T2, and the active layer pattern of the first reset transistor T1 and the active layer pattern of the compensation transistor T2 are connected to the first connection point P. Exemplarily, the second active film layer 106 is an oxide layer.

[0130] like Figure 5A and Figure 6L As shown, the array substrate 10 further includes a second source-drain metal layer 112 disposed on a side of the first source-drain metal layer 109 away from the base substrate 101; the second source-drain metal layer 112 includes a plurality of data signal lines Dt; Fig. 7E The connection end Dt1 of the data signal line Dt is connected to the active layer pattern of the write transistor T4 through the third via hole K3. The third via hole K3 connects the second source-drain metal layer 112 and the first active film layer 103.

[0131] like Fig.6I As shown, the first source-drain metal layer 109 further includes a first connecting portion 1091. Fig.7D As shown, the first end 1091a of the first connection portion 1091 is connected to the active layer pattern of the driving transistor T3 through the second via hole K2, and the second end 1091b of the first connection portion 1091 is connected to the first connection point P through the fourth via hole K4. The second via hole K2 connects the first source-drain metal layer 109 and the first active film layer 103, and the fourth via hole K4 connects the first source-drain metal layer 109 and the second active film layer 103.

[0132] like Figure 5A and Fig.6I As shown, the first source-drain metal layer 109 further includes an isolation pattern G1. Figure 5A and Fig. 7E As shown, the orthographic projection of the isolation pattern G1 on the base substrate 101 is located between the orthographic projection of the first connection portion 1091 on the base substrate 101 and the orthographic projection of the connection end Dt1 of the data signal line Dt on the base substrate 101, and the isolation pattern G1 transmits a voltage-stabilized signal. Exemplarily, the isolation pattern G1 transmits a first voltage signal vdd.

[0133] For example, Fig.6I As shown, the first source-drain metal layer 109 includes a data line switching pattern SR. Figure 6I to Figure 6L As shown, the connection end Dt1 of the data signal line Dt is connected to the data line transfer pattern SR through a portion of the third via hole K3. Figure 6B , Figure 6G , Fig.6I As shown, the data line switching pattern SR is connected to the active layer pattern of the write transistor T4 through another portion of the third via hole K3.

[0134] It is understandable that, according to the foregoing content, if Figure 5A As shown, Figure 6J and Figure 6K As shown, a passivation layer 110 and a first flat layer 111 are disposed between the first source-drain metal layer 109 and the second source-drain metal layer 112, wherein an upper third via K31 is disposed on the first flat layer 111, and a middle third via K32 is disposed on the passivation layer 110, and the upper third via K31 and the middle third via K32 are located opposite to each other. Figure 6L The connection end Dt1 of the data signal line Dt is connected to the data line transfer pattern SR located in the first source-drain metal layer 109 through the upper third via hole K31 and the middle third via hole K32. Figure 6GAs shown, a first type via group K is provided between the first source-drain metal layer 109 and the first active film layer 103, and the first type via group K penetrates the film layer between the first source-drain metal layer 109 and the first active film layer 103. The first type via group K includes a lower third via K33, which is directly opposite to the upper third via K31 and the middle third via K32, forming a third via K3. Figure 6B , Figure 6G , Fig.6I The data line switching pattern SR is connected to the active layer pattern of the write transistor T4 located in the first active film layer 103 through the lower third via K33 penetrating the first type via group K, so as to ensure that the write transistor T4 receives the data signal transmitted by the data signal line Dt.

[0135] By setting a data line switching pattern SR in the first source-drain metal layer 109 , the data line switching pattern SR connects the second source-drain metal layer 112 and the first active film layer 103 , thereby connecting the data signal line Dt to the write transistor T4 to achieve data signal transmission.

[0136] For example, Figure 6G As shown, the first type via group K also includes a second via K2, combined with Figure 6B and Fig.6I , Fig.7D , the first end 1091a of the first connection portion 1091 is connected to the active layer pattern of the driving transistor T3 through the second via hole K2; Figure 6H As shown, a second type via group O is provided between the first source-drain metal layer 109 and the second active film layer 106, and the second type via group O includes a fourth via K4. Fig.6I , Fig. 6E , Fig.7D , the second end 1091b of the first connection portion 1091 is connected to the first connection point P through the fourth via K4, and the first connection point P is connected to the first reset transistor T1 and the compensation transistor T2. Thus, the driving transistor T3 located in different active film layers is electrically connected to the first reset transistor T1 and the compensation transistor T2 through the first connection portion 1091. The positions of the first connection portion 1091, the second via K2 and the fourth via K4 can be analogous to Figure 4A The position of the first node N1 in .

[0137] For example, refer to Fig.6I and Fig. 7EThe first source-drain metal layer 109 also includes an isolation pattern G1, wherein the orthographic projection of the isolation pattern G1 on the base substrate 101 is located between the orthographic projection of the first connection portion 1091 on the base substrate 101 and the orthographic projection of the connection end Dt1 of the data signal line Dt on the base substrate 101. This arrangement can isolate the signal transmitted by the data signal line Dt from the signal transmitted by the first connection portion 1091 in a direction perpendicular to the base substrate 101, thereby avoiding crosstalk and other adverse phenomena caused by the jump of the signal transmitted by the data signal line Dt on the voltage of the first connection portion 1091, and has the function of stabilizing the voltage, thereby improving the voltage stability of the first node N1 in the pixel driving circuit, so that the driving current generated by the driving transistor is not affected by the jump of the data signal, thereby improving the display effect.

[0138] In some embodiments, reference Fig.6I and Fig. 7E , the isolation pattern G1 is connected to the second portion 12b.

[0139] It is understandable that, referring to Fig. 7E , Fig. 7E The isolation pattern G1 shown is connected to the second portion 12b, that is, the isolation pattern G1 and the second portion 12b can transmit the same signal, namely, the first voltage signal vdd. In this way, on the basis of making the isolation pattern G1 play a voltage stabilizing role, there is no need to introduce additional voltage stabilizing signal lines, simplifying the film layer structure, and at the same time, the isolation pattern G1 and the first voltage signal line 12 can be formed in one preparation process, simplifying the preparation process of the array substrate.

[0140] In some embodiments, reference Figure 4A and Figure 6B , the pixel driving circuit 200 further includes a first light emission control transistor T5, and the first active film layer 103 further includes an active layer pattern of the first light emission control transistor T5; the active layer pattern of the driving transistor T3, the active layer pattern of the writing transistor T4 and the active layer pattern of the first light emission control transistor T5 are connected to the second connection point Q. Fig. 7E As shown, the second connection point Q overlaps with the orthographic projection of the data signal line Dt on the base substrate 101 , and the second connection point Q overlaps with the orthographic projection of the second portion 12 b on the base substrate 101 .

[0141] For example, refer to Figure 4A , Figure 5A , Figure 6B and Fig. 7EAccording to the above and the foregoing contents, the first active film layer 103 includes an active layer pattern of the driving transistor T3, an active layer pattern of the writing transistor T4, and an active layer pattern of the first light-emitting control transistor T5, and the active layer pattern of the driving transistor T3, the active layer pattern of the writing transistor T4, and the active layer pattern of the first light-emitting control transistor T5 are connected to the second connection point Q. It can be seen that the second connection point Q is also located in the first active film layer 103, and there is a first source-drain metal between the first active film layer 103 and the second source-drain metal layer 112. Layer 109, the second connection point Q is set to overlap with the orthographic projection of the data signal line Dt on the base substrate 101, and the second connection point Q and the orthographic projection of the second part 12b on the base substrate 101 overlap, that is, the second part 12b located in the first source-drain metal layer 109 can play a certain role in shielding the signal between the second connection point Q and the data signal line Dt, reduce the adverse effect of the jump of the signal transmitted by the data signal line Dt on the voltage of the second connection point Q, and thus ensure the consistency of the voltage on the writing path of the data signal line Dt.

[0142] In some embodiments, continue to refer to Figure 5A , Fig.6D , Fig. 7E and Figure 7F , the second connection point Q overlaps with the orthographic projection of the first conductive pattern 11 a on the base substrate 101 .

[0143] It can be understood that, in combination with the above description, reference Figure 5A , Fig.6D and Fig. 7E A second gate metal layer 105 is provided between the first active film layer 103 and the second source-drain metal layer 112. The second connection point Q is arranged to overlap with the positive projection of the first conductive pattern 11a on the base substrate 101, that is, the first conductive pattern 11a located in the second gate metal layer 105 can also play a certain role in shielding the signal between the second connection point Q and the data signal line Dt, thereby reducing the adverse effect of the jump of the signal transmitted by the data signal line Dt on the voltage of the second connection point Q, thereby ensuring the consistency of the voltage on the writing path of the data signal line Dt.

[0144] In some embodiments, reference Figure 6G and Fig.6I The first source-drain metal layer 109 includes a second initialization signal line Vin2, the second initialization signal line Vin2 extends along the first direction X, and the first type via group K also includes a seventh via K7, the second initialization signal line Vin2 is connected to the active layer pattern of the second reset transistor T7 through the seventh via K7 in the first type via group K, so that the second reset transistor T7 receives the initialization signal transmitted by the second initialization signal line Vin2.

[0145] In some embodiments, continue to refer to Figure 6G , Fig.6I , Fig.7D and Fig. 7E The first source-drain metal layer 109 includes a first transfer pattern R1, wherein the first transfer pattern R1 of the first source-drain metal layer 109 is connected to the active layer pattern of the second light-emitting control transistor T6 of the first active film layer 103 through the eighth via K8 penetrating the first type via group K, and the light-emitting control signal line EM passes through the first transfer pattern R1 and the active layer pattern of the second light-emitting control transistor T6.

[0146] In some embodiments, continue to refer to Fig. 6E , Figure 6G , Figure 6H , Fig.6I , Fig.7D and Fig. 7E The first source-drain metal layer 109 includes a second transfer pattern R2, wherein the second transfer pattern R2 is connected to the active layer pattern of the compensation transistor T2 of the second active film layer 106 through the ninth via K9 penetrating the second type via group O, and the second transfer pattern R2 is also connected to the active layer pattern of the second light-emitting control transistor T6 of the first active film layer 103 through the tenth via K10 penetrating the first type via group O, so that the compensation transistor T2 is electrically connected to the second light-emitting control transistor T6.

[0147] In some embodiments, reference Fig. 6E , Figure 6G , Figure 6H , Fig.6I , Fig.7D and Fig. 7E The first source-drain metal layer 109 includes a third transfer pattern R3, wherein the third transfer pattern R3 is connected to the active layer pattern of the first reset transistor T1 of the second active film layer 106 through the eleventh via K11 penetrating the second type via group O, and at the same time, the third transfer pattern R3 is connected to the first initialization signal line Vin1 of the second gate metal layer 105 through the twelfth via K12 penetrating the first type via group K, so that the first reset transistor T1 receives the initialization signal transmitted by the first initialization signal line Vin1.

[0148] In some embodiments, reference Figure 6B , Fig.6D , Figure 6G and Fig.7D The second portion 12b of the first source-drain metal layer 109 is connected to the first light-emitting control transistor T5 of the first active film layer 103 through the thirteenth via hole K13 penetrating the first type via hole group K, and the light-emitting control signal line EM passes through the active layer pattern of the first light-emitting control transistor T5.

[0149] The embodiment of the present disclosure further provides a display panel 100, which includes the array substrate 10 provided by any of the above embodiments. Therefore, the display panel 100 provided by the present invention has all the beneficial effects of the array substrate 10 provided by any of the above embodiments, which will not be described in detail here.

[0150] In some embodiments, reference Figure 5A The display panel 100 also includes a light-emitting device layer and a packaging layer arranged on the array substrate 10. The array substrate 10 includes: a base substrate 101 and a pixel driving circuit stack 20. The pixel driving circuit stack 20 includes a plurality of transistors. The light-emitting device layer and the packaging layer are sequentially stacked on the pixel driving circuit stack 20.

[0151] The light-emitting device layer includes an anode layer 114 , a pixel defining layer 115 , a light-emitting layer 116 and a cathode layer 117 which are arranged on the second planar layer 113 .

[0152] In some embodiments, reference Figure 6N , Figure 7G and Fig. 8A The anode layer 114 includes a plurality of anodes 1141, each anode 1141 is connected to a pixel driving circuit 200; the display panel 100 includes a plurality of pixel regions A, the pixel region A includes three sub-pixel regions A1 arranged in sequence along a row direction, the three sub-pixel regions A1 are respectively a first sub-pixel region A11, a second sub-pixel region A12 and a third sub-pixel region A13, in one pixel region A, the anode 1141 includes a first anode 1141a, a second anode 1141b and a third anode 1141c.

[0153] The array substrate 10 also includes a second source-drain metal layer 112, which includes a plurality of second voltage signal lines 14 extending along a second direction Y; the orthographic projections of the first anode 1141a and the second anode 1141b on the base substrate 101 overlap with the second voltage signal line 14 located in the first sub-pixel area A11.

[0154] The second source-drain metal layer 112 also includes a plurality of second voltage signal lines 14 extending along the second direction Y. Fig. 8A It can be obtained that the orthographic projections of the first anode 1141a and the second anode 1141b on the substrate 101 overlap with the second voltage signal line 14 located in the first sub-pixel area A11, which can improve the space utilization rate of the pixel area A. At the same time, compared with the case where the orthographic projections of the first anode 1141a and the second anode 1141b on the substrate 101 do not overlap with the second voltage signal line 14 located in the first sub-pixel area A11, there is no additional loss of light transmittance.

[0155] In some embodiments, continue to refer to Figure 6L and Fig. 8A , in the first sub-pixel area A11, the second voltage signal line 14 includes a first voltage pattern 141 and a second voltage pattern 142, the ratio of an overlapping area between the first anode 1141a and the first voltage pattern 141 to an area of ​​the first anode 1141a is greater than 90%, and the ratio of an overlapping area between the second anode 1141b and the second voltage pattern 142 to an area of ​​the second anode 1141b is greater than 90%.

[0156] For example, refer to Figure 6N , Fig. 8A and Figure 8B , in the first sub-pixel area A11, the second voltage signal line 14 includes a first voltage pattern 141 and a second voltage pattern 142 arranged along the second direction Y, wherein the first anode 1141a overlaps with the first voltage pattern 141, the second anode 1141b overlaps with the second voltage pattern 142, and the ratio of the overlapping area of ​​the first anode 1141a and the first voltage pattern 141 to the area of ​​the first anode 1141a is greater than 90%, and the ratio of the overlapping area of ​​the second anode 1141b and the second voltage pattern 142 to the area of ​​the second anode 1141b is greater than 90%. It can be understood that, for example, the overlapping area between the first anode 1141a and the first voltage pattern 141 is S1, and the area of ​​the first anode 1141a is S3, then S1 / S3>0.9, and S1 is smaller than S3; the overlapping area between the second anode 1141b and the second voltage pattern 142 is S2, and the area of ​​the second anode 1141b is S4, then S2 / S4>0.9, and S2 is smaller than S4.

[0157] The orthographic projection area of ​​the first voltage pattern 141 and the second voltage pattern 142 in the second voltage signal line 14 set above on the base substrate 101 is larger than that of other positions. On the one hand, the resistance of the second voltage signal line 14 can be reduced to reduce the voltage drop of the voltage signal provided by the second voltage signal line 14 during the transmission process, thereby improving the brightness uniformity of the display panel; on the other hand, the first voltage pattern 141 and the second voltage pattern 142 overlap with the first anode 1141a and the second anode 1141b, which can ensure that there is no additional loss of light transmittance. In addition, the first voltage pattern 141 is set below the first anode 1141a, and the second voltage pattern 142 is set below the second anode 1141b, so as to cushion the first anode 1141a and the second anode 1141b and improve the flatness of the film layer of the first anode 1141a and the second anode 1141b.

[0158] In some embodiments, Fig. 8A and Figure 8BAs shown, the second source-drain metal layer 112 includes a plurality of data signal lines Dt extending along the second direction Y; the third anode 1141c overlaps with the data signal line Dt located in the second sub-pixel area A12, the second voltage signal line 14 located in the second sub-pixel area A12, and the second voltage signal line 14 located in the third sub-pixel area A13.

[0159] It is understandable that, referring to Fig. 8A and Figure 8B , Fig. 8A and Figure 8B The third anode 1141c shown in FIG. 1 is partially located in the second sub-pixel region A12 and partially located in the third sub-pixel region A13. In the second sub-pixel region A12, the third anode 1141c overlaps with the data signal line Dt located in the second sub-pixel region A12 and the second voltage signal line 14 located in the second sub-pixel region A12. In the third sub-pixel region A13, the third anode 1141c overlaps with the second voltage signal line 14 located in the third sub-pixel region A13. This arrangement can improve the space utilization of the sub-pixel region A1. At the same time, compared with the case where the third anode 1141c is projected on the base substrate 101 and does not overlap with the data signal line Dt and the second voltage signal line 14, there is no additional loss of light transmittance.

[0160] For example, refer to Figure 8B , the third anode 1141c is symmetrical about the data signal line Dt, that is, the first distance between the first boundary of the third anode 1141c on one side of the data signal line Dt and the data signal line Dt in the first direction X is equal to the second distance between the second boundary of the third anode 1141c on the other side of the data signal line Dt and the data signal line Dt in the first direction X; at the same time, the area of ​​the portion where the third anode 1141c overlaps with the second voltage signal line 14 located in the second sub-pixel area A12 is the first area, and the area of ​​the portion where the third anode 1141c overlaps with the second voltage signal line 14 located in the third sub-pixel area A13 is the second area, and the first area and the second area are approximately equal. In this arrangement, the portions of the third anode 1141c located on both sides of the data signal line Dt are padded by the second voltage signal line 14, which can ensure the flatness of the surface of the third anode 1141c and the stability of signal transmission.

[0161] In some embodiments, Figure 5A As shown, the display panel 100 further includes a second flat layer 113 disposed on the array substrate 10 and between the anode layer 114 and a pixel defining layer 115 disposed on a side of the anode layer 114 away from the base substrate 101. Fig.6O , a plurality of pixel openings 1151 are disposed on the pixel defining layer 115 , and the pixel openings 1151 expose a portion of the corresponding anode 1141 ;

[0162] like Figure 5B and Fig. 9 As shown, the second source-drain metal layer 112 of the third sub-pixel region A13 includes a bridge pattern L, and the third anode 1141 includes an anode connection portion 11411, and the anode connection portion 11411 is connected to the bridge pattern L through a sixth via hole K6 penetrating the second planar layer 113;

[0163] like Figure 5B As shown, the second planar layer 113 has a climbing area C1 around the sixth via hole K6 , and an angle exists between the surface of the portion of the second planar layer 113 located in the climbing area C1 and the base substrate 101 .

[0164] The distance between the orthographic projection of the pixel opening 1151 corresponding to the third anode 1141c on the substrate 101 and the orthographic projection of the anode connecting portion 11411 on the substrate 101 in a set direction is greater than the size of the orthographic projection of the climbing area C1 on the substrate 101 in the set direction, and the set direction is parallel to the substrate 101.

[0165] For example, refer to Fig. 8A and Fig. 9 , there are multiple pixel openings 1151 on the pixel defining layer 115. It can be seen from FIG. 8A that the orthographic projection area of ​​each pixel opening 1151 on the base substrate 101 is smaller than the orthographic projection area of ​​the corresponding anode 1141 exposed on the base substrate 101, that is, the pixel opening 1151 exposes a portion of the corresponding anode 1141.

[0166] For example, Fig.6I , Figure 6J , Figure 6K , Figure 6L and Fig. 8A As shown, according to the foregoing content, the second source-drain metal layer 112 includes a plurality of bridge patterns L, and three bridge patterns L are provided in each pixel area A, namely, a first bridge pattern L1, a second bridge pattern L2, and a third bridge pattern L3, wherein the first anode 1141a, the second anode 1141b, and the third anode 1141c are respectively connected to the first bridge pattern L1, the first bridge pattern L2, and the first bridge pattern L3 through via holes penetrating the second flat layer 113, and the first bridge pattern L1 is connected to the first transfer pattern R1 located on the first sub-pixel area A11 of the first source-drain metal layer 109 through a fourteenth via K141 provided on the passivation layer 110 and a fourteenth via K142 on the first flat layer 111, and the first transfer pattern R1 is connected to the first sub-pixel area A11 of the first source-drain metal layer 109. Figure 6B and Figure 7GThe first transfer pattern R1 is connected to the active layer pattern of the second light-emitting control transistor T6 of the first active film layer 103 through the eighth via hole K8 in the first type via hole group K, thereby realizing the connection between the first anode 1141a and the second light-emitting control transistor T6; the second bridge pattern L2 is connected to the first transfer pattern R1 located on the second sub-pixel area A12 of the first source-drain metal layer 109 by penetrating the fifteenth via hole K151 provided on the passivation layer 110 and the fifteenth via hole K152 on the first flat layer 111, Figure 6B and Figure 7G The first transfer pattern R1 in the second sub-pixel area A12 is connected to the active layer pattern of the second light-emitting control transistor T6 of the first active film layer 103 through the eighth via hole K8 in the first type of via hole group K, thereby realizing the connection between the second anode 1141b and the second light-emitting control transistor T6; the third bridge pattern L3 is connected to the first transfer pattern R1 located on the third sub-pixel area A13 of the first source-drain metal layer 109 by penetrating the sixteenth via hole K161 provided on the passivation layer 110 and the sixteenth via hole K162 on the first flat layer 111, and the third bridge pattern L3 is connected to the first transfer pattern R1 located on the third sub-pixel area A13 of the first source-drain metal layer 109. Figure 6B and Figure 7G The first transfer pattern R1 in the third sub-pixel area A13 is connected to the active layer pattern of the second light-emitting control transistor T6 of the first active film layer 103 through the eighth via K8 in the first type via group K, thereby realizing the connection between the second anode 1141b and the second light-emitting control transistor T6.

[0167] The anode connection portion 11411 contacts the bridge pattern L through a sixth via hole K6 penetrating the second planar layer 113 , and the bridge pattern L is a third bridge pattern L3 .

[0168] It is understandable that, referring to Figure 5B and Fig. 9 , Figure 5B for Fig. 9 The cross-sectional structure diagram obtained by making a cross section along the cross-sectional line EE, combined with Figure 6M The second flat layer 113 has a climbing area C1 around the sixth via hole K6, that is, the second flat layer 113 is not flat around the sixth via hole K6, and in the climbing area C1, the surface of the second flat layer 113 has an arc-shaped transition. Therefore, there is a certain angle between the surface of the second flat layer 113 and the plane where the base substrate 101 is located, and the angle ranges from 0° to 90°, for example, 0°, 30°, 60°, 90°, etc.

[0169] It should be noted that, continue to refer to Figure 5B and Fig. 9, a distance D1 in a set direction between an orthographic projection of the pixel opening 1151 corresponding to the third anode 1141c on the substrate 101 and an orthographic projection of the anode connecting portion 11411 on the substrate 101 is greater than a dimension D2 of an orthographic projection of the climbing area C1 on the substrate 101 in a set direction, wherein D2 is, for example, 2.5um to 3um, and the set direction is parallel to the substrate 101. Exemplarily, the set direction may be any direction parallel to the surface of the substrate 101. Figure 5B The setting direction shown is only an example. The setting direction is, for example, the first direction X. Therefore, the obtained distance D1 is the shortest distance.

[0170] Continue to refer to Figure 5B and Fig. 9 , it can be obtained that the boundary of the pixel opening 1151 corresponding to the third anode 1141c is an arc transition compared to the first anode 1141a and the second anode 1141b, and Fig. 9 The orthographic projection of the pixel opening 1151 corresponding to the third anode 1141c on the substrate 101 is not a rectangle, but an anisotropic structure. By setting the structure of the pixel opening 1151 corresponding to the third anode 1141c and limiting the distance from the anode connecting portion 11411, the flatness of the position corresponding to the pixel opening 1151 area can be guaranteed. The light-emitting layer 116 is arranged in the pixel opening 1151 area, so that the influence of the climbing area C1 of the second flat layer 113 on the flatness of the light-emitting layer 116 at the periphery of the sixth via hole K6 can be avoided, and the undesirable problem of asymmetric color deviation of the sub-pixels in the third sub-pixel area A13 can be further avoided, and the display effect of the display panel can be improved.

[0171] Continue to refer to Figure 5A The light-emitting layer 116 includes a plurality of light-emitting portions, each of which overlaps with an anode 1141. A plurality of pixel openings are formed in the pixel defining layer 115, each of which exposes a portion of an anode 1141. The light-emitting portions in the light-emitting layer 116 are disposed in the pixel openings 1151 in a one-to-one correspondence, so that the edges of the light-emitting portions overlap with the edges of the pixel openings 1151.

[0172] The cathode layer 117 is located on a side of the pixel defining layer 115 and the light emitting layer 116 away from the array substrate 10 .

[0173] In some embodiments, reference Figure 3 and Figure 5AThe light emitting device OLED includes an anode 1141 and a cathode, and a light emitting layer 116 sandwiched between the anode 1141 and the cathode. Voltage is applied to the anode and the cathode respectively to generate an electric field between the two, which can drive the holes in the anode 1141 and the electrons in the cathode to recombine in the light emitting layer, so that the light emitting layer 116 emits light. Among them, the anode 1141 is arranged on the array substrate 10 and can be electrically connected to the pixel driving circuit 200.

[0174] The display panel 100 may further include a spacer PS, and the spacer PS is used to support a Fine Metal Mask (FMM) when evaporating the light-emitting layer.

[0175] The encapsulation layer is located on the side of the cathode layer 117 away from the array substrate 10. Exemplarily, the encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer. The encapsulation layer is used to encapsulate the light-emitting device to protect the light-emitting device OLED and avoid corrosion caused by external water and oxygen.

[0176] Some embodiments of the present disclosure provide a display device 1000, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a car computer, a wearable display device, etc. The embodiments of the present disclosure do not impose any particular restrictions on the specific form of the above display device. Figure 1 As shown, the display device 1000 includes the display panel 100 provided by any of the above embodiments. Therefore, the display device 1000 provided by the present invention has all the beneficial effects of the display panel 100 provided by any of the above embodiments, which will not be described in detail here.

[0177] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An array substrate, characterized in that: include: A plurality of sub-pixel regions arranged in an array, a row of sub-pixel regions arranged along a first direction, a column of sub-pixel regions arranged along a second direction, and the first direction and the second direction intersect; A pixel driving circuit is arranged in the sub-pixel region, and the pixel driving circuit includes a capacitor; The array substrate comprises: substrate substrate; A second gate metal layer is provided on one side of the base substrate, the second gate metal layer includes a plurality of conductive connection lines extending along the first direction, the conductive connection lines include a plurality of first conductive patterns and a plurality of second conductive patterns alternately connected along the first direction, the first conductive pattern is a first electrode plate of the capacitor; A first source-drain metal layer is disposed on a side of the second gate metal layer away from the substrate, the first source-drain metal layer includes a plurality of first voltage signal lines extending along the first direction, the first voltage signal lines include a plurality of first portions and a plurality of second portions alternately connected along the first direction; The second conductive pattern overlaps with the first portion, and the conductive connecting line is connected to the first voltage signal line.

2. The array substrate according to claim 1, characterized in that: The first portion includes a first sub-portion and a second sub-portion, the first sub-portion has no overlap with the orthographic projection of the first conductive pattern on the base substrate, and the orthographic projection of the second sub-portion on the base substrate is located within the orthographic projection of the first conductive pattern on the base substrate; An orthographic projection of the first sub-portion on the base substrate coincides with an orthographic projection of the second conductive pattern on the base substrate.

3. The array substrate according to claim 1, characterized in that: The second portion overlaps with the first conductive pattern, and the second portion is electrically connected to the first conductive pattern through at least two first vias.

4. The array substrate according to claim 1, characterized in that: Also includes: A light-shielding layer is arranged between the base substrate and the second gate metal layer, and the light-shielding layer includes a plurality of light-shielding metal traces extending along the first direction; the light-shielding metal traces include a plurality of light-shielding patterns and a plurality of first connection patterns alternately connected along the first direction, and the first connection pattern overlaps with the orthographic projection of the second conductive pattern on the base substrate.

5. The array substrate according to claim 4, characterized in that: The first connection pattern includes a first sub-connection pattern, and the first sub-connection pattern has no overlap with the orthographic projection of the first conductive pattern on the base substrate; An orthographic projection of the first connection pattern on the base substrate coincides with an orthographic projection of the second conductive pattern on the base substrate.

6. The array substrate according to claim 4, characterized in that: The pixel driving circuit includes a driving transistor, a writing transistor, a first reset transistor and a compensation transistor; The array substrate further includes: A first active film layer disposed between the light shielding layer and the second gate metal layer; the first active film layer includes an active layer pattern of the driving transistor and an active layer pattern of the writing transistor; a second active film layer disposed between the second gate metal layer and the first source-drain metal layer; the first active film layer includes an active layer pattern of a first reset transistor and an active layer pattern of a compensation transistor, and the active layer pattern of the first reset transistor and the active layer pattern of the compensation transistor are connected to a first connection point; A second source-drain metal layer is disposed on a side of the first source-drain metal layer away from the substrate; the second source-drain metal layer includes a plurality of data signal lines; the connection end of the data signal line is connected to the active layer pattern of the write transistor through a third via hole; The first source-drain metal layer further includes a first connection portion, a first end of the first connection portion is connected to the active layer pattern of the driving transistor through a second via hole, and a second end of the first connection portion is connected to the first connection point through a fourth via hole; The first source-drain metal layer also includes an isolation pattern, the orthographic projection of the isolation pattern on the base substrate is located between the orthographic projection of the first connection portion on the base substrate and the orthographic projection of the connection end of the data signal line on the base substrate, and the isolation pattern transmits a regulated voltage signal.

7. The array substrate according to claim 6, characterized in that: The isolation pattern is connected to the second portion.

8. The array substrate according to claim 6, characterized in that: The pixel driving circuit further includes a first light emission control transistor, and the first active film layer further includes an active layer pattern of the first light emission control transistor; The active layer pattern of the driving transistor, the active layer pattern of the writing transistor and the active layer pattern of the first light emission control transistor are connected to a second connection point; The second connection point overlaps with an orthographic projection of the data signal line on the base substrate, and the second connection point overlaps with an orthographic projection of the second portion on the base substrate.

9. The array substrate according to claim 8, characterized in that: The second connection point overlaps with an orthographic projection of the first conductive pattern on the base substrate.

10. The array substrate according to claim 6, characterized in that: The second source-drain metal layer further includes a plurality of second voltage signal lines extending along the second direction. In the sub-pixel region, one of the second voltage signal lines is connected to one of the first voltage signal lines through a fifth via hole.

11. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 10.

12. The display panel according to claim 11, characterized in that: The display panel further includes: An anode layer is provided on the array substrate, the anode layer comprising a plurality of anodes; each anode is connected to a pixel driving circuit; The display panel includes a plurality of pixel regions, the pixel region includes three sub-pixel regions sequentially arranged along a row direction, the three sub-pixel regions are respectively a first sub-pixel region, a second sub-pixel region and a third sub-pixel region, and the anode includes a first anode, a second anode and a third anode; The array substrate further comprises a second source-drain metal layer, wherein the second source-drain metal layer comprises a plurality of second voltage signal lines extending along a second direction; The orthographic projections of the first anode and the second anode on the base substrate overlap with the second voltage signal line located in the first sub-pixel region.

13. The display panel according to claim 12, characterized in that: In the first sub-pixel area, the second voltage signal line includes a first voltage pattern and a second voltage pattern, the ratio of an overlapping area between the first anode and the first voltage pattern to an area of ​​the first anode is greater than 90%, and the ratio of an overlapping area between the second anode and the second voltage pattern to an area of ​​the second anode is greater than 90%.

14. The display panel according to claim 12, characterized in that: The second source-drain metal layer includes a plurality of data signal lines extending along a second direction; The third anode overlaps with the data signal line located in the second sub-pixel region, the second voltage signal line located in the second sub-pixel region, and the second voltage signal line located in the third sub-pixel region.

15. The display panel according to claim 12, characterized in that: Also includes: A second planar layer disposed on the array substrate and between the anode layer; A pixel defining layer is disposed on a side of the anode layer away from the substrate, wherein a plurality of pixel openings are disposed on the pixel defining layer, and the pixel openings expose a portion of the corresponding anode; The second source-drain metal layer of the third sub-pixel region includes a bridge pattern, the third anode includes an anode connecting portion, and the anode connecting portion is connected to the bridge pattern through a sixth via hole penetrating the second planar layer; The second flat layer has a climbing area at the periphery of the sixth via hole, and an angle exists between the surface of the portion of the second flat layer located in the climbing area and the substrate; A distance in a set direction between an orthographic projection of a pixel opening corresponding to the third anode on the substrate and an orthographic projection of the anode connection portion on the substrate is greater than a size of an orthographic projection of the climbing area on the substrate in the set direction, and the set direction is parallel to the substrate.

16. A display device, characterized in that: include: The display panel according to any one of claims 11 to 15.

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