Display device

Abstract

The present disclosure provides a display device including: a substrate on which a plurality of sub-pixels are defined, each sub-pixel including a light emitting area and a non-light emitting area; an overcoat layer disposed on the substrate and having a plurality of microlenses, the plurality of microlenses including a recessed portion and a connecting portion in the light emitting region; a first electrode disposed on the overcoat layer; a bank layer exposing a portion of the first electrode on the overcoat layer and defining the light emitting region; a light emitting layer covering the first electrode exposed by the bank layer; and a second electrode disposed on the light emitting layer, wherein the bank layer includes a first bank region disposed adjacent to at least a portion of the light emitting region and having a first thickness, and a second bank region having a second thickness greater than the first thickness.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0127003 filed in the Korean Intellectual Property Office on September 22, 2023, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device in which the thickness of a bank layer can be varied according to a position, thereby suppressing the occurrence of field brightness deviation and spots and improving a charging rate at a low grayscale. Background Art

[0004] Display devices that visually display electrical information signals have been rapidly developed with the advent of the information age. Various studies are being conducted to develop various display devices that are thin and lightweight, consume low power, and have improved performance.

[0005] As representative display devices, there are liquid crystal display (LCD) devices, field emission display (FED) devices, electrowetting display (EWD) devices, organic light emitting display (OLED) devices, and the like.

[0006] As a representative organic light-emitting display device, an electroluminescent display device refers to a display device that emits light autonomously. Unlike a liquid crystal display device, an electroluminescent display device does not require a separate light source, so a lightweight and thin display device can be manufactured. In addition, since the electroluminescent display device operates at a low voltage, the electroluminescent display device is advantageous in terms of power consumption. In addition, since the electroluminescent display device is also excellent in achieving color, response speed, viewing angle, and contrast (CR), the electroluminescent display device is expected to be used in various fields. Summary of the invention

[0007] Technical problem to be solved by the invention

[0008] An object to be achieved by the present disclosure is to provide a display device capable of suppressing the occurrence of field brightness degradation and spots and improving the charging rate at low grayscale.

[0009] Another object to be achieved by the present disclosure is to provide a display device with an improved aperture ratio.

[0010] Still another object to be achieved by the present disclosure is to provide a display device having improved reliability by suppressing the penetration of moisture into the periphery of the device.

[0011] The objects of the present disclosure are not limited to the above objects and other objects not mentioned above may be clearly understood by those skilled in the art from the following description.

[0012] Means of solving the problem

[0013] In one aspect of the present disclosure, a display device is provided, comprising: a substrate on which a plurality of sub-pixels are defined, each sub-pixel including a light-emitting region and a non-light-emitting region; an outer coating layer disposed on the substrate and having a plurality of micro-lenses, the plurality of micro-lenses including a concave portion and a connection portion in the light-emitting region; a first electrode disposed on the outer coating layer; a bank layer, the bank layer exposing a portion of the first electrode on the outer coating layer and defining the light-emitting region; a light-emitting layer, the light-emitting layer covering the first electrode exposed by the bank layer; and a second electrode disposed on the light-emitting layer, wherein the bank layer comprises: a first bank region, the first bank region being disposed adjacent to at least a portion of the light-emitting region and having a first thickness; and a second bank region, the second bank region having a second thickness greater than the first thickness. Therefore, applying different thicknesses to the bank layers in the first and second bank regions can suppress the deterioration of field brightness and the occurrence of spots, and improve the charging rate at low grayscales.

[0014] Additional details of example embodiments are included in the detailed description and the accompanying drawings.

[0015] Technical Effects

[0016] According to the present disclosure, the thickness of the bank layer at a position adjacent to at least a portion of the light-emitting region in the display panel is less than the thickness of the bank layer in the region other than the region adjacent to the light-emitting region. Therefore, the occurrence of viewing differences between the fields of view can be suppressed, the deviation of the field of view brightness and the occurrence of spots can be minimized, and the charging rate at low grayscale can be improved.

[0017] In addition, according to the present disclosure, for each sub-pixel, a different thickness is applied to the partition layer on the repair portion set between the light-emitting area and the non-light-emitting area, which can minimize the impact on normal sub-pixels adjacent to the defective sub-pixel during the repair process, maximize the aperture ratio, and improve the afterimage performance.

[0018] In addition, according to the present disclosure, a groove pattern is formed in a non-display area of ​​a display panel, which can suppress the penetration of moisture into the display panel.

[0019] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0021] Figure 1 is a block diagram of a display device according to an embodiment of the present disclosure;

[0022] Figure 2 is a circuit diagram of a pixel of a display device according to an embodiment of the present disclosure;

[0023] Figure 3 yes Figure 2 Schematic top view of a pixel in FIG.

[0024] Figure 4 is a schematic cross-sectional view of a light emitting region of a sub-pixel;

[0025] Figure 5 is along Figure 3 A cross-sectional view taken along line V-V';

[0026] Figure 6 is along Figure 3 A cross-sectional view taken along line VI-VI';

[0027] Figure 7 is along Figure 3 A cross-sectional view taken along line VII-VII';

[0028] Figure 8 is along Figure 3 A cross-sectional view taken along line VIII-VIII' in FIG.

[0029] Fig. 9 is along Figure 1 A cross-sectional view taken along line IX-IX'. DETAILED DESCRIPTION

[0030] By referring to the exemplary embodiments described in detail below and the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving these advantages and features will be clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only as examples so that those skilled in the art can fully understand the content disclosed by the present disclosure and the scope of the present disclosure.

[0031] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, in the following description of the present disclosure, a detailed explanation of known related art may be omitted to avoid making the subject matter of the present disclosure unnecessarily difficult to understand. Terms such as "including", "having" and "consisting of..." used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". Unless otherwise expressly stated, any reference to the singular may include the plural.

[0032] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0033] When terms such as "on," "over," "below," and "beside" are used to describe the positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used together with the terms "immediately next to" or "directly."

[0034] When an element or layer is referred to as being “on” another element or layer, the other layer or element may be directly on or interposed between the other element.

[0035] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below may be the second component in the technical concept of the present disclosure.

[0036] Throughout the specification, like reference numerals generally refer to like elements.

[0037] For convenience of description, the size and thickness of each component shown in the drawings are illustrated, and the present disclosure is not limited to the size and thickness of the components shown.

[0038] The features of the various embodiments of the present disclosure may be partially or completely coupled or combined with each other, may be technically interlocked and operated in various ways, and the embodiments may be performed independently or in association with each other.

[0039] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0040] Figure 1 is a block diagram of a display device according to an embodiment of the present disclosure.

[0041] refer to Figure 1, the display device 100 of the embodiment of the present disclosure may include an image processing part 151, a timing controller 152, a data driving part 153, a gate driving part 154, and a display panel DP.

[0042] In this case, the image processing part 151 may output a data signal DATA and a data enable signal DE provided from the outside, etc. The image processing part 151 may output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal in addition to the data enable signal DE.

[0043] The timing controller 152 receives a data signal DATA in addition to a data enable signal DE or a driving signal including a vertical synchronization signal, a horizontal synchronization signal, and a clock signal from the image processing part 151. Based on the driving signal, the timing controller 152 may output a gate timing control signal GDC for controlling the operation timing of the gate driving part 154, and output a data timing control signal DDC for controlling the operation timing of the data driving part 153.

[0044] In addition, in response to the data timing control signal DDC provided from the timing controller 152, the data driving part 153 can sample and latch the data signal DATA provided from the timing controller 152, convert the data signal DATA into a gamma reference voltage, and output the gamma reference voltage. The data driving part 153 can output the data signal DATA through the data lines DL1 to DLn.

[0045] In addition, the gate driving part 154 may output a gate signal while shifting the level of a gate voltage in response to the gate timing control signal GDC provided from the timing controller 152. The gate driving part 154 may output the gate signal through the gate lines GL1 to GLm.

[0046] When the pixels P emit light in response to the data signals DATA and the gate signals provided from the data driving part 153 and the gate driving part 154, the display panel DP may display an image. Figure 4 The detailed structure of the pixel P is described in detail.

[0047] The display panel DP may include a display area AA and a non-display area NA.

[0048] The display area AA is a region of the display panel DP where an image is displayed.

[0049] A plurality of pixels P and a circuit for operating the plurality of pixels P may be provided in the display area AA. The plurality of pixels P are the smallest units constituting the display area AA. A display element may be provided in each of the plurality of pixels P. For example, an organic light emitting element including an anode, a light emitting layer, and a cathode may be provided in each of the plurality of pixels P. However, the present disclosure is not limited thereto. In addition, the circuit for operating the plurality of pixels P may include a driving element, a circuit, and the like. For example, the circuit may include a thin film transistor, a storage capacitor, a gate line, a data line, and the like. However, the present disclosure is not limited thereto.

[0050] The non-display area NA is an area where no image is displayed.

[0051] The non-display area NA may be bent so that the non-display area NDA is not visible from the front surface. The non-display area NDA may be covered by a housing (not shown). The non-display area NDA is referred to as a bezel area.

[0052] Figure 1 It is shown that the non-display area NA surrounds the display area AA having a quadrilateral shape. However, the shapes and arrangements of the display area AA and the non-display area NA are not limited to Figure 1 That is, the display area AA and the non-display area NA may be suitable for the design of an electronic device equipped with the flexible display device 100. For example, an exemplary shape of the display area AA may be a pentagonal shape, a hexagonal shape, a circular shape, an elliptical shape, etc.

[0053] Various lines and circuits for operating the organic light emitting elements in the display area AA may be provided in the non-display area NA. For example, the non-display area NA may include connection lines for transmitting signals to a plurality of sub-pixels and circuits in the display area AA. The non-display area NDA may include a gate in panel (GIP) line or a driving IC such as a gate driving portion 154 and a data driving portion 153. However, the present disclosure is not limited thereto.

[0054] The display device 100 may also include various additional elements configured to generate various signals or operate pixels in the display area AA. Additional elements for operating pixels may include inverter circuits, multiplexers, electrostatic discharge (ESD) circuits, etc. The display device 100 may also include additional elements related to functions other than the function of operating pixels. For example, the display device 100 may also include additional elements that provide a touch detection function, a user authentication function (e.g., fingerprint recognition), a multi-level pressure detection function, a tactile feedback function, etc. The above-mentioned additional elements may be located in the non-display area NA and / or in an external circuit connected to the connection interface.

[0055] In the following, reference will be made to Figure 2The circuit of the pixel P of the display device 100 is described in more detail.

[0056] Figure 2 is a circuit diagram of a pixel of a display device according to an embodiment of the present disclosure.

[0057] refer to Figure 2 The pixel circuit is connected to a data line DL supplied with a data voltage Vdata, a reference voltage line RL supplied with a reference voltage Vref, and a gate line GL supplied with a scan signal Vscan. The scan signal Vscan is a signal swinging between a gate high voltage VGH and a gate low voltage VGL.

[0058] The pixel P includes a light emitting element OLED, a driving element DT, a first switching element ST1, a second switching element ST2, and a storage capacitor Cst. The driving element DT and the switching elements ST1 and ST2 may each be implemented as a transistor.

[0059] The light emitting element OLED may be implemented as an OLED including an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, a light emitting layer EML, an electron transport layer ETL, an electron injection layer EIL, etc. However, the present disclosure is not limited thereto. The light emitting element OLED is a light emitting element connected between a low potential driving power supply EVSS and a third node Ns, the third node Ns is connected to a source electrode of a driving element DT, and the light emitting element OLED is configured to emit light according to a driving current. The light emitting element OLED may be configured to display red, green, blue, or white.

[0060] The driving element DT includes a gate electrode connected to a first node Ng, a drain electrode connected to a second node Nd, and a source electrode connected to a third node Ns. The driving element DT operates the light emitting element OLED by adjusting the amount of current applied to the light emitting element OLED in response to a gate-source voltage VGS. A pixel driving voltage VDD may be applied to the drain electrode of the driving element DT.

[0061] The first switching element ST1 includes a gate electrode connected to the gate line GL, a drain electrode connected to the data line DL, and a source electrode connected to the first node Ng. The first switching element ST1 is turned on in response to a scan signal Vscan from the gate line GL. When the first switching element ST1 is turned on, the data line DL to which the data voltage Vdata is applied is electrically connected to the first node Ng, so that the data voltage Vdata is applied to the gate electrode of the driving element DT and the storage capacitor Cst.

[0062] The second switching element ST2 includes a gate electrode connected to the gate line GL, a drain electrode connected to the reference voltage line RL, and a source electrode connected to the third node Ns. The second switching element ST2 is turned on in response to the scan signal Vscan from the gate line GL, and the reference voltage line RL and the third node Ns are electrically connected so that the reference voltage Vref is applied to the third node Ns. The reference voltage Vref is set to a voltage lower than the pixel drive voltage EVDD. At the same time, when it is necessary to sense the electrical characteristics of the driving element DT, the second switching element ST2 can be turned on. In this case, a sensing signal can be applied from the gate driver 13 to the gate electrode of the second switching element ST2. Because the sensing signal can be generated independently of the scan signal Vscan, the on / off timing of the second switching element ST2 can be controlled at the desired sensing time.

[0063] The storage capacitor Cst is connected between the first node Ng and the third node Ns, and maintains the gate-source voltage Vgs of the driving element DT during the light emitting period. As the gate-source voltage Vgs increases, the driving current increases, and the light emission amount of the pixel P increases. That is, the brightness of the pixel P increases in proportion to the size of the voltage (that is, the data voltage Vdata to be applied to the first node Ng).

[0064] Adjacent pixel circuits may be configured to be connected to at least one reference voltage line RL. Figure 2 , but the four pixel circuits can be configured to share one reference voltage line RL. According to the above configuration, the number of reference voltage lines RL can be reduced, and the aperture ratio can be increased. That is, because the number of reference voltage lines RL is reduced, more sub-pixels can be set. Therefore, it is advantageous in terms of improving resolution. However, the present disclosure is not limited thereto. Various modifications can be made to the number of reference voltage lines RL, the number of shared pixels P, and the type of shared pixels P.

[0065] Figure 2 The sub-pixel shown has a 3T (transistor) 1C (capacitor) structure including a first switching element ST1, a second switching element ST2, a driving element DT, a capacitor Cst, and a light emitting element OLED. However, the sub-pixel may have various configurations such as 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, etc.

[0066] In the following, reference will be made to Figure 3 The pixel P of the display device 100 is described in more detail.

[0067] Figure 3 yes Figure 2 Schematic top plan view of a pixel in FIG.

[0068] refer to Figure 3 , the pixel P includes sub-pixels SP each having a light emitting area EA and a non-light emitting area NEA. The sub-pixels SP may be basic light emitting units constituting the display device 100. The sub-pixels SP constituting one pixel P may emit light beams having different colors.

[0069] The sub-pixels SP are arranged along a first direction (e.g., an x-axis direction). For example, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, the third sub-pixel SP3 may be a white sub-pixel, and the fourth sub-pixel SP4 may be a blue sub-pixel. However, the present disclosure is not limited thereto. For example, since the green sub-pixel SP2 and the white sub-pixel SP3 contribute relatively more to the luminous efficiency and brightness, the green sub-pixel SP2 and the white sub-pixel SP3 may have a smaller size than the red sub-pixel SP1 and the blue sub-pixel SP4.

[0070] The emission area EA may include a light emitting element OLED. The non-emission area NEA may include a driving element DT operating the light emitting element OLED, a first switching element ST1, a second switching element ST2, and a storage capacitor Cst. The non-emission area NEA may also be referred to as a circuit portion.

[0071] For example, the emission area EA and the non-emission area NEA are arranged in a second direction (y-axis direction) perpendicular to the first direction (x-axis direction). The light emitting element OLED can emit light by operating a pixel circuit disposed in the non-emission area NEA in each subpixel SP.

[0072] In each sub-pixel SP, the emission area EA may be defined by a bank formed on the anode electrode of the light emitting element OLED, the bank being configured to expose a portion of the anode electrode. That is, the anode electrode exposed by the bank may be defined as the emission area EA of each sub-pixel SP.

[0073] The non-emission area NEA may include a line configured to apply a driving signal to the sub-pixel SP. The line may include a line extending in a first direction (x-axis direction) and a line extending in a second direction (y-axis direction). The pixels P may share the line with each other.

[0074] The wiring extending in the first direction (x-axis direction) may include the gate line GL. The wiring extending in the first direction may intersect the wiring extending in the second direction.

[0075] The lines extending in the second direction (y-axis direction) may include power lines VDD, reference voltage lines RL, and data lines DL. The lines extending in the second direction may pass between sub-pixels SP adjacent to each other in the first direction (x-axis direction) while extending in the second direction.

[0076] The wiring connected to the pixel P and the electrode constituting the transistor may be provided on the same layer or on different layers with one or more insulating layers interposed therebetween. The wiring and the electrode may be electrically connected to each other through a contact hole for electrical connection formed through the insulating layer.

[0077] The data line DL may be connected to the first switching element ST1 in the corresponding sub-pixel SP. The gate line GL may be connected to the first switching element ST1 or the second switching element ST2 in each sub-pixel SP.

[0078] The driving voltage is commonly applied to the pixel circuits in the sub-pixels SP through the power line VDD. The power line VDD may be connected to the driving element DT in each sub-pixel SP.

[0079] The reference voltage Vref applied to the reference voltage line RL is applied to one or more sub-pixels SP through the branch line RBL. The branch line RBL may be connected to the second switching element ST2 in each sub-pixel SP. The branch line RBL is disposed on the circuit portion. The branch line RBL extends in the first direction, and transmits a signal from the reference voltage line RL extending in the second direction to the sub-pixels SP arranged in the first direction. More specifically, the first branch line BL1 connects the reference voltage line RL and two sub-pixels SP1 and SP4 disposed at two opposite ends, and the second branch line BL2 connects the reference voltage line RL and two sub-pixels SP2 and SP3 disposed at the center. The branch line RBL and the reference voltage line RL may be disposed on different layers, and the branch line RBL may be electrically connected to the reference voltage line RL through a contact hole. Because the first branch line BL1 is connected to the first sub-pixel SP1 and the fourth sub-pixel SP4 spaced apart from each other and between which two sub-pixels SP2 and SP3 are interposed, the first branch line BL1 may be longer than the second branch line BL2. The central portion of the first branch line BL1 may be concavely bent so as not to interfere with the second branch line BL2. The second branch line BL2 is disposed under the concave central portion of the first branch line BL1 and is connected to the adjacent second and third sub-pixels SP2 and SP3 .

[0080] The branch line RBL is disposed on the same layer as the drain electrode of the second switching element ST2. The branch line RBL is electrically connected to the active layer of the second switching element ST2 through the second switching contact hole.

[0081] In each sub-pixel SP, the anode electrode of the light emitting element OLED disposed in the emission area EA extends in the second direction and is electrically connected to the corresponding driving element DT and the corresponding storage capacitor Cst in the non-emission area NEA.

[0082] Below, we will refer to Figure 4A cross-sectional structure of the light emitting area EA of one sub-pixel of the display device is described.

[0083] Figure 4 is a schematic cross-sectional view of a light emitting region of a sub-pixel.

[0084] refer to Figure 4 , the organic light emitting display device 100 according to an embodiment of the present disclosure includes a substrate 110, a buffer layer 111, a gate insulating layer 112, a driving element DT, a passivation layer 113, an overcoat layer 130, an organic light emitting element OLED and a bank layer BNK. For ease of description, Figure 4 Only a cross-sectional view of one sub-pixel of the organic light emitting display device 100 is shown.

[0085] refer to Figure 4 , the display device 100 according to an embodiment of the present disclosure may include a sub-pixel SP having a color filter on transistor (COT) structure. For example, the color of each sub-pixel SP may be realized by a color filter layer CF disposed on an upper layer of the driving element DT to overlap with the light emitting area EA of the sub-pixel SP. For example, the color filter layer CF may include a red color filter, a green color filter, and a blue color filter, which are separated to correspond to the red sub-pixel SP1, the green sub-pixel SP2, and the blue sub-pixel SP4 and are located on the same plane. For example, in the case where the light emitting element 140 emits white light, the red color filter CF (R) may be disposed in an area corresponding to the light emitting area of ​​the light emitting element 140, so that the red sub-pixel SP may be realized. In addition, the green color filter CF (G) may be disposed in an area corresponding to the light emitting area of ​​the light emitting element 140, so that the green sub-pixel SP may be realized. In addition, the blue color filter CF (B) may be disposed in an area corresponding to the light emitting area of ​​the light emitting element 140, so that the blue sub-pixel SP may be realized. In addition, the color filter layer CF is not disposed in a region corresponding to the light emitting region of the light emitting element 140 so that a white sub-pixel SP can be implemented. A detailed description of the color filter layer CF will be described below.

[0086] The substrate 110 supports various constituent elements of the organic light emitting display device 100. The substrate 110 may be made of an insulating material. For example, the substrate 110 may be made of glass or a plastic material such as polyimide (PI).

[0087] Although not in Figure 4, but a metal layer may be further provided on the substrate 110 and provided in a region overlapping with the channel region of the driving element DT. The metal layer may play a role of light shielding and may be referred to as a light shielding layer LS. For example, the light shielding layer may be provided not only under the channel region of the driving element DT, but also under the channel regions of the first switching element ST1 and the second switching element ST2.

[0088] The buffer layer 111 is disposed on the substrate 110. The buffer layer 111 is a layer for protecting the driving element DT from impurities such as alkali ions leaking from the substrate 110 or a layer disposed under the substrate 110. The buffer layer 111 may be made of silicon oxide (SiOx) or silicon nitride (SiNx), or be configured as a multilayer including silicon oxide (SiOx) or silicon nitride (SiNx).

[0089] The driving element DT is disposed on the buffer layer 111 .

[0090] The driving element DT includes an active layer 121, a gate electrode 122, a source electrode 123, and a drain electrode 124. For example, the active layer 121 may be formed on the substrate 110, a gate insulating layer 112 for isolating the gate electrode 122 and the active layer 121 is formed on the active layer 121 and the lower substrate 110, the gate electrode 122 is formed on the gate insulating layer 112, and the source electrode 123 and the drain electrode 124 are formed on the active layer 121 and the gate insulating layer 112. The source electrode 123 and the drain electrode 124 may be electrically connected to the active layer 121, while being adjacent to the active layer 121 and formed on a partial area of ​​the gate insulating layer 112. In the present disclosure, for ease of description, only the driving element is shown among various thin film transistors that may be included in the light-emitting display device 100. However, a switching element may also be included. In addition, in the present disclosure, the driving element DT is described as having a coplanar structure. However, a thin film transistor having an anti-staggered structure may also be used.

[0091] More specifically, the active layer 121 is disposed on the buffer layer 111. The active layer 121 may be made of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), an oxide semiconductor, an organic semiconductor, etc. In the case where the active layer 121 is made of an oxide semiconductor, the active layer 121 may be made of indium gallium zinc oxide (IGZO), etc. However, the present disclosure is not limited thereto.

[0092] The gate insulating layer 112 is disposed on the active layer 121. The gate insulating layer 112 isolates the active layer 121 and the gate electrode 122. The gate insulating layer 112 may be configured as a single layer made of silicon nitride (SiNx) or silicon oxide (SiOx) as an inorganic material. Alternatively, the gate insulating layer 112 may be configured as a multilayer made of silicon nitride (SiNx) or silicon oxide (SiOx). However, the present disclosure is not limited thereto.

[0093] The gate electrode 122 is disposed on the gate insulating layer 112. The gate electrode 122 may be made of a conductive metal, such as titanium (Ti), copper (Cu), aluminum (Al), molybdenum (Mo), or an alloy thereof. However, the present disclosure is not limited thereto.

[0094] The source electrode 123 and the drain electrode 124 are disposed on the gate insulating layer 112. The source electrode 123 and the drain electrode 124 may be electrically connected to the active layer 121 through a contact hole formed in the gate insulating layer 112. The source electrode 123 and the drain electrode 124 may each be made of various conductive materials, such as magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or alloys thereof. However, the present disclosure is not limited thereto.

[0095] The passivation layer 113 may be conformally disposed on the driving element DT. For example, the passivation layer 113 may be formed according to the shape of the top surface of the driving element DT. In addition, the passivation layer 113 may be formed to cover the driving element DT, and the passivation layer 113 may be disposed on the front surface of the substrate 110 on which the driving element DT is disposed.

[0096] The passivation layer 113 may be provided to cover the driving element DT. The passivation layer 113 may protect the driving element DT from oxygen or moisture from outside the light-emitting display device 100. Various organic or inorganic films may be used as the passivation layer 113, and the passivation layer 113 may have various structures, such as a structure in which only an organic film is deposited, a structure in which only an inorganic film is deposited, or a structure in which organic / inorganic films are deposited alternately. For example, the passivation layer 113 may be made of silicon nitride (SiNx), silicon oxide (SiOx), etc. However, the present disclosure is not limited thereto.

[0097] The color filter layer CF may be disposed on the passivation layer 113 so as to overlap with the emission area EA of the sub-pixel SP. In this case, the emission area EA refers to an area in which the emission layer 142 emits light through the first electrode 141 and the second electrode 143. For example, the color filter layer CF is formed to overlap with the emission area EA. However, the formation position and size of the color filter layer CF may be determined not only by the size and position of the emission area, but also by various factors, such as the distance between the color filter layer CF and the first electrode 141, the distance between the color filter layer CF and the concave portion of the overcoat layer 130, and the distance from the emission area.

[0098] The overcoat layer 130 is disposed on the color filter layer CF and the passivation layer 113. For example, the overcoat layer 130 may be made of any one of acrylic resin, epoxy resin, phenolic resin, polyamide-based resin, polyimide-based resin, unsaturated polyester-based resin, polyphenylene-based resin, polyphenylene sulfide-based resin, benzocyclobutene, and photoresist. However, the present disclosure is not limited thereto.

[0099] The outer coating 130 has a plurality of microlenses, and the plurality of microlenses include a plurality of concave portions 131 formed to overlap with the color filter layer CF and a connecting portion 132 configured to connect the plurality of concave portions 131. The plurality of concave portions 131 may each have a hemispherical or hemispherical shape. The outer coating 130 provides a planarized top surface on a portion where the plurality of concave portions 131 are not formed. The plurality of microlenses may extract light captured in the light emitting element 140 to the outside, thereby improving the efficiency of the display device 100. More specifically, light emitted from the light emitting layer 142 to be described below may be totally reflected at an interface between the first electrode 141 (ie, anode) and the outer coating 130. However, since the outer coating 130 of the display device 100 according to an embodiment of the present disclosure includes a plurality of concave portions 131 and a connecting portion 132, the outer coating 130 may define a microlens array structure. Therefore, it is highly unlikely that the incident angle of light emitted from the light emitting layer 142 and entering the interface of the overcoat layer 130 is less than the total reflection threshold angle, which can reduce the amount of light trapped in the display device 100 .

[0100] In the case where a microlens including a plurality of concave portions 131 is formed on the overcoat layer 130 by a process such as photolithography, Figure 4As shown, there is a connection portion 132 between multiple concave portions 131 on the outer coating 130, that is, a peak-shaped portion where the morphology changes rapidly. However, the multiple light-emitting layers 142 of the organic light-emitting element ED are formed in a manner such as thermal evaporation, which reduces the step coverage of the multiple light-emitting layers 142. In addition, the multiple light-emitting layers 142 are formed to have a very thin thickness of several hundred nanometers. There may be an area where no organic light-emitting layer is formed on the first electrode 141, and there is a high possibility that the first electrode 141 and the second electrode 143 are short-circuited. Therefore, although Figure 4 Although not shown in the drawings, an insulating layer may be additionally provided between the first electrode 141 and the overcoat layer 130 to mitigate a height difference that may be caused by the plurality of concave portions 131 .

[0101] The light emitting element 140 is disposed on the overcoat layer 130. The light emitting element 140 includes an anode 141, a light emitting layer 142, and a cathode 143.

[0102] The anode 141 is formed on the overcoat layer 130 while corresponding to the light emitting region of each pixel P. The anode 141 may be electrically connected to the drain electrode 124 of the driving element DT through a contact hole of the overcoat layer 130. The anode 141 may be made of a metal material.

[0103] The bank layer BNK is disposed on the anode 141 and the overcoat layer 130. The bank layer BNK may cover an end of the anode 141 and define a light emitting area EA. Therefore, the bank layer BNK may expose the anode 141 corresponding to the light emitting area. The bank layer BNK may be disposed at a boundary between adjacent sub-pixels SP and reduce color mixing of light beams emitted from the light emitting elements 140 of the plurality of sub-pixels SP.

[0104] The bank layer BNK may be made of a black material. The bank layer BNK may include a black material and is used to cover a metal layer that can be visually identified by the display area AA. For example, the bank layer BNK may be made of a carbon-based mixture. For example, the bank layer BNK may include carbon black. However, the present disclosure is not limited thereto.

[0105] Reference Figure 5 and Figure 6 The bank layer BNK is described in more detail.

[0106] A spacer may be further formed on the bank layer BNK. The spacer may be made of the same material as the bank layer BNK. The spacer may be used to suppress damage to the light emitting element 140 caused by a fine metal mask (FMM) used to pattern the organic light emitting layer 142.

[0107] The light emitting layer 142 is disposed on the anode 141 exposed by the bank layer BNK. The light emitting layer 142 may include a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, and the like.

[0108] The second electrode 143 (ie, cathode) is disposed on the light emitting layer 142. Since the cathode 143 provides electrons to the light emitting layer 142, the cathode 143 may be made of a conductive material having a low work function. The cathode 143 may be configured as a single layer over the plurality of sub-pixels SP. That is, the cathodes 143 of the plurality of sub-pixels SP may be connected to each other and integrated.

[0109] In the following, reference will be made to Figure 5 and Figure 6 A cross-sectional structure of a bank layer disposed between the emission areas EA of a display device is described.

[0110] Figure 5 is along Figure 3 A cross-sectional view taken along line V-V'. Figure 6 is along Figure 3 In addition to the bank layer, Figure 5 and Figure 6 The display device 100 shown in FIG. 1 is similar in configuration to the display device 100 shown in FIG. Figure 4 Therefore, for the convenience of description, repeated description of components of the display device 100 except the bank layer BNK will be omitted.

[0111] According to an embodiment of the present disclosure, the bank layer BNK may include a first bank region BNK1 adjacent to at least a portion of the emission region EA and a second bank region BNK2 having a different thickness from the first bank region BNK1 .

[0112] In the prior art, when a plurality of microlenses are applied to improve the efficiency of a display device by extracting light captured in a light-emitting element to the outside, during the process of performing a heat treatment on the bank layer, the bank layer flows into the plurality of microlenses on the outer coating layer, which results in a problem of a residual film being formed in the concave portion of the outermost periphery of the plurality of microlenses. In this case, there is a problem that the viewing difference between the left field of view and the right field of view causes deviation and spots in the brightness of the field of view due to the residual film in the concave portion of the outermost periphery of the plurality of microlenses. Therefore, in the case where the thickness of the bank layer is reduced to prevent the bank layer from flowing into the plurality of microlenses and forming a residual film, there is a problem that the charging rate at low grayscale is reduced and the aperture ratio is reduced.

[0113] Therefore, according to an embodiment of the present disclosure, the above-mentioned problem is suppressed by applying different thicknesses to the bank layer BNK according to positions.

[0114] According to an embodiment of the present disclosure, the bank layer BNK adjacent to at least a portion of the emission area EA is defined by a first bank area BNK1 having a first thickness d1. The first bank area BNK1 may be disposed between the emission areas EA of two sub-pixels SP adjacent to each other along a first direction (x-axis direction). For example, a plurality of sub-pixels SP may be arranged in a first direction, and the length of the emission area EA in a second direction (y-axis direction) perpendicular to the first direction is longer than the length in the first direction (x-axis direction). In this case, the first direction may be a direction of a user's viewing angle. For example, the first bank area BNK1 may overlap with a data line DL extending in a second direction perpendicular to the first direction.

[0115] like Figure 5 As shown, according to an embodiment of the present disclosure, the first bank region BNK1 disposed between the emission regions EA of two sub-pixels SP adjacent to each other along the first direction may have a first thickness d1. For example, the first thickness d1 may be 1.0 μm to 2.0 μm.

[0116] According to an embodiment of the present disclosure, the first bank region BNK1 has a first thickness d1 so that the first bank region BNK1 does not flow into the plurality of microlenses even if heat treatment is performed after forming the bank layer BNK. For example, in the first bank region BNK1, a side surface of the bank layer BNK may overlap with the connection portion 132 of the plurality of microlenses, but not overlap with the concave portion 131 of the plurality of microlenses.

[0117] In addition, according to an embodiment of the present disclosure, the bank layer BNK includes a second bank region BNK2 , and a second thickness d2 of the second bank region BNK2 is greater than a first thickness d1 of the first bank region BNK1 .

[0118] According to an embodiment of the present disclosure, the circuit portion may also be disposed between the emission areas EA of two sub-pixels SP adjacent to each other in a second direction (y-axis direction) perpendicular to the first direction (x-axis direction). In this case, the circuit portion may be disposed in the non-emission area NEA of the sub-pixel SP. For example, the second bank region BNK2 having a second thickness d2 greater than the first thickness d1 of the first bank region BNK1 may overlap the circuit portion.

[0119] According to an embodiment of the present disclosure, since the second bank region BNK2 has the second thickness d2, the second bank region BNK2 may flow into the plurality of microlenses during a process of performing a heat treatment after forming the bank layer BNK, which may cause a residual film. For example, in the second bank region BNK2, a side surface of the bank layer BNK may overlap with some of the concave portions 131 disposed at the periphery of the plurality of microlenses.

[0120] like Figure 6 As shown, the second bank region BNK2 relatively far from the light emitting region EA has a second thickness d2 relatively greater than the first thickness d1, so that the distance between the cathode 143 and the line provided on the circuit portion can be increased, which can minimize the parasitic capacitance that may occur between the line and the cathode 143. In addition, minimizing the parasitic capacitance can improve the charging rate at low grayscale. For example, the second thickness d2 can be 2.5μm to 3.5μm.

[0121] According to an embodiment of the present disclosure, a bank layer BNK including a first bank region BNK1 and a second bank region BNK2 having different thicknesses may be implemented by using a half-tone mask including a light-transmitting portion, a semi-light-transmitting portion, and a light-blocking portion. Specifically, after forming the bank layer BNK on the overcoat layer 130, the mask is positioned on the substrate 110 including the bank layer BNK. In this case, the mask may be a half-tone mask including a light-transmitting portion, a semi-light-transmitting portion, and a light-blocking portion. Specifically, the light-transmitting portion of the mask may be positioned to correspond to the light-emitting region EA of the sub-pixel SP, the semi-light-transmitting portion of the mask may be positioned to correspond to the portion between the light-emitting regions EA of the sub-pixel SP, and the light-blocking portion of the mask may be positioned to correspond to the non-light-emitting region NEA of the sub-pixel SP. Thereafter, after irradiating the bank layer BNK with light by using the mask, a development process is performed. In this case, a portion of the bank layer on the outer coating layer that is not exposed due to the light blocking portion of the mask is retained in a complete manner, a portion of the bank layer on the outer coating layer that is exposed through the light transmitting portion is completely removed, and a portion of the bank layer on the outer coating layer that is exposed through the semi-transmitting portion is removed by a partial thickness. Thereafter, heat treatment is performed so that a first bank region BNK1 having a first thickness d1 is configured in a region corresponding to the semi-transmitting portion, a second bank region BNK2 having a second thickness d2 is configured in a region corresponding to the light blocking portion, and an emission region EA is configured in a region corresponding to the light transmitting portion.

[0122] According to an embodiment of the present disclosure, a half-tone mask is used to realize a configuration in which a first thickness d1 of a first bank region BNK1 adjacent to a light emitting region EA having a plurality of microlenses is relatively smaller than a second thickness d2 of a second bank region BNK2 away from the light emitting region. Therefore, even if heat treatment is performed, the bank layer in the first bank region BNK1 having the first thickness d1 can be prevented from flowing into the concave portion 131 disposed at the outermost periphery of the plurality of microlenses and forming a residual film. Therefore, since a residual film is not formed in the plurality of microlenses, a vertical stripe problem in which a lens disposed at the outermost periphery of the microlenses is visually recognized can be suppressed.

[0123] Reference together Figure 3The display device 100 according to an embodiment of the present disclosure may further include repair portions RP respectively disposed in the non-emission regions NEA of the plurality of sub-pixels SP. For example, the repair portion RP may be disposed between the emission region EA and the non-emission region NEA or between the emission region EA and the circuit portion. In this case, the bank layer BNK may further include a third bank region BNK3 disposed to overlap with the repair portion RP.

[0124] In the display device 100, the repair portion RP refers to a region where, when a defective sub-pixel on the display panel is detected, lines or electrodes of some nodes of a pixel circuit of the defective sub-pixel are irradiated with a laser beam to block a current path to the defective sub-pixel. That is, the defective sub-pixel becomes a dark spot by blocking the current path by irradiating the repair portion RP with a laser beam, which can suppress abnormal operation of the sub-pixel and minimize the situation where the user visually recognizes the defective sub-pixel.

[0125] Hereinafter, a case where the repair portion RP is formed on the branch line RBL will be described. That is, the current path can be blocked by irradiating the repair portion RP disposed on the branch line RBL with a laser beam. However, the present disclosure is not limited thereto. The repair portion RP may also be formed on a line or node connected from the gate line GL to the first switching element ST1 or the second switching element ST2 in each sub-pixel SP.

[0126] In the following, reference will be made to Figure 7 and Figure 8 The bank layer BNK in the region overlapping with the branch line RBL of each sub-pixel SP is described.

[0127] Figure 7 is along Figure 3 A cross-sectional view taken along line VII-VII'. Figure 8 is along Figure 3 Specifically, Figure 7 is a cross-sectional view showing the light emitting area EA, the repair portion RP, and the circuit portion in the red sub-pixel SP1, Figure 8 is a cross-sectional view showing the emission area EA, the repair portion RP, and the circuit portion in the green sub-pixel SP2.

[0128] Also refer to Figure 3, the plurality of sub-pixels SP according to an embodiment of the present disclosure may further each include a branch line RBL disposed between the emission area EA and the non-emission area NEA (e.g., disposed between the emission area EA and the circuit portion). For example, the branch line RBL may be formed on the same layer as the gate electrode of the second switching element ST2 and made of the same metal. In this case, the bank layer BNK may further include a third bank region BNK3 disposed to overlap with the branch line RBL.

[0129] According to an embodiment of the present disclosure, the thickness d3 of the third bank region BNK3 may be equal to or less than the second thickness, or equal to the first thickness. For example, the thickness d3 of the third bank region BNK3 may be equal to the thickness d2 of the second bank region BNK2. Alternatively, the thickness d3 of the third bank region BNK3 may be less than the thickness d2 of the second bank region BNK2 and equal to the thickness d1 of the first bank region BNK2. The thickness d3 of the third bank region BNK3 may vary depending on the sub-pixel SP in which the third bank region BNK3 is located. Hereinafter, the thickness d3 of the third bank region BNK3 disposed to overlap the branch line RBL in each sub-pixel SP will be described.

[0130] According to an embodiment of the present disclosure, the plurality of sub-pixels SP may include a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4. For example, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, the third sub-pixel SP3 may be a white sub-pixel, and the fourth sub-pixel SP4 may be a blue sub-pixel. However, the present disclosure is not limited thereto. In this case, the plurality of sub-pixels SP except the white sub-pixel SP3 may each include a color filter layer CF disposed on the substrate to overlap the light emitting area EA and the branch line RBL.

[0131] According to an embodiment of the present disclosure, in the case where a defective sub-pixel is detected during an inspection process performed after the pixel array of the display panel is completely formed, a current path to the defective sub-pixel can be blocked by irradiating the lines or electrodes of some nodes of the pixel circuit of the defective sub-pixel with a laser beam. Therefore, the defective sub-pixel can be turned into a dark spot, which can minimize the situation where the user visually recognizes the defective sub-pixel.

[0132] Also refer to Figure 3, a repair process can be performed by irradiating the metal of the branch line RBL that supplies power to the pixel circuit with a laser beam, so that the defective sub-pixel becomes a dark spot. For example, the repair process can be performed by irradiating the first to fourth repair parts RP1, RP2, RP3 and RP4 of the branch line RBL with a laser beam. For example, in the case where the first sub-pixel SP1 is a defective sub-pixel, the first repair part RP1 of the branch line RBL can be irradiated with a laser beam, and the power supply to the first sub-pixel SP1 can be cut off. The metal line can be disconnected by melting with a laser beam generated by a general laser device. In this case, the emitted laser beam is absorbed by the color filter layer CF (for example, a red filter or a blue filter) or the barrier layer BNK, so that the laser beam does not affect the normal sub-pixels located near the defective sub-pixel.

[0133] However, in the case where a laser beam is emitted from below the substrate, in a white sub-pixel in which no color filter layer is provided and in a green sub-pixel in which a green color filter layer that transmits a laser beam having a wavelength (e.g., 532 nm) is provided, the laser beam is not absorbed by the color filter layer and the laser beam may affect normal sub-pixels located near the defective sub-pixel.

[0134] Therefore, according to an embodiment of the present disclosure, the thickness d3 of the third bank region BNK3 in the sub-pixel SP (i.e., the green sub-pixel SP2 and the white sub-pixel SP3 in which the laser beam is not absorbed by the color filter layer or the color filter layer is not provided) may be greater than the thickness d3 of the third bank region BNK3 in the sub-pixel SP (i.e., the red sub-pixel SP1 and the blue sub-pixel SP4 in which the laser beam is absorbed by the color filter layer). Therefore, in the sub-pixel SP in which the laser beam is not absorbed by the color filter layer or the color filter layer is not provided, the laser beam is absorbed by the third bank region BNK3, so that the laser beam does not affect the normal sub-pixel located near the defective sub-pixel.

[0135] For example, the thickness d3 of the third bank region BNK3 in the sub-pixels SP (i.e., the red sub-pixel SP1 and the blue sub-pixel SP4 in which the laser beam is absorbed by the color filter layer) may be equal to the first thickness d1. The thickness d3 of the third bank region BNK3 in the green sub-pixel SP2 and the white sub-pixel SP3 in which the laser beam is not absorbed by the color filter layer or the color filter layer is not provided may be equal to the second thickness d2.

[0136] According to an embodiment of the present disclosure, since the thickness d3 of the third bank region BNK3 in the red sub-pixel SP1 and the blue sub-pixel SP4 is equal to the first thickness d1, the third bank region BNK3 in the red sub-pixel SP1 and the blue sub-pixel SP4 does not flow into the plurality of micro-lenses even if heat treatment is performed after the bank layer BNK is formed. For example, in the third bank region BNK3 in the red sub-pixel SP1 and the blue sub-pixel SP4, the side surface of the bank layer BNK may overlap with the connection portion 132 of the plurality of micro-lenses, but not overlap with the concave portion 131 of the plurality of micro-lenses.

[0137] In addition, according to an embodiment of the present disclosure, since the thickness d3 of the third bank region BNK3 in the green sub-pixel SP2 and the white sub-pixel SP3 is equal to the second thickness d2, when heat treatment is performed after forming the bank layer BNK, the third bank region BNK3 in the green sub-pixel SP2 and the white sub-pixel SP3 may flow into the plurality of microlenses and form a residual film. For example, in the third bank region BNK3 in the green sub-pixel SP2 and the white sub-pixel SP3, the side surface of the bank layer BNK may overlap with some of the concave portions 131 disposed at the periphery of the plurality of microlenses.

[0138] In addition, according to an embodiment of the present disclosure, because the thickness d3 of the third partition area BNK3 in the green sub-pixel SP2 and the white sub-pixel SP3 is equal to the second thickness d2, even if a defective sub-pixel appears in the green sub-pixel SP2 or the white sub-pixel SP3 and a laser beam is emitted to block the current path leading to the defective sub-pixel, the laser beam can be absorbed by the third partition area BNK3 of the green sub-pixel SP2 or the third partition area BNK3 of the white sub-pixel SP3, which is formed to be relatively thicker than the third partition area BNK3 of the red sub-pixel SP1 and the third partition area BNK3 of the blue sub-pixel SP4.

[0139] According to the embodiment of the present disclosure, since the thickness d3 of the third bank region BNK3 of the green sub-pixel SP2 or the third bank region BNK3 of the white sub-pixel SP3 is relatively large, the laser beam can be easily absorbed. Therefore, the color filter layer does not need to be additionally provided in the third bank region BNK3 of the green sub-pixel SP2 or the third bank region BNK3 of the white sub-pixel SP3. Therefore, the aperture ratio of the sub-pixel SP can be maximized, thereby improving the afterimage performance of the display device.

[0140] In the following, reference will be made to Fig. 9 The bank layer disposed in the non-display area NA of the display panel DP is described.

[0141] Fig. 9 is along Figure 1A cross-sectional view taken along line IX-IX'.

[0142] The display panel DP includes a display area AA in which a plurality of sub-pixels SP are disposed and a non-display area NA configured to surround the display area AA.

[0143] The non-display area NA may include a bank layer BNK extending from the display area AA along all four surfaces surrounding the display area AA, and at least one trench pattern T disposed closer to the periphery of the non-display area NA than the bank layer BNK extending from the display area AA. In this case, the bank layer BNK extending from the display area AA may be referred to as a first bank B1.

[0144] The groove pattern T formed in the non-display area NA at the periphery of the display area AA may suppress the penetration or propagation of moisture from the peripheral portion of the display panel DP into the display panel DP.

[0145] In addition, the non-display area NA may also include a plurality of second partition banks B2 arranged to be closer to the periphery of the non-display area NA than at least one groove pattern T. For example, the first partition bank B1 may be divided by a plurality of groove patterns T arranged in the non-display area NA of the display panel DP, so that a second partition bank B2 may be formed.

[0146] The thickness of the second bank B2 separated from the first bank B1 by the trench pattern T is smaller than that of the first bank B1, so that the first bank B1 can be prevented from overflowing into the trench pattern T and forming a residual film in the trench pattern T during the heat treatment performed after the first bank B1 is formed. Therefore, the deterioration of the moisture permeability can be suppressed.

[0147] For example, the thickness of first bank B1 may be 2.5 μm to 3.5 μm, and the thickness of second bank B2 may be 1.0 μm to 2.0 μm.

[0148] Exemplary embodiments of the present disclosure may be described as follows:

[0149] According to one aspect of the present disclosure, a display device includes: a substrate on which a plurality of sub-pixels are defined, each sub-pixel including a light-emitting area and a non-light-emitting area; an outer coating layer disposed on the substrate and having a plurality of micro-lenses, the plurality of micro-lenses including a recessed portion and a connecting portion in the light-emitting area; a first electrode disposed on the outer coating layer; a bank layer, the bank layer exposing a portion of the first electrode on the outer coating layer and defining the light-emitting area; a light-emitting layer, the light-emitting layer covering the first electrode exposed by the bank layer; and a second electrode disposed on the light-emitting layer, the bank layer including: a first bank region, the first bank region being disposed adjacent to at least a portion of the light-emitting area and having a first thickness; and a second bank region, the second bank region having a second thickness greater than the first thickness.

[0150] The bank layer may be made of a black material.

[0151] The plurality of sub-pixels may be arranged in a first direction, and the first bank region may be provided between light emitting regions of two sub-pixels adjacent to each other in the first direction.

[0152] The first bank region may overlap a data line extending in a second direction perpendicular to the first direction.

[0153] The light emitting area may have a length in a second direction perpendicular to the first direction longer than a length in the first direction, and the first direction may be a direction of a user's viewing angle.

[0154] The display device may further include a circuit portion provided between light emitting regions of two sub-pixels adjacent to each other in a second direction perpendicular to the first direction, and the second bank region may overlap the circuit portion.

[0155] The display device may further include a repair portion disposed between the circuit portion and the light emitting region of each of the plurality of sub-pixels, and the bank layer may further include a third bank region disposed to overlap the repair portion.

[0156] The thickness of the third bank region may be equal to or smaller than the second thickness.

[0157] The thickness of the third bank region may be equal to the first thickness.

[0158] The plurality of sub-pixels may include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, and a thickness of the third bank region in the second sub-pixel and the third sub-pixel may be greater than a thickness of the third bank region in the remaining sub-pixels.

[0159] The display device may further include a color filter layer, which is arranged to overlap the light-emitting area and the repair part on the substrate, and the color filter layer can be separated to correspond to the first sub-pixel, the second sub-pixel and the fourth sub-pixel respectively and be located on the same plane with each other.

[0160] The thickness of the third bank region in the second and third subpixels may be equal to the second thickness, and the thickness of the third bank region in the remaining subpixels of the plurality of subpixels may be equal to the first thickness.

[0161] The second sub-pixel may emit green light, and the third sub-pixel may emit white light.

[0162] The substrate may include a display area in which the plurality of sub-pixels are disposed and a non-display area surrounding the display area, the non-display area may include a first partition wall extending from the display area, at least one groove pattern disposed closer to a periphery of the non-display area than the first partition wall, and a plurality of second partition walls disposed closer to a periphery of the non-display area than the groove patterns, and a thickness of the second partition wall may be less than a thickness of the first partition wall.

[0163] The thickness of the first bank may be 2.5 μm to 3.5 μm, and the thickness of the second bank may be 1.0 μm to 2.0 μm.

[0164] A side surface of the bank layer in the first bank region may overlap with the connection portion of the plurality of microlenses, and a side surface of the bank layer in the second bank region may overlap with some of the concave portions disposed at the periphery of the plurality of microlenses.

[0165] A side surface of the bank layer in the third bank region in the remaining sub-pixels among the plurality of sub-pixels may overlap with the connection portions of the plurality of microlenses.

[0166] A side surface of the bank layer in the third bank region in the second sub-pixel and the third sub-pixel may overlap with some of the concave portions disposed at the periphery of the plurality of microlenses.

[0167] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the attached claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: a substrate on which a plurality of sub-pixels are defined, each sub-pixel including a light-emitting region and a non-light-emitting region; an outer coating layer disposed on the substrate and having a plurality of micro lenses including a concave portion and a connection portion in the light emitting region; a first electrode disposed on the outer coating; a bank layer, the bank layer exposing a portion of the first electrode on the outer coating layer and defining the light emitting area; a light-emitting layer, the light-emitting layer covering the first electrode exposed by the bank layer; as well as a second electrode, the second electrode being disposed on the light-emitting layer, The bank layer comprises: a first bank region, the first bank region being disposed adjacent to at least a portion of the light emitting region and having a first thickness; as well as A second bank region has a second thickness greater than the first thickness. 2 . The display device according to claim 1 , wherein the bank layer is made of a black material. 3 . The display device according to claim 1 , wherein the plurality of sub-pixels are arranged along a first direction, and the first bank region is provided between the light emitting regions of two sub-pixels adjacent to each other along the first direction. 4 . The display device of claim 3 , wherein the first bank region overlaps a data line extending in a second direction perpendicular to the first direction. 5 . The display device according to claim 3 , wherein a length of the light emitting area in a second direction perpendicular to the first direction is longer than a length in the first direction, and the first direction is a direction of a user's viewing angle.

6. The display device according to claim 3, further comprising: a circuit portion, the circuit portion being disposed between the light emitting regions of two sub-pixels adjacent to each other in a second direction perpendicular to the first direction, The second bank region partially overlaps with the circuit.

7. The display device according to claim 6, further comprising: a repairing portion disposed between the circuit portion and the light emitting region of each of the plurality of sub-pixels, The bank layer further includes a third bank region, and the third bank region is configured to overlap with the repair portion. 8 . The display device according to claim 7 , wherein a thickness of the third bank region is equal to or smaller than the second thickness. 9 . The display device according to claim 7 , wherein a thickness of the third bank region is equal to the first thickness. 10 . The display device according to claim 7 , wherein a thickness of the third bank region varies depending on a sub-pixel in which the third bank region is located.

11. The display device according to claim 10, wherein the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel, and a thickness of the third partition region in the second sub-pixel and the third sub-pixel is greater than a thickness of the third partition region in the remaining sub-pixels.

12. The display device according to claim 11, further comprising: a color filter layer, the color filter layer being disposed on the substrate to overlap the light emitting area and the repairing portion, The color filter layers are separated to correspond to the first sub-pixel, the second sub-pixel, and the fourth sub-pixel, respectively, and are located on the same plane as each other.

13. The display device according to claim 11, wherein the thickness of the third bank region in the second sub-pixel and the third sub-pixel is equal to the second thickness, and the thickness of the third bank region in the remaining sub-pixels among the plurality of sub-pixels is equal to the first thickness. 14 . The display device according to claim 13 , wherein the second sub-pixel emits green light, and the third sub-pixel emits white light.

15. The display device according to claim 1, wherein the substrate comprises: A display area, wherein the plurality of sub-pixels are arranged in the display area; as well as a non-display area, the non-display area surrounding the display area, The non-display area includes: a first bank extending from the display area; at least one groove pattern, the at least one groove pattern being disposed closer to an outer periphery of the non-display area than the first bank; and a plurality of second banks disposed closer to the periphery of the non-display area than the groove pattern, and The thickness of the second bank is smaller than the thickness of the first bank. 16 . The display device according to claim 1 , wherein a thickness of the first bank is 2.5 μm to 3.5 μm, and a thickness of the second bank is 1.0 μm to 2.0 μm.

17. A display device according to claim 1, wherein a side surface of the partition layer in the first partition area overlaps with the connecting portion of the plurality of microlenses, and a side surface of the partition layer in the second partition area overlaps with some of the concave portions arranged at the periphery of the plurality of microlenses. 18 . The display device according to claim 14 , wherein a side surface of the bank layer in the third bank region in the remaining sub-pixels among the plurality of sub-pixels overlaps with the connection portions of the plurality of microlenses.

19. The display device according to claim 14, wherein a side surface of the bank layer in the third bank region in the second sub-pixel and the third sub-pixel overlaps with some of the concave portions disposed at the periphery of the plurality of microlenses.

Images