Display device

Abstract

Disclosed is a display device including: a first pixel electrode on a substrate; a first light emitting layer on the first pixel electrode; a first common electrode on the first light emitting layer; a first bank on the substrate, and exposing the first common electrode through the first bank; and a second bank on the first bank and having a side surface protruding beyond a side surface of the first bank. A width of a lower surface of the first bank is less than a width of an upper surface of the first bank.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0128129 filed in the Korean Intellectual Property Office on September 25, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] An aspect of an embodiment of the present disclosure relates to a display device. Background Art

[0003] With the development of the information age, the demand for display devices for displaying images in various forms has increased. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat panel display device, such as a liquid crystal display device, a field emission display device, and an organic light emitting display device. Among the flat panel display devices, the light emitting display device includes a light emitting element, and each pixel in the display panel in the light emitting display device can be self-luminous (for example, each pixel can be self-luminous), thereby displaying an image without a backlight unit that provides light to the display panel.

[0004] Recently, display devices have been applied to eyeglass-type devices to provide virtual reality (VR) and augmented reality (AR). In order to be applied to eyeglass-type devices, the display device is implemented in a very small size of about 2 inches or less. However, the display device should have a high pixel integration so that the display device can provide images with high resolution. For example, the display device can have a high pixel integration of about 400 pixels per inch (PPI) or more.

[0005] As described above, the display device is implemented in a very small size, but when the display device has a high pixel integration, the area of ​​the light emitting region in which the light emitting element is disposed is reduced. Therefore, it is difficult to implement a light emitting element separated at each light emitting region through a mask process. Summary of the invention

[0006] An embodiment of the present disclosure provides a display device having a light emitting element separated for each light emitting region formed without a mask process.

[0007] An embodiment of the present disclosure also provides a display device in which light emission deviation that may occur in each pixel is reduced.

[0008] Aspects and features of the present disclosure are not limited to those described above, and additional aspects and features of the present disclosure not mentioned herein will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0009] According to an embodiment of the present disclosure, a display device includes: a substrate; a first pixel electrode on the substrate; a first light-emitting layer on the first pixel electrode; a first common electrode on the first light-emitting layer; a first bank on the substrate, and the first common electrode is exposed through the first bank; and a second bank on the first bank and having a side surface protruding beyond the side surface of the first bank. The width of the lower surface of the first bank is smaller than the width of the upper surface of the first bank.

[0010] The first common electrode may be in contact with a side surface of the first bank.

[0011] An angle between a lower surface of the first bank and a side surface of the first bank may be greater than 90°.

[0012] The first bank may include at least one of polysilicon, amorphous carbon, graphite, and graphene.

[0013] The second bank may include SiO x 、SiN y 、SiO x N y and at least one of a metal.

[0014] The display device may further include an auxiliary electrode between the substrate and the first bank.

[0015] The auxiliary electrode may contact the first common electrode.

[0016] The display device may further include: a third bank on the second bank; and a fourth bank on the third bank. The fourth bank may have a side surface protruding beyond a side surface of the third bank.

[0017] A width of a lower surface of the third bank may be smaller than a width of an upper surface of the third bank and smaller than a width of the second bank.

[0018] The display device may further include a first inorganic layer on the second bank and the first common electrode.

[0019] The display device may further include a first covering layer between the first common electrode and the first inorganic layer.

[0020] The display device may also include: a second pixel electrode on the substrate and separated from the first pixel electrode; a second light-emitting layer on the second pixel electrode; a second common electrode on the second light-emitting layer and separated from the first common electrode; and a second inorganic layer on the second common electrode and the second embankment and separated from the first inorganic layer.

[0021] The display device may further include: a first light emitting pattern between the second bank and the first inorganic layer and may include the same material as that of the first light emitting layer; and a first electrode pattern between the first light emitting pattern and the first inorganic layer and may include the same material as that of the first common electrode.

[0022] According to an embodiment of the present disclosure, a display device includes: a substrate; a first pixel electrode on the substrate; a first light-emitting layer on the first pixel electrode; a first common electrode on the first light-emitting layer; a first bank on the substrate, and the first common electrode is exposed through the first bank; and a second bank on the first bank and having a side surface protruding beyond the side surface of the first bank. The first bank includes at least one of polysilicon, amorphous carbon, graphite, and graphene, and the first common electrode contacts the side surface of the first bank.

[0023] The second bank includes SiO x 、SiN y 、SiO x N y and at least one of a metal.

[0024] The display device may further include a first inorganic layer on an upper surface of the first common electrode, side surfaces of the first bank, and upper and lower surfaces of the second bank.

[0025] According to an embodiment of the present disclosure, a display device includes: a substrate; a first pixel electrode on the substrate; a pixel defining layer on the substrate, and the first pixel electrode is exposed through the pixel defining layer; a first light emitting layer on the first pixel electrode; a first common electrode on the first light emitting layer; an auxiliary electrode on the pixel defining layer and in contact with the first common electrode; a first bank on the auxiliary electrode; and a second bank on the first bank and having a side surface protruding beyond the side surface of the first bank. The width of the lower surface of the first bank is different from the width of the upper surface of the first bank.

[0026] A width of a lower surface of the first bank may be smaller than a width of an upper surface of the first bank.

[0027] A cross-section of the first bank may have a width decreasing from the upper surface toward the lower surface.

[0028] The auxiliary electrode may include at least one of copper, aluminum, and molybdenum.

[0029] In the display device according to the embodiment of the present disclosure, the penetration of etchant or moisture into the light emitting element can be avoided. In addition, damage to the light emitting element due to the etchant or moisture can be avoided, so that the brightness difference between the light emitting elements can be reduced.

[0030] The aspects and features of the embodiments of the present disclosure are not limited to those mentioned above, and include more various aspects and features in the following description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] Figure 1 is a perspective view showing a display device according to an embodiment;

[0033] Figure 2 yes Figure 1 A cross-sectional view of the display device shown in ;

[0034] Figure 3 is a plan view showing the arrangement of a light emitting element, a lower inorganic encapsulation layer, and a second bank of a display device according to one embodiment;

[0035] Figure 4 is a cross-sectional view of a portion of a display device according to an embodiment;

[0036] Figure 5 It is shown Figure 4 An enlarged view of area A1 in FIG.

[0037] Figures 6 to 10 is an enlarged view showing a display device according to another embodiment;

[0038] Fig.11 is a diagram showing a virtual reality device including a display device according to an embodiment;

[0039] Fig.12 and Fig.13 is a diagram showing a head mounted display device including a display device according to one embodiment; and

[0040] Fig.14 According to an embodiment Figures 11 to 13 A cross-sectional view of a pixel in the display device shown in FIG. DETAILED DESCRIPTION

[0041] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings in which embodiments of the present disclosure are shown. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0042] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or coupled to the other element or layer, or one or more intervening elements or layers may also be present. When an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For example, when a first element is described as being "coupled to" or "coupled to" a second element, the first element may be directly coupled or coupled to the second element, or the first element may be indirectly coupled or coupled to the second element via one or more intervening elements.

[0043] In the accompanying drawings, for clarity of illustration, the sizes of various elements, layers, etc. may be exaggerated. The same reference numerals represent the same elements. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. In addition, when describing the embodiments of the present disclosure, the use of "may" relates to "one or more embodiments of the present disclosure". Expressions such as "at least one (kind / person) in ... " and "any one (kind / person) in ... " modify the entire row of elements after a row of elements without modifying the individual elements in the row. For example, the expression "at least one (kind / person) in a, b, and c" represents only a, only b, only c, both a and b, both a and c, both b and c, all or variations of a, b, and c. As used herein, the term "use" and its variations may be considered to be synonymous with the term "utilize" and its variations, respectively. As used herein, the terms "substantially", "about (approximately)" and similar terms are used as approximate terms rather than as degree terms, and are intended to explain the inherent deviations of the measured values ​​or calculated values ​​that will be recognized by those of ordinary skill in the art.

[0044] It will be understood that, although the terms first, second, third, etc. can be used here to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish an element, a component, a region, a layer or a part from another element, another component, another region, another layer or another part. Therefore, without departing from the teaching of the exemplary embodiment, the first element, the first component, the first region, the first layer or the first part discussed below can be referred to as the second element, the second component, the second region, the second layer or the second part.

[0045] For ease of description, spatially relative terms such as "under," "below," "below," "above," "on," etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the accompanying drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as "under" or "below" other elements or features is then oriented to be "above" or "above" the other elements or features. Thus, the term "under" may encompass both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0046] The terms used herein are for the purpose of describing the embodiments of the present disclosure, and are not intended to be limitations of the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form "one (kind / person)" is also intended to include the plural form. It will also be understood that when the terms "include", "comprise" and / or its variations are used in this specification, the description indicates the presence of stated features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups.

[0047] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0048] Figure 1 is a perspective view showing a display device according to an embodiment.

[0049] Reference Figure 1 According to one embodiment, the display device 10 may be included in an electronic device to provide an image displayed on the electronic device. The electronic device may refer to all electronic devices that include (or provide) a display screen. For example, a television, a laptop computer, a monitor, a billboard, an Internet of Things (IoT) device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, smart glasses, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic diary, an electronic book, a portable multimedia player (PMP), a navigator, a game console, a digital camera, a video camera, etc. that provide a display screen may be included in the electronic device.

[0050] The shape of the display device 10 may be variously modified. For example, in a plan view, the display device 10 may have a shape similar to a rectangular shape having short sides in the first direction DR1 and long sides in the second direction DR2. Corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 meet may be rounded to have a curvature, but are not limited thereto, and may form a right angle. The planar shape of the display device 10 may be formed similar to other polygonal shapes, a circular shape, or an elliptical shape, without being limited to a rectangular shape.

[0051] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400 (see FIG. Figure 2 ).

[0052] The display panel 100 may have a main area MA and a sub area SBA.

[0053] The main area MA may include a display area DA having pixels for displaying an image and a non-display area NDA disposed near the display area DA (e.g., adjacent to the display area DA). The display area DA may emit light from a plurality of light-emitting areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining a light-emitting area or an opening area, and a self-luminous element.

[0054] For example, the self-luminous element may include at least one of an organic light emitting diode including an organic light emitting layer, a quantum dot light emitting diode (LED) including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED.

[0055] A plurality of pixels, a plurality of scan lines, a plurality of data lines, and a plurality of power lines may be provided in the display area DA. Each of the plurality of pixels may be defined as a minimum unit for emitting light, and each of the above-mentioned self-luminous elements may be each pixel. The plurality of scan lines may supply a scan signal received from a scan driver to the plurality of pixels. The plurality of data lines may supply a data voltage received from a display driver 200 to the plurality of pixels. The plurality of power lines may supply a power voltage received from a display driver 200 to the plurality of pixels.

[0056] The non-display area NDA may be an outer area around the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a scan driver for supplying a scan signal to a scan line and a fan-out line for connecting the display driver 200 to the display area DA.

[0057] The sub-region SBA may extend from one side of the main region MA. The sub-region SBA may include a flexible material that can withstand bending, folding, curling, etc. For example, when the sub-region SBA is bent, the sub-region SBA may overlap with the main region MA in the thickness direction (e.g., the third direction DR3). The sub-region SBA may include a display driver 200 and a pad (also referred to as a "pad", "solder pad") portion connected to the circuit board 300. In another embodiment, the sub-region SBA may be omitted, and the display driver 200 and the pad portion may be disposed in the non-display area NDA.

[0058] The display driver 200 may output a signal and a voltage for driving the display panel 100. The display driver 200 may supply a data voltage to a data line. The display driver 200 may supply a power voltage to a power line, and may supply a scan control signal to a scan driver. The display driver 200 may be formed by an integrated circuit (IC), and may be packaged on the display panel 100 by a chip on glass (COG) process, a chip on plastic (COP) process, or an ultrasonic bonding process. For example, the display driver 200 may be disposed in a sub-region SBA, and may overlap with the main region MA in a thickness direction (e.g., a third direction DR3) by bending of the sub-region SBA. For another example, the display driver 200 may be packaged on a circuit board 300.

[0059] The circuit board 300 may be attached to the pad portion of the display panel 100 by using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip on film.

[0060] Figure 2 It is viewed from the side Figure 1 In other words, Figure 2 Involved Figure 1 The display device shown in FIG. 1 is shown on one side in a folded state.

[0061] Reference Figure 2 , the display panel 100 may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, a thin film encapsulation layer TFEL, and a color filter layer CFL.

[0062] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, curled, etc. For example, the substrate SUB may be a silicon substrate, a germanium substrate, or a silicon germanium substrate, but is not limited thereto. In another embodiment, the substrate SUB may include a polymer resin such as polyimide (PI). In other embodiments, the substrate SUB may include a glass material or a metal material.

[0063] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting (or forming) a pixel circuit of a pixel. The thin film transistor layer TFTL may also include a gate line, a data line, a power line, a scan control line, a fan-out line for connecting the display driver 200 to the data line, and a lead for connecting the display driver 200 to the pad portion. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a thin film transistor.

[0064] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistors, gate lines, data lines, and power lines of each pixel of the thin film transistor layer TFTL may be disposed in the display area DA. The scanning control lines and fan-out lines of the thin film transistor layer TFTL may be disposed in the non-display area NDA. The lead lines of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0065] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements and a pixel defining layer defining pixels, the plurality of light emitting elements including a first electrode, a second electrode, and a light emitting layer configured to emit light. The plurality of light emitting elements of the light emitting element layer EML may be disposed in the display area DA.

[0066] In one embodiment, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin film transistor of the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively, and may be combined with each other in the organic light-emitting layer to emit light.

[0067] In another embodiment, the light emitting element may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0068] The thin film encapsulation layer TFEL may cover the upper surface and the side surface of the light emitting element layer EML and may protect the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer to encapsulate the light emitting element layer EML.

[0069] The color filter layer CFL may be disposed on the thin film encapsulation layer TFEL. The color filter layer CFL may include a plurality of color filters corresponding to the plurality of light emitting regions, respectively. Each of the color filters may selectively transmit light of a specific wavelength, and may block or absorb light of another wavelength. The color filter layer CFL may absorb a portion of light introduced from the outside of the display device 10 (or incident from the outside of the display device 10) to reduce reflected light caused by external light. Therefore, the color filter layer CFL may prevent color distortion caused by external light reflection.

[0070] Since the color filter layer CFL is directly disposed on the thin film encapsulation layer TFEL, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively reduced.

[0071] In some embodiments, the display device 10 may further include an optical device. The optical device may emit or receive infrared light, ultraviolet light, or light in the visible band. For example, the optical device may be an optical sensor for sensing light incident on the display device 10, such as a proximity sensor, an illumination sensor, a camera sensor, a fingerprint sensor, or an image sensor.

[0072] Figure 3 is a plan view showing a portion of a display device according to an embodiment. Figure 3 is a plan view showing the arrangement of the light emitting elements ED1 , ED2 , and ED3 , the lower inorganic encapsulation layers TL1 , TL2 , and TL3 , and the second bank BN2 in the display area DA of the display device 10 .

[0073] Reference Figure 3 , the second bank BN2 may expose a portion of the display area DA while covering the display area DA. Figure 3 The lower inorganic encapsulation layers TL1, TL2, and TL3 may cover the boundary portions of the openings on the second bank BN2 and may cover the light emitting elements ED1, ED2, and ED3 in the openings.

[0074] Although the area not covered by the second bank BN2 and exposed Figure 3, but the region may have a polygonal shape such as a triangular shape, a quadrilateral shape, or a hexagonal shape, and the shapes of the lower inorganic encapsulation layers TL1, TL2, and TL3 covering the exposed region and its periphery may also be changed. A portion of the lower inorganic encapsulation layers TL1, TL2, and TL3 may be disposed at a level higher than (or higher than) the level of the second bank BN2, and the light emitting elements ED1, ED2, and ED3 may be disposed at a level lower than (or lower than) the level of the second bank BN2.

[0075] The plurality of light emitting elements ED1, ED2 and ED3 can be set to Type, for example, rhombus Type or diamond pixel arrangement. is a registered trademark of Samsung Display Co., Ltd. For example, the first light emitting element ED1 and the third light emitting element ED3 may be spaced apart from each other in the first direction DR1 and may be alternately arranged in the first direction DR1 and the second direction DR2. The second light emitting element ED2 may be spaced apart from another adjacent second light emitting element ED2 in the first direction DR1 and the second direction DR2. The second light emitting element ED2 and the first light emitting element ED1 or the second light emitting element ED2 and the third light emitting element ED3 may be alternately arranged along any direction on a plane defined by the first direction DR1 and the second direction DR2. The shape and arrangement of the region not covered by the second dam BN2 and exposed and the plurality of light emitting elements are not limited to Figure 3 The arrangement shown in .

[0076] Figure 4 is a cross-sectional view of a portion of a display device according to an embodiment. In detail, Figure 4 It is along Figure 3 A cross-sectional view taken along line II'. Figure 4 The cross sections of the substrate SUB, the thin film transistor layer TFTL, the light emitting element layer EML, the thin film encapsulation layer TFEL, and the color filter layer CFL are shown.

[0077] The thin film transistor layer TFTL may include a first buffer layer BF1, a lower metal layer, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0078] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic film for preventing air or moisture from penetrating. For example, the first buffer layer BF1 may include a plurality of inorganic films alternately stacked on each other.

[0079] The lower metal layer may be selectively disposed on the first buffer layer BF1. For example, the lower metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0080] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer. The second buffer layer BF2 may include an inorganic film for preventing penetration of air or moisture. For example, the second buffer layer BF2 may include a plurality of inorganic films alternately stacked on each other.

[0081] The thin film transistor TFT may be disposed on the second buffer layer BF2 and may constitute a pixel circuit of each of the plurality of pixels. For example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0082] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap with the lower metal layer and the gate electrode GE in the third direction DR3, and may be insulated from the gate electrode GE by the gate insulating layer GI. A portion of the semiconductor layer ACT may form a source electrode SE and a drain electrode DE by making the material of the semiconductor layer ACT conductive (e.g., may be doped to make the material of the semiconductor layer ACT conductive).

[0083] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT in the third direction DR3 with the gate insulating layer GI interposed therebetween.

[0084] The gate insulating layer GI may be disposed on the semiconductor layer ACT. For example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2 and may insulate the semiconductor layer ACT from the gate electrode GE. The gate insulating layer GI may include a contact hole (eg, a contact opening) through which the first connection electrode CNE1 passes.

[0085] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include a contact hole (e.g., a contact opening) through which the first connection electrode CNE1 passes. The contact hole in the first interlayer insulating layer ILD1 may be connected to a contact hole in the gate insulating layer GI and a contact hole (e.g., a contact opening) in the second interlayer insulating layer ILD2 (e.g., may lead to a contact hole in the gate insulating layer GI and a contact hole in the second interlayer insulating layer ILD2).

[0086] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE may overlap the gate electrode GE in the third direction DR3. The capacitor electrode CPE and the gate electrode GE may form a capacitance therebetween.

[0087] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may have a contact hole (e.g., a contact opening) through which the first connection electrode CNE1 passes. The contact hole in the second interlayer insulating layer ILD2 may be connected to the contact hole in the first interlayer insulating layer ILD1 and the contact hole in the gate insulating layer GI (e.g., may lead to the contact hole in the first interlayer insulating layer ILD1 and the contact hole in the gate insulating layer GI).

[0088] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into (or formed in) a contact hole formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0089] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may have a contact hole (eg, a contact opening) through which the second connection electrode CNE2 passes.

[0090] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 with the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED. The second connection electrode CNE2 may be inserted into a contact hole formed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0091] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may have contact holes (eg, contact openings) through which the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED pass.

[0092] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a light emitting element ED, a pixel defining layer PDL, cover layers CAP1, CAP2, and CAP3, and a bank structure BNS. The light emitting element ED may include pixel electrodes AE1, AE2, and AE3, light emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3.

[0093] The display device 10 may have a plurality of light emitting areas EA1, EA2, and EA3 disposed in the display area DA. The light emitting areas EA1, EA2, and EA3 may be areas where light emitted from the light emitting elements ED1, ED2, and ED3 passes through the color filter layer CFL in the third direction DR3, and the pixel electrodes AE1, AE2, and AE3, the light emitting layers EL1, EL2, and EL3, and the common electrodes CE1, CE2, and CE3 may be sequentially stacked on each other in the light emitting elements ED1, ED2, and ED3, respectively. The light emitting areas EA1, EA2, and EA3 may include a first light emitting area EA1, a second light emitting area EA2, and a third light emitting area EA3 that are spaced apart from each other and emit light of the same color or different colors.

[0094] In one embodiment, the areas or sizes of the first to third light emitting areas EA1, EA2, and EA3 may be the same as each other. Figure 4 In the display device 10 shown in , the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have the same size, but are not limited thereto. In the display device 10, the first to third light emitting areas EA1, EA2, and EA3 may have different areas or sizes. For example, the size of the second light emitting area EA2 may be larger than the size of each of the first light emitting area EA1 and the third light emitting area EA3, and the size of the third light emitting area EA3 may be larger than the size of the first light emitting area EA1. The intensity of light emitted from the corresponding light emitting areas EA1, EA2, and EA3 may vary according to the sizes of the light emitting areas EA1, EA2, and EA3, and the sizes of the light emitting areas EA1, EA2, and EA3 may be adjusted so that the color of the picture displayed on the display device 10 can be controlled. Figure 4 In the embodiment shown in FIG. 8 , the sizes of the light emitting areas EA1 , EA2 , and EA3 are shown to be the same as one another, but the present disclosure is not limited thereto.

[0095] In the display device 10, one first light-emitting area EA1, one second light-emitting area EA2, and one third light-emitting area EA3 disposed adjacent to each other may form one pixel group. One pixel group may include light-emitting areas EA1, EA2, and EA3 emitting light of different colors, thereby presenting a white grayscale (e.g., thereby emitting or being configured to emit white light), but the present disclosure is not limited thereto. The combination of light-emitting areas EA1, EA2, and EA3 constituting one pixel group may be variously modified according to the arrangement of the light-emitting areas EA1, EA2, and EA3 and the color of the light emitted from the light-emitting areas EA1, EA2, and EA3.

[0096] A plurality of openings formed in the embankment structure BNS of the light emitting element layer EML may be defined along the boundary of the embankment structure BNS. The first embankment BN1 and the second embankment BN2 of the embankment structure BNS may surround the light emitting regions EA1, EA2, and EA3 (e.g., may extend around the periphery of the light emitting regions EA1, EA2, and EA3). Each of the openings may include (or may form) one of the first to third light emitting regions EA1, EA2, and EA3.

[0097] The display device 10 may include a plurality of light emitting elements ED1, ED2, and ED3 respectively disposed in different light emitting areas EA1, EA2, and EA3. The light emitting elements ED1, ED2, and ED3 may include a first light emitting element ED1 disposed in a first light emitting area EA1, a second light emitting element ED2 disposed in a second light emitting area EA2, and a third light emitting element ED3 disposed in a third light emitting area EA3.

[0098] Each of the light emitting elements ED1, ED2, and ED3 may include pixel electrodes AE1, AE2, and AE3, light emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3, and the light emitting elements ED1, ED2, and ED3 respectively disposed in different light emitting areas EA1, EA2, and EA3 may emit light of different colors according to the materials of the light emitting layers EL1, EL2, and EL3. For example, the first light emitting element ED1 disposed in the first light emitting area EA1 may emit a red first light having a peak wavelength in the range of about 610 nm to about 650 nm, the second light emitting element ED2 disposed in the second light emitting area EA2 may emit a green second light having a peak wavelength in the range of about 510 nm to about 550 nm, and the third light emitting element ED3 disposed in the third light emitting area EA3 may emit a blue third light having a peak wavelength in the range of about 440 nm to about 480 nm. The first to third light emitting areas EA1 , EA2 , and EA3 constituting one pixel may include light emitting elements ED1 , ED2 , and ED3 for emitting light of different colors to represent a white grayscale.

[0099] In another embodiment, the light-emitting layers EL1, EL2, and EL3 may include two or more materials for emitting light of different colors, so that one light-emitting layer can emit mixed light (e.g., mixed color light). For example, the light-emitting layers EL1, EL2, and EL3 may include both a material for emitting red light and a material for emitting green light to emit yellow light, or may include all of a material for emitting red light, a material for emitting green light, and a material for emitting blue light to emit white light. The light-emitting layers EL1, EL2, and EL3 may have a series structure in which a plurality of light-emitting stacks are stacked one on another. For example, the light-emitting layers EL1, EL2, and EL3 may emit white light by stacking a first stack including a material for emitting red light, a second stack including a material for emitting green light, and a third stack including a material for emitting blue light. In another embodiment, the light-emitting layers EL1, EL2, and EL3 may include a third stack including a material for emitting blue light and a fourth stack including a material for emitting yellow light to emit white light.

[0100] The pixel electrodes AE1, AE2, and AE3 may be disposed on the second passivation layer PAS2. The pixel electrodes AE1, AE2, and AE3 may be disposed in a plurality of light emitting areas EA1, EA2, and EA3, respectively. The pixel electrodes AE1, AE2, and AE3 may include a first pixel electrode AE1 disposed in the first light emitting area EA1, a second pixel electrode AE2 disposed in the second light emitting area EA2, and a third pixel electrode AE3 disposed in the third light emitting area EA3. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be spaced apart from each other on the second passivation layer PAS2.

[0101] The pixel electrodes AE1, AE2 and AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first and second connection electrodes CNE1 and CNE2. The edges of the spaced-apart pixel electrodes AE1, AE2 and AE3 may be covered by the pixel defining layer PDL so that the first to third pixel electrodes AE1, AE2 and AE3 may be insulated from each other.

[0102] The pixel electrodes AE1, AE2 and AE3 may include a transparent electrode material and / or a conductive metal material. The metal material may be one or more of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), lanthanum (La) and titanium (Ti). The pixel electrodes AE1, AE2 and AE3 may also include titanium nitride (TiN). The transparent electrode material may be one or more of indium tin oxide (ITO), indium zinc oxide (IZO) and indium tin zinc oxide (ITZO). The pixel electrodes AE1, AE2 and AE3 may have a multilayer structure of a transparent electrode material and a conductive metal material.

[0103] The pixel defining layer PDL may be disposed on the second passivation layer PAS2, the residual pattern RP, and the pixel electrodes AE1, AE2, and AE3. The pixel defining layer PDL may be disposed entirely on the second passivation layer PAS2, and may cover the side surfaces of the pixel electrodes AE1, AE2, and AE3 and the residual pattern RP while exposing a portion of the upper surfaces of the pixel electrodes AE1, AE2, and AE3. For example, the pixel defining layer PDL may expose the first pixel electrode AE1 in the first light emitting area EA1, and the first light emitting layer EL1 may be disposed directly on the first pixel electrode AE1.

[0104] The pixel defining layer PDL may include an inorganic insulating material and may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, a tantalum oxide layer, a hafnium oxide layer, a zinc oxide layer, and an amorphous silicon layer.

[0105] According to one embodiment, the pixel defining layer PDL may be disposed on the pixel electrodes AE1, AE2, and AE3, and may be spaced apart from the upper surfaces of the pixel electrodes AE1, AE2, and AE3. The pixel defining layer PDL may not directly contact the upper surfaces of the pixel electrodes AE1, AE2, and AE3, but may partially overlap the upper surfaces of the pixel electrodes AE1, AE2, and AE3 in the thickness direction (e.g., the third direction DR3) of the substrate SUB, and the residual pattern RP may be disposed between the pixel defining layer PDL and the pixel electrodes AE1, AE2, and AE3. However, the pixel defining layer PDL may directly contact the side surfaces of the pixel electrodes AE1, AE2, and AE3. The side surface of the pixel defining layer PDL may protrude more toward the light emitting regions EA1, EA2, and EA3 than the side surface of the second bank BN2 (e.g., the side surface of the pixel defining layer PDL may protrude toward the light emitting regions EA1, EA2, and EA3 beyond the side surface of the second bank BN2).

[0106] The residual pattern RP may be disposed on the edge of each of the pixel electrodes AE1, AE2, and AE3. Due to the residual pattern RP, the pixel defining layer PDL may not directly contact the upper surface of the pixel electrodes AE1, AE2, and AE3. In the manufacturing process of the display device 10, a portion of the sacrificial layer disposed on the pixel electrodes AE1, AE2, and AE3 may be removed so that the residual pattern RP may be formed. The residual pattern RP may include a metal or oxide semiconductor material. In the illustrated embodiment, the side surface of the residual pattern RP pointing to the light emitting areas EA1, EA2, and EA3 is shown as being much more recessed than the side surface of the pixel defining layer PDL, but the present disclosure is not limited thereto. The side surface of the residual pattern RP facing the light emitting areas EA1, EA2, and EA3 may be aligned with the side surface of the pixel defining layer PDL facing the light emitting areas EA1, EA2, and EA3, or may protrude much more than the side surface of the pixel defining layer PDL. The side surface of the pixel defining layer PDL may be the outermost surface pointing to the light emitting areas EA1, EA2, and EA3.

[0107] The light-emitting layers EL1, EL2, and EL3 may be disposed on the pixel electrodes AE1, AE2, and AE3. The light-emitting layers EL1, EL2, and EL3 may be organic light-emitting layers made of organic materials and may be formed on the pixel electrodes AE1, AE2, and AE3 by a deposition process. The light-emitting layers EL1, EL2, and EL3 may have a multilayer structure, and each of a hole injection material, a hole transport material, a light-emitting material, an electron transport material, and / or an electron injection material may constitute a layer of the light-emitting layers EL1, EL2, and EL3. When the thin film transistor TFT applies a voltage (e.g., a predetermined voltage) to the pixel electrodes AE1, AE2, and AE3 of the light-emitting elements ED1, ED2, and ED3 and the common electrodes CE1, CE2, and CE3 of the light-emitting elements ED1, ED2, and ED3 receive a common voltage or a cathode voltage, holes and electrons may be injected and transported, and the holes and electrons may be recombined with each other in the light-emitting layers EL1, EL2, and EL3 to emit light.

[0108] The light-emitting layers EL1, EL2, and EL3 may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3, which are respectively arranged in different light-emitting areas EA1, EA2, and EA3. The first light-emitting layer EL1 may be arranged on the first pixel electrode AE1 in the first light-emitting area EA1, the second light-emitting layer EL2 may be arranged on the second pixel electrode AE2 in the second light-emitting area EA2, and the third light-emitting layer EL3 may be arranged on the third pixel electrode AE3 in the third light-emitting area EA3. The plurality of light-emitting layers EL1, EL2, and EL3 may emit light of different colors, respectively, or one of the light-emitting layers EL1, EL2, and EL3 may emit mixed light (e.g., light of mixed colors). In one embodiment, the first light-emitting layer EL1 may emit red light, the second light-emitting layer EL2 may emit green light, and the third light-emitting layer EL3 may emit blue light. In another embodiment, the first light-emitting layer EL1 may emit yellow light as a mixture of red light and green light, and the second light-emitting layer EL2 may emit blue light. In another embodiment, the first light-emitting layer EL1 may emit white light as a mixture of red light, green light, and blue light. The light emitting layer for emitting mixed light or white light may have a tandem structure in which a plurality of light emitting stacks are stacked.

[0109] The light emitting layers EL1, EL2, and EL3 may be disposed on an upper surface of the pixel defining layer PDL. In one embodiment, the light emitting layers EL1, EL2, and EL3 may be disposed in a space between the pixel electrodes AE1, AE2, and AE3 and the pixel defining layer PDL. In one embodiment, the light emitting layers EL1, EL2, and EL3 may contact the pixel defining layer PDL, the residual pattern RP, and the pixel electrodes AE1, AE2, and AE3.

[0110] The common electrodes CE1, CE2, and CE3 may be disposed on the light emitting layers EL1, EL2, and EL3. The common electrodes CE1, CE2, and CE3 may include a transparent conductive material so that light generated from the light emitting layers EL1, EL2, and EL3 may be emitted. The common electrodes CE1, CE2, and CE3 may receive a common voltage or a low potential voltage. When the pixel electrodes AE1, AE2, and AE3 receive a voltage corresponding to the data voltage and the common electrodes CE1, CE2, and CE3 receive a low potential voltage, a potential difference may be formed between the pixel electrodes AE1, AE2, and AE3 and the common electrodes CE1, CE2, and CE3 so that the light emitting layers EL1, EL2, and EL3 may emit light.

[0111] The common electrodes CE1, CE2, and CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3 respectively disposed in different light emitting areas EA1, EA2, and EA3. The first common electrode CE1 may be disposed on the first light emitting layer EL1 in the first light emitting area EA1, the second common electrode CE2 may be disposed on the second light emitting layer EL2 in the second light emitting area EA2, and the third common electrode CE3 may be disposed on the third light emitting layer EL3 in the third light emitting area EA3. The first to third common electrodes CE1, CE2, and CE3 may be spaced apart from each other.

[0112] The cover layers CAP1, CAP2, and CAP3 may be disposed on the common electrodes CE1, CE2, and CE3, respectively. The cover layers CAP1, CAP2, and CAP3 may include an organic material or an inorganic insulating material to cover the light emitting elements ED1, ED2, and ED3. The cover layers CAP1, CAP2, and CAP3 may prevent the light emitting elements ED1, ED2, and ED3 from being damaged by external air. In an embodiment, the cover layers CAP1, CAP2, and CAP3 may include an organic material (such as a-NPD, NPB, TPD, m-MTDATA, Alq 3 , LiF and / or CuPc) or an inorganic material (such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride).

[0113] The capping layers CAP1, CAP2, and CAP3 may include first, second, and third capping layers CAP1, CAP2, and CAP3, respectively disposed in different light emitting areas EA1, EA2, and EA3. The first to third capping layers CAP1, CAP2, and CAP3 may be spaced apart from each other.

[0114] Figure 5 is an enlarged view of the embankment structure BNS, and is Figure 4 A magnified view of area A1. Figure 5 The bank structure BNS disposed between the first light emitting area EA1 and the second light emitting area EA2 is shown, but referring to Figure 5 The description may be equally applied to the embankment structure BNS between the second light emitting area EA2 and the third light emitting area EA3 and the embankment structure BNS between the third light emitting area EA3 and the first light emitting area EA1.

[0115] The display device 10 may include a plurality of embankment structures BNS disposed on the pixel defining layer PDL. The embankment structure BNS may have a structure in which embankments BN1 and BN2 including materials different from each other are sequentially stacked, may have a plurality of openings including light-emitting areas EA1, EA2, and EA3 (e.g., forming or overlapping the light-emitting areas EA1, EA2, and EA3), and may be disposed to overlap with a light-blocking layer to be described later. The light-emitting elements ED1, ED2, and ED3 of the display device 10 may be disposed to overlap with the openings in the embankment structure BNS.

[0116] The first bank BN1 may be disposed on the pixel defining layer PDL. The first bank BN1 may have a lower surface facing the pixel defining layer PDL and an upper surface facing the second bank BN2.

[0117] The areas (e.g., surface areas) of the lower surface and the upper surface of the first bank BN1 may be different from each other. For example, the width w11 of the lower surface and the width w12 of the upper surface of the first bank BN1 may be different from each other. Here, the width may be a length measured in a direction parallel to the substrate SUB (e.g., the upper surface of the substrate SUB) (or parallel to the substrate SUB (e.g., the upper surface of the substrate SUB)). The first bank BN1 may have a trapezoidal cross-section. The first bank BN1 may have a conical or inverted conical cross-section. The conical shape refers to a shape having an angle of less than 90° between the lower surface (e.g., bottom surface) and the side surface in a cross-sectional view of the first bank BN1 taken along the thickness direction of the substrate (e.g., the third direction DR3). In addition, the inverted conical shape refers to a shape having an angle of greater than 90° between the lower surface (e.g., bottom surface) and the side surface in a cross-sectional view of the first bank BN1 taken along the thickness direction of the substrate (e.g., the third direction DR3).

[0118] In one embodiment, the width w11 of the lower surface of the first bank BN1 may be smaller than the width w12 of the upper surface. The angle θ1 between the lower surface and the side of the first bank BN1 may be an obtuse angle greater than 90°. The first bank BN1 may have an inverted tapered cross-sectional shape whose width decreases (or narrows) from the upper surface toward the lower surface. The first bank BN1 may have a third width w13 between the upper surface and the lower surface, and the third width w13 may be a value between the width w11 of the lower surface and the width w12 of the upper surface. When the width w11 of the lower surface of the first bank BN1 is smaller than the width w12 of the upper surface, the deposited materials of the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 may be smoothly separated.

[0119] The side surface of the first bank BN1 may be more recessed than the side surface of the pixel defining layer PDL in a direction opposite to the direction pointing to the light emitting areas EA1, EA2, and EA3 (e.g., in a direction away from the light emitting areas EA1, EA2, and EA3). The width w11 of the lower surface of the first bank BN1 may be less than the width of the upper surface of the pixel defining layer PDL. The side surface of the first bank BN1 may be more recessed than the side surface of the second bank BN2 in a direction opposite to the direction pointing to the light emitting areas EA1, EA2, and EA3 (e.g., in a direction away from the light emitting areas EA1, EA2, and EA3).

[0120] The first bank BN1 may include a conductive material. In one embodiment, the first bank BN1 may include a conductive material that does not include a metal. In an embodiment, the first bank BN1 may include one or more of polysilicon, amorphous carbon, graphite, and graphene. Graphite and graphene may include amorphous carbon between hexagonal crystals of carbon. When the first bank BN1 includes a non-metallic conductive material, any concerns about high resistance due to metal oxides may be alleviated, and moisture penetration may be avoided due to high adhesion between the first bank BN1 and the lower inorganic encapsulation layers TL1, TL2, and TL3.

[0121] In one embodiment, the thickness or height of the first bank BN1 may be about to about When the first bank BN1 is within this range, the deposited materials of the light emitting layers EL1, EL2 and EL3 and the common electrodes CE1, CE2 and CE3 may be broken (or separated) at the boundaries of the openings in the bank structure BNS. In one embodiment, the thickness of the first bank BN1 may be substantially greater than the thickness of the second bank BN2.

[0122] The first bank BN1 may expose the common electrodes CE1, CE2, and CE3. According to one embodiment, the common electrodes CE1, CE2, and CE3 may be in direct contact with the first bank BN1. One end and the other end (e.g., opposite ends) of the common electrodes CE1, CE2, and CE3 may be in contact with the side surface of the first bank BN1. The common electrodes CE1, CE2, and CE3 of different light emitting elements ED1, ED2, and ED3 may be in direct contact with the first bank BN1, and the first bank BN1 may include a conductive material so that the common electrodes CE1, CE2, and CE3 may be electrically connected to each other through the first bank BN1.

[0123] The light emitting layers EL1, EL2, and EL3 may be in direct contact with the side surface of the first bank BN1. The area in which the common electrodes CE1, CE2, and CE3 contact the side surface of the first bank BN1 may be larger than the area in which the light emitting layers EL1, EL2, and EL3 contact the side surface of the first bank BN1. The common electrodes CE1, CE2, and CE3 may be disposed on the side surface of the first bank BN1 to reach a larger area than the light emitting layers EL1, EL2, and EL3, or disposed at a higher position on the side surface of the first bank BN1. Because the common electrodes CE1, CE2, and CE3 of different light emitting elements ED1, ED2, and ED3 are electrically connected to each other through the first bank BN1, the common electrodes CE1, CE2, and CE3 may contact the first bank BN1 in more areas to provide various advantages.

[0124] The second bank BN2 may be disposed on the first bank BN1. The second bank BN2 may have a tip, that is, have an area that protrudes more than the first bank BN1 (e.g., protrudes beyond the first bank BN1). The side surface of the second bank BN2 may protrude more toward the light-emitting areas EA1, EA2, and EA3 than the side surface of the first bank BN1. For example, the width w2 of the second bank BN2 may be greater than the width w12 of the upper surface of the first bank BN1. Although the second bank BN2 is shown as having a constant width, the second bank BN2 may have different widths at the upper and lower surfaces. In such an embodiment, the width of the lower surface of the second bank BN2 may be greater than the width w12 of the upper surface of the first bank BN1.

[0125] Since the side surface of the second bank BN2 has a shape that protrudes more toward the light emitting areas EA1 , EA2 , and EA3 than the side surface of the first bank BN1 , the first bank BN1 may form an undercut structure below the tip of the second bank BN2 .

[0126] In the display device 10, according to one embodiment, the embankment structure BNS may have a tip protruding toward the light-emitting regions EA1, EA2, and EA3, so that the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 spaced apart from each other can be formed by a deposition process and an etching process without using a mask. In addition, different layers can be formed separately in different light-emitting regions EA1, EA2, and EA3 by a deposition process. For example, although the light-emitting layers EL1, EL2, and EL3 of the light-emitting elements ED1, ED2, and ED3 and the common electrodes CE1, CE2, and CE3 can be formed by a deposition process without using a mask, the deposited material can be disconnected by the tip of the second embankment BN2 through the embankment structure BNS interposed therebetween without being connected between the light-emitting regions EA1, EA2, and EA3 (for example, not connected through the light-emitting regions EA1, EA2, and EA3). After the material for forming a specific layer is formed on the entire surface of the display device 10, different layers can be formed separately in different light-emitting regions EA1, EA2, and EA3 by etching to remove the layer formed in the undesired region. Different light emitting elements ED1, ED2 and ED3 can be formed in the light emitting areas EA1, EA2 and EA3 respectively through deposition and etching processes without using a mask process, so unnecessary elements in the display device 10 can be omitted and the size of the non-display area NDA can be reduced or minimized.

[0127] Because the first bank BN1 and the second bank BN2 include respective materials different from each other, the side shape of the bank structure BNS may have a structure formed due to a difference in etching rates in an etching process. According to one embodiment, the second bank BN2 may include a material having an etching rate slower than that of the first bank BN1, so that the first bank BN1 may be further etched during the etching process, so that the lower surface of the tip of the second bank BN2 may be exposed, and an undercut may be formed under the second bank BN2.

[0128] The second bank BN2 may include a silicon inorganic material such as silicon oxide, silicon nitride and / or silicon oxynitride, or may include a metal. In one embodiment, the second bank BN2 may include SiO x 、SiN y 、SiO x N y and one or more of metals. Examples of the metal included in the second bank BN2 may be titanium (Ti) or molybdenum (Mo), but are not limited thereto. In one embodiment, the second bank BN2 may have a single-layer structure or a multi-layer structure of the above materials.

[0129] The tip of the second bank BN2 may overlap the common electrodes CE1, CE2, and CE3, the light-emitting layers EL1, EL2, and EL3, and / or the pixel defining layer PDL in a third direction DR3 perpendicular to the substrate SUB. The common electrodes CE1, CE2, and CE3 may be spaced apart from each other, and one end and the other end (e.g., opposite ends) of each of the common electrodes CE1, CE2, and CE3 may overlap the second bank BN2 in a thickness direction (e.g., third direction DR3) of the substrate SUB. The maximum vertical distance from the substrate SUB to the common electrodes CE1, CE2, and CE3 may be less than the maximum vertical distance from the substrate SUB to the upper surface of the first bank BN1.

[0130] Figure 6 is an enlarged view showing a bank structure BNS of a display device according to another embodiment. Figure 6 The embodiments shown in Figure 5 The embodiment shown in FIG. 1 is different in that the auxiliary electrode AXE is disposed between the first bank BN1 and the pixel defining layer PDL. The above description may be applied to other elements except the auxiliary electrode AXE, and the auxiliary electrode AXE will be described in detail.

[0131] The auxiliary electrode AXE may contact the common electrodes CE1, CE2, and CE3 and may include a conductive material. The common electrodes CE1, CE2, and CE3 may be electrically connected to each other through the auxiliary electrode AXE and the first bank BN1. The auxiliary electrode AXE may include a low-resistance metal. In one embodiment, the auxiliary electrode AXE may include one or more of copper, aluminum, and molybdenum.

[0132] In one embodiment, the light emitting layers EL1, EL2 and EL3 may directly contact the auxiliary electrode AXE and may not contact the first bank BN1. The areas of the common electrodes CE1, CE2 and CE3 contacting the first bank BN1 and the auxiliary electrode AXE may be larger than the areas of the light emitting layers EL1, EL2 and EL3 contacting the auxiliary electrode AXE.

[0133] The width of the auxiliary electrode AXE may be different from the width of the lower surface of the first bank BN1. In one embodiment, the width of the auxiliary electrode AXE may be greater than the width of the lower surface of the first bank BN1. The width of the auxiliary electrode AXE may be less than the width of the upper surface of the pixel defining layer PDL.

[0134] Figure 7 is an enlarged view showing a display device according to another embodiment. Figure 7 The embodiments shown in Figure 6 The embodiment shown in FIG. 1 is different in that the common electrodes CE1 , CE2 , and CE3 do not contact the first bank BN1 , and ends of the common electrodes CE1 , CE2 , and CE3 are spaced apart from the side surface of the first bank BN1 .

[0135] When the common electrodes CE1, CE2, and CE3 are disconnected from the first bank BN1 and are not electrically connected to the first bank BN1 or the common electrodes CE1, CE2, and CE3 are not formed on the side surface of the first bank BN1, the common electrodes CE1, CE2, and CE3 spaced apart from each other may be electrically connected to each other through the auxiliary electrode AXE. The common electrodes CE1, CE2, and CE3 may contact the upper surface and the side surface of the auxiliary electrode AXE.

[0136] The light emitting layers EL1, EL2 and EL3 may directly contact the auxiliary electrode AXE. An area where the common electrodes CE1, CE2 and CE3 contact the auxiliary electrode AXE may be greater than an area where the light emitting layers EL1, EL2 and EL3 contact the auxiliary electrode AXE.

[0137] Figure 8 is an enlarged view showing a bank structure BNS of a display device according to another embodiment. Figure 8 The embodiments shown in Figure 5 The embodiment shown in FIG. 1 is different in that the third bank BN3 and the fourth bank BN4 are stacked on the second bank BN2 .

[0138] The third bank BN3 may be disposed on the second bank BN2. The third bank BN3 may have a lower surface facing the second bank BN2 and an upper surface opposite to the lower surface.

[0139] The areas (e.g., surface areas) of the lower surface and the upper surface of the third bank BN3 may be different from each other. The width w31 of the lower surface of the third bank BN3 and the width w32 of the upper surface of the third bank BN3 may be different from each other. The third bank BN3 may have a trapezoidal cross-sectional shape. The third bank BN3 may have a conical or inverted conical cross-sectional shape.

[0140] In one embodiment, a width w31 of a lower surface of the third bank BN3 may be smaller than a width w32 of an upper surface of the third bank BN3. A width w31 of a lower surface of the third bank BN3 may be smaller than a width w2 of the second bank BN2.

[0141] Figure 8 An embodiment is shown in which the width w31 of the lower surface of the third bank BN3 is the same as the width w11 of the lower surface of the first bank BN1, but the present disclosure is not limited thereto. The width w31 of the lower surface of the third bank BN3 may be different from the width w11 of the lower surface of the first bank BN1. The width w31 of the lower surface of the third bank BN3 may be greater than or less than the width w11 of the lower surface of the first bank BN1. Figure 8, although the width w32 of the upper surface of the third bank BN3 is shown to be the same as the width w12 of the upper surface of the first bank BN1, the present disclosure is not limited thereto. The width w32 of the upper surface of the third bank BN3 may be different from the width w12 of the upper surface of the first bank BN1. The width w32 of the upper surface of the third bank BN3 may be greater than or less than the width w12 of the upper surface of the first bank BN1.

[0142] The angle θ2 between the lower surface and the side of the third bank BN3 may be an obtuse angle greater than 90°. The angle θ2 between the lower surface and the side of the third bank BN3 may be the same as or different from the angle θ1 defined between the lower surface and the side of the first bank BN1. The angle θ2 between the lower surface and the side of the third bank BN3 may be greater than or less than the angle θ1 between the lower surface and the side of the first bank BN1.

[0143] The thickness of the third bank BN3 may be greater than the thickness of the fourth bank BN4. The thickness of the third bank BN3 may be the same as or different from the thickness of the first bank BN1.

[0144] The third bank BN3 may include a conductive material. In one embodiment, the third bank BN3 may include a conductive material that does not include metal. In an embodiment, the third bank BN3 may include one or more of polysilicon, amorphous carbon, graphite, and graphene. In one embodiment, the third bank BN3 may include the same material as the first bank BN1.

[0145] The fourth bank BN4 may be disposed on the third bank BN3. A side surface of the fourth bank BN4 may protrude more toward the light emitting areas EA1, EA2, and EA3 than a side surface of the third bank BN3. A width w4 of the fourth bank BN4 may be greater than a width w32 of an upper surface of the third bank BN3. Figure 8 Although shown as having a constant width in FIG. 1 , the fourth bank BN4 may have a width difference between the upper surface and the lower surface. The width of the lower surface of the fourth bank BN4 may be greater than the width w32 of the upper surface of the third bank BN3.

[0146] The fourth bank BN4 may include a material different from that of the third bank BN3. The fourth bank BN4 may include a silicon inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride, or may include a metal. In one embodiment, the fourth bank BN4 may include SiO x 、SiN y 、SiO x N y and one or more of metals. Examples of the metal included in the fourth bank BN4 may be titanium (Ti) or molybdenum (Mo), but are not limited thereto. In one embodiment, the fourth bank BN4 may include the same material as that of the second bank BN2.

[0147] Fig. 9 is an enlarged view showing a display device according to another embodiment. Fig. 9 The embodiments shown in Figure 8 The embodiment shown in FIG. 4 is different in that the auxiliary electrode AXE is disposed between the first bank BN1 and the pixel defining layer PDL. Figure 6 The description of can be equally applied to the auxiliary electrode AXE.

[0148] Fig.10 is an enlarged view showing a display device according to another embodiment. Fig.10 The embodiments shown in Fig. 9 The embodiment shown in FIG. 1 is different in that the common electrodes CE1, CE2 and CE3 are not in contact with the first bank BN1, and the ends of the common electrodes CE1, CE2 and CE3 are spaced apart from the side surface of the first bank BN1. Figure 7 As described above, the common electrodes CE1 , CE2 , and CE3 spaced apart from each other may be electrically connected to each other through the auxiliary electrode AXE.

[0149] Reference Figure 4 , the display device 10 may include trace patterns TRP1, TRP2, and TRP3 that become traces of the deposition process on the bank structure BNS. The trace patterns TRP1, TRP2, and TRP3 may include light emitting patterns ELP1, ELP2, and ELP3, electrode patterns CEP1, CEP2, and CEP3, and cover patterns CPP1, CPP2, and CPP3, and may surround outer edges of the light emitting areas EA1, EA2, and EA3 on the second bank BN2 (e.g., may extend around outer edges of the light emitting areas EA1, EA2, and EA3 on the second bank BN2).

[0150] The trace patterns TRP1, TRP2, and TRP3 may be traces formed when the deposited material is disconnected from the light-emitting layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3, and the covering layers CAP1, CAP2, and CAP3 in the light-emitting areas EA1, EA2, and EA3 through the tip of the embankment structure BNS (or the tip formed by the embankment structure BNS). When the light-emitting material is completely deposited, the light-emitting layers EL1, EL2, and EL3 may be formed in the openings, and the light-emitting patterns ELP1, ELP2, and ELP3 may be formed on the embankment structure BNS. The light-emitting patterns ELP1, ELP2, and ELP3 may be disconnected from the light-emitting layers EL1, EL2, and EL3 through the tip of the embankment structure BNS. Similarly, the common electrodes CE1, CE2, and CE3 and / or the electrode patterns CEP1, CEP2, and CEP3 and the covering layers CAP1, CAP2, and CAP3 and / or the covering patterns CPP1, CPP2, and CPP3 may be disconnected through the tip, and their traces may remain on the embankment structure BNS. The trace patterns TRP1, TRP2, and TRP3 may be formed by patterning each of the light emitting areas EA1, EA2, and EA3 or by patterning the periphery of the opening.

[0151] The display device 10 may include light emitting patterns ELP1, ELP2, and ELP3 disposed over the bank structure BNS. The light emitting patterns EL1, ELP2, and ELP3 may include first, second, and third light emitting patterns ELP1, ELP2, and ELP3 disposed on the second bank BN2 of the bank structure BNS.

[0152] The first light emitting pattern ELP1 may include the same material as that of the first light emitting layer EL1 of the first light emitting element ED1, the second light emitting pattern ELP2 may include the same material as that of the second light emitting layer EL2 of the second light emitting element ED2, and the third light emitting pattern ELP3 may include the same material as that of the third light emitting layer EL3 of the third light emitting element ED3. Each of the light emitting patterns ELP1, ELP2, and ELP3 may be formed in (or during) a process of forming the light emitting layers EL1, EL2, and EL3 including the same material, and may be disposed adjacent to the light emitting areas EA1, EA2, and EA3 in which the light emitting layers EL1, EL2, and EL3 are disposed, respectively.

[0153] The display device 10 according to one embodiment may include a plurality of electrode patterns CEP1, CEP2, and CEP3 disposed on the embankment structure BNS, and the plurality of electrode patterns CEP1, CEP2, and CEP3 may include the same material as that of the common electrodes CE1, CE2, and CE3. The first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be directly disposed on the first light-emitting pattern ELP1, the second light-emitting pattern ELP2, and the third light-emitting pattern ELP3, respectively. The arrangement relationship of the electrode patterns CEP1, CEP2, and CEP3 with the light-emitting patterns ELP1, ELP2, and ELP3 may be the same as the arrangement relationship of the light-emitting layers EL1, EL2, and EL3 with the common electrodes CE1, CE2, and CE3.

[0154] The display device 10 may include cover patterns CPP1, CPP2, and CPP3 disposed above the embankment structure BNS. The first cover pattern CPP1, the second cover pattern CPP2, and the third cover pattern CPP3 may be disposed directly on the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3, respectively. The arrangement relationship of the cover patterns CPP1, CPP2, and CPP3 with the electrode patterns CEP1, CEP2, and CEP3 may be the same as the arrangement relationship of the common electrodes CE1, CE2, and CE3 with the cover layers CAP1, CAP2, and CAP3.

[0155] The thin film encapsulation layer TFEL may be disposed on the light emitting elements ED1, ED2, and ED3 and the embankment structure BNS, and may cover the plurality of light emitting elements ED1, ED2, and ED3 and the embankment structure BNS. The thin film encapsulation layer TFEL may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one organic film to protect the light emitting element layer EML from particles such as dust.

[0156] In an embodiment, the thin film encapsulation layer TFEL may include a lower inorganic encapsulation layer TFE1 , an organic encapsulation layer TFE2 , and an upper inorganic encapsulation layer TFE3 that are sequentially stacked on one another.

[0157] Each of the lower inorganic encapsulation layer TFE1 and the upper inorganic encapsulation layer TFE3 may include one or more inorganic insulating materials. The inorganic insulating material may be any one of silicon oxide, silicon nitride and silicon oxynitride, and may be, for example, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride.

[0158] The organic encapsulation layer TFE2 may include a polymer material. The polymer material may include an acrylic resin, an epoxy resin, a polyimide, and a polyethylene. For example, the organic encapsulation layer TFE2 may include an acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.). The organic encapsulation layer TFE2 may be formed by curing a monomer or coating a polymer.

[0159] The lower inorganic encapsulation layer TFE1 may be disposed on the light emitting elements ED1, ED2, and ED3, the trace patterns TRP1, TRP2, and TRP3, and the embankment structure BNS. The lower inorganic encapsulation layer TFE1 may include a first inorganic layer TL1, a second inorganic layer TL2, and a third inorganic layer TL3, and the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 are disposed to correspond to different light emitting areas EA1, EA2, and EA3, respectively. Each of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may include an inorganic insulating material to cover the light emitting elements ED1, ED2, and ED3. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may prevent the light emitting elements ED1, ED2, and ED3 from being damaged by external air.

[0160] The lower inorganic encapsulation layer TFE1 (TL1, TL2 and TL3) can be formed by a chemical vapor deposition (CVD) method, and thus can be formed along the step difference of the deposition layer. For example, the first inorganic layer TL1, the second inorganic layer TL2 and the third inorganic layer TL3 can even form a thin film under the undercut caused by the tip of the embankment structure BNS (or formed by the tip of the embankment structure BNS). The lower inorganic encapsulation layers TL1, TL2 and TL3 can be disposed on the light-emitting elements ED1, ED2 and ED3, the electrode patterns CEP1, CEP2 and CEP3 and the embankment structure BNS. The first inorganic layer TL1 can be disposed along the side surface of the first embankment BN1 adjacent to the first light-emitting element ED1, the first covering layer CAP1 and the first common electrode CE1 to cover the first light-emitting element ED1, the first covering layer CAP1 and the first common electrode CE1, and can be disposed to cover the first light-emitting pattern ELP1, the first electrode pattern CEP1 and the first covering pattern CPP1 by passing through the side surface of the second embankment BN2 (or extending along the side surface of the second embankment BN2).

[0161] The first inorganic layer TL1 may not overlap with the second light emitting element ED2 and the third light emitting element ED3, and may be disposed only on the first light emitting element ED1 and the embankment structure BNS near the first light emitting element ED1. The second inorganic layer TL2 may not overlap with the first light emitting element ED1 and the third light emitting element ED3, and may be disposed only on the second light emitting element ED2 and the embankment structure BNS near the second light emitting element ED2. The third inorganic layer TL3 may not overlap with the first light emitting element ED1 and the second light emitting element ED2, and may be disposed only on the third light emitting element ED3 and the embankment structure BNS near the third light emitting element ED3.

[0162] The first inorganic layer TL1 may be formed after forming the first common electrode CE1, the second inorganic layer TL2 may be formed after forming the second common electrode CE2, and the third inorganic layer TL3 may be formed after forming the third common electrode CE3. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may be arranged to be spaced apart from each other on the embankment structure BNS. Therefore, a portion of the second embankment BN2 or the fourth embankment BN4 may not overlap with the first to third inorganic layers TL1, TL2, and TL3, and a portion of the upper surface of the second embankment BN2 or the fourth embankment BN4 may be exposed in the space between the first to third inorganic layers TL1, TL2, and TL3 without being covered by the first to third inorganic layers TL1, TL2, and TL3. The exposed upper surface of the second embankment BN2 or the fourth embankment BN4 may be in direct contact with the organic encapsulation layer TFE2 of the thin film encapsulation layer TFEL.

[0163] Reference Figure 3 and Figure 4, each of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may have a boundary at the outer surface of the light emitting area EA1, EA2, and EA3 in which the light emitting elements ED1, ED2, and ED3 are disposed. In a plan view, the first trace pattern to the third trace pattern TRP1, TRP2, and TRP3 may have a ring shape. The trace patterns TRP1, TRP2, and TRP3 may be positioned on the tip of the second bank BN2, and may have an inner boundary adjacent to the light emitting area EA1, EA2, and EA3 and an outer boundary positioned between the light emitting areas EA1, EA2, and EA3 while being farther away from the light emitting areas EA1, EA2, and EA3 than the inner boundary. When the electrode patterns CEP1, CEP2, and CEP3 of the trace patterns TRP1, TRP2, and TRP3 and the light emitting patterns ELP1, ELP2, and ELP3 are removed, the outer boundaries of the trace patterns TRP1, TRP2, and TRP3 may be changed by adjusting the etching process. The outer boundaries of the trace patterns TRP1, TRP2 and TRP3 may be aligned with or adjacent to the boundaries of the lower inorganic encapsulation layers TL1, TL2 and TL3. In one embodiment, the outer boundaries of the trace patterns TRP1, TRP2 and TRP3 may be positioned closer to the emission areas EA1, EA2 and EA3 than the boundaries of the lower inorganic encapsulation layers TL1, TL2 and TL3.

[0164] The organic encapsulating layer TFE2 may be disposed on the second bank BN2 and the lower inorganic encapsulating layers TL1, TL2, and TL3. A portion of the organic encapsulating layer TFE2 may be in contact with the second bank BN2 or the fourth bank BN4.

[0165] The upper inorganic encapsulation layer TFE3 may be disposed on the organic encapsulation layer TFE2. The upper inorganic encapsulation layer TFE3 may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0166] The light-blocking layer may be selectively disposed on the thin film encapsulation layer TFEL. The light-blocking layer may be positioned between the light-emitting areas EA1, EA2, and EA3. The light-blocking layer may include a light-absorbing material. For example, the light-blocking layer may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but they are not limited thereto. The light-blocking layer may prevent color mixing due to transmission of visible light between the first light-emitting area to the third light-emitting area EA1, EA2, and EA3, thereby improving the color reproducibility of the display device 10.

[0167] The display device 10 may include a plurality of color filters CF1, CF2, and CF3 disposed on the light emitting areas EA1, EA2, and EA3. Each of the plurality of color filters CF1, CF2, and CF3 may have a color filter pattern region and a light blocking region. The color filter pattern region may be formed to overlap with the light emitting areas EA1, EA2, and EA3 or the opening in the embankment structure BNS, and may form a light output region through which light emitted from the light emitting areas EA1, EA2, and EA3 is output. The light blocking region is a region in which a plurality of color filters CF1, CF2, and CF3 are stacked so that light cannot be transmitted therethrough.

[0168] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 that are respectively set to correspond to different light-emitting areas EA1, EA2, and EA3. The color filters CF1, CF2, and CF3 may include a colorant (such as a dye or a pigment) for absorbing light of another band other than the light of a specific band, and may be set to correspond to the color of the light emitted from the light-emitting areas EA1, EA2, and EA3. For example, the first color filter CF1 may be a red color filter that is set to overlap with the first light-emitting area EA1 and transmits only the red first light. The second color filter CF2 may be a green color filter that is set to overlap with the second light-emitting area EA2 and transmits only the green second light. The third color filter CF3 may be a blue color filter that is set to overlap with the third light-emitting area EA3 and transmits only the blue third light.

[0169] Because the color filters CF1, CF2, and CF3 are arranged to overlap each other, the display device 10 can reduce the intensity of the reflected light due to the external light. In addition, the color sense of the reflected light due to the external light can be controlled by adjusting the layout, shape, area, etc. of the color filters CF1, CF2, and CF3 in the plan view.

[0170] An overcoat OC may be disposed on the color filters CF1, CF2, and CF3 to flatten the upper ends (or upper surfaces) of the color filters CF1, CF2, and CF3. The overcoat OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat OC may include a colorless light-transmitting organic material such as acrylic resin.

[0171] Fig.11 is a view showing a virtual reality device including a display device according to one embodiment. Fig.11 The display device 10_1 shown in FIG. 1 may include a display device 10_1 according to the reference Figures 1 to 10 A display device according to any one of the above-described embodiments.

[0172] Reference Fig.11The virtual reality device 1 may be a glasses-type display. The virtual reality device 1 may include a display device 10_1, a left-eye lens 10a, a right-eye lens 10b, a support frame 20, glasses frame legs 30a and 30b, a reflective member 40, and a display device housing 50.

[0173] In some embodiments, the virtual reality device 1 can be applied to a head mounted display (HMD) including a head mounted band that can be mounted on the head instead of the glasses frame legs 30a and 30b. Therefore, the virtual reality device 1 can be applied to various electronic devices in various forms.

[0174] The display device housing 50 may include a display device 10_1 and a reflective member 40. The image displayed on the display device 10_1 may be reflected by the reflective member 40 and provided to the right eye of the user through the right eye lens 10b. Therefore, the user may view the virtual reality (or augmented reality) image displayed on the display device 10_1 through the right eye.

[0175] The display device housing 50 may be disposed at the right end of the support frame 20, but its position is not limited thereto. For example, the display device housing 50 may be disposed at the left end of the support frame 20, and in such an embodiment, the image displayed on the display device 10_1 may be reflected by the reflective member 40 and provided to the left eye of the user through the left eye lens 10a. Therefore, the user may view the virtual reality image displayed on the display device 10_1 through the left eye.

[0176] As another example, the display device housing 50 may be provided at both the left and right ends of the support frame 20, and in such an embodiment, the user may view the virtual reality image displayed on the display device 10_1 through both the left eye and the right eye.

[0177] Fig.12 and Fig.13 is a view showing a head mounted display device including a display device according to one embodiment. Fig.12 and Fig.13 The display device 10_2 shown in FIG. 1 may include the display device 10_2 according to the above reference Figures 1 to 10 A display device according to any of the described embodiments.

[0178] Reference Fig.12 and Fig.13 , the display device 10_2 may be applied to a head mounted display (HMD) device. The first display device 1100 may provide an image to the right eye of the user, and the second display device 1200 may provide an image to the left eye of the user.

[0179] The first lens array 1310 may be disposed between the first display device 1100 and the receiving portion cover 1700. The first lens array 1310 may include a plurality of lenses 1311. The plurality of lenses 1311 may include convex lenses protruding toward the receiving portion cover 1700.

[0180] The second lens array 1410 may be disposed between the second display device 1200 and the receiving portion cover 1700. The second lens array 1410 may include a plurality of lenses 1411. The plurality of lenses 1411 may include convex lenses convex toward the receiving portion cover 1700.

[0181] The display panel receiving portion 1600 may receive the first display device 1100, the second display device 1200, the first lens array 1310, and the second lens array 1410. One surface of the display panel receiving portion 1600 may be open to receive the first display device 1100, the second display device 1200, the first lens array 1310, and the second lens array 1410.

[0182] The receiving portion cover 1700 may cover the open surface of the display panel receiving portion 1600. The receiving portion cover 1700 may have a first opening 1710 in which the left eye of the user is arranged and a second opening 1720 in which the right eye of the user is arranged. For example, the first opening 1710 and the second opening 1720 may be formed in a rectangular shape, but the shapes of the first opening 1710 and the second opening 1720 are not limited thereto. As another example, the first opening 1710 and the second opening 1720 may be formed in a circular or oval shape. As another example, the first opening 1710 and the second opening 1720 may be formed as a single opening.

[0183] The first opening 1710 may be aligned with the first display device 1100 and the first lens array 1310, and the second opening 1720 may be aligned with the second display device 1200 and the second lens array 1410. Therefore, the user may view the image of the first display device 1100 virtually magnified by the first lens array 1310 through the first opening 1710, and may view the image of the second display device 1200 virtually magnified by the second lens array 1410 through the second opening 1720.

[0184] The head mounting band 1800 can fix the display panel receiving part 1600 to the user's head so that the first opening 1710 and the second opening 1720 of the receiving part cover 1700 are respectively disposed at the user's left and right eyes. The head mounting band 1800 can be connected to the upper surface, left and right sides of the display panel receiving part 1600.

[0185] Fig.14 It is shown Figures 11 to 13A cross-sectional view of a pixel according to an embodiment in a display device shown in FIG. Fig.14 The display device shown in FIG. 1 may include Figure 4 The light emitting element layer EML, the thin film encapsulation layer TFEL, and the color filter layer CFL shown in FIG. 1 are illustrated, and the same elements as those described above will be briefly described or will not be described repeatedly.

[0186] Reference Fig.14 , the display panel may include a semiconductor backplane SBP, a light emitting backplane EBP, a light emitting element layer EML, a thin film encapsulation layer TFEL and a color filter layer CFL.

[0187] The semiconductor back plate SBP may include a semiconductor substrate SSUB, first to third semiconductor insulating layers SIL1 , SIL2 , and SIL3 , and a contact terminal CTE.

[0188] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well regions WA may be disposed on the upper surface of the semiconductor substrate SSUB (or formed in the upper surface of the semiconductor substrate SSUB). The plurality of well regions WA may be regions doped with a second type of impurity different from the first type of impurity. For example, when the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. As another example, when the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0189] The semiconductor substrate SSUB may include a plurality of pixel transistors PTR. The pixel transistor PTR may include a well region WA, a source region SCA, a drain region DRA, a channel region CH, a first lightly doped impurity region LDD1, a second lightly doped impurity region LDD2, a lower insulating layer BIL, a gate electrode GE, and a side insulating layer FIL.

[0190] The well area WA may be disposed on an upper portion of the semiconductor substrate SSUB. The well area WA may accommodate the source area SCA, the drain area DRA, the channel area CH, the first lightly doped impurity area LDD1, and the second lightly doped impurity area LDD2.

[0191] The source region SCA may correspond to the source electrode of the pixel transistor PTR, and the drain region DRA may correspond to the drain electrode of the pixel transistor PTR. Each of the source region SCA and the drain region DRA may be doped with first type impurities. The source region SCA may be disposed at one side of the gate electrode GE, and the drain region SA may be disposed at the other side of the gate electrode GE.

[0192] The channel region CH may be disposed between the source region SCA and the drain region DRA. The lower insulating layer BIL may be disposed on the channel region CH to insulate the channel region CH and the gate electrode GE from each other. The gate electrode GE may be disposed on the lower insulating layer BIL. The gate electrode GE may overlap the channel region CH and the well region WA in the thickness direction. The side insulating layer FIL may be disposed on the side surface of the gate electrode GE and the upper surface of the lower insulating layer BIL.

[0193] The first lightly doped impurity region LDD1 may be disposed between the channel region CH and the source region SCA, and the second lightly doped impurity region LDD2 may be disposed between the channel region CH and the drain region DRA. Due to the lower insulating layer BIL, the first lightly doped impurity region LDD1 may have an impurity concentration lower than that of the source region SCA. Due to the lower insulating layer BIL, the second lightly doped impurity region LDD2 may have an impurity concentration lower than that of the drain region DRA. The distance between the source region SCA and the drain region DRA may be increased by the first lightly doped impurity region LDD1 and the second lightly doped impurity region LDD2. Therefore, since the length of the channel region CH of the pixel transistor PTR may be increased, channel punch-through and hot carriers due to a short channel may be avoided.

[0194] The first semiconductor insulating layer SIL1 may be disposed on the semiconductor substrate SSUB. The first semiconductor insulating layer SIL1 may include silicon carbon nitride (SiCN) or silicon oxide (SiO x ) inorganic film, but not limited to this.

[0195] The second semiconductor insulating layer SIL2 may be disposed on the first semiconductor insulating layer SIL1. The second semiconductor insulating layer SIL2 may include silicon oxide (SiO x ) inorganic film, but not limited to this.

[0196] A plurality of contact terminals CTE may be disposed on the second semiconductor insulating layer SIL2. The contact terminal CTE may be connected to one of the gate electrode GE, the source region SCA, and the drain region DRA of the pixel transistor PTR through a hole (e.g., an opening) passing through the first semiconductor insulating layer SIL1 and the second semiconductor insulating layer SIL2. The contact terminal CTE may include at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd).

[0197] The third semiconductor insulating layer SIL3 may be disposed on a side surface of each of the plurality of contact terminals CTE. The upper surface of each of the plurality of contact terminals may be exposed without being covered by the third semiconductor insulating layer SIL3. The third semiconductor insulating layer SIL3 may include silicon oxide (SiO x ) inorganic film, but not limited to this.

[0198] The light emitting back panel EBP may include first to eighth metal layers MTL1 to MTL8 , first to eighth via holes VIA1 to VIA8 , and first to ninth interlayer insulating layers ILD1 to ILD9 .

[0199] The first metal layer MTL1 to the eighth metal layer MTL8 may be electrically connected to the contact terminal CTE exposed from the semiconductor backplane SBP to form a pixel circuit. For example, the semiconductor backplane SBP may include a plurality of pixel transistors PTR, and the light emitting backplane EBP may include a connection electrode for connecting the pixel transistors PTR and at least one capacitor connected to the pixel transistors PTR. The light emitting backplane EBP may electrically connect the pixel circuit to the first light emitting element ED1.

[0200] The first interlayer insulating layer ILD1 may be disposed on the semiconductor backplane SBP. The first via VIA1 may be connected to the contact terminal CTE exposed from the semiconductor backplane SBP by passing through the first interlayer insulating layer ILD1. The first metal layer MTL1 may be disposed on the first interlayer insulating layer ILD1 and thus connected to the first via VIA1.

[0201] The second interlayer insulating layer ILD2 may be disposed on the first interlayer insulating layer ILD1 and the first metal layer MTL1. The second via VIA2 may be connected to the first metal layer MTL1 through the second interlayer insulating layer ILD2. The second metal layer MTL2 may be disposed on the second interlayer insulating layer ILD2 and thus may be connected to the second via VIA2.

[0202] The third interlayer insulating layer ILD3 may be disposed on the second interlayer insulating layer ILD2 and the second metal layer MTL2. The third via VIA3 may be connected to the second metal layer MTL2 by passing through the third interlayer insulating layer ILD3. The third metal layer MTL3 may be disposed on the third interlayer insulating layer ILD3 and thus connected to the third via VIA3.

[0203] The fourth interlayer insulating layer ILD4 may be disposed on the third interlayer insulating layer ILD3 and the third metal layer MTL3. The fourth via VIA4 may be connected to the third metal layer MTL3 by passing through the fourth interlayer insulating layer ILD4. The fourth metal layer MTL4 may be disposed on the fourth interlayer insulating layer ILD4 and thus connected to the fourth via VIA4.

[0204] The fifth interlayer insulating layer ILD5 may be disposed on the fourth interlayer insulating layer ILD4 and the fourth metal layer MTL4. The fifth via VIA5 may be connected to the fourth metal layer MTL4 by passing through the fifth interlayer insulating layer ILD5. The fifth metal layer MTL5 may be disposed on the fifth interlayer insulating layer ILD5 and thus connected to the fifth via VIA5.

[0205] The sixth interlayer insulating layer ILD6 may be disposed on the fifth interlayer insulating layer ILD5 and the fifth metal layer MTL5. The sixth via VIA6 may be connected to the fifth metal layer MTL5 by passing through the sixth interlayer insulating layer ILD6. The sixth metal layer MTL6 may be disposed on the sixth interlayer insulating layer ILD6 and thus connected to the sixth via VIA6.

[0206] The seventh interlayer insulating layer ILD7 may be disposed on the sixth interlayer insulating layer ILD6 and the sixth metal layer MTL6. The seventh via VIA7 may be connected to the sixth metal layer MTL6 by passing through the seventh interlayer insulating layer ILD7. The seventh metal layer MTL7 may be disposed on the seventh interlayer insulating layer ILD7 and thus connected to the seventh via VIA7.

[0207] The eighth interlayer insulating layer ILD8 may be disposed on the seventh interlayer insulating layer ILD7 and the seventh metal layer MTL7. The eighth via VIA8 may be connected to the seventh metal layer MTL7 by passing through the eighth interlayer insulating layer ILD8. The eighth metal layer MTL8 may be disposed on the eighth interlayer insulating layer ILD8 and thus connected to the eighth via VIA8. The ninth interlayer insulating layer ILD9 may be disposed on the eighth interlayer insulating layer ILD8 and the eighth metal layer MTL8.

[0208] The first to eighth metal layers ML1 to ML8 and the first to eighth vias VIA1 to VIA8 may include substantially the same material. The first to eighth metal layers ML1 to ML8 and the first to eighth vias VIA1 to VIA8 may include at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). The first to ninth interlayer insulating layers ILD1 to ILD9 may include silicon oxide (SiO x ) inorganic film, but not limited to this.

[0209] The thickness of the first metal layer MTL1, the thickness of the second metal layer MTL2, the thickness of the third metal layer MTL3, the thickness of the fourth metal layer MTL4, the thickness of the fifth metal layer MTL5, and the thickness of the sixth metal layer MTL6 may be respectively greater than the thickness of the first via VIA1, the thickness of the second via VIA2, the thickness of the third via VIA3, the thickness of the fourth via VIA4, the thickness of the fifth via VIA5, and the thickness of the sixth via VIA6. Each of the thickness of the second metal layer MTL2, the thickness of the third metal layer MTL3, the thickness of the fourth metal layer MTL4, the thickness of the fifth metal layer MTL5, and the thickness of the sixth metal layer MTL6 may be greater than the thickness of the first metal layer MTL1. The thickness of the second metal layer MTL2, the thickness of the third metal layer MTL3, the thickness of the fourth metal layer MTL4, the thickness of the fifth metal layer MTL5, and the thickness of the sixth metal layer MTL6 may be substantially the same as each other. For example, the thickness of the first metal layer MTL1 may be about 1000 Å. Each of the thickness of the second metal layer MTL2, the thickness of the third metal layer MTL3, the thickness of the fourth metal layer MTL4, the thickness of the fifth metal layer MTL5, and the thickness of the sixth metal layer MTL6 may be approximately Each of the thickness of the first via hole VIA1, the thickness of the second via hole VIA2, the thickness of the third via hole VIA3, the thickness of the fourth via hole VIA4, the thickness of the fifth via hole VIA5, and the thickness of the sixth via hole VIA6 may be approximately

[0210] Each of the thickness of the seventh metal layer MTL7 and the thickness of the eighth metal layer MTL8 may be greater than each of the thickness of the first metal layer MTL1, the thickness of the second metal layer MTL2, the thickness of the third metal layer MTL3, the thickness of the fourth metal layer MTL4, the thickness of the fifth metal layer MTL5, and the thickness of the sixth metal layer MTL6. Each of the thickness of the seventh metal layer MTL7 and the thickness of the eighth metal layer MTL8 may be greater than each of the thickness of the seventh via VIA7 and the thickness of the eighth via VIA8. Each of the thickness of the seventh via VIA7 and the thickness of the eighth via VIA8 may be greater than each of the thickness of the first via VIA1, the thickness of the second via VIA2, the thickness of the third via VIA3, the thickness of the fourth via VIA4, the thickness of the fifth via VIA5, and the thickness of the sixth via VIA6. The thickness of the seventh metal layer MTL7 and the thickness of the eighth metal layer MTL8 may be substantially the same as each other. For example, each of the thickness of the seventh metal layer MTL7 and the thickness of the eighth metal layer MTL8 may be about 100 Å. Each of the thickness of the seventh via hole VIA7 and the thickness of the eighth via hole VIA8 may be approximately

[0211] As the resolution increases, the display device can include multiple pixels in a relatively small area. The light-emitting backplane EBP may include a first metal layer MTL1 to an eighth metal layer MTL8 to implement a connection electrode for connecting a pixel transistor PTR and at least one capacitor connected to the pixel transistor PTR, thereby implementing a pixel circuit in a relatively small area. Therefore, the light-emitting element layer EML can be formed on a silicon wafer including a semiconductor backplane SBP and a light-emitting backplane EBP, and the display device can implement an image with ultra-high resolution.

[0212] Above Figures 5 to 10 The light emitting element layer EML and thin film encapsulation layer TFEL shown in FIG can also be applied to Fig.14 The light emitting element layer EML and the thin film encapsulation layer TFEL shown in FIG.

[0213] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the described embodiments without departing substantially from the present disclosure. Therefore, the disclosed embodiments of the present disclosure are used in a generic and descriptive sense rather than for the purpose of limitation.

Claims

1. A display device, comprising: substrate; A first pixel electrode, on the substrate; a first light-emitting layer, on the first pixel electrode; a first common electrode, on the first light-emitting layer; a first bank on the substrate, and exposing the first common electrode through the first bank; as well as The second bank is on the first bank and has a side surface protruding beyond the side surface of the first bank, and the width of the lower surface of the first bank is smaller than the width of the upper surface of the first bank.

2. The display device according to claim 1, wherein: The first common electrode contacts the side surface of the first bank.

3. The display device according to claim 1, wherein: An angle between the lower surface of the first bank and the side surface of the first bank is greater than 90°.

4. The display device according to claim 1, wherein: The first bank includes at least one of polysilicon, amorphous carbon, graphite, and graphene.

5. The display device according to claim 1, wherein: The second bank includes SiO x 、SiN y 、SiO x N y and at least one of a metal.

6. The display device according to claim 1, further comprising: An auxiliary electrode is provided between the substrate and the first bank.

7. The display device according to claim 6, wherein: The auxiliary electrode contacts the first common electrode.

8. The display device according to claim 1, further comprising: a third bank, on the second bank; as well as The fourth bank is on the third bank and has a side surface protruding beyond the side surface of the third bank.

9. The display device according to claim 8, wherein: A width of a lower surface of the third bank is smaller than a width of an upper surface of the third bank and smaller than a width of the second bank.

10. The display device according to claim 1, further comprising: A first inorganic layer is on the second bank and the first common electrode.

11. The display device according to claim 10, further comprising: A first covering layer is between the first common electrode and the first inorganic layer.

12. The display device according to claim 10, further comprising: a second pixel electrode, on the substrate and spaced apart from the first pixel electrode; a second light emitting layer, on the second pixel electrode; a second common electrode, on the second light emitting layer and spaced apart from the first common electrode; as well as A second inorganic layer is on the second common electrode and the second bank and is spaced apart from the first inorganic layer.

13. The display device according to claim 10, further comprising: a first light emitting pattern between the second bank and the first inorganic layer and including the same material as that of the first light emitting layer; as well as The first electrode pattern is between the first light emitting pattern and the first inorganic layer and includes the same material as that of the first common electrode.

14. A display device, comprising: substrate; A first pixel electrode, on the substrate; a first light-emitting layer, on the first pixel electrode; a first common electrode, on the first light-emitting layer; a first bank on the substrate, and exposing the first common electrode through the first bank; as well as a second bank on the first bank and including a side surface protruding beyond a side surface of the first bank, wherein the first bank comprises at least one of polysilicon, amorphous carbon, graphite and graphene, and Wherein, the first common electrode contacts the side surface of the first bank.

15. The display device according to claim 14, wherein: The second bank includes SiO x 、SiN y 、SiO x N y and at least one of a metal.

16. The display device according to claim 14, further comprising: A first inorganic layer is on an upper surface of the first common electrode, the side surfaces of the first bank, and an upper surface and a lower surface of the second bank.

17. A display device, comprising: substrate; A first pixel electrode, on the substrate; a pixel defining layer on the substrate, through which the first pixel electrode is exposed; a first light-emitting layer, on the first pixel electrode; a first common electrode, on the first light-emitting layer; an auxiliary electrode, on the pixel defining layer and in contact with the first common electrode; a first bank on the auxiliary electrode; as well as The second bank is on the first bank and includes a side surface protruding beyond the side surface of the first bank, and a width of a lower surface of the first bank and a width of an upper surface of the first bank are different from each other.

18. The display device according to claim 17, wherein: The width of the lower surface of the first bank is smaller than the width of the upper surface of the first bank.

19. The display device according to claim 18, wherein: A cross-sectional width of the first bank decreases from the upper surface toward the lower surface.

20. The display device according to claim 17, wherein: The auxiliary electrode includes at least one of copper, aluminum and molybdenum.

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