Semiconductor device structure based on OLED display, forming method and display device

Abstract

The invention relates to a semiconductor device structure based on OLED display, a forming method and a display device.The semiconductor device structure comprises a substrate, the substrate comprises a first well region, a second well region, a first conduction structure located on the first well region and a second conduction structure located on the second well region, and the first conduction structure and the second conduction structure are connected; the first active region is located in the first well region and comprises a source electrode region and a drain electrode region, and the second active region is located in the second well region and forms a grid electrode. According to the embodiment of the invention, the second conduction structure and the conduction process of the second conduction structure are added through the device structure, so that a conductive channel between the source region and the drain region is more difficult to open, the sub-threshold swing is improved, the change range of the gate voltage is increased, the compensation space becomes larger, and the performance of the device is improved. Therefore, the purpose of improving the display effect of a final product is achieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device structure, a formation method and a display device based on OLED display. Background Art

[0002] Microdisplay technology is an important technology in the booming display field. It integrates all the pixel units and drive units required for a display screen into one chip, giving it the advantages of small area, high resolution and low power consumption.

[0003] Organic light-emitting diodes (OLEDs), which are light-emitting devices, are current-type organic light-emitting devices, and the brightness of their light is proportional to the current passing through them. In some common drive circuits, the current range required to control the light emission of OLEDs from the darkest to the brightest is 10pA (picoamperes)-10nA (nanoamperes). Since the current range required to control the light emission of OLEDs from the darkest to the brightest is small, it is difficult for general devices to meet such a small current requirement. The subthreshold current of metal-oxide-semiconductor field-effect transistors (MOSFETs), that is, MOS tubes, just meets the current range required for OLED light emission. Therefore, drive circuits usually use MOS tubes to control OLED light emission.

[0004] Figure 1 is a MOS tube transfer characteristic curve diagram provided by an embodiment of the present application, such as Figure 1 As shown in Figure 1, this curve represents the relationship between the control voltage and current of some MOS tubes. Figure 1 It can be seen that for some MOS tubes, when the current is in the range of 10pA-10nA, the control voltage is between 0.5-0.8V, that is, the control voltage varies in the range of about 0.3V, which indicates that the input voltage of the drive circuit needs to be controlled within 0.3V.

[0005] However, whether in the manufacturing process or the application process of MOS tubes, the threshold voltage drift of MOS tubes cannot be ignored. Therefore, in order to achieve the same luminous intensity of OLEDs in different pixels under the same input voltage, the adverse effects of threshold voltage drift on OLED luminescence should be alleviated as much as possible. Summary of the invention

[0006] In order to solve the above technical problems, the present application provides a semiconductor device structure, a formation method and a display device based on OLED display.

[0007] In a first aspect, the present application discloses a semiconductor device structure based on OLED display, including:

[0008] The substrate comprises a first well region and a second well region; the first well region is implanted with first doping ions, and the second well region is implanted with second doping ions; the first doping ions and the second doping ions have different conductivity types;

[0009] A first conductive structure located on the first well region and a second conductive structure located on the second well region; the first conductive structure and the second conductive structure are connected;

[0010] A first active region located in the first well region; the first active region includes a source region and a drain region; the source region and the drain region are implanted with third doping ions; the source region and the drain region are respectively located on two sides of the first conductive structure;

[0011] a second active region located in the second well region; the second active region comprises a first doped region, fourth doping ions are implanted into the first doped region, and the first doped region forms a gate;

[0012] The second doping ions, the third doping ions, and the fourth doping ions have the same conductivity type.

[0013] In some possible embodiments, the second active region further includes a second doping region; the second doping region is implanted with fourth doping ions;

[0014] The first doping region and the second doping region are respectively located at two sides of the second conductive structure; the first doping region and the second doping region form a gate.

[0015] In some possible embodiments, the first conductive structure and the second conductive structure have the same size in the first direction;

[0016] The first active region and the second active region have the same size in the second direction;

[0017] An area of ​​a first overlapping region corresponding to the first active region and the first conductive structure is equal to an area of ​​a second overlapping region corresponding to the second active region and the second conductive structure.

[0018] In some possible embodiments, a size of the first conductive structure in the first direction is larger than a size of the second conductive structure in the first direction;

[0019] The first active region and the second active region have the same size in the second direction;

[0020] An area of ​​a first overlapping region corresponding to the first active region and the first conductive structure is greater than an area of ​​a second overlapping region corresponding to the second active region and the second conductive structure.

[0021] In some possible embodiments, the first conductive structure and the second conductive structure have the same size in the first direction;

[0022] The size of the first active region in the second direction is smaller than the size of the second active region in the second direction;

[0023] An area of ​​a first overlapping region corresponding to the first active region and the first conductive structure is smaller than an area of ​​a second overlapping region corresponding to the second active region and the second conductive structure.

[0024] In some possible embodiments, the second active region further includes a second doping region; the second doping region is implanted with second doping ions; the first doping region and the second doping region are respectively located on both sides of the second conductive structure; the first doping region forms a gate;

[0025] The size of the first conductive structure in the first direction is greater than the size of the second conductive structure in the first direction;

[0026] The first active region and the second active region have the same size in the second direction;

[0027] An area of ​​a first overlapping region corresponding to the first active region and the first conductive structure is greater than an area of ​​a second overlapping region corresponding to the second active region and the second conductive structure.

[0028] In some possible embodiments,

[0029] The concentration of the first doping ions implanted into the first well region is a first concentration;

[0030] The concentration of the third doping ions implanted into the source region and the drain region is the second concentration;

[0031] The second concentration is greater than the first concentration;

[0032] The concentration of the second doping ions implanted into the second well region is a third concentration;

[0033] The concentration of the fourth doping ions implanted into the first doping region is a fourth concentration;

[0034] The fourth concentration is greater than the third concentration.

[0035] In some possible embodiments, the concentration of the second doping ions implanted into the second well region is a fifth concentration;

[0036] The fifth concentration is greater than the third concentration, and the fifth concentration is less than the fourth concentration.

[0037] In some possible embodiments, the first conductive structure and the second conductive structure are polysilicon.

[0038] In some possible embodiments, the first conductive structure and the second conductive structure are an integral structure.

[0039] In a second aspect, the present application discloses a method for forming a semiconductor device structure based on an OLED display, the method comprising:

[0040] providing a substrate;

[0041] A first well region and a second well region are formed in the substrate; the first well region is implanted with first doping ions, and the second well region is implanted with second doping ions; the first doping ions and the second doping ions have different conductivity types;

[0042] forming a first conductive structure and a second conductive structure on the first well region and the second well region; the first conductive structure and the second conductive structure are connected;

[0043] A first active region is formed in the first well region; the first active region includes a source region and a drain region; the source region and the drain region are implanted with third doping ions; the source region and the drain region are respectively located on two sides of the first conductive structure;

[0044] A second active region is formed in the second well region; the second active region includes a first doped region, fourth doped ions are implanted into the first doped region, and the first doped region forms a gate;

[0045] The second doping ions, the third doping ions, and the fourth doping ions have the same conductivity type.

[0046] In some possible embodiments, the second active region further includes a second doping region; the second doping region is implanted with fourth doping ions;

[0047] The first doping region and the second doping region are respectively located at two sides of the second conductive structure; the first doping region and the second doping region form a gate.

[0048] In a third aspect, an embodiment of the present application discloses a display device, which includes a semiconductor device structure based on OLED display as described above.

[0049] In a fourth aspect, an embodiment of the present application discloses an electronic device, which includes a semiconductor device structure based on OLED display as described above.

[0050] The technical solution provided by the embodiment of the present application has the following technical effects:

[0051] The semiconductor device structure of the embodiment of the present application includes a substrate, the substrate includes a first well region and a second well region, the first well region is injected with a first doping ion, the second well region is injected with a second doping ion, the first doping ion and the second doping ion have different conductivity types, a first conductive structure located on the first well region and a second conductive structure located on the second well region, the first conductive structure and the second conductive structure are connected, a first active region located in the first well region, the first active region includes a source region and a drain region, the source region and the drain region are injected with a third doping ion, the source region and the drain region are respectively located on both sides of the first conductive structure, a second active region located in the second well region, the second active region includes a first doping region, the first doping region is injected with a fourth doping ion, the first doping region forms a gate, and the second doping ion, the third doping ion and the fourth doping ion have the same conductivity type. In the embodiment of the present application, the gate voltage corresponding to the second conductive structure is controlled so that the second conductive structure can drive the first conductive structure to form an inversion layer, thereby making the source region and the drain region conductive, which is equivalent to adding the second conductive structure and the conduction process of the second conductive structure, making it more difficult to open the conductive channel between the source region and the drain region, thereby increasing the subthreshold swing, thereby increasing the variation range of the gate voltage, making the compensation space larger, thereby achieving the goal of improving the display effect of the final product. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions and advantages in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 is a MOS tube transfer characteristic curve diagram provided in an embodiment of the present application;

[0054] Figure 2 is a schematic diagram of an OLED driving circuit provided in an embodiment of the present application;

[0055] Figure 3 It is a schematic diagram of a channel conduction structure of a MOS tube provided in an embodiment of the present application;

[0056] Figure 4 A three-dimensional schematic diagram of a semiconductor device structure provided in an embodiment of the present application Figure 1 ;

[0057] Figure 5 This is an application diagram of a semiconductor device structure provided in an embodiment of the present application. Figure 1 ;

[0058] Figure 6A schematic top view of a semiconductor device structure provided in an embodiment of the present application Figure 1 ;

[0059] Figure 7 A schematic top view of a semiconductor device structure provided in an embodiment of the present application Figure 2 ;

[0060] Figure 8 A three-dimensional schematic diagram of a semiconductor device structure provided in an embodiment of the present application Figure 2 ;

[0061] Fig. 9 This is an application diagram of a semiconductor device structure provided in an embodiment of the present application. Figure 2 ;

[0062] Fig.10 A schematic top view of a semiconductor device structure provided in an embodiment of the present application Figure 3 ;

[0063] Fig.11 A schematic top view of a semiconductor device structure provided in an embodiment of the present application Figure 4 ;

[0064] Fig.12 A schematic top view of a semiconductor device structure provided in an embodiment of the present application Figure 5 ;

[0065] Fig.13 A schematic top view of a semiconductor device structure provided in an embodiment of the present application Figure 6 ;

[0066] Fig.14 It is a schematic diagram of a method for forming a semiconductor device structure based on OLED display provided in an embodiment of the present application. DETAILED DESCRIPTION

[0067] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0068] It should be noted that the "one embodiment" or "embodiment" referred to in the specification of the embodiment of the present application refers to a specific feature, structure or characteristic that can be included in at least one implementation of the present application. It should be understood that in the specification and claims of the embodiment of the present application and the above-mentioned drawings, the orientation or position relationship indicated by the terms "upper", "lower", "top", "bottom", etc. is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" can explicitly or implicitly include one or more of the features. Moreover, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. In addition, in the description of the present embodiment, unless otherwise specified, "plurality" means two or more. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system or product including a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0069] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0070] In order to make the purpose, technical solution and advantages disclosed in the embodiments of the present application more clear, the embodiments of the present application are further described in detail in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the embodiments of the present application and are not used to limit the embodiments of the present application.

[0071] In the embodiment of the present application, the threshold voltage V t It refers to the gate voltage when a conductive channel is formed between the source and drain of the MOS tube. The subthreshold current refers to the gate voltage V G Below the threshold voltage V t , that is, a tiny leakage current between the source and the drain when in the subthreshold state.

[0072] In the embodiment of the present application, in the ideal current-voltage characteristic of the MOS tube, when the gate voltage V G Less than the threshold voltage V t , the drain current is 0. However, in actual situations, when the gate voltage V G Less than the threshold voltage V t When it is greater than 0, the MOS tube is in a weak inversion state on the surface (different from the strong inversion state when it is turned on). This area is called the subthreshold region. When the MOS tube works in the subthreshold region, although there are carriers in the conductive channel, the concentration is low, so the leakage current is very small at this time, but it is actually not 0. This leakage current is called the subthreshold current.

[0073] Figure 2 is a schematic diagram of an OLED driving circuit provided in an embodiment of the present application, such as Figure 2 As shown, the driving circuit on the left is a simplified schematic diagram. In actual application, the driving circuit can be a 2T1C circuit, a 6T1C circuit, etc.

[0074] Optionally, one end of the light-emitting OLED is grounded, and the other end is connected to the source end of the MOS tube, and the drain end of the MOS tube is connected to the power supply. The different brightness of the light-emitting OLED is achieved by controlling the gate voltage V of the MOS tube. G That is, the control voltage in FIG. 2 generates different leakage currents. Optionally, the leakage current ranges from 10pA to 10nA.

[0075] Figure 3 is a schematic diagram of a channel conduction structure of a MOS tube provided in an embodiment of the present application, such as Figure 3 As shown, it includes the source and drain non-conducting stage above the arrow corresponding to the NMOS tube and the source and drain conducting stage below the arrow. The NMOS tube includes a P-type substrate 301, an oxide layer 302, polysilicon 303, a source region 304 and a drain region 305.

[0076] like Figure 3As shown, the NMOS tube uses a P-type semiconductor as a substrate. On a low-doped P-type substrate 301, two high-doped N-type semiconductors, namely the source region 304 and the drain region 305, are made through a diffusion process, and the wiring is led out as the source and the drain respectively. An oxide layer 302 is added on the P-type substrate, and the pins are led out through polysilicon 303 to form a gate. Among them, the P-type semiconductor can provide a large number of holes, and the N-type semiconductor can provide a large number of electrons.

[0077] Optionally, there are two back-to-back PN junctions between the source region 304 and the drain region 305. When the gate voltage is 0, there is always one PN junction in a reverse biased state, and there is no conductive channel between the source region 304 and the drain region 305. At this time, even if a voltage is applied to the drain, there is no leakage current.

[0078] When the gate voltage is greater than the threshold voltage, such as Figure 3 As shown, a conductive channel 306 is formed between the source region 304 and the drain region 305. Because the conductive channel is an N-type conductive channel, which is opposite to the conductivity type of the P-type substrate 301, it is called an inversion layer. Similarly, the channel conduction structure of the PMOS tube can be obtained.

[0079] In some optional embodiments, the driving circuit usually uses a MOS tube (NMOS tube or PMOS tube) to control the OLED to emit light. However, because the threshold voltage drift of the MOS tube will have an adverse effect on achieving the goal of achieving the same luminous intensity of OLEDs in different pixels under the same input voltage, in some optional implementations, some additional circuits can be added to the original MOS tube to compensate for the impact of the threshold voltage drift and improve the display effect of the final product.

[0080] In some possible embodiments, the compensation effect of the threshold voltage drift is related to the variation range of the gate voltage (corresponding to the current 10pA-10nA in this application). The larger the variation range of the gate voltage, the larger the compensation space, and the better the display effect of the final product.

[0081] In some possible embodiments, the variation range of the gate voltage may be expanded by increasing the subthreshold swing (STS) of the device.

[0082] Figure 4 A three-dimensional schematic diagram of a semiconductor device structure provided in an embodiment of the present application Figure 1 ,like Figure 4 As shown, the semiconductor device structure includes:

[0083] Substrate ( Figure 4The substrate includes a first well region 401 and a second well region 402, wherein the first well region 401 is implanted with first doping ions and the second well region 402 is implanted with second doping ions, wherein the first doping ions and the second doping ions have different conductivity types.

[0084] A first conductive structure 403 located on the first well region 401 and a second conductive structure 404 located on the second well region 402, wherein the first conductive structure 403 and the second conductive structure 404 are connected. In an optional embodiment, the first conductive structure 403 and the second conductive structure 404 can be two parts (such as Figure 4 ), but the two parts are connected together by contact. In another optional embodiment, the first conductive structure 403 and the second conductive structure 404 can be an integral structure.

[0085] The first active region 405 is located in the first well region 401, and the first active region 405 includes a source region 4051 and a drain region 4052. The source region 4051 and the drain region 4052 are both implanted with third doping ions, and the source region 4051 and the drain region 4052 are respectively located on both sides of the first conductive structure. Optionally, the source region 4051 can form a source, and the drain region 4052 can form a drain.

[0086] The second active region 406 is located in the second well region 402, and the second active region 406 includes a first doping region, the first doping region is implanted with fourth doping ions, and the first doping region forms a gate, wherein the second doping ions, the third doping ions and the fourth doping ions have the same conductivity type.

[0087] Optionally, that the second active region includes the first doped region may be embodied as the second active region being the first doped region.

[0088] Optionally, the first conductive structure and the second conductive structure are metal or polysilicon. When the first conductive structure and the second conductive structure are an integral structure, the first conductive structure and the second conductive structure can be a whole metal structure or a whole polysilicon structure.

[0089] As described above, the embodiment of the present application adds some additional circuits based on the original MOS tube to compensate for the impact of threshold voltage drift and improve the display effect of the final product. Figure 4 The semiconductor device structure shown can be viewed as two parts, the left part (including the first well region 401, the first active region 405 located in the first well region 401, and the first conductive structure 403 located on the first well region 401) can be viewed as an NMOS transistor or a PMOS transistor. The semiconductor device structure is introduced below based on whether the left part is an NMOS transistor or a PMOS transistor.

[0090] In an optional embodiment, Figure 4 The left part of is an NMOS transistor, which includes a first well region 401 on the substrate, and a first active region 405 in the first well region 401, the first active region 405 including a source region 4051 and a drain region 4052, and a first conductive structure 403 located on the first well region 401. The first doping ions injected into the first well region 401 are P-type impurities, and the third doping ions injected into the source region 4051 and the drain region 4052 are N-type impurities, wherein the concentration of the first doping ions injected into the first well region 401 is a first concentration, and the concentration of the third doping ions injected into the source region 4051 and the drain region 4052 is a second concentration, and the second concentration is higher than the first concentration.

[0091] Optional, such as Figure 4 As shown, there may be an oxide layer between the first well region 401 and the first conductive structure 403 .

[0092] Figure 4 The right part of includes a second well region 402 on the substrate, a second active region 406 on the second well region 402, and a second conductive structure 404 located on the second well region 402. The first conductive structure 403 and the second conductive structure 404 may be connected by contact.

[0093] Optionally, the second doping ions injected into the second well region 402 are N-type impurities, and the fourth doping ions injected into the first doping region included in the second active region 406 are N-type impurities, wherein the concentration of the second doping ions injected into the second well region 402 is the third concentration, and the concentration of the fourth doping ions injected into the first doping region is the fourth concentration, and the fourth concentration is higher than the third concentration.

[0094] Optionally, the concentration of the first doping ions injected into the first well region 401 and the concentration of the second doping ions injected into the second well region 402 may be the same or different, that is, the first concentration may be equal to the third concentration or may not be equal to the third concentration.

[0095] Optionally, the concentration of the fourth doping ions injected into the first doping region and the concentration of the third doping ions injected into the source region 4051 and the drain region 4052 may be the same or different, that is, the second concentration may be equal to the fourth concentration or may not be equal to the fourth concentration.

[0096] Optionally, the concentrations of the second doping ions and the fourth doping ions may also be the same.

[0097] Optionally, the third doping ion and the fourth doping ion may be the same doping ion (with the same concentration, dosage or element). The third doping ion and the fourth doping ion may also be doping ions with the same conductivity type but different concentrations, dosages or elements.

[0098] Optional, such as Figure 4 As shown, there may be an oxide layer between the second well region 402 and the second conductive structure 404 .

[0099] In an optional embodiment, Figure 4 The left part of is a PMOS transistor, which includes a first well region 401 on the substrate, and a first active region 405 in the first well region 401, the first active region 405 including a source region 4051 and a drain region 4052, and a first conductive structure 403 located on the first well region 401. The first doping ions injected into the first well region 401 are N-type impurities, and the third doping ions injected into the source region 4051 and the drain region 4052 are P-type impurities, wherein the concentration of the first doping ions injected into the first well region 401 is a first concentration, and the concentration of the third doping ions injected into the source region 4051 and the drain region 4052 is a second concentration, and the second concentration is higher than the first concentration.

[0100] Optional, such as Figure 4 As shown, there may be an oxide layer between the first well region 401 and the first conductive structure 403 .

[0101] Figure 4 The right part of the substrate includes a second well region 402 on the substrate, a second active region 406 in the second well region 402, and a second conductive structure 404 located on the second well 402. The first conductive structure 403 and the second conductive structure 404 may be connected by contact.

[0102] Optionally, the second doping ions injected into the second well region 402 are P-type impurities, and the fourth doping ions injected into the first doping region included in the second active region 406 are P-type impurities, wherein the concentration of the second doping ions injected into the second well region 402 is the third concentration, and the concentration of the fourth doping ions injected into the first doping region is the fourth concentration, and the fourth concentration is higher than the third concentration.

[0103] Optionally, the concentration of the first doping ions injected into the first well region 401 and the concentration of the second doping ions injected into the second well region 402 may be the same or different, that is, the first concentration may be equal to the third concentration or may not be equal to the third concentration.

[0104] Optionally, the concentration of the fourth doping ions injected into the first doping region and the concentration of the third doping ions injected into the source region 4051 and the drain region 4052 may be the same or different, that is, the second concentration may be equal to the fourth concentration or may not be equal to the fourth concentration.

[0105] Optionally, the third doping ion and the fourth doping ion may be the same doping ion (with the same concentration, dosage or element). The third doping ion and the fourth doping ion may also be doping ions with the same conductivity type but different concentrations, dosages or elements.

[0106] Optional, such as Figure 4 As shown, there may be an oxide layer between the second well region 402 and the second conductive structure 404 .

[0107] Since the structures of the NMOS tube and the PMOS tube, as well as the expanded semiconductor device structures and circuit principles, are corresponding, the embodiments in this article will be described using the semiconductor device structure corresponding to the NMOS as an example, and the semiconductor device structure corresponding to the PMOS can be inferred by reference to this, and will not be repeated in the full article.

[0108] Figure 5 This is an application diagram of a semiconductor device structure provided in an embodiment of the present application. Figure 1 ,correspond Figure 4 The semiconductor device structure shown. Figure 5 It includes the source-drain non-conduction stage above the arrow and the source-drain conduction stage below the arrow. Among them, the left figure in the source-drain non-conduction stage and the source-drain conduction stage reflects Figure 4 The cross-sectional view on the left shows the source-drain non-conducting stage and the source-drain conducting stage. Figure 4 Cross-section of the right part.

[0109] In the embodiment of the present application, the first doped region of the second active region 406 forms a gate, the fourth doped ions injected into the first doped region and the second doped ions injected into the second well region 402 are N-type impurities, and there will be a large number of electrons, and the first doped ions injected into the first well region 401 are P-type impurities, and there are a large number of holes.

[0110] When the gate voltage is 0, the second well region 402 does not change. When the gate voltage is greater than 0, since the fourth doping ions injected into the first doping region and the second doping ions injected into the second well region 402 are N-type impurities, a large number of electrons will gather in the area of ​​the second well region 402 close to the oxide layer, so that a large number of holes will gather on the side of the second conductive structure 404 (such as polysilicon) close to the oxide layer. Since the first conductive structure 403 and the second conductive structure 404 are in contact and connected or are a whole, a large number of holes will also gather on the side of the first conductive structure 403 close to the oxide layer. At this time, the large number of holes gathered on the side of the first conductive structure 403 close to the oxide layer repel the holes in the first well region 401 close to the oxide layer, attract electrons, form a conductive channel, and turn on the source and drain. When the drain is connected to a voltage source, a subthreshold leakage current will be generated, thereby lighting up the OLED through the source.

[0111] Figure 3 The semiconductor structure shown directly controls the gate voltage, and forms a conductive channel between the source region and the drain region through the inversion of polysilicon, thereby conducting the source and drain. Figure 5 The semiconductor device structure shown in FIG. 1 needs to control the gate voltage of the right part first, so that the polysilicon corresponding to the right part forms an inversion and conducts to the polysilicon corresponding to the left part, thereby forming a conductive channel between the source region 4051 and the drain region 4052. Figure 3 In the semiconductor structure shown (ordinary MOS tube), the formation of the conductive channel is more difficult, that is, it is more difficult to open the conductive channel, so its subthreshold swing is increased, thereby increasing the variation range of the gate voltage, making the compensation space larger, thereby achieving the goal of improving the display effect of the final product.

[0112] Figure 6 A schematic top view of a semiconductor device structure provided in an embodiment of the present application Figure 1 , Figure 6 for Figure 4 A top view of Figure 4 The substrate is not shown in the figure, and the first doped region of the second active region 406 forms a gate (CT in the figure). CT in this article is a schematic conductor connection electrode.

[0113] In an optional embodiment, if Figure 6 As shown, the first conductive structure 403 and the second conductive structure 404 have the same size in the first direction. Specifically, when the first conductive structure 403 and the second conductive structure 404 are an integral structure, the top view of the integral structure can be as follows: Fig.10 A rectangle is shown.

[0114] In the embodiment of the present application, the first active region 405 includes not only the source region 4051 and the drain region 4052, but also includes a region covered by the first conductive structure and ultimately used to form a conductive channel. The second active region includes not only the first doped region, but also includes a region covered by the second conductive structure.

[0115] Optionally, the first active region 405 and the second active region 406 have the same size in the second direction, that is, the first active region 405 and the second active region 406 have the same span in the second direction.

[0116] Thus, the area of ​​the first overlapping region corresponding to the first active region 405 and the first conductive structure 403 is finally reduced to Figure 6 The dotted circle on the left side of the figure shows an area of ​​the second overlapping region (indicated by the dashed circle on the left side of the figure) and the second active region 406 and the second conductive structure 404 corresponding to the second overlapping region ( Figure 6 The dotted circle on the right side of the figure indicates that the two active regions are equal, that is, the two active regions overlap with the polysilicon above, and the two overlapping areas are equal.

[0117] Figure 7 A schematic top view of a semiconductor device structure provided in an embodiment of the present application Figure 2 , Figure 7 For Figure 6 A top view of a slightly modified semiconductor device structure is shown, including Figure 4 The substrate is not shown.

[0118] In an optional embodiment, if Figure 7 As shown, the size of the first conductive structure 403 on the first well region 401 in the first direction is greater than the size of the second conductive structure 404 on the second well region 402 in the first direction.

[0119] In the embodiment of the present application, the first active region 405 includes not only the source region 4051 and the drain region 4052, but also includes a region covered by the first conductive structure and ultimately used to form a conductive channel. The second active region includes not only the first doped region, but also includes a region covered by the second conductive structure.

[0120] Optionally, the first active region 405 and the second active region 406 have the same size in the second direction, but different sizes in the first direction. For example, the size of the first active region 405 in the first direction is larger than the size of the second active region 406 in the first direction.

[0121] Thus, the area of ​​the first overlapping region corresponding to the first active region 405 and the first conductive structure 403 is finally reduced to Figure 7 The dotted circle on the left side of the figure is larger than the area of ​​the second overlapping region corresponding to the second active region 406 and the second conductive structure 404 ( Figure 7That is, the two active regions overlap with the polysilicon thereon, and of the two overlapping areas obtained, a first overlapping area corresponding to the first overlapping region is larger than a second overlapping area corresponding to the second overlapping region.

[0122] From the above Figure 6-7 The relationship between the two overlapping areas can be summarized in the two figures as follows: Figure 6 In the example, the area of ​​the first overlapping region is equal to the area of ​​the second overlapping region. Figure 7 In the embodiment, the area of ​​the first overlapping region is greater than the area of ​​the second overlapping region.

[0123] Combined with the above analysis, the semiconductor device structure in the embodiment of the present application is relatively Figure 3 In the semiconductor structure (ordinary MOS tube) shown, the formation of the conductive channel is more difficult, that is, it is more difficult to open the conductive channel. The voltage applied to the gate corresponding to the second active region will cause the polysilicon on the second overlapping area to form an inversion layer. The smaller the area of ​​the second overlapping area, the weaker the ability to conduct to the first overlapping area, so it is more difficult to open the conductive channel, that is, the subthreshold swing is increased more.

[0124] Therefore, the larger the ratio of the first overlapping area to the second overlapping area, the more difficult it is to open the conductive channel, that is, the more the subthreshold swing of the semiconductor device is increased. In this way, when the ratio of the first overlapping area to the second overlapping area is determined, the size of the first conductive structure 403 and the second conductive structure 404 in the first direction or the second direction can be flexibly adjusted, and the size of the first active area 405 and the second active area 406 in the first direction and the second direction can also be flexibly adjusted. Furthermore, in some possible embodiments that meet the conditions, the use of polysilicon materials can be saved, or the area of ​​the first active area and the second active area can be controlled and materials can be saved, so that the semiconductor device structure can be miniaturized, the area of ​​the driving tube can be saved, and the area of ​​the pixel area can be reduced, and the resolution of the final product can be improved.

[0125] Figure 8 A three-dimensional schematic diagram of a semiconductor device structure provided in an embodiment of the present application Figure 2 ,like Figure 8 As shown, the semiconductor device structure includes:

[0126] Substrate ( Figure 8 The substrate includes a first well region 401 and a second well region 402, wherein the first well region 401 is implanted with first doping ions and the second well region 402 is implanted with second doping ions, wherein the first doping ions and the second doping ions have different conductivity types.

[0127] A first conductive structure 403 located on the first well region 401 and a second conductive structure 404 located on the second well region 402, wherein the first conductive structure 403 and the second conductive structure 404 are connected by contact. In an optional embodiment, the first conductive structure 403 and the second conductive structure 404 can be two parts (such as Figure 4 In another optional embodiment, the first conductive structure 403 and the second conductive structure 404 can be as shown. Figure 8 As shown, it is an integral structure.

[0128] The first active region 405 is located in the first well region 401, and the first active region 405 includes a source region 4051 and a drain region 4052. The source region 4051 and the drain region 4052 are both implanted with third doping ions, and the source region 4051 and the drain region 4052 are respectively located on both sides of the first conductive structure. Optionally, the source region 4051 can form a source, and the drain region 4052 can form a drain.

[0129] The second active region 406 is located in the second well region 402, and the second active region 406 includes a first doping region 4061 and a second doping region 4062, and the first doping region 4061 and the second doping region 4062 are respectively located on both sides of the second conductive structure. In addition, the first doping region 4061 and the second doping region 4062 are both implanted with fourth doping ions, and the first doping region 4061 and the second doping region 4062 form a gate. The second doping ions, the third doping ions, and the fourth doping ions have the same conductivity type.

[0130] Optionally, the first conductive structure and the second conductive structure are metal or polysilicon. When the first conductive structure and the second conductive structure are an integral structure, the first conductive structure and the second conductive structure can be a whole metal structure or a whole polysilicon structure.

[0131] In an alternative embodiment, when Figure 8 The left part of is an NMOS transistor, which includes a first well region 401 on the substrate, and a first active region 405 in the first well region 401, the first active region 405 including a source region 4051 and a drain region 4052, and a first conductive structure 403 located on the first well region 401. The first doping ions injected into the first well region 401 are P-type impurities, and the third doping ions injected into the source region 4051 and the drain region 4052 are N-type impurities, wherein the concentration of the first doping ions injected into the first well region 401 is a first concentration, and the concentration of the third doping ions injected into the source region 4051 and the drain region 4052 is a second concentration, and the second concentration is higher than the first concentration.

[0132] Figure 4The right part of the substrate includes a second well region 402 on the substrate, a second active region 406 in the second well region 402, and a second conductive structure 404 located on the second well 402. The second active region 406 includes a first doped region 4061 and a second doped region 4062. The first conductive structure 403 and the second conductive structure 404 are an integral structure.

[0133] Optionally, the second doping ions injected into the second well region 402 are N-type impurities, and the fourth doping ions injected into the first doping region 4061 and the second doping region 4062 included in the second active region 406 are N-type impurities, wherein the third concentration of the second doping ions injected into the second well region 402 and the concentration of the fourth doping ions injected into the first doping region 4061 and the second doping region 4062 are fourth concentrations, and the fourth concentration is higher than the third concentration.

[0134] Optionally, the concentration of the first doping ions injected into the first well region 401 and the concentration of the second doping ions injected into the second well region 402 may be the same or different, that is, the first concentration may be equal to the third concentration or may not be equal to the third concentration.

[0135] Optionally, the concentration of the fourth doping ions injected into the first doping region 4061 and the second doping region 4062 and the concentration of the third doping ions injected into the source region 4051 and the drain region 4052 may be the same or different, that is, the second concentration may be equal to the fourth concentration or may not be equal to the fourth concentration.

[0136] Optionally, the concentrations of the second doping ions and the fourth doping ions may also be the same.

[0137] Optionally, the third doping ion and the fourth doping ion may be the same doping ion (with the same concentration, dosage or element). The third doping ion and the fourth doping ion may also be doping ions with the same conductivity type but different concentrations, dosages or elements.

[0138] Optional, such as Figure 8 As shown, there may be an oxide layer beneath the entire conductive structure (including the first conductive structure 403 and the second conductive structure 404 ).

[0139] Fig. 9 This is an application diagram of a semiconductor device structure provided in an embodiment of the present application. Figure 2 ,correspond Figure 8 The semiconductor device structure shown. Fig. 9 It includes the source-drain non-conduction stage above the arrow and the source-drain conduction stage below the arrow. Among them, the left figure in the source-drain non-conduction stage and the source-drain conduction stage reflects Figure 8The cross-sectional view on the left shows the source-drain non-conducting stage and the source-drain conducting stage. Figure 8 Cross-section of the right part.

[0140] In the embodiment of the present application, the first doping region 4061 and the second doping region 4062 form a gate, the fourth doping ions injected into the first doping region 4061 and the second doping region 4062, and the second doping ions injected into the second well region 402 are N-type impurities, and there will be a large number of electrons, and the first doping ions injected into the first well region 401 are P-type impurities, and there will be a large number of holes.

[0141] When the gate voltage is 0, the second well region 402 does not change. When the gate voltage is greater than 0, a large number of electrons will gather in the area of ​​the second well region 402 close to the oxide layer, so that a large number of holes will gather on the side of the second conductive structure 404 (such as polysilicon) close to the oxide layer. Since the first conductive structure 403 and the second conductive structure 404 are in contact and connected or are a whole, a large number of holes will also gather on the side of the first conductive structure 403 close to the oxide layer. At this time, the large number of holes gathered on the side of the first conductive structure 403 close to the oxide layer repel the holes in the first well region 401 close to the oxide layer, attract electrons, form a conductive channel, and conduct the source and drain. When the drain is connected to a voltage source, a subthreshold leakage current will be generated, thereby lighting up the OLED through the source.

[0142] Figure 3 The semiconductor structure shown directly controls the gate voltage, and forms a conductive channel between the source region and the drain region through the inversion of polysilicon, thereby conducting the source and drain. Fig. 9 The semiconductor device structure shown in FIG. 1 needs to first control the gate voltage of the right part so that the polysilicon corresponding to the right part forms an inversion and is transmitted to the polysilicon corresponding to the left part, thereby forming a conductive channel between the source region 4051 and the drain region 4052. Figure 3 In the semiconductor structure shown (ordinary MOS tube), the formation of the conductive channel is more difficult, that is, it is more difficult to open the conductive channel, so its subthreshold swing is increased, thereby increasing the variation range of the gate voltage, making the compensation space larger, thereby achieving the goal of improving the display effect of the final product.

[0143] Fig.10 A schematic top view of a semiconductor device structure provided in an embodiment of the present application Figure 3 , Fig.10 for Figure 8 A top view of Figure 8 The first doping region 4061 and the second doping region 4062 (two CTs in the figure) of the second active region 406 are connected to the gate.

[0144] In an optional embodiment, if Fig.10 As shown, the first conductive structure 403 and the second conductive structure 404 have the same size in the first direction. Specifically, when the first conductive structure 403 and the second conductive structure 404 are an integral structure, the top view of the integral structure can be as follows: Fig.10 A rectangle is shown.

[0145] In the embodiment of the present application, the first active region 405 includes not only the source region 4051 and the drain region 4052, but also includes a region covered by the first conductive structure and ultimately used to form a conductive channel. The second active region includes not only the first doped region 4061 and the second doped region 4062, but also includes a region covered by the second conductive structure.

[0146] Optionally, the first active region 405 and the second active region 406 have the same size in the second direction, that is, the first active region 405 and the second active region 406 may be regions of the same size, or the first active region 405 and the second active region 406 have the same span in the second direction.

[0147] Thus, the area of ​​the first overlapping region corresponding to the first active region 405 and the first conductive structure 403 is finally reduced to Fig.10 The dotted circle on the left side of the figure shows an area of ​​the second overlapping region (indicated by the dashed circle on the left side of the figure) and the second active region 406 and the second conductive structure 404 corresponding to the second overlapping region ( Fig.10 The dotted circle on the right side of the figure indicates that the two active regions are equal, that is, the two active regions overlap with the polysilicon above, and the two overlapping areas are equal.

[0148] Fig.11 A schematic top view of a semiconductor device structure provided in an embodiment of the present application Figure 4 , Fig.11 For Fig.10 A top view of a slightly modified semiconductor device structure is shown, including Figure 8 The substrate is not shown.

[0149] In an optional embodiment, if Fig.11 As shown, the size of the first conductive structure 403 on the first well region 401 in the first direction is greater than the size of the second conductive structure 404 on the second well region 402 in the first direction.

[0150] In the embodiment of the present application, the first active region 405 includes not only the source region 4051 and the drain region 4052, but also includes a region covered by the first conductive structure and ultimately used to form a conductive channel. The second active region includes not only the first doped region 4061 and the second doped region 4062, but also includes a region covered by the second conductive structure.

[0151] Optionally, the first active region 405 and the second active region 406 have the same size in the second direction, that is, the first active region 405 and the second active region 406 may be regions of the same size, or the first active region 405 and the second active region 406 have the same span in the second direction.

[0152] Alternatively, the first active region 405 and the second active region 406 have the same size in the second direction, but different sizes in the first direction. For example, the size of the first active region 405 in the first direction is larger than the size of the second active region 406 in the first direction.

[0153] Thus, the area of ​​the first overlapping region corresponding to the first active region 405 and the first conductive structure 403 is finally reduced to Fig.11 The dotted circle on the left side of the figure is larger than the area of ​​the second overlapping region corresponding to the second active region 406 and the second conductive structure 404 ( Fig.11 That is, the two active regions overlap with the polysilicon thereon, and of the two overlapping areas obtained, a first overlapping area corresponding to the first overlapping area is larger than a second overlapping area corresponding to the second overlapping area.

[0154] Fig.12 A schematic top view of a semiconductor device structure provided in an embodiment of the present application Figure 5 , Fig.12 For Fig.10 A top view of a slightly modified semiconductor device structure is shown, including Figure 8 The substrate is not shown.

[0155] In an optional embodiment, if Fig.12 As shown, the first conductive structure 403 and the second conductive structure 404 have the same size in the first direction. Specifically, when the first conductive structure 403 and the second conductive structure 404 are an integral structure, the top view of the integral structure can be as follows: Fig.10 A rectangle is shown.

[0156] In the embodiment of the present application, the first active region 405 includes not only the source region 4051 and the drain region 4052, but also includes a region covered by the first conductive structure and ultimately used to form a conductive channel. The second active region includes not only the first doped region 4061 and the second doped region 4062, but also includes a region covered by the second conductive structure.

[0157] Optionally, a size of the first active region 405 in the second direction is smaller than a size of the second active region 406 in the second direction, that is, a span of the first active region 405 is smaller than a span of the second active region 406 .

[0158] Thus, the area of ​​the first overlapping region corresponding to the first active region 405 and the first conductive structure 403 is finally reduced to Fig.12 The dotted circle on the left side of the figure is smaller than the area of ​​the second overlapping region corresponding to the second active region 406 and the second conductive structure 404 ( Fig.12 That is, the two active regions overlap with the polysilicon thereon, and of the two overlapping areas obtained, a first overlapping area corresponding to the first overlapping region is smaller than a second overlapping area corresponding to the second overlapping region.

[0159] From the above Figure 10-12 The relationship between the two overlapping areas can be summarized in the three figures as follows: Fig.10 , the area of ​​the first overlapping region is equal to the area of ​​the second overlapping region; Fig.11 , the area of ​​the first overlapping region is greater than the area of ​​the second overlapping region; Fig.12 In the embodiment, the area of ​​the first overlapping region is smaller than the area of ​​the second overlapping region.

[0160] Combined with the above analysis, the semiconductor device structure in the embodiment of the present application is relatively Figure 3 In the semiconductor structure (ordinary MOS tube) shown, the formation of the conductive channel is more difficult, that is, it is more difficult to open the conductive channel. The voltage applied to the gate corresponding to the second active area will cause the polysilicon on the second overlapping area to form an inversion layer. The smaller the area of ​​the second overlapping area, the weaker the ability to conduct to the first overlapping area, and the larger the area of ​​the second overlapping area, the stronger the ability to conduct to the first overlapping area. It is more difficult to conduct from a small overlapping area to a large heavy area, so it is more difficult to open the conductive channel, that is, the subthreshold swing is increased more. However, it is less difficult to conduct from a large overlapping area to a small heavy area, so it is easier to open the conductive channel, and the subthreshold swing is increased less.

[0161] Therefore, the larger the ratio of the first overlapping area to the second overlapping area, the more difficult it is to open the conductive channel, that is, the more the subthreshold swing of the semiconductor device is improved. In this way, when the ratio of the first overlapping area to the second overlapping area is determined, the size of the first conductive structure 403 and the second conductive structure 404 in the first direction or the second direction can be flexibly adjusted, and the size of the first active area 405 and the second active area 406 in the first direction and the second direction can also be flexibly adjusted. Furthermore, in some possible embodiments that meet the conditions, polysilicon materials can be saved, or the areas of the first active area and the second active area can be controlled and materials can be saved, so that the semiconductor device structure can be miniaturized.

[0162] In the embodiment of the present application, Figure 4 The semiconductor device structure shown and Figure 8An important difference in the semiconductor device structure shown is that Figure 4 In the embodiment, the first doped region of the second active region 406 forms a gate, and in Figure 8 In the embodiment, the first doping region 4061 and the second doping region 4062 form a gate. However, since the fourth doping ions injected into the second active region 406 and the second doping ions injected into the second well region 402 are examples of the same conductivity type (N-type impurities), the realization of the function is not delayed. However, compared with forming a gate by the first doping region of the second active region 406, when the first doping region 4061 and the second doping region 4062 form a gate, the electrons gathered in the region of the second well region 402 close to the oxide layer will be more uniform, so that a large number of holes gathered on one side of the second conductive structure 404 (such as polysilicon) close to the oxide layer are also distributed more uniformly. On the other hand, forming a gate by the first doping region of the second active region 406 will save more materials than forming a gate by the first doping region 4061 and the second doping region 4062.

[0163] Fig.13 A schematic top view of a semiconductor device structure provided in an embodiment of the present application Figure 6 , Fig.13 For Fig.10 A top view of a slightly modified semiconductor device structure is shown, including Figure 8 The substrate includes a first well region 401 and a second well region 402, wherein the first well region 401 is implanted with first doping ions, and the second well region 402 is implanted with second doping ions, wherein the first doping ions and the second doping ions have different conductivity types.

[0164] A first conductive structure 403 located on the first well region 401 and a second conductive structure 404 located on the second well region 402, wherein the first conductive structure 403 and the second conductive structure 404 are connected. In an optional embodiment, the first conductive structure 403 and the second conductive structure 404 can be two parts (such as Figure 4 In another optional embodiment, the first conductive structure 403 and the second conductive structure 404 can be as shown. Fig.13 As shown, it is an integral structure.

[0165] The first active region 405 is located in the first well region 401, and the first active region 405 includes a source region 4051 and a drain region 4052. The source region 4051 and the drain region 4052 are both implanted with third doping ions, and the source region 4051 and the drain region 4052 are respectively located on both sides of the first conductive structure. Optionally, the source region 4051 can be connected to a source, and the drain region 4052 can be connected to a drain.

[0166] The second active region 406 is located in the second well region 402, and the second active region 406 includes a first doping region 4061 and a second doping region 4062, and the first doping region 4061 and the second doping region 4062 are respectively located on both sides of the second conductive structure. In addition, the first doping region 4061 and the second doping region 4062 are both implanted with fourth doping ions, and the first doping region 401 forms a gate, or the second doping region 4062 forms a gate.

[0167] In an optional embodiment, if Fig.13 As shown, the size of the first conductive structure 403 on the first well region 401 in the first direction is greater than the size of the second conductive structure 404 on the second well region 402 in the first direction.

[0168] In the embodiment of the present application, the first active region 405 includes not only the source region 4051 and the drain region 4052, but also includes a region covered by the first conductive structure and ultimately used to form a conductive channel. The second active region includes not only the first doped region 4061 and the second doped region 4062, but also includes a region covered by the second conductive structure.

[0169] Optionally, the first active region 405 and the second active region 406 have the same size in the second direction, that is, the first active region 405 and the second active region 406 have the same span in the second direction.

[0170] Alternatively, the first active region 405 and the second active region 406 have the same size in the second direction, but different sizes in the first direction. For example, the size of the first active region 405 in the first direction is larger than the size of the second active region 406 in the first direction.

[0171] Thus, the area of ​​the first overlapping region corresponding to the first active region 405 and the first conductive structure 403 is finally reduced to Fig.13 The dotted circle on the left side of the figure is larger than the area of ​​the second overlapping region corresponding to the second active region 406 and the second conductive structure 404 ( Fig.13 That is, the two active regions overlap with the polysilicon thereon, and of the two overlapping areas obtained, a first overlapping area corresponding to the first overlapping area is larger than a second overlapping area corresponding to the second overlapping area.

[0172] In some possible embodiments, the concentration of the first doping ions implanted in the first well region is a first concentration, the concentration of the third doping ions implanted in the source region and the drain region is a second concentration, and the second concentration is greater than the first concentration. The concentration of the second doping ions implanted in the second well region is a third concentration, and the concentration of the fourth doping ions implanted in the first doping region is a fourth concentration, and the fourth concentration is greater than the third concentration.

[0173] In the embodiment of the present application, on the basis of improving the subthreshold swing by adjusting the semiconductor device structure, the subthreshold swing can be further improved or reduced by adjusting the concentration of doped ions. However, the subthreshold swing finally obtained is larger than the original MOS tube ( Figure 3 The subthreshold swing of ).

[0174] For example, in Fig. 9 In the semiconductor device structure shown, the subthreshold swing can be further adjusted by adjusting the concentration of the second doping ion in the second well region 402. Optionally, the concentration of the second doping ion in the second well region 402 can be increased from the third concentration to the fifth concentration. The higher the concentration, the more electrons in the second well region 402 increase. The fifth concentration is greater than the third concentration, and the fifth concentration is less than the fourth concentration.

[0175] When the gate voltage is greater than 0, the area of ​​the second well region 402 near the oxide layer will gather more electrons, so that the second conductive structure 404 (such as polysilicon) near the oxide layer will gather more holes. Since the first conductive structure 403 and the second conductive structure 404 are connected or are a whole, more holes are also gathered on the side of the first conductive structure 403 near the oxide layer. At this time, a large number of holes gathered on the side of the first conductive structure 403 near the oxide layer repel the holes in the first well region 401 near the oxide layer, attract electrons, and more easily form a conductive channel, turning on the source and drain. When the drain is connected to a voltage source, a subthreshold leakage current will be generated, thereby lighting up the OLED through the source. Since it is easier to turn on the conductive channel, that is, the subthreshold swing will be reduced.

[0176] Similarly, when the concentration of the second doped ion in the second well region 402 is reduced from the first concentration to the sixth concentration, when the gate voltage is greater than 0, the area of ​​the second well region 402 close to the oxide layer will gather fewer electrons, so that the second conductive structure 404 (such as polysilicon) close to the oxide layer gathers fewer holes. Since the first conductive structure 403 and the second conductive structure 404 are connected or are a whole, the side of the first conductive structure 403 close to the oxide layer also gathers fewer holes. At this time, the large number of holes gathered on the side of the first conductive structure 403 close to the oxide layer repels the holes in the first well region 401 close to the oxide layer, attracting electrons, making it more difficult to form a conductive channel, turning on the source and drain. When the drain is connected to a voltage source, a subthreshold leakage current is generated, thereby lighting up the OLED through the source. Since it is more difficult to turn on the conductive channel, that is, the subthreshold swing will increase.

[0177] Optionally, the sixth concentration is less than the second concentration.

[0178] Therefore, on the basis of increasing the subthreshold swing by adjusting the semiconductor device structure, if the concentration of the second doping ions in the second well region 402 is further increased, the subthreshold swing will decrease, and vice versa.

[0179] Fig.14 It is a schematic diagram of a method for forming a semiconductor device structure based on an OLED display according to an exemplary embodiment. It should be noted that this specification provides method operation steps as described in the embodiments or flow charts, but more or fewer operation steps may be included based on conventional or non-creative labor. The order of steps listed in the embodiments is only one way of executing the steps among many orders, and does not represent the only order of execution. When the actual system or product is executed, it can be executed in sequence or in parallel according to the method shown in the embodiments or drawings (for example, in a parallel processor or multi-threaded processing environment). Specifically, Fig.14 As shown, the flow chart at least includes the following steps S1401-S1403:

[0180] In step S1401 , a substrate is provided.

[0181] In step S1403, a first well region and a second well region are formed in the substrate; the first well region is implanted with first doping ions, and the second well region is implanted with second doping ions; the first doping ions and the second doping ions have different conductivity types.

[0182] In an optional embodiment, the first doping ions in the first well region have a first concentration, and the concentration of the second doping ions in the second well region has a third concentration. The first concentration may be equal to the third concentration, or may not be equal to the third concentration.

[0183] In step S1405 , a first conductive structure and a second conductive structure are formed on the first well region and the second well region; the first conductive structure and the second conductive structure are connected.

[0184] In an optional embodiment, the first conductive structure and the second conductive structure may be two parts, but the two parts are connected together. In another optional embodiment, the first conductive structure 403 and the second conductive structure 404 may be an integral structure, that is, when formed, they are formed together as an integral structure.

[0185] Optionally, the first conductive structure and the second conductive structure are metal or polysilicon. When the first conductive structure and the second conductive structure are an integral structure, the first conductive structure and the second conductive structure can be a whole metal structure or a whole polysilicon structure.

[0186] In step S1407, a first active region is formed in the first well region; the first active region includes a source region and a drain region; the source region and the drain region are implanted with third doping ions; the source region and the drain region are respectively located on two sides of the first conductive structure.

[0187] In an optional embodiment, the source region can be connected to form a source, and the drain region can be connected to form a drain.

[0188] Optionally, the concentration of the third doping ions implanted into the source region and the drain region is a second concentration, and the second concentration is greater than the first concentration.

[0189] In step S1409, a second active region is formed in the second well region; the second active region includes a first doped region, the first doped region is implanted with fourth doped ions, and the first doped region forms a gate; wherein the second doped ions, the third doped ions and the fourth doped ions have the same conductivity type.

[0190] In an optional embodiment, the second active region includes a first doping region and a second doping region, both of which are implanted with fourth doping ions and are located on both sides of the second conductive structure. Optionally, the first doping region and the second doping region can form a gate.

[0191] In an optional embodiment, the ion concentration of the second well region into which the second doping ions are implanted is a fifth concentration, and the fifth concentration is greater than the third concentration.

[0192] In the embodiment of the present application, the process of forming a semiconductor device structure based on OLED display (including materials, temperature, thickness, etc.) can refer to the process of forming a CMOS tube in the prior art, and will not be repeated here.

[0193] In another optional embodiment, Figure 4 The left part structure of the semiconductor device structure shown is existing, so the left part structure of the semiconductor device structure can be provided, and on this basis, the right part structure is formed.

[0194] It should be noted that the method provided in the above embodiment belongs to the same concept as the structural embodiment, and its specific implementation process is detailed in the structural embodiment, which will not be repeated here.

[0195] Correspondingly, an embodiment of the present application further provides a display device, which includes the above-mentioned semiconductor device structure and also includes a light-emitting device connected to the semiconductor device structure.

[0196] Correspondingly, an embodiment of the present application further provides an electronic device, which includes the above-mentioned semiconductor device structure.

[0197] The electronic device described in the embodiments of the present application may be any electronic product or device such as a smart phone, a desktop computer, a tablet computer, a laptop computer, a digital assistant, an augmented reality (AR) / virtual reality (VR) device, an intelligent voice interaction device, a smart home appliance, a smart wearable device, a vehicle-mounted terminal device, or any intermediate product including the above-mentioned storage device.

[0198] It should be noted that the above-mentioned sequence of the embodiments of the present application is for description only and does not represent the advantages and disadvantages of the embodiments. The above-mentioned specific embodiments of this specification are described. Other embodiments are within the scope of the attached claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0199] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0200] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0201] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A semiconductor device structure based on OLED display, characterized in that: include: A substrate; the substrate comprises a first well region and a second well region; the first well region is implanted with first doping ions, and the second well region is implanted with second doping ions; the first doping ions and the second doping ions have different conductivity types; a first conductive structure located on the first well region and a second conductive structure located on the second well region; the first conductive structure and the second conductive structure are connected; a first active region located in the first well region; the first active region includes a source region and a drain region; the source region and the drain region are implanted with third doping ions; the source region and the drain region are respectively located on two sides of the first conductive structure; a second active region located in the second well region; the second active region comprises a first doped region, fourth doping ions are implanted into the first doped region, and the first doped region forms a gate; The second doping ions, the third doping ions, and the fourth doping ions have the same conductivity type.

2. The semiconductor device structure based on OLED display according to claim 1, characterized in that: The second active region further includes a second doping region; the second doping region is implanted with the fourth doping ions; The first doping region and the second doping region are respectively located at two sides of the second conductive structure; the first doping region and the second doping region form a gate.

3. The semiconductor device structure based on OLED display according to claim 2, characterized in that: The first conductive structure and the second conductive structure have the same size in the first direction; The first active region and the second active region have the same size in the second direction; An area of ​​a first overlapping region corresponding to the first active region and the first conductive structure is equal to an area of ​​a second overlapping region corresponding to the second active region and the second conductive structure.

4. The semiconductor device structure based on OLED display according to claim 2, characterized in that: The size of the first conductive structure in the first direction is greater than the size of the second conductive structure in the first direction; The first active region and the second active region have the same size in the second direction; An area of ​​a first overlapping region corresponding to the first active region and the first conductive structure is greater than an area of ​​a second overlapping region corresponding to the second active region and the second conductive structure.

5. The semiconductor device structure based on OLED display according to claim 2, characterized in that: The first conductive structure and the second conductive structure have the same size in the first direction; The size of the first active region in the second direction is smaller than the size of the second active region in the second direction; An area of ​​a first overlapping region corresponding to the first active region and the first conductive structure is smaller than an area of ​​a second overlapping region corresponding to the second active region and the second conductive structure.

6. The semiconductor device structure based on OLED display according to claim 1, characterized in that: The second active region further includes a second doping region; the second doping region is implanted with the fourth doping ions; the first doping region and the second doping region are respectively located on both sides of the second conductive structure; the first doping region forms a gate; The size of the first conductive structure in the first direction is greater than the size of the second conductive structure in the first direction; The first active region and the second active region have the same size in the second direction; An area of ​​a first overlapping region corresponding to the first active region and the first conductive structure is greater than an area of ​​a second overlapping region corresponding to the second active region and the second conductive structure.

7. The semiconductor device structure based on OLED display according to claim 1, characterized in that: The concentration of the first doping ions implanted into the first well region is a first concentration; The concentration of the third doping ions implanted into the source region and the drain region is the second concentration; The second concentration is greater than the first concentration; The concentration of the second doping ions implanted into the second well region is a third concentration; The concentration of the fourth doping ions implanted into the first doping region is a fourth concentration; The fourth concentration is greater than the third concentration.

8. The semiconductor device structure based on OLED display according to claim 7, characterized in that: The concentration of the second doping ions implanted into the second well region is a fifth concentration; The fifth concentration is greater than the third concentration, and the fifth concentration is less than the fourth concentration.

9. The semiconductor device structure based on OLED display according to any one of claims 1 to 8, characterized in that: The first conductive structure and the second conductive structure are polysilicon.

10. The semiconductor device structure based on OLED display according to claim 9, characterized in that: The first conductive structure and the second conductive structure are an integral structure.

11. A method for forming a semiconductor device structure based on OLED display, characterized in that: The method comprises: providing a substrate; A first well region and a second well region are formed in the substrate; the first well region is implanted with first doping ions, and the second well region is implanted with second doping ions; the first doping ions and the second doping ions have different conductivity types; forming a first conductive structure and a second conductive structure on the first well region and the second well region; the first conductive structure and the second conductive structure are connected; A first active region is formed in the first well region; the first active region includes a source region and a drain region; the source region and the drain region are implanted with third doping ions; the source region and the drain region are respectively located on two sides of the first conductive structure; forming a second active region in the second well region; the second active region comprises a first doped region, fourth doping ions are implanted into the first doped region, and the first doped region forms a gate; The second doping ions, the third doping ions, and the fourth doping ions have the same conductivity type.

12. The method for forming a semiconductor device structure according to claim 11, characterized in that: The second active region further includes a second doping region; the second doping region is implanted with the fourth doping ions; The first doping region and the second doping region are respectively located at two sides of the second conductive structure; the first doping region and the second doping region form a gate.

13. A display device, characterized in that: The display device comprises the semiconductor device structure based on OLED display according to any one of claims 1 to 10.

14. An electronic device, characterized in that: The electronic device comprises the semiconductor device structure based on OLED display according to any one of claims 1 to 10.

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