Display panel and display device

Abstract

The invention provides a display panel and a display device. According to the display panel, the first metal layer is arranged on the inorganic layer group, and the second metal layer is in lap joint with the first metal layer through the first via hole formed in the first insulating layer, so that the lap joint of the second metal layer and the first metal layer only needs the thickness of one first insulating layer, and the offset of the second metal layer is reduced; and the problem that the thickness of the metal layer is not uniform due to overlarge offset is effectively prevented.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The terminal part of a conventional display panel is usually composed of multiple layers of metal, and an insulating layer is generally provided between each metal layer. These metal layers usually need to be punched to achieve electrical connection.

[0003] However, in the actual manufacturing process, due to the presence of multiple inorganic layers, a large step difference (i.e., height difference) will be generated when punching and connecting, and the thickness of the metal layer will be uneven during the deposition process. When etching the metal layer, the area with a large step difference may cause the thickness of the metal layer to be uneven, causing the thinner part of the metal layer to be over-etched, and the thicker part of the metal layer to remain, which ultimately leads to structural abnormalities in the terminal part. Summary of the invention

[0004] In view of this, the present application provides a display panel and a display device, which are used to improve the problem of excessively large step difference of multiple metal layers in the terminal portion of the display panel.

[0005] The technical solution adopted by this application to solve the above technical problems is:

[0006] In a first aspect, an embodiment of the present application provides a display panel, comprising a display area and a non-display area arranged around the display area, the display panel comprising a substrate, an inorganic layer group, and a terminal portion, the substrate being located in the display area and the non-display area, the inorganic layer group being arranged on the substrate and being located in the display area and the non-display area, the terminal portion being arranged on a side of the inorganic layer group away from the substrate and being located in the non-display area;

[0007] Among them, the terminal part includes a first metal layer, a first insulating layer and a second metal layer, the first metal layer is arranged on the side of the inorganic layer group away from the substrate, the first insulating layer is arranged on the side of the inorganic layer group away from the substrate and covers part of the first metal layer, the first insulating layer is provided with a first via hole, the first via hole exposes the first metal layer, the second metal layer is arranged on the side of the first insulating layer away from the substrate, and the second metal layer is overlapped with the first metal layer through the first via hole.

[0008] Optionally, the first metal layer is a metal layer in the same layer as the gate layer in the display area, the first insulating layer is an insulating layer in the same layer as the first interlayer dielectric layer in the display area, and the second metal layer is a metal layer in the same layer as the first source and drain layer in the display area.

[0009] Optionally, the terminal portion also includes a first planarization layer and a third metal layer, the first planarization layer is arranged on the side of the first insulating layer away from the substrate and covers a portion of the second metal layer, the first planarization layer is provided with a second via hole exposing the second metal layer, the third metal layer is arranged on the side of the first planarization layer away from the substrate, and the third metal layer is overlapped with the second metal layer through the second via hole.

[0010] Optionally, the terminal portion also includes a second planarization layer and a fourth metal layer, the second planarization layer is arranged on a side of the first planarization layer away from the substrate and covers a portion of the third metal layer, the second planarization layer is provided with a third via hole exposing the third metal layer, the fourth metal layer is arranged on a side of the second planarization layer away from the substrate, and the fourth metal layer is overlapped with the third metal layer through the third via hole.

[0011] Optionally, the terminal portion includes a fifth metal layer and a second insulating layer, the second insulating layer is arranged on a side of the fourth metal layer away from the substrate and covers the fourth metal layer, the second insulating layer is provided with a fourth via hole exposing the fourth metal layer, the fifth metal layer is arranged on a side of the second insulating layer away from the substrate, and the fifth metal layer is overlapped with the fourth metal layer through the fourth via hole.

[0012] Optionally, the inorganic layer group includes a first gate insulation layer, a second gate insulation layer, a second interlayer dielectric layer and a third gate insulation layer stacked in sequence, the first metal layer is arranged on a side of the third gate insulation layer away from the substrate, the first insulation layer is arranged on a side of the third gate insulation layer away from the substrate and covers a portion of the first metal layer, the first insulation layer is provided with the first via hole, and the second metal layer is overlapped with the first metal layer through the first via hole.

[0013] In a second aspect, an embodiment of the present application provides a display panel, comprising a display area and a non-display area arranged around the display area, the display panel comprising a substrate, an inorganic layer group, and a terminal portion, the substrate being located in the display area and the non-display area, the inorganic layer group being arranged on the substrate and being located in the display area and the non-display area, the terminal portion being arranged on a side of the inorganic layer group away from the substrate and being located in the non-display area;

[0014] Among them, the terminal part includes a second metal layer, a first planarization layer and a third metal layer, the second metal layer is arranged on the side of the inorganic layer group away from the substrate, the first planarization layer is arranged on the side of the inorganic layer group away from the substrate and covers part of the second metal layer, the first planarization layer is provided with a second via hole, the second via hole exposes the second metal layer, the third metal layer is arranged on the side of the first planarization layer away from the substrate, and the third metal layer is overlapped with the second metal layer through the second via hole.

[0015] Optionally, the second metal layer is a metal layer in the same layer as the first source and drain layer in the display area, the third metal layer is a metal layer in the same layer as the second source and drain layer in the display area, and the first planarization layer is located in the display area and the non-display area.

[0016] Optionally, the terminal portion also includes a fourth metal layer and a second planarization layer, the second planarization layer is arranged on a side of the first planarization layer away from the substrate and covers a portion of the third metal layer, the second planarization layer is provided with a third via hole exposing the third metal layer, the fourth metal layer is arranged on a side of the second planarization layer away from the substrate, and the fourth metal layer is overlapped with the third metal layer through the third via hole.

[0017] Optionally, the terminal portion includes a fifth metal layer and a second insulating layer, the second insulating layer is arranged on a side of the fourth metal layer away from the substrate and covers the fourth metal layer, the second insulating layer is provided with a fourth via hole exposing the fourth metal layer, the fifth metal layer is arranged on a side of the second insulating layer away from the substrate, and the fifth metal layer is overlapped with the fourth metal layer through the fourth via hole.

[0018] Optionally, the inorganic layer group includes a first gate insulating layer, a second gate insulating layer, a second interlayer dielectric layer, a third gate insulating layer and a first interlayer dielectric layer stacked in sequence, and the second metal layer is arranged on a side of the first interlayer dielectric layer away from the substrate.

[0019] In a third aspect, an embodiment of the present application provides a display device, comprising the display panel as described in the first aspect or the second aspect.

[0020] In summary, due to the adoption of the above technical solution, this application has at least the following beneficial effects:

[0021] The embodiment of the present application provides a display panel and a display device, by arranging a first metal layer on an inorganic layer group, and overlapping the second metal layer with the first metal layer through a first via hole opened in the first insulating layer, so that the overlap of the second metal layer with the first metal layer only needs to pass through the thickness of one layer of the first insulating layer, which is conducive to reducing the step difference of the second metal layer, and then effectively preventing the problem of uneven thickness of the metal layer caused by excessive step difference. In detail, firstly, the first metal layer is arranged on the inorganic layer group, so that the first metal layer can be arranged as close to the second metal layer as possible; then, only one layer of the first insulating layer is arranged on the first metal layer, and the first insulating layer is opened, so that the second metal layer only needs to pass through one layer of the first insulating layer to achieve overlap with the first metal layer. Compared with the conventional technology in which the first metal layer and the second metal layer are separated by multiple inorganic layers and metal layers, and the second metal layer needs to pass through the thickness of multiple inorganic layers and metal layers before it can overlap with the first metal layer, the step difference generated by the overlap of the second metal layer with the first metal layer in the present application is greatly reduced, thereby greatly reducing the risk of over-engraving or metal residue in the second metal layer due to excessive step difference. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present application;

[0023] Figure 2 A schematic structural diagram of a terminal portion in a display panel provided in an embodiment of the present application;

[0024] Figure 3 A schematic structural diagram of another terminal portion in a display panel provided in an embodiment of the present application;

[0025] Figure 4 for Figure 3 A plan view of the connection between the data line and the metal layer in the terminal portion is provided.

[0026] Description of reference numerals:

[0027] 1. Substrate; 2. Inorganic layer group; 21. First gate insulating layer; 22. Second gate insulating layer; 23. Third gate insulating layer; 24. First interlayer dielectric layer; 25. Second interlayer dielectric layer; 3. Terminal portion; 31. First metal layer; 32. First insulating layer; 321. First via hole; 33. Second metal layer; 34. First planarization layer; 341. Second via hole; 35. Third metal layer; 36. Second planarization layer; 361. Third via hole; 37. Fourth metal layer; 38. Second insulating layer; 381. Fourth via hole; 39. Fifth metal layer; 4. Through hole; 5. Data line; AA, display area; BB, non-display area. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0029] In the description of this application, it should be understood that the words "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0030] In this application, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any embodiment described in this application as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0031] See also Figure 1 and Figure 2 , an embodiment of the present application provides a display panel, which has a display area AA and a non-display area BB, and the non-display area BB is arranged around the display area AA. On the display area AA, a plurality of pixels are arranged for image display. The display panel includes a substrate 1, an inorganic layer group 2, and a terminal portion 3. The substrate 1 is located in the display area AA and the non-display area BB, the inorganic layer group 2 is arranged on the substrate 1 and is located in the display area AA and the non-display area BB, and the terminal portion 3 is arranged on the side of the inorganic layer group 2 away from the substrate 1 and is located in the non-display area BB. The terminal portion 3 is used to bind with an integrated circuit board or a flexible circuit board. After the terminal portion 3 is bound with the integrated circuit board or the flexible circuit board, the terminal portion 3 can transmit signals between the integrated circuit board or the flexible circuit board and the pixels or touch electrodes. The substrate 1 can be a flexible substrate or a rigid substrate. For example, the material of the flexible substrate can be polyimide, polycarbonate, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, polyarylate or glass fiber reinforced plastic. The material of the rigid substrate can be glass, etc.

[0032] The terminal portion 3 includes a first metal layer 31, a first insulating layer 32, and a second metal layer 33. The first metal layer 31 and the second metal layer 33 may be formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0033] The first metal layer 31 is disposed on the side of the inorganic layer group 2 away from the substrate 1. The first insulating layer 32 is disposed on the side of the inorganic layer group 2 away from the substrate 1 and covers a portion of the first metal layer 31. The first insulating layer 32 is provided with a first via 321, and the first via 321 exposes the first metal layer 31. The second metal layer 33 is disposed on the side of the first insulating layer 32 away from the substrate 1, and the second metal layer 33 overlaps the first metal layer 31 through the first via 321.

[0034] The technical solution provided in the present application is to arrange the first metal layer 31 on the inorganic layer group 2, and the second metal layer 33 is overlapped with the first metal layer 31 through the first via 321 opened in the first insulating layer 32, so that the overlap of the second metal layer 33 and the first metal layer 31 only needs to pass through the thickness of one layer of the first insulating layer 32, which is beneficial to reducing the step difference of the second metal layer 33, and then effectively preventing the problem of uneven metal layer thickness caused by excessive step difference. In detail, the first metal layer 31 is firstly arranged on the inorganic layer group 2 so that the first metal layer 31 can be arranged as close to the second metal layer 33 as possible; then, only one first insulating layer 32 is arranged on the first metal layer 31, and the first insulating layer 32 is opened so that the second metal layer 33 only needs to pass through one first insulating layer 32 to achieve overlap with the first metal layer 31. Compared with the conventional technology in which multiple inorganic layers and metal layers are separated between the first metal layer 31 and the second metal layer 33, the second metal layer 33 needs to pass through the thickness of multiple inorganic layers and metal layers to be able to overlap with the first metal layer 31. In the present application, the step difference generated by the overlap of the second metal layer 33 and the first metal layer 31 is greatly reduced, thereby greatly reducing the risk of over-engraving or metal residue in the second metal layer 33 due to excessive step difference.

[0035] It should be noted that the first metal layer 31 is a metal layer of the same layer as the gate layer in the display area AA, that is, the first metal layer 31 and the gate layer for forming the thin film transistor in the display area AA are substantially deposited as the same metal layer during the molding process, and then the metal layer is patterned, so that the gate layer is formed in the display area AA, and the first metal layer 31 is formed in the terminal part 3, and the first metal layer 31 is in the same layer as the gate layer. The first insulating layer 32 is an insulating layer of the same layer as the first interlayer dielectric layer 24 in the display area AA, that is, the first insulating layer 32 and the first interlayer dielectric layer 24 in the display area AA are substantially deposited as the same inorganic layer during the molding process, and then the inorganic layer is patterned, so that the first interlayer dielectric layer 24 is formed in the display area AA, and the first insulating layer 32 is formed in the terminal part 3, and the first insulating layer 32 is in the same layer as the first interlayer dielectric layer 24. The second metal layer 33 is a metal layer in the same layer as the first source and drain layer in the display area AA, that is, the second metal layer 33 and the first source and drain layer in the display area AA for forming the thin film transistor are substantially deposited as the same metal layer during the molding process, and then the metal layer is patterned, so that the first source and drain layer is formed in the display area AA, and the second metal layer 33 is formed in the terminal portion 3, and the second metal layer 33 is in the same layer as the first source and drain layer.

[0036] In some embodiments, see Figure 2 The terminal portion 3 further includes a first planarization layer 34 and a third metal layer 35. The first planarization layer 34 is disposed on a side of the first insulating layer 32 away from the substrate 1 and covers a portion of the second metal layer 33. The first planarization layer 34 is provided with a second via hole 341 exposing the second metal layer 33, and the third metal layer 35 is disposed on a side of the first planarization layer 34 away from the substrate 1, and the third metal layer 35 overlaps the second metal layer 33 through the second via hole 341. In this embodiment, on the basis that the second metal layer 33 only needs to pass through one layer of the first insulating layer 32, the third metal layer 35 also only needs to pass through the thickness of one layer of the first planarization layer 34 through the second via hole 341 to achieve the overlap of the third metal layer 35 and the second metal layer 33, which is beneficial to further reduce the step difference of the third metal layer 35 on the basis of reducing the step difference of the second metal layer 33, and avoid the situation that the third metal layer 35 is over-etched or metal residue occurs during the pattern etching process.

[0037] It should be noted that the third metal layer 35 is a metal layer on the same layer as the second source and drain layer in the display area AA, that is, the third metal layer 35 and the second source and drain layer in the display area AA for forming the thin film transistor are actually deposited as the same metal layer during the molding process, and then the metal layer is patterned, so that the second source and drain layer is formed in the display area AA, and the third metal layer 35 is formed in the terminal portion 3. The third metal layer 35 is on the same layer as the second source and drain layer, which is beneficial to saving process steps and process costs.

[0038] In addition, by overlapping the third metal layer 35 with the second metal layer 33 , the cross-sectional area of ​​the source and drain layers can be increased, thereby achieving the purpose of reducing the resistance of the terminal portion 3 .

[0039] In some embodiments, see Figure 2 The terminal portion 3 further includes a second planarization layer 36 and a fourth metal layer 37. The second planarization layer 36 is disposed on a side of the first planarization layer 34 away from the substrate 1 and covers a portion of the third metal layer 35. The second planarization layer 36 is provided with a third via hole 361 exposing the third metal layer 35. The fourth metal layer 37 is disposed on a side of the second planarization layer 36 away from the substrate 1, and the fourth metal layer 37 overlaps the third metal layer 35 through the third via hole 361. In this embodiment, on the basis that the second metal layer 33 only needs to pass through one layer of the first insulating layer 32, and the third metal layer 35 only needs to pass through one layer of the first planarization layer 34, the fourth metal layer 37 also only needs to pass through the thickness of one layer of the second planarization layer 36 through the third via hole 361 to achieve the overlap of the fourth metal layer 37 and the third metal layer 35, which is conducive to further reducing the step difference of the fourth metal layer 37 on the basis of reducing the step difference of the second metal layer 33 and the step difference of the third metal layer 35, and avoiding the situation that the fourth metal layer 37 is over-etched or metal residue occurs during the pattern etching process.

[0040] It should be noted that the fourth metal layer 37 is a metal layer on the same layer as the third source and drain layer in the display area AA, that is, the fourth metal layer 37 and the third source and drain layer in the display area AA for forming the thin film transistor are actually deposited as the same metal layer during the molding process, and then the metal layer is patterned, so that the third source and drain layer is formed in the display area AA, and the fourth metal layer 37 is formed in the terminal portion 3. The fourth metal layer 37 is on the same layer as the third source and drain layer, which is beneficial to saving process steps and process costs.

[0041] In addition, by overlapping the second metal layer 33 , the third metal layer 35 and the fourth metal layer 37 in sequence, the cross-sectional area of ​​the source and drain layers can be further increased, thereby further achieving the purpose of reducing the resistance of the terminal portion 3 .

[0042] In some embodiments, see Figure 2The terminal portion 3 includes a fifth metal layer 39 and a second insulating layer 38. The second insulating layer 38 is arranged on the side of the fourth metal layer 37 away from the substrate 1 and covers the fourth metal layer 37. The second insulating layer 38 is provided with a fourth via 381 for exposing the fourth metal layer 37. The fifth metal layer 39 is arranged on the side of the second insulating layer 38 away from the substrate 1, and the fifth metal layer 39 is overlapped with the fourth metal layer 37 through the fourth via 381. The second insulating layer 38 is composed of an inorganic material (such as SiO2, SiN) or an organic material (such as polyimide PI) with excellent insulation performance. The second insulating layer 38 is provided with a fourth via 381 at a position corresponding to the required signal transmission, exposing part of the fourth metal layer 37 for electrical connection of the fifth metal layer 39. The non-opened area provides insulation protection to avoid short circuit or signal interference. The fifth metal layer 39 is arranged on the side of the second insulating layer 38 away from the substrate 1, and is electrically overlapped with the exposed fourth metal layer 37 through the fourth via 381. The fifth metal layer 39 is usually made of a transparent conductive material (such as ITO) to ensure that the touch function area can achieve both conductivity and good optical transmittance. The fifth metal layer 39 serves as a sensing or transmission path for touch signals to realize the touch operation function of the display panel.

[0043] It should be noted that the fifth metal layer 39 is a metal layer in the same layer as the touch metal layer in the display area AA, and the second insulating layer 38 is an insulating layer in the same layer as the touch insulating layer in the display area AA.

[0044] In some embodiments, see Figure 2 The inorganic layer group 2 includes a first gate insulating layer 21, a second gate insulating layer 22, a second interlayer dielectric layer 25 and a third gate insulating layer 23 stacked in sequence. The first gate insulating layer 21, the second gate insulating layer 22, the second interlayer dielectric layer 25 and the third gate insulating layer 23 all extend from the display area AA to the non-display area BB. The first metal layer 31 is arranged on the side of the third gate insulating layer 23 away from the substrate 1, the first insulating layer 32 is arranged on the side of the third gate insulating layer 23 away from the substrate 1 and covers part of the first metal layer 31, the first insulating layer 32 is provided with a first via hole 321, and the second metal layer 33 overlaps with the first metal layer 31 through the first via hole 321. By arranging the first metal layer 31 on the third gate insulating layer 23, the first metal layer 31 can be as close to the second metal layer 33 as possible, without passing through the multiple inorganic layers in the inorganic layer group 2, and only through the first insulating layer 32 to achieve the overlap of the first metal layer 31 and the second metal layer 33, which greatly reduces the step formed by the second metal layer 33.

[0045] See also Figure 1 and Figure 3, the embodiment of the present application also provides another display panel, which has a display area AA and a non-display area BB, and the non-display area BB is arranged around the display area AA. On the display area AA, a plurality of pixels are arranged for image display. The display panel includes a substrate 1, an inorganic layer group 2 and a terminal portion 3. The substrate 1 is located in the display area AA and the non-display area BB, the inorganic layer group 2 is arranged on the substrate 1 and is located in the display area AA and the non-display area BB, and the terminal portion 3 is arranged on the side of the inorganic layer group 2 away from the substrate 1 and is located in the non-display area BB. The terminal portion 3 is used to bind with an integrated circuit board or a flexible circuit board. After the terminal portion 3 is bound with the integrated circuit board or the flexible circuit board, the terminal portion 3 can transmit signals between the integrated circuit board or the flexible circuit board and the pixels or touch electrodes. The substrate 1 can be a flexible substrate or a rigid substrate. For example, the material of the flexible substrate can be polyimide, polycarbonate, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, polyarylate or glass fiber reinforced plastic. The material of the rigid substrate can be glass, etc.

[0046] The terminal portion 3 includes a second metal layer 33, a first planarization layer 34, and a third metal layer 35. The first metal layer 31 and the second metal layer 33 may be formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0047] Among them, the second metal layer 33 is arranged on the side of the inorganic layer group 2 away from the substrate 1, the first planarization layer 34 is arranged on the side of the inorganic layer group 2 away from the substrate 1 and covers part of the second metal layer 33, the first planarization layer 34 is provided with a second via 341, the second via 341 exposes the second metal layer 33, and the third metal layer 35 is arranged on the side of the first planarization layer 34 away from the substrate 1, and the third metal layer 35 overlaps the second metal layer 33 through the second via 341. By arranging the second metal layer 33 on the inorganic layer group 2, only one layer of the first planarization layer 34 is spaced between the second metal layer 33 and the third metal layer 35. The third metal layer 35 can overlap the second metal layer 33 by passing through the first planarization layer 34 through the first via 321, ensuring that when the third metal layer 35 overlaps the second metal layer 33, there will be no excessive step difference, thereby reducing the risk of partial metal residue and partial metal over-etching of the third metal layer 35 during the pattern etching process. The display surface provided in this embodiment is different from the display panel provided in the aforementioned embodiment in that the display panel in this embodiment eliminates the first metal layer 31 and replaces the first metal layer 31 with the second metal layer 33, thereby effectively avoiding the step difference caused by the overlap of the first metal layer 31 and the second metal layer 33, and further reducing the step difference of the subsequent overlap of the third metal layer 35 and the fourth metal layer 37.

[0048] Please note that, see Figure 4 Although the first metal layer 31 below the second metal layer 33 of the terminal part 3 is removed, the first metal layer 31 of the same layer as the gate layer in the display area AA is still provided at the end of the terminal part 3, but the first metal layer 31 is no longer located at the pin of the terminal part 3. In addition, a through hole 4 is opened at the end of the terminal part 3 using via technology, and the through hole 4 exposes the first metal layer 31, so that the data line 5 can be overlapped with the first metal layer 31 at the end of the terminal part 3 through the through hole 4.

[0049] It should also be noted that the second metal layer 33 is the same metal layer as the first source and drain layer in the display area AA, the third metal layer 35 is the same metal layer as the second source and drain layer in the display area AA, and the first planarization layer 34 is located in the display area AA and the non-display area BB.

[0050] In some embodiments, see Figure 3 , the terminal portion 3 further includes a fourth metal layer 37 and a second planarization layer 36. The second planarization layer 36 is disposed on a side of the first planarization layer 34 away from the substrate 1 and covers a portion of the third metal layer 35. The second planarization layer 36 is provided with a third via hole 361 for exposing the third metal layer 35. The fourth metal layer 37 is disposed on a side of the second planarization layer 36 away from the substrate 1, and the fourth metal layer 37 overlaps the third metal layer 35 through the third via hole 361. In this embodiment, on the basis that the third metal layer 35 only needs to pass through one layer of the first planarization layer 34, the fourth metal layer 37 also only needs to pass through the thickness of one layer of the second planarization layer 36 through the third via hole 361 to achieve the overlap of the fourth metal layer 37 and the third metal layer 35, which is beneficial to further reduce the step difference of the fourth metal layer 37 on the basis of reducing the step difference of the third metal layer 35, and avoid the situation that the fourth metal layer 37 is over-etched or metal residue occurs during the pattern etching process.

[0051] In addition, by overlapping the fourth metal layer 37 with the third metal layer 35 , the cross-sectional area of ​​the source and drain layers can be increased, thereby achieving the purpose of reducing the resistance of the terminal portion 3 .

[0052] In some embodiments, see Figure 3The terminal portion 3 further includes a fifth metal layer 39 and a second insulating layer 38. The second insulating layer 38 is disposed on a side of the fourth metal layer 37 away from the substrate 1 and covers the fourth metal layer 37. The second insulating layer 38 is provided with a fourth via 381 for exposing the fourth metal layer 37. The fifth metal layer 39 is disposed on a side of the second insulating layer 38 away from the substrate 1, and the fifth metal layer 39 is overlapped with the fourth metal layer 37 through the fourth via 381. The second insulating layer 38 is composed of an inorganic material (such as SiO2, SiN) or an organic material (such as polyimide PI) with excellent insulation performance. The second insulating layer 38 is provided with a fourth via 381 at a position corresponding to the required signal transmission, exposing part of the fourth metal layer 37 for electrical connection of the fifth metal layer 39. The non-opened area provides insulation protection to avoid short circuit or signal interference. The fifth metal layer 39 is disposed on a side of the second insulating layer 38 away from the substrate 1, and is electrically overlapped with the exposed fourth metal layer 37 through the fourth via 381. The fifth metal layer 39 is usually made of a transparent conductive material (such as ITO) to ensure that the touch function area can achieve both conductivity and good optical transmittance. The fifth metal layer 39 serves as a sensing or transmission path for touch signals to realize the touch operation function of the display panel.

[0053] It should be noted that the fifth metal layer 39 is a metal layer in the same layer as the touch metal layer in the display area AA, and the second insulating layer 38 is an insulating layer in the same layer as the touch insulating layer in the display area AA.

[0054] In some embodiments, see Figure 3 The inorganic layer group 2 includes a first gate insulating layer 21, a second gate insulating layer 22, a second interlayer dielectric layer 25, a third gate insulating layer 23 and a first interlayer dielectric layer 24 stacked in sequence. The second metal layer 33 is disposed on the side of the first interlayer dielectric layer 24 away from the substrate 1. By arranging the second metal layer 33 on the first interlayer dielectric layer 24, the third metal layer 35 can be as close to the second metal layer 33 as possible, and the third metal layer 35 can overlap with the second metal layer 33 by only passing through the first planarization layer 34 without passing through the multiple inorganic layers in the inorganic layer group 2, thereby greatly reducing the step formed by the third metal layer 35.

[0055] In summary, the first technical solution in the present application arranges the first metal layer 31 on the inorganic layer group 2 so that the first metal layer 31 is arranged close to the second metal layer 33. Compared with the conventional technology, the second metal layer 33 can overlap with the first metal layer 31 without passing through the multiple inorganic layers in the inorganic layer group 2, which is conducive to reducing the step difference of the second metal layer 33. The second technical solution cancels the first metal layer 31 and arranges the second metal layer 33 on the inorganic layer group 2 so that the second metal layer 33 no longer overlaps with the first metal layer 31, and there is no step difference problem. Furthermore, the third metal layer 35 only needs to pass through the first planarization layer 34. The step difference is greatly reduced compared with the conventional technology, thereby reducing the risk of over-etching the thinner part of the source and drain layer and leaving the thicker part.

[0056] The embodiment of the present application further provides a display device, which includes the display panel described in any of the above embodiments. The display device has all the structures and beneficial effects of the display panel, which will not be described in detail here.

[0057] At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0058] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more application embodiments, in the above description of the embodiments of the present application, multiple features are sometimes merged into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of the present application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

Claims

1. A display panel, characterized in that: The display panel comprises a display area and a non-display area arranged around the display area, wherein the display panel comprises a substrate, an inorganic layer group and a terminal portion, wherein the substrate is located in the display area and the non-display area, the inorganic layer group is arranged on the substrate and is located in the display area and the non-display area, and the terminal portion is arranged on a side of the inorganic layer group away from the substrate and is located in the non-display area; Among them, the terminal part includes a first metal layer, a first insulating layer and a second metal layer, the first metal layer is arranged on the side of the inorganic layer group away from the substrate, the first insulating layer is arranged on the side of the inorganic layer group away from the substrate and covers part of the first metal layer, the first insulating layer is provided with a first via hole, the first via hole exposes the first metal layer, the second metal layer is arranged on the side of the first insulating layer away from the substrate, and the second metal layer is overlapped with the first metal layer through the first via hole.

2. The display panel according to claim 1, wherein: The first metal layer is a metal layer in the same layer as the gate layer in the display area, the first insulating layer is an insulating layer in the same layer as the first interlayer dielectric layer in the display area, and the second metal layer is a metal layer in the same layer as the first source and drain layer in the display area.

3. The display panel according to claim 1, wherein: The terminal portion also includes a first planarization layer and a third metal layer. The first planarization layer is arranged on a side of the first insulating layer away from the substrate and covers a portion of the second metal layer. The first planarization layer is provided with a second via hole exposing the second metal layer. The third metal layer is arranged on a side of the first planarization layer away from the substrate, and the third metal layer is overlapped with the second metal layer through the second via hole.

4. The display panel according to claim 3, wherein: The terminal portion also includes a second planarization layer and a fourth metal layer, the second planarization layer is arranged on a side of the first planarization layer away from the substrate and covers a portion of the third metal layer, the second planarization layer is provided with a third via hole exposing the third metal layer, the fourth metal layer is arranged on a side of the second planarization layer away from the substrate, and the fourth metal layer is overlapped with the third metal layer through the third via hole.

5. The display panel according to claim 4, wherein: The terminal portion includes a fifth metal layer and a second insulating layer, the second insulating layer is arranged on a side of the fourth metal layer away from the substrate and covers the fourth metal layer, the second insulating layer is provided with a fourth via hole exposing the fourth metal layer, the fifth metal layer is arranged on a side of the second insulating layer away from the substrate, and the fifth metal layer is overlapped with the fourth metal layer through the fourth via hole.

6. The display panel according to any one of claims 1 to 5, characterized in that: The inorganic layer group includes a first gate insulating layer, a second gate insulating layer, a second interlayer dielectric layer and a third gate insulating layer stacked in sequence, the first metal layer is arranged on a side of the third gate insulating layer away from the substrate, the first insulating layer is arranged on a side of the third gate insulating layer away from the substrate and covers a portion of the first metal layer, the first insulating layer is provided with the first via hole, and the second metal layer is overlapped with the first metal layer through the first via hole.

7. A display panel, characterized in that: The display panel comprises a display area and a non-display area arranged around the display area, wherein the display panel comprises a substrate, an inorganic layer group and a terminal portion, wherein the substrate is located in the display area and the non-display area, the inorganic layer group is arranged on the substrate and is located in the display area and the non-display area, and the terminal portion is arranged on a side of the inorganic layer group away from the substrate and is located in the non-display area; Among them, the terminal part includes a second metal layer, a first planarization layer and a third metal layer, the second metal layer is arranged on the side of the inorganic layer group away from the substrate, the first planarization layer is arranged on the side of the inorganic layer group away from the substrate and covers part of the second metal layer, the first planarization layer is provided with a second via hole, the second via hole exposes the second metal layer, the third metal layer is arranged on the side of the first planarization layer away from the substrate, and the third metal layer is overlapped with the second metal layer through the second via hole.

8. The display panel according to claim 7, wherein: The second metal layer is a metal layer in the same layer as the first source and drain layer in the display area, the third metal layer is a metal layer in the same layer as the second source and drain layer in the display area, and the first planarization layer is located in the display area and the non-display area.

9. The display panel according to claim 7, wherein: The terminal portion also includes a fourth metal layer and a second planarization layer, the second planarization layer is arranged on a side of the first planarization layer away from the substrate and covers a portion of the third metal layer, the second planarization layer is provided with a third via hole exposing the third metal layer, the fourth metal layer is arranged on a side of the second planarization layer away from the substrate, and the fourth metal layer is overlapped with the third metal layer through the third via hole.

10. The display panel according to claim 9, wherein: The terminal portion includes a fifth metal layer and a second insulating layer, the second insulating layer is arranged on a side of the fourth metal layer away from the substrate and covers the fourth metal layer, the second insulating layer is provided with a fourth via hole exposing the fourth metal layer, the fifth metal layer is arranged on a side of the second insulating layer away from the substrate, and the fifth metal layer is overlapped with the fourth metal layer through the fourth via hole.

11. The display panel according to any one of claims 7 to 10, characterized in that: The inorganic layer group includes a first gate insulating layer, a second gate insulating layer, a second interlayer dielectric layer, a third gate insulating layer and a first interlayer dielectric layer stacked in sequence, and the second metal layer is arranged on a side of the first interlayer dielectric layer away from the substrate.

12. A display device, characterized in that: The display panel comprises the display panel as claimed in any one of claims 1 to 6 or the display panel as claimed in any one of claims 7 to 11.

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