Centrifugal pump flow control circuit

Abstract

The centrifugal pump flow control circuit comprises a synchronous and asynchronous regulator, and the synchronous and asynchronous regulator comprises a plurality of digital potentiometers, a plurality of operational amplifiers, a plurality of multiplexing chips, a plurality of resistors, a counting chip and a switch; a second pin of a digital potentiometer U3 in the plurality of digital potentiometers is connected with a second pin of a digital potentiometer U4, a fourteenth pin of a counting chip U9 and an output end of an operational amplifier U10, and a third pin is connected with a first pin of a multiplexing chip U7, a twelfth pin of the multiplexing chip U7, one end of a resistor R9 and a voltage control signal J17 end; a seventh pin is connected with a seventh pin of the digital potentiometer U4, a seventh pin of the digital potentiometer U5, a ninth pin of the counting chip U9 and one end of a resistor R11; and a third pin of the digital potentiometer U4 is connected with a fifth pin of the digital potentiometer U5, a sixth pin of the digital potentiometer U5, a twelfth pin of the multiplexing chip U8 and a voltage control signal J16 end.

Description

Technical Field

[0001] The invention relates to the technical field of centrifugal pumps, and in particular to a flow control circuit for a centrifugal pump. Background Art

[0002] The flow control of the centrifugal pump can not only adjust the flow by changing the impeller speed, but also adjust the bypass valve opening to change the flow in the circuit. In addition, the parallel and series control of the centrifugal pump is also an effective regulation method. The specific selection of which regulation method can be determined according to the actual application scenario and demand. However, in the parallel application of centrifugal pumps, centrifugal pumps of the same model are required to form a water supply system. This is to avoid the pressure head imbalance caused by the different flow rates of centrifugal pumps with different parameters after being connected to the grid, resulting in a decrease in efficiency, especially in waterways containing more pumping systems. This decrease is particularly obvious. In actual applications, the inventor found that it is difficult to purchase the same model of water pumps when reconstructing and replacing the supply network that has been put into use. Although water pumps with similar parameters can be used as substitutes, due to different characteristic curves, the above-mentioned pressure problems will still occur. Therefore, a centrifugal pump flow control circuit is proposed to avoid the imbalance problem caused by different flow rates when different water pumps are connected to the grid. Summary of the invention

[0003] In view of the above technical problems, the object of the present invention is to provide a centrifugal pump flow control circuit, including a synchronous and asynchronous regulator, wherein the synchronous and asynchronous regulator includes a plurality of digital potentiometers, a plurality of operational amplifiers, a plurality of multiplexing chips, a plurality of resistors, a counting chip, and a switch;

[0004] The second pin of the digital potentiometer U3 in the said several digital potentiometers is connected to the second pin of the digital potentiometer U4, the fourteenth pin of the counting chip U9, and the output end of the operational amplifier U10; the third pin is connected to the first pin of the multiplexing chip U7, the twelfth pin of the multiplexing chip U7, one end of the resistor R9, and the end of the voltage control signal J1_7; the seventh pin is connected to the seventh pin of the digital potentiometer U4, the seventh pin of the digital potentiometer U5, the ninth pin of the counting chip U9, and one end of the resistor R11; the third pin of the digital potentiometer U4 is connected to the fifth pin of the digital potentiometer U5, the sixth pin of the digital potentiometer U5, the twelfth pin of the multiplexing chip U8, and the end of the voltage control signal J1_6; the second pin of the digital potentiometer U5 is connected to the output end of the operational amplifier U6, and the third pin, the other end of the resistor R9, one end of the switch SW2 are connected to the power supply; the in-phase end of the operational amplifier U6 is connected to the thirteenth pin of the multiplexing chip U7, and the inverting end is connected to the thirteenth pin of the multiplexing chip U8; The third pin of chip U7 is connected to the in-phase end of operational amplifier U10, the fourth pin is connected to the flow sampling signal J1_5 end, the ninth pin and the tenth pin are respectively connected to the ninth pin of multiplexing chip U8, the tenth pin of multiplexing chip U8, the eleventh pin of counting chip U9, the fifteenth pin of counting chip U9, one end of resistor R10, and the other end of switch SW2, the eleventh pin is connected to the first pin of multiplexing chip U8, the fourth pin of multiplexing chip U8, and the single control flow signal J1_2 end; the third pin of multiplexing chip U8 is connected to the inverting end of operational amplifier U10, and the eleventh pin is connected to the flow sampling signal J1_4 end; the fifth pin of digital potentiometer U3, the sixth pin of digital potentiometer U3, the fifth pin of digital potentiometer U4, the sixth pin of digital potentiometer U4, the sixth pin of multiplexing chip U7, the sixth pin of multiplexing chip U8, the thirteenth pin of counting chip U9, the other end of resistor R10, the other end of resistor R11 and the ground end are connected.

[0005] Furthermore, it also includes a converter, which includes a plurality of digital potentiometers, a plurality of operational amplifiers, a plurality of resistors, and an inverter;

[0006] The second pin of the digital potentiometer U11 in the plurality of triggers is connected to the output end of the inverter U13, the third pin and the third pin of the digital potentiometer U15 are connected to the power supply, the fifth pin and the sixth pin are connected to the third pin of the digital potentiometer U12, the fifth pin of the digital potentiometer U12, and the in-phase end of the operational amplifier U14, the seventh pin is connected to the seventh pin of the digital potentiometer U12, the seventh pin of the digital potentiometer U15, the seventh pin of the digital potentiometer U17, and the output end of the operational amplifier U20; the second pin of the digital potentiometer U12 is connected to the input end of the inverter U13, the output end of the operational amplifier U14, the second pin of the digital potentiometer U15, and the second pin of the digital potentiometer U17; the inverting end of the operational amplifier U14 is connected to the output end of the operational amplifier U16, the in-phase end of the operational amplifier U20, and one end of the resistor R14 ; The fifth pin and the sixth pin of the digital potentiometer U15 are connected to the inverting end of the operational amplifier U19 and one end of the resistor R12; the inverting end of the operational amplifier U16 is connected to one end of the resistor R13 and the other end of the resistor R14; the third pin and the fifth pin of the digital potentiometer U17 are connected to the total flow voltage reference signal J1_3, and the sixth pin is connected to the inverting end of the operational amplifier U18 and one end of the resistor R15; the output end of the operational amplifier U18 is connected to the other end of the resistor R15 and the single control flow signal J1_2; the output end of the operational amplifier U19 is connected to the other end of the resistor R12 and the other end of the resistor R13; the inverting end of the operational amplifier U20 is connected to the quantity feedback signal J1_1; the sixth pin of the digital potentiometer U12, the in-phase end of the operational amplifier U16, the in-phase end of the operational amplifier U18, the in-phase end of the operational amplifier U19 and the ground are connected.

[0007] Furthermore, it also includes a sampling detector, which includes a plurality of operational amplifiers, a plurality of diodes, a plurality of resistors, a plurality of resistors, and a DIP switch;

[0008] The in-phase end of the operational amplifier U1 in the plurality of operational amplifiers is connected to one end of the resistor R1 and one end of the resistor R2, the inverting end is connected to one end of the resistor R3, and the output end is connected to the other end of the resistor R3 and the cathodes of the diodes D1 to D8; the in-phase end of the operational amplifier U2 is connected to one end of the resistor R6, the inverting end is connected to one end of the resistor R5 and the parallel end of the ninth pin to the sixteenth pin of the resistor RN3, the output end is connected to one end of the resistor R4, the other end of the resistor R5, and one end of the resistor R7; one end of the resistor R1 and the ninth pin of the dip switch SW1 are connected to the power supply; the other end of the resistor R7 and one end of the resistor R8 are connected to the end of the quantity feedback signal J1_1; the dip switch SW The first pin to the eighth pin of the resistor RN1 are respectively connected to the sixteenth pin to the ninth pin of the resistor RN1; the first pin to the fourth pin of the resistor RN1 are respectively connected to the first pin to the fourth pin of the resistor RN2, the first pin to the fourth pin of the resistor RN3, and the anodes of the diodes D5 to D8, and the fifth pin to the eighth pin are respectively connected to the fifth pin to the eighth pin of the resistor RN2, the fifth pin to the eighth pin of the resistor RN3, and the anodes of the diodes D1 to D4; the other end of the resistor R2, the other end of the resistor R4, the other end of the resistor R6, the other end of the resistor R8, the parallel end of the ninth pin to the sixteenth pin of the resistor RN2 and the ground are connected.

[0009] Furthermore, it also includes a flow sensor, which is used to sample the flow signal.

[0010] Furthermore, it also includes a signal voltage regulator, and the signal voltage regulator includes a potentiometer and a resistor;

[0011] One end of the potentiometer RV2 is connected to the power supply, and the other end is connected to the tap end, one end of the resistor R17, and the total flow voltage reference signal J1_3 end; the other end of the resistor R17 is connected to the ground end.

[0012] Furthermore, it also includes a voltage-controlled oscillator, wherein the input end of the voltage-controlled oscillator is connected to the voltage-controlled signal J1_6 and the voltage-controlled signal J1_7, and the output end is connected to the centrifugal pump.

[0013] Furthermore, it also includes a flow sensor and a DAC chip. The flow sensor samples the output flow of the centrifugal pump and feeds it back to the DAC to convert it into an analog signal and feed it back to J1_4 and J1_5

[0014] The beneficial effects of the present invention compared with the prior art are:

[0015] The present invention can balance the flow of centrifugal pumps of different models or different characteristic curves of different batches when forming a new water system, avoiding the problem of inconsistent pressure heads due to flow imbalance when different centrifugal pumps work in parallel, and is convenient for docking with the existing water system. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 This is a schematic diagram of a sampling detector circuit provided by the present invention.

[0018] Figure 2 This is a schematic diagram of the synchronous and asynchronous controller circuit provided by the present invention.

[0019] Figure 3 This is a schematic diagram of a converter circuit provided by the present invention.

[0020] Figure 4 This is a schematic diagram of a signal regulator provided by the present invention. DETAILED DESCRIPTION

[0021] In order to make the objects and advantages of the present invention more clearly understood, the present invention is specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or several specific implementations of the present invention, and does not strictly limit the scope of protection specifically requested by the present invention.

[0022] like Figure 2 As shown, the present invention discloses a centrifugal pump flow control circuit, specifically, including a synchronous and asynchronous regulator, wherein the synchronous and asynchronous regulator includes a plurality of digital potentiometers, a plurality of operational amplifiers, a plurality of multiplexing chips, a plurality of resistors, a counting chip, and a switch;

[0023] The second pin of the digital potentiometer U3 in the said several digital potentiometers is connected to the second pin of the digital potentiometer U4, the fourteenth pin of the counting chip U9, and the output end of the operational amplifier U10; the third pin is connected to the first pin of the multiplexing chip U7, the twelfth pin of the multiplexing chip U7, one end of the resistor R9, and the end of the voltage control signal J1_7; the seventh pin is connected to the seventh pin of the digital potentiometer U4, the seventh pin of the digital potentiometer U5, the ninth pin of the counting chip U9, and one end of the resistor R11; the third pin of the digital potentiometer U4 is connected to the fifth pin of the digital potentiometer U5, the sixth pin of the digital potentiometer U5, the twelfth pin of the multiplexing chip U8, and the end of the voltage control signal J1_6; the second pin of the digital potentiometer U5 is connected to the output end of the operational amplifier U6, and the third pin, the other end of the resistor R9, one end of the switch SW2 are connected to the power supply; the in-phase end of the operational amplifier U6 is connected to the thirteenth pin of the multiplexing chip U7, and the inverting end is connected to the thirteenth pin of the multiplexing chip U8; The third pin of chip U7 is connected to the in-phase end of operational amplifier U10, the fourth pin is connected to the flow sampling signal J1_5 end, the ninth pin and the tenth pin are respectively connected to the ninth pin of multiplexing chip U8, the tenth pin of multiplexing chip U8, the eleventh pin of counting chip U9, the fifteenth pin of counting chip U9, one end of resistor R10, and the other end of switch SW2, the eleventh pin is connected to the first pin of multiplexing chip U8, the fourth pin of multiplexing chip U8, and the single control flow signal J1_2 end; the third pin of multiplexing chip U8 is connected to the inverting end of operational amplifier U10, and the eleventh pin is connected to the flow sampling signal J1_4 end; the fifth pin of digital potentiometer U3, the sixth pin of digital potentiometer U3, the fifth pin of digital potentiometer U4, the sixth pin of digital potentiometer U4, the sixth pin of multiplexing chip U7, the sixth pin of multiplexing chip U8, the thirteenth pin of counting chip U9, the other end of resistor R10, the other end of resistor R11 and the ground end are connected.

[0024] like Figure 3 As shown, specifically, a converter is also included, and the converter includes a plurality of digital potentiometers, a plurality of operational amplifiers, a plurality of resistors, and an inverter;

[0025] The second pin of the digital potentiometer U11 in the plurality of triggers is connected to the output end of the inverter U13, the third pin and the third pin of the digital potentiometer U15 are connected to the power supply, the fifth pin and the sixth pin are connected to the third pin of the digital potentiometer U12, the fifth pin of the digital potentiometer U12, and the in-phase end of the operational amplifier U14, the seventh pin is connected to the seventh pin of the digital potentiometer U12, the seventh pin of the digital potentiometer U15, the seventh pin of the digital potentiometer U17, and the output end of the operational amplifier U20; the second pin of the digital potentiometer U12 is connected to the input end of the inverter U13, the output end of the operational amplifier U14, the second pin of the digital potentiometer U15, and the second pin of the digital potentiometer U17; the inverting end of the operational amplifier U14 is connected to the output end of the operational amplifier U16, the in-phase end of the operational amplifier U20, and one end of the resistor R14 ; The fifth pin and the sixth pin of the digital potentiometer U15 are connected to the inverting end of the operational amplifier U19 and one end of the resistor R12; the inverting end of the operational amplifier U16 is connected to one end of the resistor R13 and the other end of the resistor R14; the third pin and the fifth pin of the digital potentiometer U17 are connected to the total flow voltage reference signal J1_3, and the sixth pin is connected to the inverting end of the operational amplifier U18 and one end of the resistor R15; the output end of the operational amplifier U18 is connected to the other end of the resistor R15 and the single control flow signal J1_2; the output end of the operational amplifier U19 is connected to the other end of the resistor R12 and the other end of the resistor R13; the inverting end of the operational amplifier U20 is connected to the quantity feedback signal J1_1; the sixth pin of the digital potentiometer U12, the in-phase end of the operational amplifier U16, the in-phase end of the operational amplifier U18, the in-phase end of the operational amplifier U19 and the ground are connected.

[0026] like Figure 1 As shown, specifically, it also includes a sampling detector, which includes a plurality of operational amplifiers, a plurality of diodes, a plurality of resistors, a plurality of resistors, and a dip switch;

[0027] The in-phase end of the operational amplifier U1 in the plurality of operational amplifiers is connected to one end of the resistor R1 and one end of the resistor R2, the inverting end is connected to one end of the resistor R3, and the output end is connected to the other end of the resistor R3 and the cathodes of the diodes D1 to D8; the in-phase end of the operational amplifier U2 is connected to one end of the resistor R6, the inverting end is connected to one end of the resistor R5 and the parallel end of the ninth pin to the sixteenth pin of the resistor RN3, the output end is connected to one end of the resistor R4, the other end of the resistor R5, and one end of the resistor R7; one end of the resistor R1 and the ninth pin of the dip switch SW1 are connected to the power supply; the other end of the resistor R7 and one end of the resistor R8 are connected to the end of the quantity feedback signal J1_1; the dip switch SW The first pin to the eighth pin of the resistor RN1 are respectively connected to the sixteenth pin to the ninth pin of the resistor RN1; the first pin to the fourth pin of the resistor RN1 are respectively connected to the first pin to the fourth pin of the resistor RN2, the first pin to the fourth pin of the resistor RN3, and the anodes of the diodes D5 to D8, and the fifth pin to the eighth pin are respectively connected to the fifth pin to the eighth pin of the resistor RN2, the fifth pin to the eighth pin of the resistor RN3, and the anodes of the diodes D1 to D4; the other end of the resistor R2, the other end of the resistor R4, the other end of the resistor R6, the other end of the resistor R8, the parallel end of the ninth pin to the sixteenth pin of the resistor RN2 and the ground are connected.

[0028] Specifically, it also includes a flow sensor, which is used to sample a flow signal.

[0029] like Figure 4 As shown, specifically, it also includes a signal voltage regulator, and the signal voltage regulator includes a potentiometer and a resistor;

[0030] One end of the potentiometer RV2 is connected to the power supply, and the other end is connected to the tap end, one end of the resistor R17, and the total flow voltage reference signal J1_3; the other end of the resistor R17 is connected to the ground end, and the voltage regulator is used to generate the J1_3 signal.

[0031] Specifically, it also includes a voltage-controlled oscillator, the input end of the voltage-controlled oscillator is connected to the voltage-controlled signal J1_6 and the voltage-controlled signal J1_7, and the output end is connected to the centrifugal pump.

[0032] Specifically, it also includes a flow sensor and a DAC chip. The flow sensor samples the output flow of the centrifugal pump and feeds it back to the DAC to convert it into an analog signal and feed it back to J1_4 and J1_5.

[0033] Working principle of the invention

[0034] In the attached figure, J1_1 is a quantity feedback signal, J1_2 is a single control flow signal, J1_3 is a total flow voltage reference signal, J1_4 and J1_5 are flow sampling signals of a single centrifugal pump in each group of centrifugal pumps, J1_6 and J1_7 are voltage control signals, and the voltage control signal is used to feed back to the centrifugal pump to generate a pulse signal. When the centrifugal pump controller is not integrated, it is transferred through an external voltage-controlled oscillator and then fed back to the centrifugal pump controller. The voltage-controlled oscillator is not shown in the attached figure. The control process in the newly built water system is to first detect the number of centrifugal pumps through a sampling detector and send a J1_1 signal to the converter. The converter generates J1_2 to the synchronous and asynchronous controller through the J1_3 signal and the J1_1 signal. The synchronous and asynchronous controller generates different J1_6 and j1_7 to the centrifugal pump according to the J1_4 and J1_5 signals, and performs fine-tuning in the process until the control parameters are automatically reset after shutdown. When docking and controlling with the existing water system, the device corresponding to the output signal is replaced according to the existing signal, and the voltage control signal is output by the synchronous and asynchronous controller.

[0035] See attached Figure 1 The function of the sampling detector is to sample the number of connected centrifugal pumps, where the signal sampling must first be performed through the connection switch or the plug-in terminal. The attached figure shows an 8-input sampling detection circuit. The sampling is performed by selecting the number of centrifugal pumps to be started through the dip switch. The circuit generates the reference voltage required by the lower circuit according to the number. The specific principle is that the input of the dip switch SW1 is connected to the power supply. After the dip switch SW1 is turned on, the signal first passes through the resistor RN2 and the ground loop, and then passes through the diode D1 to the diode D8 to feedback to the output end of the operational amplifier U1. The resistor R1 and the resistor R2 sets the clamping voltage and feeds back to the cathodes of diodes D1 to D8 via the operational amplifier U1 and the resistor R3 follower circuit. The purpose is to allow diodes D1 to D8 to clamp the voltage to an integer when they are turned on and then input to the inverting terminal of the operational amplifier U2 through the resistor RN3. The voltage is equal to the diode conduction voltage drop plus the voltage divided by resistors R1 and R2. Resistors R5 and R4 are used in the negative feedback loop of the operational amplifier U2. The in-phase terminal of the operational amplifier U2 is grounded via resistor R6, outputs a corresponding quantity voltage, and feeds back the quantity signal J1_1 to the converter after being divided by resistors R7 and R8.

[0036] See attached Figure 3The function of the converter is to convert the quantity signal J1_1 and the total flow voltage reference signal J1_3 into different single control flow signals J1_2 to provide a control basis for the synchronous and asynchronous regulator. First, the corresponding resistance conversion must be performed after different signal inputs. Considering the different conversion coefficients, it is impossible to obtain the corresponding resistance value when the coefficients are different by simply changing the voltage division of the resistor. For example, a 5V power supply U is used to supply power in series to two resistors K1 and K2 with the same resistance value. The voltage at the connection end of the resistors K1 and K2 is U / 2=2.5V(Z). Assuming that the total resistance in K2 is The resistance value corresponds to 10 connected centrifugal pumps, then K1 / 10=Y. The resistance value represents the number of centrifugal pumps connected, and its voltage should be Z / Y=L. If the number of connected centrifugal pumps is 2, the corresponding resistance value should be 2Y, and the voltage dividing point should be 2L. Assuming that K1 and K2 resistors are 10K resistors, 2X is 2K, and 2L is 0.5V. However, when only K2 is adjusted to 2Y, that is, 2K, its corresponding voltage dividing point is U / (K1+K2)*2Y=0.83V, which is inconsistent with the required 2L voltage, and its voltage dividing point is 1 at 3K.15V, which is different from the voltage at 2K. The voltage dividing points corresponding to resistors with different coefficients are different. Therefore, it is necessary to solve the voltage conversion when different coefficient resistors are needed, which is also the resistance conversion at different voltages. The signal J1_1 fed back by the sampling detector is input to the inverting end of the operational amplifier U20, and the output end of the operational amplifier U20 outputs the start signal to the 7 pins of the digital potentiometer U11 and the digital potentiometer U12. The digital potentiometer U11 and the digital potentiometer U12 are started, and the operational amplifier U14 samples the 5 pins of the digital potentiometer U11. The voltage of the pin J1_1 is connected to the 3-pin connection terminal of the digital potentiometer U12 and compared and then fed back to the 2-pin of the inverter U13, the digital potentiometer U15 and the digital potentiometer U17. The inverter U13 inverts the signal output by the operational amplifier U14 and then sends it to the 2-pin of the digital potentiometer U11. The digital potentiometer U15 converts the voltage of the signal J1_1 into the resistance value corresponding to the signal parameter. The digital potentiometer U11 and the digital potentiometer U12 balance the different coefficients during the conversion process. The purpose is to make the digital potentiometer U11 and the digital potentiometer U12 balance the different coefficients. The digital potentiometer U12 performs resistance hedging to keep the voltage parameter input to the in-phase terminal of the operational amplifier U14 unchanged. While the digital potentiometer U12 is being regulated, the digital potentiometer U15 is also regulated synchronously. The resistance coefficient of the digital potentiometer U15 is changed, and one path is fed back to the inverting terminal of the operational amplifier U19, and the other path is fed back to the output terminal of the operational amplifier U19 through the resistor R12, and its resistance coefficient is converted into a voltage of the corresponding coefficient. Because it outputs a negative voltage, it is then converted into a positive voltage by the output terminal of the operational amplifier U19, the resistor R13, the resistor R14, etc. and input to the operational amplifier U19. Op amp U16, which then outputs to the in-phase terminal of op amp U20 for comparison and verification with the signal of J1_1. When op amp U20 outputs a signal, the 7 pins of digital potentiometers U11, U12, U15, and U17 become low-level cutoff states. Digital potentiometer U17 completes resistance synchronization based on the regulation of digital potentiometer U15, and then op amp U18 and resistor R15 negatively feedback the output to J1_2 to complete the conversion of different coefficients, and J1_2 then feeds back to the synchronous and asynchronous regulator. .

[0037] See attached Figure 2The function of the synchronous and asynchronous regulator is to balance the output flow of the centrifugal pumps in different groups during operation to ensure consistent pressure heads. This requires generating different pressure control signals based on the flow difference and J1_2. The counting chip U9 outputs a reset signal in the initial state and when the centrifugal pump is stopped after operation. The purpose of the reset is to re-parameterize the centrifugal pump when it is started for the second time, and to avoid the mismatch of parameters when the centrifugal pump is replaced. The operational amplifier U6, digital potentiometer U5, and digital potentiometer U4 form an asynchronous control area, the operational amplifier U10, digital potentiometer U3, and resistor R9 form a synchronous control area, the switch SW2 is the start signal input, and the multiplexing chip U7 and the multiplexing chip U8 are used to switch the reset and start signals. The specific principle is that when the switch SW2 is in the off state, the multiplexing chip U7 and the multiplexing chip U8 output the 12-pin signal to the 13-pin, and output the 1-pin signal to the 3-pin. The 12-pin of the multiplexing chip U8 is used to sample the voltage at the connection end of the digital potentiometer U5 and the digital potentiometer U4, and is fed back to the inverting end of the operational amplifier U6 through the 13-pin. The 1-pin of the multiplexing chip U8 is the single-ended control signal of J1_2 and is fed back to the inverting end of the operational amplifier U10. At this time, the voltage of J1_2 approaches zero. The 12-pin and 1-pin of the multiplexing chip U7 sample the voltage at the connection end of the resistor R9 and the digital potentiometer U3 and feed it back to the in-phase end of the operational amplifier U6 and the in-phase end of the operational amplifier U10. The operational amplifier U10 outputs a high level when it is initially powered on, and the digital potentiometer U3 The direction of the 5th pin of the digital potentiometer U3 changes from the 3rd pin, and the digital potentiometer U3 changes to a low-impedance state. The voltage of the 3rd pin connection end of the resistor R9 and the digital potentiometer U3 is pulled down. At the same time, the adjustment of the operational amplifier U10 is synchronized to the digital potentiometer U4. As the digital potentiometer U4 enters the low-impedance process, the operational amplifier U6 outputs a signal opposite to that of the operational amplifier U10 to the 2nd pin of the digital potentiometer U5 for asynchronous regulation. At this time, the direction of the 5th pin of the digital potentiometer U5 changes from the 6th pin, and the digital potentiometer U5 turns to a high-impedance state. As the regulation is carried out, when the voltage of the connection end of the resistor R9 and the digital potentiometer U3 changes to J1_2, the operational amplifier U10 changes from a high level to a low level and repeats. The signal is fed back to the 14th pin of the counting chip U9, and Q0 to Q8 of the counting chip U9 correspond to The pin polling output, the purpose of the over-bit output is that when the centrifugal pump is not in the initial power-on state, that is, in the start-stop stage, the output of the operational amplifier U10 will be opposite to the initial power-on output state, and the counting chip U9 is a rising edge output, so the over-bit is performed. At this time, when the 9th pin corresponding to the field effect tube Q8 of the counting chip U9 outputs, the signal is fed back to the 7th pin of the digital potentiometer U3, the digital potentiometer U4, and the digital potentiometer U5. The digital potentiometer U3, the digital potentiometer U4, and the digital potentiometer U5 stop. When the switch SW2 is closed, the 9th and 10th pins of the multiplexing chip U7 and the multiplexing chip U8 are in a high level state, and the multiplexing chip U7 and the multiplexing chip U8 input the 11th pin to the 13th pin, and output the 4th pin to the 3rd pin.Pins 13 and 3 are fed back to the correspondingly connected op amps U6 and U10. At this time, the in-phase end of op amp U6 is the J1_2 signal, the inverting end of op amp U6 is the J1_4 flow sampling signal, the in-phase end of op amp U10 is the J1_5 flow sampling signal, and the inverting end of op amp U10 is the J1_2 signal. Op amp U10 performs the first step on digital potentiometers U3 and U4. After digital potentiometers U3 and U4 change from low resistance to high resistance, op amp U6 reversely controls digital potentiometer U5 from high resistance to low resistance. At the same time, the voltage-controlled signals of J1_6 and J1_7 are sent to the centrifugal pump controller or voltage-controlled oscillator to generate Pulse signal, after the centrifugal pump starts, the flow rate rises. When J1_5 reaches J1_2, the operational amplifier U10 is cut off. When J1_4 is higher than J1_2, the operational amplifier U6 adjusts the digital potentiometer U5 again to make a reverse change, and changes the current resistance state to a high resistance state so that J1_6 and J1_7 output different voltage control signals to balance the output flow of centrifugal pumps of different models, and provide real-time feedback for fine-tuning during the output process. The signals output by J1_6 and J1_7 can be input to the centrifugal pump through an RC delay device or a timing circuit at startup. The attached figure does not show this, so as to avoid the cross-pressure change of the operational amplifier U6 when it is not followed up, causing instantaneous flow imbalance. The synchronous area in the synchronous and asynchronous regulator is composed of centrifugal pumps of the same model or consistent characteristic curve that are first or in large numbers, and the pressure control signal is output by J1_7, while the asynchronous area is composed of centrifugal pumps of the same model or consistent characteristic curve that are replaced or in small numbers, and the pressure control signal is output by J1_6. , Figure 4 It is a signal regulator used to input the J1_3 signal.

[0038] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations within the meaning and scope of the equivalent elements of the claims be included in the invention. Any marking in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A centrifugal pump flow control circuit, characterized in that: It includes a synchronous and asynchronous regulator, which includes a number of digital potentiometers, a number of operational amplifiers, a number of multiplexing chips, a number of resistors, a counting chip, and a switch; The second pin of the digital potentiometer U3 in the said several digital potentiometers is connected to the second pin of the digital potentiometer U4, the fourteenth pin of the counting chip U9, and the output end of the operational amplifier U10; the third pin is connected to the first pin of the multiplexing chip U7, the twelfth pin of the multiplexing chip U7, one end of the resistor R9, and the end of the voltage control signal J1_7; the seventh pin is connected to the seventh pin of the digital potentiometer U4, the seventh pin of the digital potentiometer U5, the ninth pin of the counting chip U9, and one end of the resistor R11; the third pin of the digital potentiometer U4 is connected to the fifth pin of the digital potentiometer U5, the sixth pin of the digital potentiometer U5, the twelfth pin of the multiplexing chip U8, and the end of the voltage control signal J1_6; the second pin of the digital potentiometer U5 is connected to the output end of the operational amplifier U6, and the third pin, the other end of the resistor R9, one end of the switch SW2 are connected to the power supply; the in-phase end of the operational amplifier U6 is connected to the thirteenth pin of the multiplexing chip U7, and the inverting end is connected to the thirteenth pin of the multiplexing chip U8; The third pin of chip U7 is connected to the in-phase end of operational amplifier U10, the fourth pin is connected to the flow sampling signal J1_5 end, the ninth pin and the tenth pin are respectively connected to the ninth pin of multiplexing chip U8, the tenth pin of multiplexing chip U8, the eleventh pin of counting chip U9, the fifteenth pin of counting chip U9, one end of resistor R10, and the other end of switch SW2, the eleventh pin is connected to the first pin of multiplexing chip U8, the fourth pin of multiplexing chip U8, and the single control flow signal J1_2 end; the third pin of multiplexing chip U8 is connected to the inverting end of operational amplifier U10, and the eleventh pin is connected to the flow sampling signal J1_4 end; the fifth pin of digital potentiometer U3, the sixth pin of digital potentiometer U3, the fifth pin of digital potentiometer U4, the sixth pin of digital potentiometer U4, the sixth pin of multiplexing chip U7, the sixth pin of multiplexing chip U8, the thirteenth pin of counting chip U9, the other end of resistor R10, the other end of resistor R11 and the ground end are connected.

2. The centrifugal pump flow control circuit according to claim 1, characterized in that: Also included is a converter, which includes a number of digital potentiometers, a number of operational amplifiers, a number of resistors, and an inverter; The second pin of the digital potentiometer U11 in the plurality of triggers is connected to the output end of the inverter U13, the third pin and the third pin of the digital potentiometer U15 are connected to the power supply, the fifth pin and the sixth pin are connected to the third pin of the digital potentiometer U12, the fifth pin of the digital potentiometer U12, and the in-phase end of the operational amplifier U14, the seventh pin is connected to the seventh pin of the digital potentiometer U12, the seventh pin of the digital potentiometer U15, the seventh pin of the digital potentiometer U17, and the output end of the operational amplifier U20; the second pin of the digital potentiometer U12 is connected to the input end of the inverter U13, the output end of the operational amplifier U14, the second pin of the digital potentiometer U15, and the second pin of the digital potentiometer U17; the inverting end of the operational amplifier U14 is connected to the output end of the operational amplifier U16, the in-phase end of the operational amplifier U20, and one end of the resistor R14 ; The fifth pin and the sixth pin of the digital potentiometer U15 are connected to the inverting end of the operational amplifier U19 and one end of the resistor R12; the inverting end of the operational amplifier U16 is connected to one end of the resistor R13 and the other end of the resistor R14; the third pin and the fifth pin of the digital potentiometer U17 are connected to the total flow voltage reference signal J1_3, and the sixth pin is connected to the inverting end of the operational amplifier U18 and one end of the resistor R15; the output end of the operational amplifier U18 is connected to the other end of the resistor R15 and the single control flow signal J1_2; the output end of the operational amplifier U19 is connected to the other end of the resistor R12 and the other end of the resistor R13; the inverting end of the operational amplifier U20 is connected to the quantity feedback signal J1_1; the sixth pin of the digital potentiometer U12, the in-phase end of the operational amplifier U16, the in-phase end of the operational amplifier U18, the in-phase end of the operational amplifier U19 and the ground are connected.

3. The centrifugal pump flow control circuit according to claim 2, characterized in that: It also includes a sampling detector, which includes a plurality of operational amplifiers, a plurality of diodes, a plurality of resistors, a plurality of resistors, and a DIP switch; The operational amplifier U1 among the plurality of operational amplifiers is connected at its in-phase end to one end of the resistor R1 and one end of the resistor R2, at its inverting end to one end of the resistor R3, and at its output end to the other end of the resistor R3 and the cathodes of the diodes D1 to D8; The in-phase end of the operational amplifier U2 is connected to one end of the resistor R6, the inverting end is connected to one end of the resistor R5 and the parallel end of the ninth pin to the sixteenth pin of the resistor RN3, the output end is connected to one end of the resistor R4, the other end of the resistor R5, and one end of the resistor R7; one end of the resistor R1, the ninth pin of the dip switch SW1 and the power supply are connected; the other end of the resistor R7, one end of the resistor R8 and the end of the quantity feedback signal J1_1 are connected; the first pin to the eighth pin of the dip switch SW1 are respectively connected to the sixteenth pin to the ninth pin of the resistor RN1; the resistor RN1 is connected to the ninth pin of the resistor RN1; The first pin to the fourth pin are respectively connected to the first pin to the fourth pin of the resistor RN2, the first pin to the fourth pin of the resistor RN3, and the anodes of the diodes D5 to D8, and the fifth pin to the eighth pin are respectively connected to the fifth pin to the eighth pin of the resistor RN2, the fifth pin to the eighth pin of the resistor RN3, and the anodes of the diodes D1 to D4; the other end of the resistor R2, the other end of the resistor R4, the other end of the resistor R6, the other end of the resistor R8, the parallel end of the ninth pin to the sixteenth pin of the resistor RN2 and the ground terminal are connected.

4. The centrifugal pump flow control circuit according to claim 1, characterized in that: A flow sensor is also included, and the flow sensor is used to sample a flow signal.

5. The centrifugal pump flow control circuit according to claim 2, characterized in that: It also includes a signal voltage regulator, which includes a potentiometer and a resistor; One end of the potentiometer RV2 is connected to the power supply, and the other end is connected to the tap end, one end of the resistor R17, and the total flow voltage reference signal J1_3 end; the other end of the resistor R17 is connected to the ground end.

6. The centrifugal pump flow control circuit according to claim 1, characterized in that: It also includes a voltage-controlled oscillator, whose input end is connected to the voltage-controlled signal J1_6 and the voltage-controlled signal J1_7, and whose output end is connected to the centrifugal pump.

7. The centrifugal pump flow control circuit according to claim 2, characterized in that: It also includes a flow sensor and a DAC chip. The flow sensor samples the output flow of the centrifugal pump and feeds it back to the DAC to convert it into an analog signal and feed it back to J1_4 and J1_5.

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