Electromagnetic capacitance bimodal intelligent defect detection system based on FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor)

Abstract

The invention discloses an electromagnetic capacitance bimodal intelligent defect detection system based on an FPGA and a DSP, and relates to the technical field of defect detection, the detection system comprises a digital control and signal processing module, an AC signal excitation module, an EMT induction signal conditioning module, an ECT induction signal conditioning module, a communication module, a man-machine interaction module and a power supply management module. The detection system realizes electromagnetic capacitance dual-mode detection through cooperative work of the FPGA and the DSP. The detection system adopts an excitation frequency of 30kHz, and an induction signal of the electromagnetic sensor is processed through instrument amplification, low-pass filtering, secondary amplification and the like; the detection system adopts 200kHz excitation frequency and processes output signals of the capacitive sensor through charge amplification, low-pass filtering, secondary amplification and the like. The detection system can realize high-precision detection of tiny defects in metal, nonmetal and composite materials, and visual display of measurement results is realized through the upper computer.

Description

Technical Field

[0001] The invention relates to the technical field of defect detection, in particular to an electromagnetic capacitance dual-mode intelligent defect detection system based on FPGA and DSP. Background Art

[0002] With the increasing requirements for product quality and safety in industrial manufacturing, aerospace, energy and other fields, defect detection technology plays an increasingly important role in these industries. Especially in the non-destructive detection of surface and internal defects of various industrial products such as metal materials and composite materials, the combination of electromagnetic and capacitive technology, as an emerging detection method, has been widely used in the detection of complex structures and materials. However, the existing electromagnetic and capacitive defect detection systems still have certain bottlenecks in terms of accuracy, response speed, processing capacity and multi-channel data processing.

[0003] Traditional electromagnetic or capacitive induction detection systems usually rely on a single signal processing method or a simple hardware architecture, which makes it difficult for the system to meet the real-time and high-precision requirements when facing high-frequency signal processing, large data collection, and real-time processing of multiple sensor signals. Moreover, since the signals generated by various sensors have different characteristics, it is difficult for a single signal conditioning module to efficiently process electromagnetic induction signals and capacitive induction signals at the same time, resulting in insufficient robustness of the detection system in complex environments.

[0004] In order to overcome these technical challenges, designing an intelligent measurement system that can efficiently process multiple types of signals simultaneously has become the focus of current technical research. Existing signal measurement systems generally face the difficulties of real-time conditioning of multi-channel sensor signals, complex signal processing, and accurate defect identification. Therefore, how to design an integrated, flexible and efficient signal measurement system has become the key to improving the performance of electromagnetic and capacitive dual-modal defect detection technology. Summary of the invention

[0005] In order to overcome the defects in the above-mentioned prior art, the present invention provides an electromagnetic capacitance dual-modal intelligent defect detection system based on FPGA and DSP to improve the signal processing accuracy and efficiency, thereby realizing efficient and reliable defect detection.

[0006] To achieve the above object, the present invention adopts the following technical solutions, including:

[0007] An electromagnetic capacitance dual-mode intelligent defect detection system based on FPGA and DSP, comprising: a digital control and signal processing module, an AC signal excitation module, an EMT induction signal conditioning module, an ECT induction signal conditioning module, and a communication module;

[0008] The digital control and signal processing module realizes the collection and processing of different types of signals by configuring the collaborative work of DSP and FPGA;

[0009] The AC signal excitation module is used to provide excitation signals for the electromagnetic sensor and the capacitive sensor, drive the sensor to work and provide accurate signal input;

[0010] The EMT induction signal conditioning module receives the electromagnetic signal from the electromagnetic sensor, i.e., the EMT sensor, and after filtering, amplification and preprocessing, sends the signal to the digital control and signal processing module;

[0011] The ECT sensing signal conditioning module receives the capacitance signal from the capacitance sensor, i.e., the ECT sensor, amplifies and filters the signal, and then sends the signal to the digital control and signal processing module;

[0012] The communication module is used to transmit the detection results and real-time signals to the host computer.

[0013] Preferably, the digital control and signal processing module includes DSP, FPGA, and clock, reset and JTAG interface circuits;

[0014] DSP and FPGA work together to form the control and signal processing core of the system; FPGA controls the AC signal excitation module to provide the required AC excitation signal to the electromagnetic sensor and the capacitive sensor, and receives the digital signal output by the ADC at the end of the EMT and ECT induction signal conditioning modules, and sends the data to DSP through the UPP protocol for FFT transformation and fractional frequency interpolation. The average value of the maximum value in the calculation result is used as the signal reflecting the defect being tested, and finally output through the communication module;

[0015] The clock, reset and JTAG interface circuits provide the DSP with clock signals, reset signals and program download and debug interfaces.

[0016] Preferably, the AC signal excitation module is composed of a two-way output digital-to-analog converter, i.e., a DAC, a transimpedance amplifier, and a single-ended to differential circuit;

[0017] For EMT sensors, the FPGA in the digital control and signal processing module generates digital signals through the DDS IP core, and transmits the digital signals to the DAC through the four-way SPI protocol driver interface to generate analog current signals, which are then converted into analog voltage signals through a transimpedance amplifier. Finally, a differential signal is generated through a single-ended to differential circuit and transmitted to the excitation coil of the EMT sensor.

[0018] For the ECT sensor, the FPGA in the digital control and signal processing module generates digital signals through the DDS IP core, and transmits the digital signals to the DAC through the four-way SPI protocol driver interface to generate analog current signals, which are then converted into analog voltage signals through a transimpedance amplifier and finally transmitted to the excitation electrode of the ECT sensor.

[0019] Preferably, the EMT sensing signal conditioning module is composed of at least 8 completely identical signal conditioning channels, each signal conditioning channel includes a front-end instrument amplifier circuit, a bandpass filter circuit, a secondary amplifier circuit and an analog-to-digital conversion circuit connected in sequence;

[0020] The differential sensing signal of the EMT sensor is first amplified by the instrument amplifier circuit and converted into a single-ended analog signal, then filtered out the clutter by the bandpass filter circuit, and then amplified 8 times by the secondary amplifier circuit and converted into a differential analog signal at the same time. The 8-channel EMT differential analog signal is collected by the analog-to-digital conversion circuit in turn, converted into a digital signal, and transmitted to the FPGA through the ADC_M driver module in the FPGA in the digital control and signal processing module.

[0021] Preferably, the ECT induction signal conditioning module is composed of at least 8 completely identical signal conditioning channels, each signal conditioning channel includes: a front-end charge amplifier circuit, a low-pass filter circuit, a secondary amplifier circuit and an analog-to-digital conversion circuit;

[0022] The sensing signal of the ECT sensor is first converted into voltage and amplified by the charge amplifier circuit, then filtered out the noise by the low-pass filter circuit, and then amplified 8 times by the secondary amplifier circuit and converted into differential analog signals at the same time. The 8-channel ECT differential analog signals are collected by the analog-to-digital conversion circuit in turn, converted into digital signals, and transmitted to the FPGA through the ADC_C driver module in the FPGA in the digital control and signal processing module.

[0023] Preferably, the communication module consists of a serial port to USB circuit and a host computer port, which is connected to the asynchronous serial communication interface SCI of the DSP in the digital control and signal processing module to convert the logic level of the DSP serial communication signal into a USB signal to realize the interaction between the system and the host computer.

[0024] Preferably, the system further comprises a human-computer interaction module;

[0025] The human-computer interaction module consists of buttons and LED indicator lights;

[0026] The buttons are connected to the DSP pins in the digital control and signal processing module, wherein the button connected to the RESET# pin has a reset function, and the remaining buttons set external interrupts through the Xbar module in the DSP, and by customizing the interrupt function in the DSP, the remaining buttons respectively realize software reset, mode selection and system startup functions;

[0027] The LED indicators are used to display the hardware and software status of the signal measurement system, including 5V and 3.3V power indicator lights, DSP and FPGA program normal operation indicator lights, EMTECT mode selection indicator lights, program ready indicator lights, work start indicator lights, operation completion indicator lights, and output error indicator lights.

[0028] Preferably, the system further comprises a power management module;

[0029] The power management module consists of a power port, a DCDC converter, and a linear regulator, and is used to convert the externally provided +15V DC power into analog power +12V, -12V, +5V, -5V and digital power 5V, 3.3V_FPGA, 3.3V_DSP, 1.8V, 1.2V, 1V required for the operation of each module of the system;

[0030] The power port includes two terminals for connecting to an externally powered +15V DC power supply and its reference ground;

[0031] DCDC converter DV1 is used to convert the external +15V DC power supply into a digital power supply 5V; the four-channel DCDC converter DV2 is used to convert the digital power supply 5V into the digital power supplies 3.3V, 1.8V and 1V required by the FPGA; the low-voltage dropout linear regulator DV3 is used to convert the digital power supply 5V into the digital power supply 3.3V_DSP required by the DSP; the DCDC converter DV4 is used to convert the digital power supply 3.3V_DSP into the digital power supply 1.2V required by the DSP;

[0032] The DCDC converter DV5 is used to convert the externally provided +15V DC power supply into a +12V DC power supply; the DCDC converter DV7 is used to convert the +12V DC power supply into a -5V DC power supply;

[0033] The DCDC converter DV6 is used to convert an externally provided +15V DC power supply into a +5V DC power supply; the DCDC converter DV8 is used to convert a +5V DC power supply into a -12V DC power supply.

[0034] The present invention also provides an electromagnetic capacitor dual-mode intelligent defect detection method based on FPGA and DSP. Using the above-mentioned electromagnetic capacitor dual-mode intelligent defect detection system based on FPGA and DSP, the defect detection method is as follows:

[0035] S1, first initialize the DSP and FPGA. For DSP, it mainly includes system clock management initialization, UPP initialization, GPIO initialization, FFT initialization, UART initialization and allowing FPGA to reset for a short time; for FPGA, during the reset period, it mainly completes the initialization of DDS IP core, SDRAM IP core, ADC driver initialization, DAC driver initialization and UPP driver initialization;

[0036] S2, after the DSP and FPGA are initialized or a test is completed, the system automatically clears various flags and data spaces, selects the corresponding test method according to the material to be tested, and enters the waiting state, waiting for the test to start;

[0037] S3, when the preparation work is completed, start the test.

[0038] If the EMT detection mode is selected, the system will perform the following operations: the DDS IP core of the FPGA generates a 30kHz digital signal, transmits the digital signal to the DAC through the four-way SPI protocol driver interface, and enables the hardware circuit to generate a 30kHz differential analog signal to drive the excitation coil of the EMT sensor; then, the FPGA controls the ADC at the end of the electromagnetic detection channel to start sampling, receives the sampling results, and transmits the results to the DSP through the UPP protocol;

[0039] If the ECT detection mode is selected, the system will perform the following operations: the DDS IP core of the FPGA generates a 200kHz digital signal, transmits the digital signal to the DAC through the four-way SPI protocol driver interface, and enables the hardware circuit to generate a 200kHz analog signal to drive the excitation electrode of the ECT sensor; then, the FPGA controls the ADC at the end of the capacitance detection channel to start sampling, receives the sampling results, and transmits the results to the DSP through the UPP protocol;

[0040] S4, when DSP receives data from FPGA, it will process it:

[0041] First, multiple FFT operations are performed on 32768 data in groups of 1024 data. Each FFT result will be corrected for frequency resolution, and finally an amplitude of 30kHz or 200kHz is obtained.

[0042] Next, the average of the maximum values ​​in multiple FFT results is calculated and used as the measurement data reflecting the defect size;

[0043] S5, after the digital signal processing is completed, the DSP sends the result to the host computer through the SCI protocol, and clears various flags and data spaces, waiting for the next detection.

[0044] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the steps of the above-mentioned electromagnetic capacitance dual-modal intelligent defect detection method based on FPGA and DSP are implemented.

[0045] The advantages of the present invention are:

[0046] (1) The present invention provides an electromagnetic capacitance dual-modal intelligent defect detection system based on FPGA and DSP, which aims to solve the problems of insufficient signal processing capability, slow system response, inability to efficiently process multi-channel signals, inability to simultaneously detect materials with multiple properties, etc. in the prior art, improve the signal processing accuracy and efficiency, and thus achieve efficient and reliable defect detection.

[0047] (2) The present invention combines electromagnetic and capacitive dual-modal signal acquisition and processing technology, fully utilizes the advantages of different signal sources in defect detection, can provide more accurate and stable detection results, solves the limitations of single-modal detection methods, and can provide high-precision and high-efficiency signal measurement in a variety of working environments. It is widely used in the field of non-destructive testing.

[0048] (3) The present invention adopts a signal processing architecture based on the collaborative work of DSP and FPGA, combined with an efficient FFT (Fast Fourier Transform) algorithm, which can not only realize rapid processing and analysis of signals, but also meet the needs of large-scale data transmission and high-frequency measurement.

[0049] (4) Through the collaborative processing of FPGA and DSP, the detection signal can be processed in real time and efficiently to meet the needs of high-precision and high-speed industrial detection.

[0050] (5) The system of the present invention can detect tiny defects in metals, non-metals and composite materials with high precision. The system includes a hardware system and a software method, and can measure at least 8 EMT / ECT sensor signals with high precision.

[0051] (6) The human-computer interaction module of the system provides an intuitive display and control interface that is simple to operate and user-friendly. It can provide real-time feedback on detection results and alarm information, thereby improving operational efficiency and safety. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 It is a system hardware block diagram of the present invention.

[0053] Figure 2 This is the schematic diagram of the excitation signal output circuit.

[0054] Figure 3 It is a schematic diagram of a single-ended to differential circuit of the present invention.

[0055] Figure 4This is a schematic diagram of an instrument amplifier circuit and a bandpass filter circuit for the i-th measurement channel of the electromagnetic detection coil of the present invention, where i=1, 2, 3, ..., 8.

[0056] Figure 5 It is a schematic diagram of a charge amplification circuit and a low-pass filter circuit of the i-th measurement channel of the capacitance detection electrode of the present invention, where i=1, 2, 3, ..., 8.

[0057] Figure 6 It is the principle diagram of ADC with 8 input channels of the present invention.

[0058] Figure 7 It is a schematic diagram of a serial port to USB circuit of the present invention.

[0059] Figure 8 It is a topological structure diagram of the power management module of the present invention.

[0060] Fig. 9 It is a signal processing flow chart of the present invention. DETAILED DESCRIPTION

[0061] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] Depend on Figure 1 As shown, an electromagnetic capacitance dual-mode intelligent defect detection system based on FPGA and DSP includes: a digital control and signal processing module, an AC signal excitation module, an EMT induction signal conditioning module, an ECT induction signal conditioning module, a human-computer interaction module, a communication module and a power management module.

[0063] The digital control and signal processing module includes a digital signal processor (DSP) TMS320F28379D, a field programmable gate array (FPGA) XC7A100T and its clock, reset and JTAG interface circuits. The DSP and FPGA work together to form the control and signal processing core of the system, in which the DSP is the main control chip. The clock, reset and JTAG interface circuits provide the DSP with clock signals, reset signals and program download and debugging interfaces. The module meets the computational requirements of the system excitation frequency and real-time processing of multi-channel sensor signals. The digital control and signal processing module provides the required AC excitation signal to the electromagnetic sensor and the capacitive sensor by controlling the AC signal excitation module, and controls the EMT and ECT induction signal conditioning modules to condition the induction output signals of the sensors. The FPGA receives the digital signals output by the ADC at the end of these signal conditioning modules, and sends the data to the DSP for FFT processing through the UPP protocol. Each channel of the two signal conditioning modules outputs 32768 16-bit digital signals to the FPGA each time. The FPGA transmits the data to the DSP through 128 UPP transmissions (512 bytes each time). The DSP performs FFT transformation on 1024-point data (shifted right by 10 points each time), performs 3174 FFT transformations in total, and performs fractional frequency interpolation. The average value of the maximum value in the calculation result is used as a signal reflecting the defect being tested, and is finally output through the communication module. In addition, the digital control and signal processing module also responds to the operation instructions of the human-computer interaction module and the communication module to set the corresponding working mode.

[0064] The AC signal excitation module is composed of a two-way output digital-to-analog converter (DAC), a transimpedance amplifier and a single-ended to differential circuit. For the EMT sensor, the FPGA in the digital control and signal processing module generates a 30KHz digital signal through the DDS IP core, and transmits the digital signal to the DAC through a four-way SPI protocol driver interface to generate a 30KHz analog current signal, which is then converted into a 30KHz analog voltage signal through a transimpedance amplifier, and finally a differential signal is generated through a single-ended to differential circuit and transmitted to the excitation coil of the EMT sensor; for the ECT sensor, the FPGA in the digital control and signal processing module generates a 200KHz digital signal through the DDS IP core, and transmits the digital signal to the DAC through a four-way SPI protocol driver interface to generate a 200KHz analog current signal, which is then converted into a 200KHz analog voltage signal through a transimpedance amplifier, and finally transmitted to the excitation electrode of the ECT sensor.

[0065] The EMT sensing signal conditioning module is composed of at least 8 completely identical signal conditioning channels (the number of channels can be increased by multiplexing data lines), and each signal conditioning channel includes: a front-end instrument amplifier circuit, a bandpass filter circuit, a secondary amplifier circuit and an analog-to-digital conversion circuit (ADC); the differential sensing signal of the EMT sensor is first amplified 8000 times by the instrument amplifier circuit, converted into a single-ended analog signal, and then filtered out clutter by the bandpass filter circuit, and then amplified 8 times by the secondary amplifier circuit and converted into a differential analog signal at the same time. The 8 EMT differential analog signals are collected by the ADC in turn, converted into digital signals, and transmitted to the FPGA through the ADC_M driver module in the FPGA in the digital control and signal processing module.

[0066] The ECT sensing signal conditioning module is composed of at least 8 completely identical signal conditioning channels (the number of channels can be increased by multiplexing data lines), and each signal conditioning channel includes: a front-end charge amplifier circuit, a low-pass filter circuit, a secondary amplifier circuit and an analog-to-digital conversion circuit (ADC); the sensing signal of the ECT sensor is first converted into a voltage and amplified by the charge amplifier circuit, and then filtered out clutter by the low-pass filter circuit, and then amplified by 8 times by the secondary amplifier circuit, and converted into a differential analog signal at the same time. The 8 ECT differential analog signals are collected by the ADC in turn, converted into digital signals, and transmitted to the FPGA through the ADC_C driver module in the FPGA in the digital control and signal processing module.

[0067] The human-computer interaction module consists of buttons and LED indicator lights; the buttons are connected to the DSP pins in the digital control and signal processing module, wherein the button connected to the RESET# pin has a reset function, and the remaining buttons set external interrupts through the Xbar module in the DSP, and by customizing the interrupt function in the DSP, the remaining buttons respectively realize software reset, mode selection and system startup functions; the LED indicator lights are used to display the hardware and software status of the signal measurement system, including 5V and 3.3V power indicator lights, DSP and FPGA program normal operation indicator lights, EMTECT mode selection indicator lights, program ready indicator lights, work start indicator lights, operation completion indicator lights, and output error indicator lights.

[0068] The communication module is composed of a serial port to USB circuit and a host computer port, and is connected to the asynchronous serial communication interface SCI of the digital signal processor DSP to convert the logic level of the DSP serial communication signal into a USB signal, thereby realizing the interaction between the system and the host computer.

[0069] The power management module is composed of a power port, a DCDC converter DV1, a DCDC converter DV2, a linear regulator DV3, a linear regulator DV4, a linear regulator DV5, and a dual-channel low-dropout linear regulator DV6, and is used to convert an externally provided +15V DC power supply into analog power supplies +12V, -12V, +5V, -5V and digital power supplies 5V, 3.3V_FPGA, 3.3V_DSP, 1.8V, 1.2V, and 1V required for the operation of each module of the system; the power port includes two wiring terminals for connecting an externally supplied +15V DC power supply and its reference ground; the DCDC converter DV1 is used to convert an externally provided +15V DC power supply into a digital power supply 5V; the four-channel DCDC converter DV2 Used to convert the digital power supply 5V into the digital power supplies 3.3V, 1.8V and 1V required by FPGA; the low voltage difference linear regulator DV3 is used to convert the digital power supply 5V into the digital power supply 3.3V_DSP required by DSP; the DCDC converter DV4 is used to convert the digital power supply 3.3V_DSP into the digital power supply 1.2V required by DSP; the DCDC converter DV5 is used to convert the externally provided +15V DC power supply into a +12V DC power supply; the DCDC converter DV6 is used to convert the externally provided +15V DC power supply into a +5V DC power supply; the DCDC converter DV7 is used to convert the +12V DC power supply into a -5V DC power supply; the DCDC converter DV8 is used to convert the +5V DC power supply into a -12V DC power supply.

[0070] In this embodiment, the digital control and signal processing module is responsible for selecting the appropriate detection method according to the signal type and detection requirements, and performing signal processing and analysis according to the selected detection method. Specifically, the digital control and signal processing module realizes the collection, filtering, amplification and processing of different types of signals (such as electromagnetic signals and capacitive signals) by configuring the collaborative work of DSP and FPGA according to the selected detection method; the AC signal excitation module is used to provide the necessary excitation signal for the EMT and ECT sensors. By generating a stable AC signal, driving the sensor to work and providing accurate signal input, the module can provide excitation signals of different frequencies and amplitudes according to different sensor requirements to ensure the quality and stability of the detection signal; the EMT induction signal conditioning module receives the signal from the electromagnetic sensor, and after filtering, amplification and preprocessing, sends the signal to the digital control and signal processing module; the ECT induction signal conditioning module receives the signal from the capacitive sensor, amplifies and filters the signal, and sends the signal to the digital control and signal processing module; the human-computer interaction module includes LED lights and operation buttons, which help users monitor the detection process in real time by displaying the detection results, system status, alarm information, etc. In addition, users can set detection parameters, start / stop detection, switch working modes, etc. through operation buttons; the communication module is used to transmit detection results and real-time signals to the host computer. The power management module selects, reduces voltage and filters ripples from two external power supplies, and generates constant current output to provide energy for the system.

[0071] See also Figure 2 The excitation signal output circuit of the same EMT detection method and ECT detection method includes a DAC chip AD3552r and a transimpedance amplifier chip AD8066. For the EMT sensor, the FPGA in the digital control and signal processing module generates a 30KHz digital signal through the DDS IP core, and transmits the digital signal to the DAC through a four-way SPI protocol driver interface to generate a 30KHz analog current signal, which is then converted into a 30KHz analog voltage signal through a transimpedance amplifier; for the ECT sensor, the FPGA in the digital control and signal processing module generates a 200KHz digital signal through the DDS IP core, and transmits the digital signal to the DAC through a four-way SPI protocol driver interface to generate a 200KHz analog current signal, which is then converted into a 200KHz analog voltage signal through a transimpedance amplifier and finally transmitted to the excitation electrode of the ECT sensor. The RFBx_1 pin of the DAC determines the output signal amplitude. When the RFB4_1 pin is connected, the output signal amplitude range is positive and negative 10V.

[0072] See also Figure 3The single-ended to differential circuit is used many times in the present invention. The conversion chip is LTC6373, and its A0, A1, and A2 pins determine the circuit output amplification factor, and the back end is connected to the RC low-pass filter circuit. When working in the excitation circuit, A0 and A1 are connected to a low level, and A2 is connected to a high level. At this time, the amplification factor is 1, that is, it is only used as a single-ended to differential circuit, without amplification, and converts the single-ended electromagnetic excitation signal into a differential signal, thereby connecting to the two ends of the electromagnetic excitation coil. When working in the electromagnetic and capacitance detection channel, A2 and A1 are connected to a low level, and A0 is connected to a high level. This amplification factor is 8, that is, while converting the single-ended detection signal into a differential signal, the signal is amplified 8 times and then connected to the input pin of the ADC.

[0073] See also Figure 4 , the instrument amplifier circuit and bandpass filter circuit of the electromagnetic detection coil measurement channel are equipped with a differential RC low-pass filter circuit at the front end, which can effectively filter out high-frequency noise and ensure the purity and stability of the signal. The electromagnetic detection coil measurement channel of the present invention uses the INA849 instrument amplifier as the front-end signal amplification part. The INA849 is an ultra-low noise instrument amplifier that uses super β input transistors, has an ultra-low input voltage noise of 1nV / √Hz and a low input bias current of up to 20nA, and the gain is set to 8000 times to ensure that weak electromagnetic signals can be effectively amplified. After amplification, the signal will enter the second-order Chebyshev bandpass filter circuit to further filter out the frequency band near 30kHz. The operational amplifier uses OPA1655, which can achieve a low voltage noise density of 2.9nV / √Hz and a current noise density of 6fA / √Hz, which can reduce the noise to an extremely low level, remove low-frequency and high-frequency interference noise, and provide higher quality signals for subsequent processing. The entire system design supports multi-channel parallel operation, and each channel operates independently, which can efficiently and accurately perform real-time detection and analysis of electromagnetic signals.

[0074] See also Figure 5In the design of the charge amplifier circuit and bandpass filter circuit of the capacitance detection plate measurement channel, a protection resistor R97 is provided at the front end to ensure the purity and stability of the signal. The charge amplifier circuit uses the operational amplifier OPA627 and adopts advanced precision FET transistors, which can achieve extremely low input bias current without affecting the input voltage noise performance. Through the unique cascade circuit design, the circuit maintains a low input bias current of 5pA under a wide range of input common-mode voltages, thereby ensuring that the weak charge signal can be effectively converted into a voltage signal. The amplified signal will enter the second-order Butterworth low-pass filter circuit. The operational amplifier uses OPA827, which has a low bias current of 3pA and a gain-bandwidth product of 22MHz, ensuring that high-frequency interference noise above 1MHz is effectively filtered out for subsequent processing. The entire system design supports multi-channel parallel operation, and each channel operates independently, thereby achieving efficient and accurate real-time detection and analysis of capacitance signals.

[0075] See also Figure 6 The ADC chip selected by the present invention is AD7606C, which is an analog-to-digital converter with high-precision and multi-channel parallel sampling capabilities. AD7606C can support a maximum sampling rate of 1MSPS, and has 8 independent channels, which can sample multiple signal sources at the same time, greatly improving the real-time data processing capability of the system. The input buffer of the chip has a minimum analog input impedance of 1MΩ, which can effectively match the previous signal source, ensuring that even in the case of a high impedance source, there will be no significant attenuation or distortion of the sampled signal, ensuring the accuracy and stability of the signal. In addition, AD7606C also has a high bandwidth option of 220kHz, which can support wide-band signal sampling and adapt to high-frequency application requirements. This high-bandwidth feature enables the system to collect more complex dynamic signals, and performs well in various high-frequency changing electromagnetic field detections, ensuring that the time domain and frequency domain information of the signal are not lost. The simultaneous sampling and high-speed conversion capabilities of AD7606C give it a significant advantage in multi-channel data acquisition systems, and are particularly suitable for high-precision application scenarios that require synchronous sampling and processing of multiple channels. Its low power consumption design also contributes to the stability and reliability of the system in long-term operation. Overall, the performance characteristics of AD7606C provide efficient and accurate data acquisition support for the detection module of the present invention, meeting the technical requirements of multi-channel synchronization, fast response and high-bandwidth processing.

[0076] See also Figure 7, the serial port to USB chip selected by the present invention is FT232RN, which is a powerful USB to serial port interface converter, which can convert the serial signal transmitted by the digital signal processor (DSP) through the asynchronous serial communication interface (SCI) into a standard USB signal, thereby realizing the data interaction between the system and the host computer. The FT232RN chip has a built-in full-function USB interface, supports the USB 2.0 high-speed standard, and converts the TTL logic level of the DSP into the differential signal of the USB through its internal conversion circuit, ensuring the signal integrity and reliability during the data transmission process. Through the connection of FT232RN with the host computer, the system can realize real-time data interaction with the PC-side application software. The host computer can communicate bidirectionally with the embedded system through the USB port to perform data monitoring, real-time analysis and configuration parameter adjustment. The USB interface not only realizes fast and stable data transmission, but also greatly simplifies the connection between the system and the host computer, avoiding the limitations of the traditional serial port interface, such as short transmission distance and complex connection. The use of the FT232RN chip makes the entire system have higher compatibility and longer communication distance in the communication process with the host computer, and is easy to install and intuitive to operate. In addition, since the USB interface is widely supported in computers and embedded systems, the versatility and expansibility of the system are further improved, making the present invention applicable to more diverse application scenarios.

[0077] See also Figure 8The power management module consists of a power port, a DCDC converter DV1, a DCDC converter DV2, a linear regulator DV3, a linear regulator DV4, a linear regulator DV5, and a dual-channel low-dropout linear regulator DV6. It is used to convert the externally provided +15V DC power supply into analog power supplies +12V, -12V, +5V, -5V and digital power supplies 5V, 3.3V_FPGA, 3.3V_DSP, 1.8V, 1.2V, and 1V required for the operation of each module of the system. Among them, 3.3V_FPGA and 1.2V are DSP working power supplies, and 3.3V_FPGA, 1.8V, and 1V are FPGA working power supplies; the power port includes two wiring terminals for connecting to an externally supplied +15V DC power supply and its reference ground; the DCDC converter DV1 is used to convert the externally provided +15V DC power supply into analog power supplies +12V, -12V, +5V, and -5V, and digital power supplies 5V, 3.3V_FPGA, 3.3V_DSP, 1.8V, 1.2V, and 1V. The four-channel DCDC converter DV2 is used to convert the digital power supply 5V into the digital power supplies 3.3V, 1.8V and 1V required by the FPGA; the low-voltage difference linear regulator DV3 is used to convert the digital power supply 5V into the digital power supply 3.3V_DSP required by the DSP; the DCDC converter DV4 is used to convert the digital power supply 3.3V_DSP into the digital power supply 1.2V required by the DSP; the DCDC converter DV5 is used to convert the externally provided +15V DC power supply into a +12V DC power supply; the DCDC converter DV6 is used to convert the externally provided +15V DC power supply into a +5V DC power supply; the DCDC converter DV7 is used to convert the +12V DC power supply into a -5V DC power supply; and the DCDC converter DV8 is used to convert the +5V DC power supply into a -12V DC power supply.

[0078] See also Fig. 9 The main program software flow of the system of the present invention is a cyclic program. After the system is powered on, the main program automatically runs, performs initialization and corresponding processing operations, and waits for response interrupts. The basic processing flow is as follows:

[0079] S1, first initialize the DSP and FPGA, and configure each required module. For DSP, it mainly includes system clock management initialization, UPP initialization, GPIO initialization, FFT initialization, UART initialization, and allowing FPGA to reset for a short time; for FPGA, during the reset period, it mainly completes the operations such as DDS IP core initialization, SDRAM IP core initialization, ADC driver initialization, DAC driver initialization and UPP driver initialization.

[0080] S2, then, after the DSP and FPGA are initialized or a test is completed, the system will automatically clear various flags and data spaces, and manually select the corresponding test method according to the material to be tested, enter the waiting state, and wait for the test to start.

[0081] S3, when the preparation is completed and the start detection button is pressed,

[0082] If the EMT detection mode is selected, the system will perform the following operations: the DDS IP core of the FPGA generates a 30kHz digital signal, transmits the digital signal to the DAC through the four-way SPI protocol driver interface, and enables the hardware circuit to generate a 30kHz differential analog signal to drive the excitation coil of the EMT sensor. Subsequently, the FPGA controls the ADC at the end of the electromagnetic detection channel to start sampling, receives the sampling results, and transmits the results to the DSP through the UPP protocol.

[0083] If the ECT detection mode is selected, the system will perform the following operations: the DDS IP core of the FPGA generates a 200kHz digital signal, transmits the digital signal to the DAC through the four-way SPI protocol driver interface, and enables the hardware circuit to generate a 200kHz analog signal to drive the excitation electrode of the ECT sensor. Subsequently, the FPGA controls the ADC at the end of the capacitance detection channel to start sampling, receives the sampling results, and transmits the results to the DSP through the UPP protocol.

[0084] S4, when DSP receives data from FPGA, it will process it: first, multiple FFT operations are performed in groups of 1024 data among 32768 data. Each FFT result will be corrected for frequency resolution to improve accuracy, and finally an amplitude of 30kHz (EMT) or 200kHz (ECT) is obtained. Then, the average value of the maximum value in multiple FFT results is calculated and used as the measurement data reflecting the defect size.

[0085] S5, after the digital signal processing is completed, the DSP sends the result to the host computer through the SCI protocol, and clears various flags and data spaces, waiting for the next detection.

[0086] The system of the present invention can detect tiny defects in metal, non-metal and composite materials with high precision. The system includes a hardware system and a software method, and can measure at least 8 EMT / ECT sensor signals with high precision.

[0087] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An electromagnetic capacitance dual-mode intelligent defect detection system based on FPGA and DSP, characterized in that: include: Digital control and signal processing module, AC signal excitation module, EMT induction signal conditioning module, ECT induction signal conditioning module, communication module; The digital control and signal processing module realizes the collection and processing of different types of signals by configuring the collaborative work of DSP and FPGA; The AC signal excitation module is used to provide excitation signals for the electromagnetic sensor and the capacitive sensor, drive the sensor to work and provide accurate signal input; The EMT induction signal conditioning module receives the electromagnetic signal from the electromagnetic sensor, i.e., the EMT sensor, and after filtering, amplification and preprocessing, sends the signal to the digital control and signal processing module; The ECT sensing signal conditioning module receives the capacitance signal from the capacitance sensor, i.e., the ECT sensor, amplifies and filters the signal, and then sends the signal to the digital control and signal processing module; The communication module is used to transmit the detection results and real-time signals to the host computer.

2. The electromagnetic capacitance dual-mode intelligent defect detection system based on FPGA and DSP according to claim 1 is characterized in that: The digital control and signal processing module includes DSP, FPGA, and clock, reset and JTAG interface circuits; DSP and FPGA work together to form the control and signal processing core of the system; FPGA controls the AC signal excitation module to provide the required AC excitation signal to the electromagnetic sensor and the capacitive sensor, and receives the digital signal output by the ADC at the end of the EMT and ECT induction signal conditioning modules, and sends the data to DSP through the UPP protocol for FFT transformation and fractional frequency interpolation. The average value of the maximum value in the calculation result is used as the signal reflecting the defect being tested, and finally output through the communication module; The clock, reset and JTAG interface circuits provide the DSP with clock signals, reset signals and program download and debug interfaces.

3. The electromagnetic capacitance dual-mode intelligent defect detection system based on FPGA and DSP according to claim 1 is characterized in that: The AC signal excitation module is composed of a two-way output digital-to-analog converter, i.e., a DAC, a transimpedance amplifier, and a single-ended to differential circuit; For EMT sensors, the FPGA in the digital control and signal processing module generates digital signals through the DDS IP core, and transmits the digital signals to the DAC through the four-way SPI protocol driver interface to generate analog current signals, which are then converted into analog voltage signals through a transimpedance amplifier. Finally, a differential signal is generated through a single-ended to differential circuit and transmitted to the excitation coil of the EMT sensor. For the ECT sensor, the FPGA in the digital control and signal processing module generates digital signals through the DDS IP core, and transmits the digital signals to the DAC through the four-way SPI protocol driver interface to generate analog current signals, which are then converted into analog voltage signals through a transimpedance amplifier and finally transmitted to the excitation electrode of the ECT sensor.

4. The electromagnetic capacitance dual-mode intelligent defect detection system based on FPGA and DSP according to claim 1 is characterized in that: The EMT induction signal conditioning module is composed of at least 8 identical signal conditioning channels, each of which includes a front-end instrument amplifier circuit, a bandpass filter circuit, a secondary amplifier circuit and an analog-to-digital conversion circuit connected in sequence; The differential sensing signal of the EMT sensor is first amplified by the instrument amplifier circuit and converted into a single-ended analog signal, then filtered out the clutter by the bandpass filter circuit, and then amplified 8 times by the secondary amplifier circuit and converted into a differential analog signal at the same time. The 8-channel EMT differential analog signal is collected by the analog-to-digital conversion circuit in turn, converted into a digital signal, and transmitted to the FPGA through the ADC_M driver module in the FPGA in the digital control and signal processing module.

5. The electromagnetic capacitance dual-mode intelligent defect detection system based on FPGA and DSP according to claim 1 is characterized in that: The ECT induction signal conditioning module is composed of at least 8 identical signal conditioning channels, each of which includes: a front-end charge amplifier circuit, a low-pass filter circuit, a secondary amplifier circuit and an analog-to-digital conversion circuit; The sensing signal of the ECT sensor is first converted into voltage and amplified by the charge amplifier circuit, then filtered out the noise by the low-pass filter circuit, and then amplified 8 times by the secondary amplifier circuit and converted into differential analog signals at the same time. The 8-channel ECT differential analog signals are collected by the analog-to-digital conversion circuit in turn, converted into digital signals, and transmitted to the FPGA through the ADC_C driver module in the FPGA in the digital control and signal processing module.

6. The electromagnetic capacitance dual-mode intelligent defect detection system based on FPGA and DSP according to claim 1 is characterized in that: The communication module consists of a serial port to USB circuit and a host computer port, which is connected to the asynchronous serial communication interface SCI of the DSP in the digital control and signal processing module, converts the logic level of the DSP serial communication signal into a USB signal, and realizes the interaction between the system and the host computer.

7. The electromagnetic capacitance dual-mode intelligent defect detection system based on FPGA and DSP according to claim 1 is characterized in that: The system also includes a human-computer interaction module; The human-computer interaction module consists of buttons and LED indicator lights; The buttons are connected to the DSP pins in the digital control and signal processing module, wherein the button connected to the RESET# pin has a reset function, and the remaining buttons set external interrupts through the Xbar module in the DSP, and by customizing the interrupt function in the DSP, the remaining buttons respectively realize software reset, mode selection and system startup functions; The LED indicators are used to display the hardware and software status of the signal measurement system, including 5V and 3.3V power indicator lights, DSP and FPGA program normal operation indicator lights, EMTECT mode selection indicator lights, program ready indicator lights, work start indicator lights, operation completion indicator lights, and output error indicator lights.

8. The electromagnetic capacitance dual-mode intelligent defect detection system based on FPGA and DSP according to claim 1 is characterized in that: The system also includes a power management module; The power management module consists of a power port, a DCDC converter, and a linear regulator, and is used to convert the externally provided +15V DC power into analog power +12V, -12V, +5V, -5V and digital power 5V, 3.3V_FPGA, 3.3V_DSP, 1.8V, 1.2V, 1V required for the operation of each module of the system; The power port includes two terminals for connecting to an externally powered +15V DC power supply and its reference ground; DCDC converter DV1 is used to convert the external +15V DC power supply into a digital power supply 5V; the four-channel DCDC converter DV2 is used to convert the digital power supply 5V into the digital power supplies 3.3V, 1.8V and 1V required by the FPGA; the low-voltage dropout linear regulator DV3 is used to convert the digital power supply 5V into the digital power supply 3.3V_DSP required by the DSP; the DCDC converter DV4 is used to convert the digital power supply 3.3V_DSP into the digital power supply 1.2V required by the DSP; The DCDC converter DV5 is used to convert the externally provided +15V DC power supply into a +12V DC power supply; the DCDC converter DV7 is used to convert the +12V DC power supply into a -5V DC power supply; The DCDC converter DV6 is used to convert an externally provided +15V DC power supply into a +5V DC power supply; the DCDC converter DV8 is used to convert a +5V DC power supply into a -12V DC power supply.

9. An electromagnetic capacitance dual-mode intelligent defect detection method based on FPGA and DSP, characterized in that: Using the electromagnetic capacitance dual-mode intelligent defect detection system based on FPGA and DSP as described in any one of claims 1 to 8, the defect detection method is as follows: S1, first initialize the DSP and FPGA. For DSP, it mainly includes system clock management initialization, UPP initialization, GPIO initialization, FFT initialization, UART initialization and allowing FPGA to reset for a short time; for FPGA, during the reset period, it mainly completes the initialization of DDS IP core, SDRAM IP core, ADC driver initialization, DAC driver initialization and UPP driver initialization; S2, after the DSP and FPGA are initialized or a test is completed, the system automatically clears various flags and data spaces, selects the corresponding test method according to the material to be tested, and enters the waiting state, waiting for the test to start; S3, when the preparation work is completed, start the test. If the EMT detection mode is selected, the system will perform the following operations: the DDS IP core of the FPGA generates a 30kHz digital signal, transmits the digital signal to the DAC through the four-way SPI protocol driver interface, and enables the hardware circuit to generate a 30kHz differential analog signal to drive the excitation coil of the EMT sensor; Then, the FPGA controls the ADC at the end of the electromagnetic detection channel to start sampling, receives the sampling results, and transmits the results to the DSP through the UPP protocol; If the ECT detection mode is selected, the system will perform the following operations: the DDS IP core of the FPGA generates a 200kHz digital signal, which is transmitted to the DAC through the four-way SPI protocol driver interface, so that the hardware circuit generates a 200kHz analog signal to drive the excitation electrode of the ECT sensor; Then, the FPGA controls the ADC at the end of the capacitance detection channel to start sampling, receives the sampling results, and transmits the results to the DSP through the UPP protocol; S4, when DSP receives data from FPGA, it will process it: First, multiple FFT operations are performed on 32768 data in groups of 1024 data. Each FFT result will be corrected for frequency resolution, and finally an amplitude of 30kHz or 200kHz is obtained. Next, the average of the maximum values ​​in multiple FFT results is calculated and used as the measurement data reflecting the defect size; S5, after the digital signal processing is completed, the DSP sends the result to the host computer through the SCI protocol, and clears various flags and data spaces, waiting for the next detection.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by the processor, the steps of the electromagnetic capacitance dual-modal intelligent defect detection method based on FPGA and DSP as described in claim 9 are implemented.

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