Switching power supply and average current sampling circuit thereof

Abstract

The invention discloses a switching power supply and an average current sampling circuit thereof, and the circuit comprises a real-time current sampling circuit (1) which samples the real-time current flowing through an upper switch (NM1) / lower switch (NM2); a holding signal generation circuit (3) for generating the holding signal at more than half of the time of each conduction period of a first control signal / a second control signal on the basis of the first control signal of the upper switch (NM1) / the second control signal of the lower switch (NM2), the conduction period being a time period in which the control signal controls the corresponding switch to be conducted; the sampling and holding circuit (2) is used for receiving the holding signal and holding and outputting the current sampled by the real-time current sampling circuit (1) at the half conduction period moment; according to the invention, the sampling current is enough for the establishment of the sampling circuit from the inductive current at the beginning of the sampling conduction period to the more than half time of the conduction period, so that the error caused by the establishment time is avoided, and more accurate inductive average current sampling is realized.

Description

Technical Field

[0001] The invention relates to the field of switching power supplies, and in particular to a switching power supply and an average current sampling circuit thereof. Background Art

[0002] During the operation of the switching power supply, it is necessary to sample its output current. For a specific switching power supply architecture, such as a DCDCBUCK controller, the inductor current is the output current, and the sampled average inductor current is the output current. Taking the DCDC BUCK switching power supply controller as an example, its schematic circuit diagram is as follows: Figure 1 As shown. ON In the stage, K1 is closed, K2 is opened, and the current in the inductor L increases. OFF In the first stage, K2 is closed, K1 is disconnected, and the current of the inductor L decreases. The working state of the BUCK switching power supply controller is determined by the output current. From small to large output current, the working states are DCM, BCM, and CCM. The schematic diagram of the inductor current is as follows Figure 2 As shown. In DCM state, at T ON In the first stage, K1 is closed, K2 is opened, and the current of the inductor L rises from 0 to I L1 In T OFF In the stage, K2 is closed, K1 is open, and the current of inductor L changes from I L1 Decreases to 0. T DCM In the BCM state, at T ON In the first stage, K1 is closed, K2 is opened, and the current of the inductor L rises from 0 to I L1 In T OFF In the stage, K2 is closed, K1 is open, and the current of inductor L changes from I L1 Down to 0, T DCM = 0. In CCM state, at T ON In the stage, K1 is closed, K2 is open, and the current of inductor L changes from I L1 Start to rise to I L2 In T OFF In the stage, K2 is closed, K1 is open, and the current of inductor L changes from I L2 Down to I L1 , T DCM =0.

[0003] Currently, the commonly used output current sampling can be achieved through an external current detection resistor, such as Figure 3 As shown. The output current IO is detected by detecting the voltage drop VRs on the resistor Rs. Although this method can directly sample the output current, its disadvantage is that it requires an additional detection resistor Rs and a detection pin to allow the chip to detect the voltage VRs on Rs. The additional pin will reduce the versatility of the chip.

[0004] Another way to sample the output current is by using T ON and T OFF The inductor current is sampled proportionally in each phase, and then the average value of the inductor current is obtained by summing. For the BUCK switching power supply controller, the inductor current is the output current. In actual chip design, K1 will be replaced by PMOS / NMOS. K2 will be replaced by NMOS. The difference between K1 and K2 and the design of the sampling circuit will inevitably lead to deviations in the sampling ratio, resulting in sampling errors. At the same time, the sampling circuit must be used to sample the inductor current at T ON and T OFF Sampling will inevitably have a settling time. The sampled current will further deviate. The sampling diagram is shown in Figure 4 shown.

[0005] The above information disclosed in this Background section is included only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not form the prior art that is currently known to a person of ordinary skill in the art. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a switching power supply and an average current sampling circuit thereof in view of the above-mentioned defects of the prior art.

[0007] The technical solution adopted by the present invention to solve its technical problem is:

[0008] On the one hand, a switching power supply average current sampling circuit is constructed, which includes:

[0009] A real-time current sampling circuit, whose input end is connected to both ends of the upper switch / lower switch of the switching power supply, and is used to sample the real-time current flowing through the upper switch / lower switch;

[0010] a holding signal generating circuit, configured to generate the holding signal at a time when half of each conduction period of the first control signal / the second control signal is exceeded based on the first control signal of the upper switch / the second control signal of the lower switch, wherein the conduction period refers to a time period during which the control signal controls the corresponding switch to be turned on;

[0011] A sampling and holding circuit, whose control end is connected to the holding signal generating circuit, and whose input end is connected to the output end of the real-time current sampling circuit, is used to receive the holding signal to hold and output the current of the upper switch / lower switch at half the conduction cycle moment sampled by the real-time current sampling circuit.

[0012] Furthermore, the average current sampling circuit of the switching power supply described in the present invention also includes a mode detection circuit, whose input end is connected to the output end of the sampling and holding circuit, and is used to output the current held by the sampling and holding circuit during the working time period of the switching cycle of the switching power supply, and output zero current during the non-working time period of the switching cycle of the switching power supply.

[0013] Furthermore, the average current sampling circuit of the switching power supply described in the present invention also includes a current-to-voltage conversion circuit, whose input end is connected to the output end of the mode detection circuit, and is used to convert the current output by the mode detection circuit into a voltage output to the controller of the switching power supply.

[0014] Further, in the switching power supply average current sampling circuit described in the present invention, the real-time current sampling circuit includes a sampling circuit and a current mirror;

[0015] The positive and negative input terminals of the sampling circuit are connected to the two ends of the upper switch / lower switch of the switching power supply, and are used to sample the voltage across the upper switch / lower switch and convert it into a current flowing through the control tube of the current mirror. The mirror tube of the current mirror outputs the current to the sampling and holding circuit.

[0016] Further, in the average current sampling circuit of the switching power supply described in the present invention, the sampling and holding circuit includes a current input circuit, a first switch, a first capacitor, a second switch, a second capacitor, and a current output circuit connected in sequence;

[0017] The current input circuit is used to convert the current output by the real-time current sampling circuit into a first charging voltage to charge the first capacitor; the first switch control end receives a third control signal, and is used to control whether the first charging voltage charges the first capacitor based on the third control signal; the second switch control end receives a fourth control signal, and is used to control whether the first capacitor charges the second capacitor to achieve energy transfer based on the fourth control signal; the current output circuit is used to convert the voltage of the second capacitor into current output.

[0018] Furthermore, in the average current sampling circuit of the switching power supply described in the present invention, the switching cycles of the first switch, the second switch, the upper switch, and the lower switch are the same, the starting time of the conduction cycle of the first switch is synchronized with the starting time of the conduction cycle of the upper switch / lower switch, and the end time corresponds to the time when half of the conduction cycle of the upper switch / lower switch is exceeded, the starting time of the conduction cycle of the second switch lags behind the end time of the conduction cycle of the first switch by a dead zone, and the end time of the conduction cycle of the second switch is synchronized with the end time of the conduction cycle of the upper switch / lower switch.

[0019] Correspondingly, the third control signal, the fourth control signal, the first control signal, and the second control signal all have the same frequency;

[0020] The first level mutation edge of the third control signal is synchronized with the first level mutation edge of the first control signal / the second control signal, and the second level mutation edge of the third control signal is earlier than the second level mutation edge of the first control signal / the second control signal by half a conduction period of the upper switch / the lower switch; the signal between the second level mutation edge and the next first level mutation edge of the third control signal is used as the holding signal;

[0021] The first level mutation edge of the fourth control signal lags behind the second level mutation edge of the third control signal by a dead zone, and the second level mutation edge of the fourth control signal is synchronized with the second level mutation edge of the first control signal / the second control signal;

[0022] The time when the first level sudden change edge and the second level sudden change edge appear are respectively the start time and the end time of the conduction period of the corresponding switch.

[0023] Furthermore, in the switching power supply average current sampling circuit of the present invention, the current input circuit includes a first NMOS tube, whose source is grounded, whose drain is connected to the current output by the real-time current sampling circuit, whose drain is also connected to its gate, whose gate is connected to the positive electrode of the first capacitor via the first switch, and whose negative electrode is grounded;

[0024] The current output circuit includes a second NMOS tube, whose source is grounded, whose drain outputs current, whose gate is connected to the positive electrode of the second capacitor, whose negative electrode is grounded, and whose positive electrode is also connected to the positive electrode of the first capacitor via the second switch.

[0025] Furthermore, in the switching power supply average current sampling circuit of the present invention, the mode detection circuit includes a third switch and a fourth switch, one end of the third switch is connected to the current output by the sampling and holding circuit, one end of the fourth switch is connected to zero current, and the other end of the third switch and the other end of the fourth switch are connected together as the output end of the mode detection circuit;

[0026] The switching cycles of the third switch, the fourth switch, the upper switch and the lower switch are the same. The start time of the conduction cycle of the third switch is synchronized with the start time of the conduction cycle of the upper switch, and the end time corresponds to the end time of the conduction cycle of the lower switch. The switching state of the fourth switch is opposite to that of the third switch.

[0027] The third switch control terminal receives a fifth control signal, and the fourth switch control terminal receives a sixth control signal. The fifth control signal and the sixth control signal have the same frequency as the first control signal and the second control signal. The first level mutation edge of the fifth control signal is synchronized with the first level mutation edge of the first control signal, the second level mutation edge of the fifth control signal is synchronized with the second level mutation edge of the second control signal, the first level mutation edge of the sixth control signal is synchronized with the second level mutation edge of the second control signal, and the second level mutation edge of the sixth control signal is synchronized with the first level mutation edge of the first control signal.

[0028] The time when the first level sudden change edge and the second level sudden change edge appear are respectively the start time and the end time of the conduction period of the corresponding switch.

[0029] Furthermore, in the average current sampling circuit of the switching power supply described in the present invention, the current-to-voltage conversion circuit includes a first resistor, a second resistor and a third capacitor, one end of the first resistor is connected to the current output by the mode detection circuit, and is connected to the positive electrode of the third capacitor via the second resistor, the other end of the first resistor is grounded, the negative electrode of the third capacitor is grounded, and the positive electrode output voltage of the third capacitor is given to the controller of the switching power supply.

[0030] In a second aspect, a switching power supply is constructed, which includes an upper switch and a lower switch connected in series between the positive and negative poles of an input voltage, and an average current sampling circuit as described in any of the preceding items.

[0031] The switching power supply and the average current sampling circuit thereof of the present invention have the following beneficial effects: the present invention utilizes the real-time current sampling circuit to sample the real-time current flowing through the upper switch or the lower switch of the switching power supply, utilizes the sampling and holding circuit to hold the current of the real-time current sampling circuit at the moment when the upper switch or the lower switch is more than halfway through each conduction cycle, and the current at this moment is equivalent to the average inductor current, thereby realizing the sampling of the system inductor average current; the sampling current is sufficient for the establishment of the sampling circuit from the inductor current at the beginning of the sampling conduction cycle to the moment when the conduction cycle is more than halfway through, thereby avoiding the error caused by the establishment time, and realizing more accurate inductor average current sampling. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on the provided drawings without creative work:

[0033] Figure 1 This is a schematic diagram of a BUCK switching power supply controller;

[0034] Figure 2 This is a schematic diagram of the inductor current in different modes of the BUCK switching power supply controller;

[0035] Figure 3 This is a schematic diagram of a sampling scheme for the output current of a BUCK switching power supply controller;

[0036] Figure 4 It is another sampling scheme of the output current of a BUCK switching power supply controller, and a schematic diagram of current sampling in the ON and OFF stages of the switch;

[0037] Figure 5 This is a schematic diagram of a BUCK switching power supply controller;

[0038] Figure 6 This is the DCM inductor current diagram of the BUCK switching power supply controller;

[0039] Figure 7 This is the schematic diagram of the inductor current of the BUCK switching power supply controller BCM;

[0040] Figure 8 This is the CCM inductor current diagram of the BUCK switching power supply controller;

[0041] Fig. 9 It is a circuit principle block diagram of a specific embodiment of the average current sampling circuit of the switching power supply of the present invention;

[0042] Fig.10 It is the circuit structure and functional schematic diagram of the real-time current sampling circuit;

[0043] Fig.11 It is the T generated by the holding signal generating circuit OFF Schematic diagram of voltage waveform of / 2;

[0044] Fig.12 It is the circuit structure and functional diagram of the sample and hold circuit;

[0045] Fig.13 is a circuit schematic diagram of the mode detection circuit and its functional schematic diagram;

[0046] Fig.14 This is a schematic diagram of a current-voltage conversion circuit. DETAILED DESCRIPTION

[0047] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Typical embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solutions of the present application, rather than limitations on the technical solutions of the present application. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0048] Take the BUCK switching power supply as an example. Ideally, the switching cycle of the BUCK switching power supply controller follows the following four formulas:

[0049] T=T ON +T OFF +T DCM .......(1);

[0050] T PWM =T ON +T OFF .......(2);

[0051]

[0052] T represents the switching cycle of the switching power supply, which can also be called the working cycle, which consists of the working time period and the non-working time period. DCM That is, non-working time, T PWM That is, the working time period, T ON is the on-time of the upper switch, T OFF is the conduction period of the lower switch, and the working period is from T ON Start to T OFF End. IN is the input voltage, V OUT is the output voltage.

[0053] In determining T PWM Under the premise of OUT and V IN Decided T ON and T OFF The general idea of ​​the present invention is: by sampling T OFF Stage (or T ON phase) of the real-time inductor current and maintain T OFF / 2 (or T ON / 2 ) to obtain the equivalent average inductor current, thus sampling the average inductor current of the system. Sampling current sampling T OFF (or T ON ) when the inductor current reaches T OFF / 2(or T ON / 2 ) is sufficient to sample the circuit at the right time. This avoids the error caused by the settling time and enables more accurate sampling of the average inductor current.

[0054] The average current sampling circuit of the switching power supply of the present invention takes a DCDC BUCK switching power supply controller as an example. Figure 1 As shown. In actual chip design, K1 will be replaced by PMOS / NMOS. K2 will be replaced by NMOS. In this embodiment, K1 is replaced by NMOSNM1, and D1 is its parasitic substrate diode. K2 is replaced by NMOS NM2, and D2 is its parasitic substrate diode. The schematic diagram is as follows Figure 5 As shown. The BUCK switching power supply controller is based on the load current I O From small to large, they are DCM, BCM, and CCM.

[0055] Working in DCM, control signals of NM1 and NM2 and inductor current I L Waveform Figure 6 As shown. ON In the first stage, NM1 is turned on, NM2 is turned off, and the inductor current increases from 0 to I L1 Generally, in order to avoid NM1 and NM2 being turned on at the same time, causing V IN When NM1 is turned off, NM2 will not turn on immediately, but after a dead time T DE Then turn on NM2. DE In the 2nd stage, both NM1 and NM2 are turned off, and the inductor current flows through D2. DE The design time will be much shorter than T ON / T OFF , we can assume T DE = 0. T OFF In the phase, NM1 is turned off and NM2 is turned on, and the current flows from I L1 drops to 0. At T OFF After the stage, the system will not immediately enter T ON stage, but wait for T DCM Then enter the next T ON . T DCM In the OFF phase, both NM1 and NM2 remain off, and the inductor current is 0. DCM The length depends on the output current I O The output current I O The smaller the T DCM The longer the whole T PWM The average inductor current during the cycle is:

[0056]

[0057] I L1 / 2 is T ON / 2 or T OFF / 2, the inductor current at the moment Figure 6 It can also be intuitively seen that the area of ​​the shaded area is 1 a =1 b , 2 a =2 b , 1 a +2 a +1 c =1 b +2 b +1 c So by sampling T ON / 2 or T OFF The inductor current at the moment T PWM The average inductor current in the entire working cycle is:

[0058]

[0059] As long as you get The relationship between the sampling T ON / 2 or T OFF The inductor current at the moment / 2 can be used to obtain the average inductor current I L_AV .

[0060] Under BCM conditions, the control signal of NM1 / NM2 and the inductor current waveform are as follows: Figure 7 As shown. ON In the first stage, NM1 is turned on, NM2 is turned off, and the inductor current increases from 0 to I L1 Generally, to avoid NM1 / NM2 being turned on at the same time, V IN When NM1 is turned off, NM2 will not turn on immediately, but after a dead time T DE Then turn on NM2. DE In the second stage, NM1 / NM2 are both turned off, and the inductor current flows through D2. OFF In the phase, NM1 is turned off and NM2 is turned on, and the current flows from I L1 Similarly, in order to avoid NM1 / NM2 being turned on at the same time, it is necessary to pass T DE Then enter T ON stage. Generally speaking, T DE The design time will be much shorter than T ON / T OFF In the analysis, it can be assumed that T DE = 0. According to the instructions Figure 7 It can be intuitively obtained that the entire T PWM The average inductor current during the cycle is:

[0061]

[0062] I L1 / 2 is T ON / 2 or T OFF / 2, the inductor current at the moment Figure 7 It can also be intuitively seen that the area of ​​the shaded area is 1 a =1 b , 2 a =2 b , 1 a +2 a +1 c =1 b +2 b +1 c So by sampling T ON / 2 or T OFF The inductor current at the moment T PWM The average inductor current in the entire working cycle is I L1 / 2So by sampling T ON / 2 or T OFF The inductor current at the moment T PWM The average inductor current in the phase, and the average inductor current in the entire working cycle I L_AV For I L1 / 2.

[0063] Under CCM conditions, the control signal of NM1 / NM2 and the inductor current waveform are as follows: Figure 8 As shown. ON In the stage, NM1 is turned on and NM2 is turned off, and the inductor current changes from I L1a Up to I L2 Generally, to avoid NM1 / NM2 being turned on at the same time, V IN When NM1 is turned off, NM2 will not turn on immediately, but after a dead time T DE Then turn on NM2. DE In the second stage, NM1 / NM2 are both turned off, and the inductor current flows through D2. OFF In the phase, NM1 is turned off and NM2 is turned on, and the current flows from I L2 Down to I L1b Similarly, in order to avoid NM1 / NM2 being turned on at the same time, T DE Then enter T ON stage. Generally speaking, T DE The design time will be much shorter than T ON / T OFF In the analysis, it can be assumed that T DE= 0. When the circuit is working stably, T ON Phase I L2 -I L1a The difference is equal to T OFF Phase I L2 -I L1b , that is I L1a =I L1b According to the instructions Figure 8 It can be intuitively obtained that the entire T PWM The average inductor current during the cycle is:

[0064]

[0065] and That is T ON / 2 or T OFF / 2. Figure 8 It can be seen intuitively that the area of ​​the shaded area is 1 a =1 b , 2 a =2 b , 1 a +2 a +1 c =1 b +2 b +1 c So by sampling T ON / 2 or T OFF The inductor current at the moment T PWM The average inductor current in the phase, and the average inductor current in the entire working cycle I L_AV for

[0066] Through the above analysis, for CCM and BCM, only T ON / 2 or T OFF / 2 corresponds to I L The current can directly get the average inductor current I L_AV For DCM, we only need to introduce The average inductor current I in the entire cycle under DCM can be calculated. L_AV . Due to T ON , T OFF , T DCM It is the internal signal of the switching power supply controller, so it can be obtained through a simple circuit.

[0067] refer to Fig. 9 In one specific embodiment, in order to sample Figure 5The average current of the inductor of the BUCK circuit shown in the figure, the average current sampling circuit of this embodiment includes: a real-time current sampling circuit 1, a sampling and holding circuit 2, a holding signal generating circuit 3, a mode detection circuit 4, and a current-voltage conversion circuit 5.

[0068] A real-time current sampling circuit 1, whose input end is connected to both ends of the upper switch (NM1) switch NM1 / lower switch NM2 of the switching power supply, and is used to sample the real-time current flowing through the upper switch NM1 or the lower switch NM2;

[0069] The holding signal generating circuit 3 is used for generating a first control signal based on the first control signal of the upper switch NM1 (reference Figure 6-8 PWM (NM1) signal in) / second control signal of the lower switch NM2 (reference Figure 6-8 PWM (NM2) signal in the first control signal / second control signal), at the half-point of each conduction cycle of the first control signal / second control signal (if it is the first control signal, the half-point of its conduction cycle is T ON / 2 moment; if it is the second control signal, then the moment when the half of its conduction period is T OFF / 2 moment) to generate the holding signal, the on-period refers to the time period during which the control signal controls the corresponding switch to be turned on; reference Figure 6-8 , the conduction period of the first control signal is T ON The conduction period of the second control signal is T OFF stage.

[0070] The sampling and holding circuit 2 has a control end connected to the holding signal generating circuit 3, and an input end connected to the output end of the real-time current sampling circuit 1, and is used to receive the holding signal to hold and output the current at the half-on cycle of the upper switch NM1 / lower switch NM2 sampled by the real-time current sampling circuit 1. The switching cycle of the upper switch NM1 and the lower switch NM2 is consistent with the length of the switching cycle of the switching power supply, and the conduction periods of the upper switch NM1 and the lower switch NM2 are T ON , T OFF .Conduction period T ON From the beginning to the most recent conduction period T OFF End the working period of the switching power supply, the conduction period T OFF After the end of the most recent conduction cycle T ON The non-working time period of the switching power supply begins.

[0071] A mode detection circuit 4, whose input end is connected to the output end of the sample and hold circuit 2, is used to output the current held by the sample and hold circuit 2 during the working time period of the switching cycle of the switching power supply, and output zero current during the non-working time period of the switching cycle of the switching power supply;

[0072] The current-to-voltage conversion circuit 5 has an input end connected to the output end of the mode detection circuit 4 and is used to convert the current output by the mode detection circuit 4 into a voltage and output it to the controller of the switching power supply.

[0073] Taking sampling T OFF Taking the inductor current at the moment / 2 as an example, Fig. 9 In the example, the inductor current I is sampled by the real-time current sampling circuit 1 when NM2 is turned on. L The holding signal generating circuit 3 controls the sampling and holding circuit 2 to sample and hold T OFF I at / 2 moment L The mode detection circuit 4 outputs the T held by the sampling and holding circuit 2 in CCM and BCM. OFF / 2 moment current is directly output, in DCM T ON +T OFF The sample and hold circuit 2 holds T OFF / 2, the current is directly output at T DCM The output current of the stage is 0. Finally, the sampled average current is converted into a voltage output by the current-to-voltage conversion circuit 5. It should be noted that the present invention is applicable to any circuit that needs to sample the average current of the inductor or the output current. Here, the DCDC BUCK switching power supply controller is used as an example for the convenience of description. For T ON / 2, T OFF / 2 detection is equivalent, here only T OFF / 2 detection as an example.

[0074] Each circuit is described below.

[0075] Specifically, refer to Fig.10 In the figure, (a) is a circuit structure diagram, and (b) is a related waveform principle diagram. The real-time current sampling circuit 1 includes a sampling circuit and a current mirror. The sampling circuit functions to sample NM2 at T OFF The inductor current I L_TOFF , get K*I by sampling L_TOFF , where K<1. L_TOFF To K*I L_TOFF This function can be realized by a variety of sampling circuit structures, or similar functions can be realized. This is a mature current sampling technology and will not be described in detail here. The positive and negative input terminals of the sampling circuit are connected to the two ends of the lower switch NM2 of the switching power supply (if sampling T ON / 2 moment current, it is connected to both ends of the upper switch NM1 instead, sampling the voltage across both ends of the lower switch NM2 and converting it into a current flowing through the control tube PM1 of the current mirror, and the mirror tube PM2 of the current mirror outputs current to the sample and hold circuit 2.

[0076] Specifically, refer to Fig.11 , the main function of the signal generating circuit 3 is to generate T OFF / 2 voltage waveform, the T OFF The / 2 waveform is used to control the sample and hold circuit 2. OFF The / 2 waveform is obtained based on the second control signal (i.e., the control signal PWM(NM2) of NM2), specifically, the duty cycle of PWM(NM2) is halved while the start time of the conduction period remains unchanged. This waveform transformation can be achieved through various existing circuit structures, so it will not be explained in detail. In other embodiments, if the T of NM1 is to be sampled, ON / 2, the holding signal generating circuit 3 generates T based on the first control signal PWM (NM1). ON / 2 voltage waveform.

[0077] Specifically, refer to Fig.12 The main function of the sample and hold circuit 2 is to maintain T OFF / 2 current. Fig.12 (a) is a circuit structure diagram, and (b) is a related waveform principle diagram. The sampling and holding circuit 2 includes a current input circuit composed of a first NMOS tube NM3, a first switch S1, a first capacitor C1, a second switch S2, a second capacitor C2, and a current output circuit composed of a second NMOS tube NM4.

[0078] NM3 is connected to the real-time current sampling circuit 1 and the first capacitor C1. Specifically, the source of NM3 is grounded, the drain of NM3 is connected to the current output by the real-time current sampling circuit 1, the drain of NM3 is also connected to its gate, the gate of NM3 is connected to the positive electrode of the first capacitor C1 via the first switch S1, and the negative electrode of the first capacitor C1 is grounded. The source of NM4 is grounded, the drain of NM4 outputs current, the gate of NM4 is connected to the positive electrode of the second capacitor C2, the negative electrode of the second capacitor C2 is grounded, and the positive electrode of the second capacitor C2 is also connected to the positive electrode of the first capacitor C1 via the second switch S2.

[0079] NM3 is used to convert the current output by the real-time current sampling circuit 1 into a first charging voltage to charge the first capacitor C1. Fig.10The current is converted into the gate voltage of NM3 through the current mirror of PM1 and PM2, and the gate voltage is the first charging voltage. The control end of the first switch S1 receives the third control signal PWM (S1), which is used to control whether the first charging voltage charges the first capacitor C1 based on the third control signal PWM (S1); the control end of the second switch S2 receives the fourth control signal PWM (S2), which is used to control whether the first capacitor C1 charges the second capacitor C2 based on the fourth control signal PWM (S2), so as to transfer the energy of the first capacitor C1 to the second capacitor C2. NM4 is used to convert the voltage of the second capacitor C2 into current output.

[0080] The switching cycles of the first switch S1, the second switch S2, the upper switch NM1, and the lower switch NM2 are the same, the start time of the conduction cycle of the first switch S1 is synchronized with the start time of the conduction cycle of the upper switch NM1 / lower switch NM2, and the end time corresponds to the time when the conduction cycle of the upper switch NM1 / lower switch NM2 is more than halfway, the start time of the conduction cycle of the second switch S2 lags behind the end time of the conduction cycle of the first switch S1 by a dead zone, and the end time of the conduction cycle of the second switch S2 is synchronized with the end time of the conduction cycle of the upper switch NM1 / lower switch NM2. It can also be understood that the first switch S1 is turned on in the first half of the conduction cycle of the lower switch NM2, and the second switch S2 is turned on in the second half of the conduction cycle of the lower switch NM2.

[0081] PWM (S1) waveform is as follows Fig.12 As shown in Fig.11 T OFF / 2 voltage waveform, which has the same frequency as the second control signal PWM (NM2), and the first level mutation edge of the third control signal PWM (S1) is synchronized with the first level mutation edge of the second control signal PWM (NM2) (if the T of NM1 is to be sampled ON / 2, the first level mutation edge of the third control signal PWM (S1) is adjusted to be synchronized with the first level mutation edge of the first control signal PWM (NM1), and the second level mutation edge of the third control signal PWM (S1) is earlier than the second level mutation edge of the second control signal PWM (NM2) by half the conduction period T of the lower switch NM2. OFF (Similarly, if you want to sample the T of NM1 ON / 2, the second level mutation edge of the third control signal PWM (S1) should be adjusted to be ahead of the second level mutation edge of the first control signal PWM (NM1) by half the conduction period T of the upper switch NM1. ON ).

[0082] The first level mutation edge and the second level mutation edge appear at the start and end time of the conduction period of the corresponding switch, respectively. In this embodiment, the first level mutation edge is a rising edge, and the second level mutation edge is a falling edge. It can be understood that, depending on the type of switch, the first level mutation edge of the control signal of different switches may be different. For example, for NMOS, the first level mutation edge of its control signal is a rising edge, while for PMOS, the first level mutation edge of the control signal is a falling edge.

[0083] The signal between the second level sudden edge and the next first level sudden edge of the third control signal PWM (S1) is used as the holding signal. During this holding signal period, the first switch S1 is disconnected and the capacitor C1 is no longer charged.

[0084] The fourth control signal is as follows: Fig.12 As shown in the PWM (S2) waveform in FIG, the fourth control signal PWM (S2) has the same frequency as the third control signal PWM (S1), the first level mutation edge of the fourth control signal PWM (S2) lags behind the second level mutation edge of the third control signal PWM (S1) by a dead zone, and the second level mutation edge of the fourth control signal PWM (S2) is synchronized with the second level mutation edge of the second control signal PWM (NM2) (if the T of NM1 is to be sampled). ON / 2, the second level mutation edge of PWM(S2) is synchronized with the second level mutation edge of the first control signal PWM(NM1).

[0085] like Fig.12 , sample and hold circuit 2 samples and holds T OFF / 2, the current flowing through NM3 is K*I L_TOFF , the gate voltage of NM3 directly reflects the size of the sampling current. OFF At the beginning, S1 is open and S2 is closed. When time reaches T OFF At time T / 2, S1 and S2 are closed. At this time, the voltage on capacitor C1 is equal to the voltage of NM3 at T OFF / 2. This voltage directly reflects T OFF K*I at the moment / 2 L_TOFF After a short dead time T DES After that, S1 is closed and S2 is opened, which reduces the voltage V on C1. SAM Transfer to C2. OFF When the falling edge arrives, S1 and S2 are closed. After several cycles of conversion, V SAM =V HOLD , V HOLD Control NM4, at this time NM4 output is T OFF / 2. If the output current IO Changes occur and multiple cycles are required before V HOLD Only then will the latest output current I be updated O The corresponding inductor current value. So V SAM Can reflect the current T in real time OFF cycle of the inductor current. And V HOLD It must go through multiple cycles of conversion to output the corresponding value. This ensures the stability of the sampled value and prevents large fluctuations. The function of the sample-and-hold circuit can be realized through a variety of circuit structures, not limited to Fig.12 The circuit shown.

[0086] Specifically, the mode detection circuit 4 refers to Fig.13 , Fig.13 (a) is a circuit schematic diagram, and (b) is a related waveform schematic diagram. The mode detection circuit 4 includes a third switch S3 and a fourth switch S4. One end of the third switch S3 is connected to the NM4 drain output current of the sampling and holding circuit 2, and one end of the fourth switch S4 is connected to zero current. The other end of the third switch S3 and the other end of the fourth switch S4 are connected together as the output end of the mode detection circuit 4. The switching cycles of the third switch S3, the fourth switch S4, the upper switch NM1, and the lower switch NM2 are the same. The start time of the conduction cycle of the third switch S3 is synchronized with the start time of the conduction cycle of the upper switch NM1, and the end time corresponds to the end time of the conduction cycle of the lower switch NM2. The switch state of the fourth switch S4 is opposite to the switch state of the third switch S3.

[0087] The control end of the third switch S3 receives the fifth control signal PWM (S3), and the control end of the fourth switch S4 receives the sixth control signal PWM (S4). The fifth control signal PWM (S3) and the sixth control signal PWM (S4) are all in the same frequency as the first control signal PWM (NM1) and the second control signal PWM (NM2). The first level mutation edge of the fifth control signal PWM (S3) is synchronized with the first level mutation edge of the first control signal PWM (NM1), the second level mutation edge of the fifth control signal PWM (S3) is synchronized with the second level mutation edge of the second control signal PWM (NM2), the first level mutation edge of the sixth control signal PWM (S4) is synchronized with the second level mutation edge of the second control signal PWM (NM2), and the second level mutation edge of the sixth control signal PWM (S4) is synchronized with the first level mutation edge of the first control signal PWM (NM1). In this embodiment, because the third switch S3 and the fourth switch S4 are of the same type, the fifth control signal PWM (S3) and the sixth control signal PWM (S4) are complementary.

[0088] like Fig.13 , the mode detection circuit 4 functions at TON and T OFF In this stage, S3 is opened and S4 is closed to make the T output of the sampling and holding circuit 2 OFF / 2, the inductor sampling current output, and at T DCM When S3 is closed and S4 is opened, the output current is 0. For BCM and CCM, due to T DCM =0, then directly output T OFF The inductor current is sampled and output at time T / 2. ON and T OFF Phase output T OFF / 2, the inductor sampling current is DCM The output current of the phase is 0. ON , T OFF , T DCM This can be directly obtained in the actual chip circuit. Only simple combinational logic is needed to realize this function.

[0089] Specifically, the current-to-voltage conversion circuit 5 refers to Fig.14 , Fig.14 (a) is a circuit schematic diagram, and (b) is a related waveform schematic diagram. The current-voltage conversion circuit 5 includes a first resistor R SAM , the second resistor R LPF and the third capacitor C LPF , the first resistor R SAM One end of the current is connected to the output of the mode detection circuit 4, and the current is connected to the output of the mode detection circuit 4 through the second resistor R LPF Connect the third capacitor C LPF The positive terminal of the first resistor R SAM The other end of the third capacitor C LPF The negative electrode of the third capacitor C LPF The positive output voltage V AV The sampling result representing the final average current is given to the controller of the switching power supply.

[0090] like Fig.14 The function of the current-to-voltage conversion circuit 5 is to convert the converted current I SAM Through R SAM Converted into voltage V AV For BCM and CCM, I SAM Through R SAM The converted voltage is a DC voltage and does not require filtering. However, in DCM, I SAM Through R SAM The converted voltage is a pulse voltage and must pass through R LPF and C LPF Filter. To get the average value. R LPF and C LPFThe larger the time constant, the smaller the ripple and the closer the output is to the average value. O When the ripple changes, it takes more time to stabilize. The actual circuit design will select a reasonable time constant according to the application requirements. A compromise between ripple and response time is considered.

[0091] It should be noted that the sampling T designed in this embodiment OFF / 2, other embodiments can also be implemented by sampling T ON / 2 time to achieve, need to be selected according to the actual chip application requirements. This embodiment is only a specific circuit requirement, need to convert current into voltage, in other embodiments, the circuit can be increased or decreased according to the demand to achieve other purposes, such as using average current mode control of DCDC, by sampling the average current to calculate the output power, etc.

[0092] In summary, the switching power supply and the average current sampling circuit thereof of the present invention have the following beneficial effects: the present invention utilizes the real-time current sampling circuit to sample the real-time current flowing through the upper switch or the lower switch of the switching power supply, utilizes the sampling and holding circuit to hold the current of the real-time current sampling circuit at the moment when the upper switch or the lower switch is more than halfway through each conduction cycle, and the current at this moment is equivalent to the average inductor current, thereby realizing the sampling of the system inductor average current; the sampling current is sufficient to establish the sampling circuit from the inductor current at the beginning of the sampling conduction cycle to the moment when the conduction cycle is more than halfway through, thereby avoiding the error caused by the establishment time, and realizing more accurate inductor average current sampling.

[0093] It should be noted that the switch in this article includes various equivalent switch electronic devices, not limited to MOS tubes or triodes, etc. The "connected" or "connected" not only includes directly connecting two entities, but also includes indirectly connecting through other entities with beneficial improvement effects.

[0094] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0095] Terms including ordinal numbers such as "first" and "second" used in this specification may be used to describe various components, but these components are not limited by these terms. The purpose of using these terms is only to distinguish one component from other components. For example, without departing from the scope of the present invention, the first component may be named as the second component, and similarly, the second component may also be named as the first component.

[0096] In the specification provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this specification.

[0097] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. Each claim itself may serve as a separate embodiment of the present invention.

[0098] It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. In the claims, any reference symbol between brackets shall not be construed as a limitation of the claims.

[0099] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A switching power supply average current sampling circuit, characterized in that: include: A real-time current sampling circuit (1), whose input end is connected to two ends of an upper switch (NM1) / lower switch (NM2) of a switching power supply, and is used to sample the real-time current flowing through the upper switch (NM1) / lower switch (NM2); A holding signal generating circuit (3) is used to generate the holding signal at a time when half of each conduction period of the first control signal / the second control signal exceeds half of each conduction period of the first control signal / the second control signal based on the first control signal of the upper switch (NM1) / the second control signal of the lower switch (NM2), wherein the conduction period refers to a time period during which the control signal controls the corresponding switch to be turned on; A sampling and holding circuit (2), whose control end is connected to the holding signal generating circuit (3), and whose input end is connected to the output end of the real-time current sampling circuit (1), is used to receive the holding signal to hold and output the current at the half conduction cycle of the upper switch (NM1) / lower switch (NM2) sampled by the real-time current sampling circuit (1).

2. The switching power supply average current sampling circuit according to claim 1, characterized in that: It also includes a mode detection circuit (4), whose input end is connected to the output end of the sampling and holding circuit (2), and is used to output the current held by the sampling and holding circuit (2) during the working time period of the switching cycle of the switching power supply, and output zero current during the non-working time period of the switching cycle of the switching power supply.

3. The switching power supply average current sampling circuit according to claim 2, characterized in that: It also includes a current-voltage conversion circuit (5), whose input end is connected to the output end of the mode detection circuit (4) and is used to convert the current output by the mode detection circuit (4) into a voltage output to the controller of the switching power supply.

4. The switching power supply average current sampling circuit according to claim 1, characterized in that: The real-time current sampling circuit (1) comprises a sampling circuit and a current mirror; The positive and negative input ends of the sampling circuit are connected to the two ends of the upper switch (NM1) / lower switch (NM2) of the switching power supply, and are used to sample the voltage across the upper switch (NM1) / lower switch (NM2) and convert it into a current flowing through the control tube (PM1) of the current mirror, and the mirror tube (PM2) of the current mirror outputs the current to the sampling and holding circuit (2).

5. The switching power supply average current sampling circuit according to claim 1, characterized in that: The sample-and-hold circuit (2) comprises a current input circuit, a first switch (S1), a first capacitor (C1), a second switch (S2), a second capacitor (C2), and a current output circuit which are connected in sequence; The current input circuit is used to convert the current output by the real-time current sampling circuit (1) into a first charging voltage to charge the first capacitor (C1); the first switch (S1) controls whether the first charging voltage charges the first capacitor (C1); the second switch (S2) controls whether the first capacitor (C1) transfers energy to the second capacitor (C2); and the current output circuit is used to convert the voltage of the second capacitor (C2) into a current output.

6. The switching power supply average current sampling circuit according to claim 5, characterized in that: The switching cycles of the first switch (S1), the second switch (S2), the upper switch (NM1), and the lower switch (NM2) are the same; the start time of the conduction cycle of the first switch (S1) is synchronized with the start time of the conduction cycle of the upper switch (NM1) / lower switch (NM2); the end time corresponds to the time when half of the conduction cycle of the upper switch (NM1) / lower switch (NM2) is exceeded; the start time of the conduction cycle of the second switch (S2) lags behind the end time of the conduction cycle of the first switch (S1) by a dead zone; the end time of the conduction cycle of the second switch (S2) is synchronized with the end time of the conduction cycle of the upper switch (NM1) / lower switch (NM2).

7. The switching power supply average current sampling circuit according to claim 6, characterized in that: The current input circuit comprises a first NMOS transistor (NM3), whose source is grounded, whose drain is connected to the current output by the real-time current sampling circuit (1), whose drain is also connected to its gate, whose gate is connected to the positive electrode of the first capacitor (C1) via the first switch (S1), and whose negative electrode is grounded; The current output circuit comprises a second NMOS tube (NM4), whose source is grounded, whose drain outputs current, whose gate is connected to the positive electrode of the second capacitor (C2), whose negative electrode is grounded, and whose positive electrode is also connected to the positive electrode of the first capacitor (C1) via the second switch (S2).

8. The switching power supply average current sampling circuit according to claim 2, characterized in that: The mode detection circuit (4) comprises a third switch (S3) and a fourth switch (S4), one end of the third switch (S3) is connected to the current output by the sample and hold circuit (2), one end of the fourth switch (S4) is connected to zero current, and the other end of the third switch (S3) and the other end of the fourth switch (S4) are connected together as the output end of the mode detection circuit (4); The switching cycles of the third switch (S3), the fourth switch (S4), the upper switch (NM1), and the lower switch (NM2) are the same; the start time of the conduction cycle of the third switch (S3) is synchronized with the start time of the conduction cycle of the upper switch (NM1), and the end time corresponds to the end time of the conduction cycle of the lower switch (NM2); the switching state of the fourth switch (S4) is opposite to the switching state of the third switch (S3).

9. The switching power supply average current sampling circuit according to claim 3, characterized in that: The current-voltage conversion circuit (5) comprises a first resistor (R SAM )、The second resistor (R LPF ) and the third capacitor (C LPF ), the first resistor (R SAM ) is connected to the current output by the mode detection circuit (4), and the current is connected to the current output by the mode detection circuit (4) through the second resistor (R LPF ) connects the third capacitor (C LPF ) is the positive electrode, the first resistor (R SAM ) is grounded, and the other end of the third capacitor (C LPF ) is grounded, and the third capacitor (C LPF )’s positive output voltage is given to the controller of the switching power supply.

10. A switching power supply, characterized in that: It comprises an upper switch (NM1) and a lower switch (NM2) which are connected in series between the positive electrode and the negative electrode of the input voltage, and an average current sampling circuit as claimed in any one of claims 1 to 9.

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