Chip fault test method and device, computer equipment, readable storage medium and program product

Abstract

The invention relates to a chip fault detection method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: testing each item to be tested of a chip to be tested on a pre-constructed electrical testing platform by adopting a pre-developed electrical testing program to obtain a testing result; if the test result indicates that the to-be-tested chip has a fault, positioning a fault module in the to-be-tested chip based on the test result; based on the fault module, determining a circuit analysis mode of the fault module; and dynamic stress excitation is performed on the fault module, circuit fault detection is performed on the fault module after dynamic stress excitation based on the circuit analysis mode, and a fault circuit in the fault module is determined. By adopting the method, the abnormal fault of the chip can be efficiently and finely detected.

Description

Technical Field

[0001] The present application relates to the field of electronic engineering technology, and in particular to a chip fault testing method, device, computer equipment, computer-readable storage medium and computer program product. Background Art

[0002] With the rapid development of the electronic information industry and the advancement of microelectronics process technology, artificial intelligence (AI) chips have been increasingly used in the fields of autonomous driving and drones. AI chips usually refer to chips with special acceleration design or software and hardware optimization for artificial intelligence algorithms, including deep learning algorithms and machine learning algorithms. Since AI chips are usually high-computing chips, their production and manufacturing technology is complex, and some problems may be hidden during the production process that affect their normal operation, so AI chip fault detection is particularly important.

[0003] Due to the complex functional structure of AI chips and the integration of a large number of neural network processing units, traditional AI chip fault detection based on electrical measurement technology is difficult to accurately locate and analyze faults, and the degree of refinement is not enough. In the fault detection of large-scale integrated circuits such as AI chips based on physical optical detection technology, it is necessary to scan and detect step by step according to the physical space, which takes a long time and has low efficiency. At the same time, it faces the problem of difficulty in effectively detecting faults that have not been fully stimulated. Summary of the invention

[0004] Based on this, it is necessary to provide a chip fault detection method, device, computer equipment, computer-readable storage medium and computer program product that can achieve refined and efficient detection and positioning of chip abnormal faults in response to the above-mentioned technical problems.

[0005] In a first aspect, the present application provides a chip fault detection method, comprising:

[0006] Using a pre-developed electrical test program on a pre-built electrical test platform, various items to be tested on the chip to be tested are tested to obtain test results;

[0007] If the test result indicates that the chip under test is faulty, locating the faulty module in the chip under test based on the test result;

[0008] Based on the fault module, a circuit analysis method of the fault module is determined; dynamic stress is stimulated on the fault module, and circuit fault detection is performed on the fault module after dynamic stress stimulation based on the circuit analysis method to determine a circuit in which a fault occurs in the fault module.

[0009] In one embodiment, the step of dynamically stimulating the fault module includes:

[0010] A state characterization parameter corresponding to the fault module is set, wherein the state characterization parameter includes at least one of an area utilization rate, a performance utilization rate, or a load utilization rate; the value of the state characterization parameter increases with an increase in the stress intensity applied to the fault module; a test interval and a test step length of the state characterization parameter are set, and the test interval is divided according to the test step length to obtain at least one test value of the state characterization parameter; and stress excitation is performed on the fault module based on the at least one test value.

[0011] In one embodiment, the circuit fault analysis is performed on the fault module after the dynamic stress is excited based on the circuit analysis method to determine the circuit where the fault occurs, including:

[0012] Stress intensity is applied to the fault module, and whenever a state characterization parameter corresponding to the fault module reaches a test value, circuit fault detection is performed on the fault module based on the circuit analysis method to obtain at least one circuit fault analysis result; based on the at least one circuit fault analysis result, a faulty circuit is determined.

[0013] In one embodiment, the determining of a faulty circuit based on the at least one circuit fault analysis result includes:

[0014] If all circuits of the faulty module are normal in any test, the circuit fault analysis result in this test is normal; if the circuit of the faulty module is faulty in any test, the circuit fault analysis result in this test is faulty, and the faulty circuit is recorded.

[0015] In one embodiment, the step of testing each item to be tested of the chip to be tested and obtaining the test result includes:

[0016] Each test item of the chip to be tested is tested; if the chip to be tested is qualified in each test item, the test result of the chip to be tested is normal; if the chip to be tested has a fault in any test item, the test result of the chip to be tested is a fault.

[0017] In one embodiment, the method further comprises:

[0018] If the test result indicates that the chip under test is normal, a result indicating that the chip is normal is output.

[0019] In a second aspect, the present application also provides a chip fault detection device, comprising:

[0020] The electrical test module is used to test various items to be tested on the chip to be tested using a pre-developed electrical test program on a pre-built electrical test platform to obtain test results;

[0021] A positioning module, configured to locate a faulty module in the chip under test based on the test result if the test result indicates that the chip under test has a fault;

[0022] A selection module, used for determining a circuit analysis method of the fault module based on the fault module;

[0023] The analysis module is used to perform dynamic stress excitation on the fault module, and perform circuit fault detection on the fault module after dynamic stress excitation based on the circuit analysis method to determine the circuit where the fault occurs in the fault module.

[0024] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0025] Using a pre-developed electrical test program on a pre-built electrical test platform, various items to be tested on the chip to be tested are tested to obtain test results;

[0026] If the test result indicates that the chip under test is faulty, locating the faulty module in the chip under test based on the test result;

[0027] Based on the fault module, a circuit analysis method of the fault module is determined; dynamic stress is stimulated on the fault module, and circuit fault detection is performed on the fault module after dynamic stress stimulation based on the circuit analysis method to determine a circuit in which a fault occurs in the fault module.

[0028] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following steps are implemented:

[0029] Using a pre-developed electrical test program on a pre-built electrical test platform, various items to be tested on the chip to be tested are tested to obtain test results;

[0030] If the test result indicates that the chip under test is faulty, locating the faulty module in the chip under test based on the test result;

[0031] Based on the fault module, a circuit analysis method of the fault module is determined; dynamic stress is stimulated on the fault module, and circuit fault detection is performed on the fault module after dynamic stress stimulation based on the circuit analysis method to determine a circuit in which a fault occurs in the fault module.

[0032] In a fifth aspect, the present application further provides a computer program product, including a computer program, which implements the following steps when executed by a processor:

[0033] Using a pre-developed electrical test program on a pre-built electrical test platform, various items to be tested on the chip to be tested are tested to obtain test results;

[0034] If the test result indicates that the chip under test is faulty, locating the faulty module in the chip under test based on the test result;

[0035] Based on the fault module, a circuit analysis method of the fault module is determined; dynamic stress is stimulated on the fault module, and circuit fault detection is performed on the fault module after dynamic stress stimulation based on the circuit analysis method to determine a circuit in which a fault occurs in the fault module.

[0036] The chip fault detection method, device, computer equipment, computer-readable storage medium and computer program product described above use a pre-developed electrical test program on a pre-built electrical test platform to test each item to be tested of the chip to be tested and obtain a test result; if the test result indicates that the chip to be tested has a fault, then based on the test result, locate the faulty module in the chip to be tested; based on the faulty module, determine the circuit analysis method of the faulty module; perform dynamic stress excitation on the faulty module, and perform circuit fault detection on the faulty module after dynamic stress excitation based on the circuit analysis method to determine the circuit in which the fault occurs in the faulty module. By first locating the faulty module and then determining the specific faulty circuit in the faulty module, the abnormal fault of the chip can be detected efficiently and finely. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 A schematic diagram of a chip fault detection method according to an embodiment of the present invention;

[0039] Figure 2 is a schematic diagram of dynamic stress excitation in one embodiment;

[0040] Figure 3 is a schematic diagram of performing electrical testing on a chip in one embodiment;

[0041] Figure 4 is a schematic diagram of performing circuit analysis on a fault module in one embodiment;

[0042] Figure 5 is a schematic diagram of a chip fault detection method in one embodiment;

[0043] Figure 6 is a schematic diagram of a circuit analysis method in one embodiment;

[0044] Figure 7 A schematic diagram of the structure of a test version in an embodiment;

[0045] Figure 8 A schematic diagram of a detailed implementation flow of a chip fault detection method in an embodiment;

[0046] Fig. 9 is a structural block diagram of a chip fault detection device in one embodiment;

[0047] Fig.10 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0049] In one embodiment, Figure 1 As shown, a chip fault detection method is provided. This embodiment takes the method applied to a terminal as an example. It can be understood that the method can also be applied to a server, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0050] Step 102 , using a pre-developed electrical testing program on a pre-built electrical testing platform, testing each item to be tested of the chip to be tested, and obtaining a test result.

[0051] The electrical test platform is a comprehensive test system that provides all the hardware and software resources required for chip testing. The electrical test program is a software program specifically used to test chips, which is usually developed by testers based on the characteristics of the chip and test requirements.

[0052] Exemplarily, a pre-developed chip electrical testing program is used on a pre-built chip electrical testing platform to test all test items of the chip to be tested, and a test result of each test item is obtained.

[0053] Step 104: if the test result indicates that the chip under test is faulty, locate the faulty module in the chip under test based on the test result.

[0054] Optionally, the method of locating the fault in the chip under test can be: if a test result of the chip is abnormal, determine the function of the chip that has a fault based on the test result, and determine the faulty module in the chip under test based on the function.

[0055] Exemplarily, if the test result indicates that the chip under test has a fault, a faulty function in the chip is determined based on the test result, and a faulty module in the chip under test is located according to the faulty function.

[0056] Step 106: Determine a circuit analysis method for the fault module based on the fault module.

[0057] Optionally, the circuit analysis method may be detection based on EMMI (Emission Microscope), detection based on OBIRCH (Optical Beam Induced Resistance Change) technology, and detection based on LIT (Lock-In Thermography) technology.

[0058] Exemplarily, based on the module with the fault, it is determined that the subsequent circuit analysis method for performing physical optical detection on the faulty module is to detect the faulty module based on EMMI.

[0059] Step 108 , dynamically stress-excite the faulty module, and perform circuit fault detection on the faulty module after dynamic stress-excited based on the circuit analysis method to determine a circuit in which a fault occurs in the faulty module.

[0060] Among them, dynamic stress excitation refers to multiple stress excitations of different degrees.

[0061] Exemplarily, dynamic stress excitation is performed on the faulty module, and circuit fault detection is performed on the faulty module after dynamic stress excitation based on EMMI, and all faulty circuits in the faulty module are determined according to the detection result.

[0062] The chip fault detection method, device, computer equipment, computer-readable storage medium and computer program product described above use a pre-developed electrical test program on a pre-built electrical test platform to test each item to be tested of the chip to be tested and obtain a test result; if the test result indicates that the chip to be tested has a fault, then based on the test result, locate the faulty module in the chip to be tested; based on the faulty module, determine the circuit analysis method of the faulty module; perform dynamic stress excitation on the faulty module, and perform circuit fault detection on the faulty module after dynamic stress excitation based on the circuit analysis method to determine the circuit in which the fault occurs in the faulty module. By first locating the faulty module and then determining the specific faulty circuit in the faulty module, the abnormal fault of the chip can be detected efficiently and finely.

[0063] In an exemplary embodiment, the dynamically stimulating stress on the faulty module includes:

[0064] A state characterization parameter corresponding to the fault module is set, wherein the state characterization parameter includes at least one of an area utilization rate, a performance utilization rate, or a load utilization rate; the value of the state characterization parameter increases with an increase in the stress intensity applied to the fault module; a test interval and a test step length of the state characterization parameter are set, and the test interval is divided according to the test step length to obtain at least one test value of the state characterization parameter; and stress excitation is performed on the fault module based on the at least one test value.

[0065] Optionally, the state characterization parameter may be a usage rate, the test interval may be 20%-100%, and the step length may be 20%.

[0066] Exemplarily, the usage rate is set as the state characterization parameter of the faulty module, the test interval is set to 20%-100%, and the step size is set to 20%, thereby obtaining test values ​​of 20%, 40%, 60%, 80% and 100%; stress stimulation is performed on the faulty module, and the usage rate of the faulty module is stimulated to 20%, and then stress stimulation is gradually performed in the order of 40%, 60%, 80% and 100%.

[0067] In this embodiment, dynamic stress stimulation is performed on the faulty module so that the faulty module reaches different utilization rates, which facilitates subsequent more comprehensive detection of the faulty module.

[0068] In an exemplary embodiment, performing circuit fault analysis on the faulty module after the dynamic stress is excited based on the circuit analysis method to determine the circuit where the fault occurs includes:

[0069] Stress intensity is applied to the fault module, and whenever a state characterization parameter corresponding to the fault module reaches a test value, circuit fault detection is performed on the fault module based on the circuit analysis method to obtain at least one circuit fault analysis result; based on the at least one circuit fault analysis result, a faulty circuit is determined.

[0070] The purpose of applying stress intensity is to make the state characterization parameter reach the corresponding test value.

[0071] For example, Figure 2 As shown, after the faulty module of the AI ​​chip is located based on the electrical measurement technology, the AI ​​chip is dynamically stimulated to detect the fault based on the usage of the AI ​​chip in different usage scenarios. Taking the situations under different usage rates as an example, the AI ​​chip is stress stimulated to increase the usage rate of the AI ​​chip to 20%, and all circuits in the faulty module are detected using the selected analysis method to obtain the first circuit fault analysis result. Similarly, the AI ​​chip is stress stimulated to increase the usage rate of the AI ​​chip to 40%, 60%, 80% and 100%, and the analysis method is used to detect the AI ​​chip when the usage rate reaches 40%, 60%, 80% and 100%, respectively. Combined with the previous circuit fault analysis results, a total of 5 circuit fault analysis results are obtained, and the collected data is used to analyze the fault detection results of the AI ​​chip under different stimulation conditions.

[0072] In this embodiment, by applying dynamic stress excitation, the impact of different excitation conditions on the AI ​​chip fault detection results can be analyzed to discover potential fault links.

[0073] In an exemplary embodiment, determining a circuit having a fault based on the at least one circuit fault analysis result includes:

[0074] If all circuits of the faulty module are normal in any test, the circuit fault analysis result in this test is normal; if the circuit of the faulty module is faulty in any test, the circuit fault analysis result in this test is faulty, and the faulty circuit is recorded.

[0075] For example, Figure 3 As shown, the neural network module in the AI ​​chip is detected to have a fault through the electrical testing platform and the electrical testing process. The neural network module includes three neural network units, and the neural network module is tested by circuit analysis. After obtaining five circuit fault analysis results, the circuits that have failed in the five circuit fault analysis results are recorded, thereby obtaining the circuit in which the neural network unit has a fault. Exemplarily, the faults of the faulty circuit may include: short circuit, leakage, high resistance and other faults.

[0076] In this embodiment, by recording the circuit in which the AI ​​chip fails under dynamic stress excitation, the complete faulty circuit can be recorded to prevent missing of certain faulty circuits.

[0077] In an exemplary embodiment, the step of testing each test item of the chip to be tested to obtain a test result includes:

[0078] Each test item of the chip to be tested is tested; if the chip to be tested is qualified in each test item, the test result of the chip to be tested is normal; if the chip to be tested has a fault in any test item, the test result of the chip to be tested is a fault.

[0079] Optionally, the chip to be tested can be an AI chip, and the test items can be: ARM Private timer test, PVT SENSOR test, RTC test, global timer test, JPEG2K test, GPIO test, SAR ADC test, GIC test, AHB DMA test, ARM Private Watchdog test, I2C test, SPI test, CAN test, Controller Area Network test, VSI TIMER-1 test, MIPI test. CSI2 Host (MIPI CSI-2 host interface, MIPI Camera Serial Interface 2 Host) test, NFC (Near Field Communication) test, RAPIDIO (RapidIO bus) test, B1533SDIO (B1533 standard SDIO interface, B1533 Standard SecureDigital Input Output) test, UART0 (Universal Asynchronous Receiver / Transmitter 0) test, Ethernet test, USB2.0 (Universal Serial Bus2.0) test, PCIE 2.0 (PCI Express 2.0) test, I2S (I2S audio bus, Inter-IC Sound) test, VIP810 test, video codec, Camera Link (Camera Link interface) test, DDR interface (Double DataRate) and SPARC (SPARC processor, Scalable Processor ARChitecture) test. .

[0080] For example, Figure 4 As shown, the chip to be tested is tested according to the items to be tested. If the results of all items are qualified, the AI ​​chip is normal and the test is terminated; if the test result of the chip in at least one item is abnormal, the faulty module of the AI ​​chip is determined based on all the abnormal test results. Optionally, the modules of the AI ​​chip include: processor core, DDR interface, PCIE interface, on-chip cache, timer, bus, neural network module, and the neural network module includes 3 neural network units.

[0081] In this embodiment, various tests are performed on the AI ​​chip through an electrical testing program, which can efficiently locate the faulty module and facilitate subsequent circuit-level detection of the faulty module.

[0082] In an exemplary embodiment, the method further comprises:

[0083] If the test result indicates that the chip under test is normal, a result indicating that the chip is normal is output.

[0084] Exemplarily, when all the results of testing the chip under test according to the test items are normal, the chip under test has no faults, and a result indicating that the chip is normal is output.

[0085] In this embodiment, when the chip is normal, the result of the chip failure is output and the subsequent detection steps are skipped, which can save the time of chip detection.

[0086] In an exemplary embodiment, Figure 5 The figure shows a schematic diagram of a chip fault detection method. First, efficient fault detection and positioning are performed on the AI ​​chip at the module level according to the test items, and the faulty module is determined to be the neural network module. Then, dynamic stress excitation is performed on each neural network unit in the neural network module, and the neural network unit is accurately detected and positioned at the circuit level using the selected circuit analysis method to determine the faulty neural network unit and the circuit in which the neural network unit has a fault.

[0087] In an exemplary embodiment, Figure 6The following are the categories of circuit analysis methods, which are mainly based on physical optics fault detection technology. Optional ones include: photoemission microscopy technology, infrared microscope analysis technology, scanning optical microscopy technology and liquid crystal detection technology. Optionally, photoemission microscopy technology can be: PEM (Photo Emission Microscope) and EMMI (Emission Microscope). Infrared microscope analysis technology can be: LIT (Lock-In Thermography) and hot spot detection. Scanning optical microscopy technology can be: OBIRCH (Optical Beam Induced Resistance Change) and TIVA (Thermal Induced Voltage Alteration).

[0088] In an exemplary embodiment, Figure 7 The figure shows the test board required for dynamic stress stimulation, which is connected to the host computer and devices for circuit analysis such as EMMI, OBIRCH or LIT; the test board includes: power module, storage module, configuration chip, FPGA (Field-Programmable Gate Array), display control module, input and output module, clock module and chip under test. Dynamic stress stimulation is performed by loading functional or performance test vectors.

[0089] In an exemplary embodiment, Figure 8 The figure shows a detailed flow chart of a chip fault detection method. First, an electrical test program is developed, an electrical test platform is constructed, and all the test items of the chip to be tested are tested to obtain the test results of each test item. When the results of the test of the chip to be tested according to the test items are all normal, the chip to be tested has no fault, and the normal result of the chip is output, and the test ends;

[0090] If the test result of the chip in at least one item is abnormal, the faulty module in the chip is determined based on all the abnormal test results.

[0091] Develop functional performance test vectors for faulty modules and develop a chip fault detection test version. Based on the faulty module, select the circuit analysis method for subsequent physical optical detection of the faulty module. Set the usage rate as the state characterization parameter of the faulty module, set the test interval to 20%-100%, and set the step size to 20%, so that the test values ​​are 20%, 40%, 60%, 80% and 100%; apply test stress to the faulty module, stimulate the usage rate of the faulty module to 20%, and then gradually stimulate stress in the order of 40%, 60%, 80% and 100%. Based on the selected analysis method, the fault module after dynamic stress excitation is tested for circuit faults. When the AI ​​chip is stressed and the utilization rate of the AI ​​chip reaches 20%, all circuits in the fault module are tested using the selected analysis method to obtain the first circuit fault analysis result. Similarly, when the utilization rate of the AI ​​chip reaches 40%, 60%, 80% and 100%, the AI ​​chip with utilization rate reaching 40%, 60%, 80% and 100% is tested using the circuit analysis method to obtain 4 circuit fault analysis results. Combined with the previous 1 circuit fault analysis result, a total of 5 circuit fault analysis results are obtained. The circuits that have failed in the 5 circuit fault analysis results are recorded, thereby obtaining the circuits with faults in the fault module.

[0092] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0093] In an exemplary embodiment, Fig. 9 As shown, a chip fault detection device is provided, including: an electrical measurement module, a positioning module, a selection module and an analysis module, wherein:

[0094] The electrical test module is used to test various items to be tested on the chip to be tested using a pre-developed electrical test program on a pre-built electrical test platform to obtain test results;

[0095] A positioning module, configured to locate a faulty module in the chip under test based on the test result if the test result indicates that the chip under test has a fault;

[0096] A selection module, used for determining a circuit analysis method of the fault module based on the fault module;

[0097] The analysis module is used to perform dynamic stress excitation on the fault module, and perform circuit fault detection on the fault module after dynamic stress excitation based on the circuit analysis method to determine the circuit where the fault occurs in the fault module.

[0098] In one embodiment, the analysis module is further configured to:

[0099] A state characterization parameter corresponding to the fault module is set, wherein the state characterization parameter includes at least one of an area utilization rate, a performance utilization rate, or a load utilization rate; the value of the state characterization parameter increases with an increase in the stress intensity applied to the fault module; a test interval and a test step length of the state characterization parameter are set, and the test interval is divided according to the test step length to obtain at least one test value of the state characterization parameter; and stress excitation is performed on the fault module based on the at least one test value.

[0100] In one embodiment, the analysis module is further configured to:

[0101] Stress intensity is applied to the fault module, and whenever a state characterization parameter corresponding to the fault module reaches a test value, circuit fault detection is performed on the fault module based on the circuit analysis method to obtain at least one circuit fault analysis result; based on the at least one circuit fault analysis result, a faulty circuit is determined.

[0102] In one embodiment, the electrical measurement module is further used to:

[0103] If all circuits of the faulty module are normal in any test, the circuit fault analysis result in this test is normal; if the circuit of the faulty module is faulty in any test, the circuit fault analysis result in this test is faulty, and the faulty circuit is recorded.

[0104] In one embodiment, the electrical measurement module is further used to:

[0105] Each test item of the chip to be tested is tested; if the chip to be tested is qualified in each test item, the test result of the chip to be tested is normal; if the chip to be tested has a fault in any test item, the test result of the chip to be tested is a fault.

[0106] In one embodiment, the electrical measurement module is further used to:

[0107] If the test result indicates that the chip under test is normal, a result indicating that the chip is normal is output.

[0108] Each module in the above chip fault detection device can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0109] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Fig.10 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store test data and circuit fault analysis results. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a chip fault detection method is implemented.

[0110] Those skilled in the art will understand that Fig.10 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0111] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0112] Using a pre-developed electrical test program on a pre-built electrical test platform, various items to be tested on the chip to be tested are tested to obtain test results;

[0113] If the test result indicates that the chip under test is faulty, locating the faulty module in the chip under test based on the test result;

[0114] Based on the fault module, a circuit analysis method of the fault module is determined; dynamic stress is stimulated on the fault module, and circuit fault detection is performed on the fault module after dynamic stress stimulation based on the circuit analysis method to determine a circuit in which a fault occurs in the fault module.

[0115] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0116] A state characterization parameter corresponding to the fault module is set, wherein the state characterization parameter includes at least one of an area utilization rate, a performance utilization rate, or a load utilization rate; the value of the state characterization parameter increases with an increase in the stress intensity applied to the fault module; a test interval and a test step length of the state characterization parameter are set, and the test interval is divided according to the test step length to obtain at least one test value of the state characterization parameter; and stress excitation is performed on the fault module based on the at least one test value.

[0117] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0118] Stress intensity is applied to the fault module, and whenever a state characterization parameter corresponding to the fault module reaches a test value, circuit fault detection is performed on the fault module based on the circuit analysis method to obtain at least one circuit fault analysis result; based on the at least one circuit fault analysis result, a faulty circuit is determined.

[0119] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0120] If all circuits of the faulty module are normal in any test, the circuit fault analysis result in this test is normal; if the circuit of the faulty module is faulty in any test, the circuit fault analysis result in this test is faulty, and the faulty circuit is recorded.

[0121] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0122] Each test item of the chip to be tested is tested; if the chip to be tested is qualified in each test item, the test result of the chip to be tested is normal; if the chip to be tested has a fault in any test item, the test result of the chip to be tested is a fault.

[0123] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0124] If the test result indicates that the chip under test is normal, a result indicating that the chip is normal is output.

[0125] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0126] Using a pre-developed electrical test program on a pre-built electrical test platform, various items to be tested on the chip to be tested are tested to obtain test results;

[0127] If the test result indicates that the chip under test is faulty, locating the faulty module in the chip under test based on the test result;

[0128] Based on the fault module, a circuit analysis method of the fault module is determined; dynamic stress is stimulated on the fault module, and circuit fault detection is performed on the fault module after dynamic stress stimulation based on the circuit analysis method to determine a circuit in which a fault occurs in the fault module.

[0129] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0130] A state characterization parameter corresponding to the fault module is set, wherein the state characterization parameter includes at least one of an area utilization rate, a performance utilization rate, or a load utilization rate; the value of the state characterization parameter increases with an increase in the stress intensity applied to the fault module; a test interval and a test step length of the state characterization parameter are set, and the test interval is divided according to the test step length to obtain at least one test value of the state characterization parameter; and stress excitation is performed on the fault module based on the at least one test value.

[0131] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0132] Stress intensity is applied to the fault module, and whenever a state characterization parameter corresponding to the fault module reaches a test value, circuit fault detection is performed on the fault module based on the circuit analysis method to obtain at least one circuit fault analysis result; based on the at least one circuit fault analysis result, a faulty circuit is determined.

[0133] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0134] If all circuits of the faulty module are normal in any test, the circuit fault analysis result in this test is normal; if the circuit of the faulty module is faulty in any test, the circuit fault analysis result in this test is faulty, and the faulty circuit is recorded.

[0135] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0136] Each test item of the chip to be tested is tested; if the chip to be tested is qualified in each test item, the test result of the chip to be tested is normal; if the chip to be tested has a fault in any test item, the test result of the chip to be tested is a fault.

[0137] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0138] If the test result indicates that the chip under test is normal, a result indicating that the chip is normal is output.

[0139] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0140] Using a pre-developed electrical test program on a pre-built electrical test platform, various items to be tested on the chip to be tested are tested to obtain test results;

[0141] If the test result indicates that the chip under test is faulty, locating the faulty module in the chip under test based on the test result;

[0142] Based on the fault module, a circuit analysis method of the fault module is determined; dynamic stress is stimulated on the fault module, and circuit fault detection is performed on the fault module after dynamic stress stimulation based on the circuit analysis method to determine a circuit in which a fault occurs in the fault module.

[0143] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0144] A state characterization parameter corresponding to the fault module is set, wherein the state characterization parameter includes at least one of an area utilization rate, a performance utilization rate, or a load utilization rate; the value of the state characterization parameter increases with an increase in the stress intensity applied to the fault module; a test interval and a test step length of the state characterization parameter are set, and the test interval is divided according to the test step length to obtain at least one test value of the state characterization parameter; and stress excitation is performed on the fault module based on the at least one test value.

[0145] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0146] Stress intensity is applied to the fault module, and whenever a state characterization parameter corresponding to the fault module reaches a test value, circuit fault detection is performed on the fault module based on the circuit analysis method to obtain at least one circuit fault analysis result; based on the at least one circuit fault analysis result, a faulty circuit is determined.

[0147] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0148] If all circuits of the faulty module are normal in any test, the circuit fault analysis result in this test is normal; if the circuit of the faulty module is faulty in any test, the circuit fault analysis result in this test is faulty, and the faulty circuit is recorded.

[0149] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0150] Each test item of the chip to be tested is tested; if the chip to be tested is qualified in each test item, the test result of the chip to be tested is normal; if the chip to be tested has a fault in any test item, the test result of the chip to be tested is a fault.

[0151] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0152] If the test result indicates that the chip under test is normal, a result indicating that the chip is normal is output.

[0153] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0154] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0155] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A chip fault detection method, characterized in that: The method comprises: Using a pre-developed electrical test program on a pre-built electrical test platform, various items to be tested on the chip to be tested are tested to obtain test results; If the test result indicates that the chip under test is faulty, locating the faulty module in the chip under test based on the test result; Based on the fault module, determining a circuit analysis method of the fault module; Dynamic stress is excited on the faulty module, and circuit fault detection is performed on the faulty module after dynamic stress is excited based on the circuit analysis method to determine a circuit in which a fault occurs in the faulty module.

2. The method according to claim 1, characterized in that The step of dynamically stimulating the fault module includes: Setting a state characterization parameter corresponding to the fault module, the state characterization parameter including at least one of an area utilization rate, a performance utilization rate, or a load utilization rate; a value of the state characterization parameter increases as the stress intensity applied to the fault module increases; Setting a test interval and a test step length of the state characterization parameter, dividing the test interval according to the test step length, and obtaining at least one test value of the state characterization parameter; Based on the at least one test value, the faulty module is stressed.

3. The method according to claim 2, characterized in that The performing circuit fault analysis on the fault module after the dynamic stress is excited based on the circuit analysis method to determine the circuit where the fault occurs includes: Applying stress intensity to the fault module, and performing circuit fault detection on the fault module based on the circuit analysis method whenever a state characterization parameter corresponding to the fault module reaches a test value, to obtain at least one circuit fault analysis result; Based on the at least one circuit fault analysis result, a circuit in which a fault occurs is determined.

4. The method according to claim 3, characterized in that The determining of a circuit having a fault based on the at least one circuit fault analysis result comprises: If in any test, all circuits of the faulty module are normal, then the circuit fault analysis result in this test is normal; If in any detection, the circuit of the fault module is faulty, the circuit fault analysis result in this detection is faulty, and the circuit with the fault is recorded.

5. The method according to claim 1, characterized in that The test results of the chip to be tested are obtained by testing each item to be tested, including: Test each test item of the chip to be tested; If the chip under test passes each test item, the test result of the chip under test is normal; If the chip under test has a fault in any test item, the test result of the chip under test is that a fault exists.

6. The method according to claim 1, characterized in that The method further comprises: If the test result indicates that the chip under test is normal, a result indicating that the chip is normal is output.

7. A chip fault detection device, characterized in that: The device comprises: The electrical test module is used to test various items to be tested on the chip to be tested using a pre-developed electrical test program on a pre-built electrical test platform to obtain test results; A positioning module, configured to locate a faulty module in the chip under test based on the test result if the test result indicates that the chip under test has a fault; A selection module, used for determining a circuit analysis method of the fault module based on the fault module; The analysis module is used to perform dynamic stress excitation on the fault module, and perform circuit fault detection on the fault module after dynamic stress excitation based on the circuit analysis method to determine the circuit where the fault occurs in the fault module.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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