Chip process corner detection circuit

Abstract

The invention provides a chip process corner detection circuit, which comprises a process corner detection unit used for collecting three groups of comparison signals in a to-be-detected chip, and each group of comparison signals comprises a first voltage signal related to the process corner and irrelevant to the temperature and a second voltage signal irrelevant to the process corner and the temperature; the comparison unit is used for determining a comparison result between the two voltage signals of each group of comparison signals; and the logic result output unit is used for performing different preset types of logic operations on all the comparison results, and determining the process corner type of the chip to be tested according to the logic operation result. The voltage irrelevant to the temperature and relevant to the process corner and the voltage irrelevant to the temperature and the process corner are output, the state of the process corner is reflected through the comparison result of the two voltages, and finally the logic operation result representing different process corner types is output through the logic result output unit. Therefore, the process corner of the to-be-detected chip can be rapidly and accurately detected, and the circuit is simple in structure and easy to realize.

Description

Technical Field

[0001] The present disclosure relates to the technical field of chip detection, and in particular to a detection circuit for a chip process angle. Background Art

[0002] In semiconductor manufacturing and integrated circuit design, process corner refers to different situations in which chip performance and characteristics change due to changes in process parameters during the manufacturing process. These changes can affect key parameters such as transistor threshold voltage, mobility, oxide thickness, and thus affect circuit performance. The concept of process corner is mainly used to evaluate and verify the performance and reliability of circuits under different manufacturing conditions. With the increase in the scale of integrated circuits, in order to improve the performance stability of chips, how to simply, quickly and accurately obtain the process corner of chips is an urgent problem to be solved in the chip design and preparation process. Summary of the invention

[0003] The purpose of the embodiments of the present disclosure is to provide a chip process corner detection circuit to solve the problem of chip process corner type detection in the prior art.

[0004] The embodiments of the present disclosure adopt the following technical scheme: a chip process angle detection circuit, comprising: a process angle detection unit, used to collect three groups of comparison signals in the chip to be tested, each group of the comparison signals includes a first voltage signal related to the process angle and independent of temperature, and a second voltage signal independent of both the process angle and temperature; a comparison unit, used to determine the comparison result between the two voltage signals of each group of comparison signals; a logic result output unit, used to perform different preset types of logic operations on all the comparison results, and determine the process angle type of the chip to be tested according to the logic operation results.

[0005] The beneficial effects of the embodiments of the present disclosure are as follows: a process angle detection circuit is used to output a voltage that is independent of temperature but related to the process angle, and a voltage that is independent of both temperature and process angle, and a comparison result of the two is used to reflect the process angle state, and finally a logic result output unit is used to output logic operation results representing different process angle types, so as to achieve rapid and accurate detection of the process angle condition of the chip to be tested, and the entire circuit structure is simple and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0007] Figure 1 It is a schematic diagram of the structure of the chip process angle detection circuit in the embodiment of the present disclosure;

[0008] Figure 2 Schematic diagram of the circuit structure of the process angle detection unit in the embodiment of the present disclosure;

[0009] Figure 3 is a schematic diagram of the circuit structure of a comparison unit in an embodiment of the present disclosure;

[0010] Figure 4 Schematic diagram of the circuit structure of the logic result output unit in the embodiment of the present disclosure;

[0011] Figure 5 V in the embodiment of the present disclosure 1p Output voltage changes;

[0012] Figure 6 is a circuit structure diagram of an N-type transistor trimming array in an embodiment of the present disclosure;

[0013] Figure 7 is a circuit structure diagram of a P-type transistor trimming array in an embodiment of the present disclosure;

[0014] Figure 8 Schematic diagram of the equivalent transistor Neq of N0 and N6 in the embodiment of the present disclosure;

[0015] Fig. 9 Schematic diagram of equivalent transistors Neq and N1 in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the following will be combined with the drawings in one or more embodiments of this specification to clearly and completely describe the technical solutions in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this document.

[0017] In order to solve the problems in the prior art, the embodiment of the present disclosure provides a chip process angle detection circuit, and its structural schematic diagram is shown as follows: Figure 1As shown, it mainly includes a process angle detection unit 10, a comparison unit 20 and a logic result output unit 30, wherein the process angle detection unit 10 is used to collect three groups of comparison signals in the chip to be tested, each group of comparison signals includes a first voltage signal related to the process angle and independent of temperature, and a second voltage signal independent of the process angle and temperature; the comparison unit 20 is used to determine the comparison result between the two voltage signals of each group of comparison signals; the logic result output unit 30 is used to perform different preset types of logic operations on all comparison results, and determine the process angle type of the chip to be tested according to the logic operation result. It should be understood that the process angle type of the chip at least includes: typical angle (TT, Typical-Typical), fast N type slow P type (FS, Fast-N / Slow-P), slow N type fast P type (SF, Slow-N / Fast-P), fast N type fast P type (FF, Fast-Fast) and slow N type slow P type (SS, Slow-Slow).

[0018] Figure 2 FIG. 2 shows a schematic diagram of the circuit structure of the process angle detection unit 10 in this embodiment. Figure 2 As shown, the process angle detection unit 10 at least includes: a first detection circuit 11 , a second detection circuit 12 , a third detection circuit 13 , a first reference circuit 14 , a second reference circuit 15 and a third reference circuit 16 .

[0019] Specifically, the first detection circuit 11 includes a first N-type transistor M1 and a first resistor R1 in the chip to be tested. The drain and gate of the first N-type transistor M1 are connected to the working voltage VDD. The source of the first N-type transistor M1 is connected to the first end of the first resistor R1 and leads to a first voltage signal V 1p , the second end of the first resistor R1 is grounded; the second detection circuit 12 includes a first P-type transistor M2 and a second resistor R2 in the chip to be tested, the source and gate of the first P-type transistor M2 are connected to the working voltage VDD, the drain of the first P-type transistor M2 is connected to the first end of the second resistor R2 and leads to the first voltage signal V 2p , the second end of the second resistor R2 is grounded; the third detection circuit 13 includes a second P-type transistor M3 and a second N-type transistor M4 in the chip to be tested, the source of the second P-type transistor M3 is connected to the working voltage VDD, the gate of the second P-type transistor M3 is connected to the gate of the second N-type transistor M4, the drain of the second P-type transistor M3 is connected to the drain of the second N-type transistor M4 and leads to the first voltage signal V of the third group of comparison signals 3p , the source of the second N-type transistor M4 is grounded.

[0020] The first reference circuit 13 includes a third resistor R3 and a fourth resistor R4 connected in series to the working voltage VDD and the ground terminal. The second voltage signal V 1n The second reference circuit 14 includes a fifth resistor R5 and a sixth resistor R6 connected in series to the working voltage VDD and the ground terminal, and a second voltage signal V of the second set of comparison signals is drawn between the fifth resistor R5 and the sixth resistor R6. 2n The third reference circuit 15 includes a seventh resistor R7 and an eighth resistor R8 connected in series to the working voltage VDD and the ground terminal, and a second voltage signal V of the third set of comparison signals is drawn between the seventh resistor R7 and the eighth resistor R8. 3n .

[0021] It should be noted that the first N-type transistor M1, the first P-type transistor M2, the second P-type transistor M3 and the second N-type transistor M4 are all transistors in the chip to be tested, which can be specifically transistors prepared under traditional silicon-based processes, BCD (Bipolar-CMOS-DMOS) processes, third-generation semiconductor processes (such as SiC (silicon carbide), GaN (gallium nitride) and AlN (aluminum nitride)). Combined with the specific structure and detection principle of the process angle detection unit 10, the first voltage signal output by the detection circuit is independent of temperature but related to different process angle states of the transistor, and the second voltage signal output by the reference voltage is independent of both temperature and process angle.

[0022] Figure 3 FIG. 2 shows a schematic diagram of the circuit structure of the comparison unit 20 in this embodiment. Figure 3 As shown, the comparison unit 20 at least includes: a first comparator 21, a second comparator 22 and a third comparator 23; wherein the positive input terminal of the first comparator 21 is connected to the first voltage signal V of the first group of comparison signals 1p , the inverting input terminal of the first comparator is connected to the second voltage signal V of the first group of comparison signals 1n The output terminal of the first comparator outputs the first comparison result V1; the positive input terminal of the second comparator 22 receives the first voltage signal V of the second group of comparison signals. 2p The inverting input terminal of the second comparator 23 is connected to the second voltage signal V of the second group of comparison signals. 2n The output terminal of the second comparator outputs the second comparison result V2; the non-inverting input terminal of the third comparator receives the first voltage signal V of the third group of comparison signals. 3p , the inverting input terminal of the third comparator is connected to the second voltage signal V of the third group of comparison signals 3n, the output terminal of the third comparator outputs the third comparison result V3. The above comparison result is output based on the magnitude of the signals input to the two input terminals of the comparator. When the signal input to the positive input terminal is greater than the signal input to the negative input terminal, the comparator outputs a high level (1), otherwise it inputs a low level (0). In this embodiment, the comparison unit compares and processes the first voltage signal that is independent of temperature but related to different process angle states of the transistor and the second voltage signal that is independent of both temperature and process angle. The comparison result represents the change in the electrical characteristics of the chip under different process angle states.

[0023] Figure 4 FIG. 4 shows a schematic diagram of the circuit structure of the logic result output unit 30 in this embodiment. Figure 4 As shown, the logic result output unit 30 at least includes a first logic operation circuit 31, a second logic operation circuit 32, a third logic operation circuit 33, a fourth logic operation circuit 34 and a fifth logic operation circuit 35, and all logic operation circuits are three-input AND gates. Among them, the first input end of the first logic operation circuit 31 is connected to the first comparison result V1, the second input end of the first logic operation circuit 31 is connected to the inverted signal of the second comparison result V2, and the third input end of the first logic operation circuit 31 is connected to the inverted signal of the third comparison result V3; the first input end of the second logic operation circuit 32 is connected to the inverted signal of the first comparison result V1, the second input end of the second logic operation circuit 32 is connected to the inverted signal of the second comparison result V2, and the third input end of the second logic operation circuit 32 is connected to the inverted signal of the third comparison result V3; the first input end of the third logic operation circuit 33 is connected to the first comparison result V1, the second input end of the third logic operation circuit 34 is connected to the inverted signal of the third comparison result V3. The second input terminal of the third logic operation circuit 3 is connected to the second comparison result V2, and the third input terminal of the third logic operation circuit 33 is connected to the inverted signal of the third comparison result V3; the first input terminal of the fourth logic operation circuit 34 is connected to the first comparison result V1, the second input terminal of the fourth logic operation circuit 34 is connected to the inverted signal of the second comparison result V2, and the third input terminal of the fourth logic operation circuit 34 is connected to the third comparison result V3; the first input terminal of the fifth logic operation circuit 35 is connected to the inverted signal of the first comparison result V1, the second input terminal of the fifth logic operation circuit 35 is connected to the second comparison result V2, and the third input terminal of the fifth logic operation circuit 35 is connected to the inverted signal of the third comparison result V3.

[0024] In this embodiment, the output result of the first logic operation circuit 31 is used to characterize whether the chip under test is a typical corner TT; the output result of the second logic operation circuit 32 is used to characterize whether the chip under test is a slow N-type slow P-type SS; the output result of the third logic operation circuit 33 is used to characterize whether the chip under test is a fast N-type fast P-type FF; the output result of the fourth logic operation circuit 34 is used to characterize whether the chip under test is a fast N-type slow P-type FS; the output result of the fifth logic operation circuit 35 is used to characterize whether the chip under test is a slow N-type fast P-type SF. In the actual implementation process, according to the truth table of the three-input AND gate and the input level of each input terminal, if the first logic operation circuit 31 outputs a high level, it means that the current chip to be tested is a typical angle TT, if the second logic operation circuit 31 outputs a high level, it means that the current chip to be tested is a slow N-type slow P-type SS, if the third logic operation circuit 33 outputs a high level, it means that the current chip to be tested is a fast N-type fast P-type FF, if the fourth logic operation circuit 34 outputs a high level, it means that the current chip to be tested is a fast N-type slow P-type FS, if the fifth logic operation circuit 35 outputs a high level, it means that the current chip to be tested is a slow N-type fast P-type SF. It should be noted that, in combination with the circuit structure of different logic operation circuits, when any of the above logic operation circuits outputs a high level, the other logic operation circuits must output a low level, so the chip to be tested is only in one process angle state.

[0025] In some embodiments, when configuring the detection circuit and the reference circuit, it is necessary to configure the parameters of the circuit elements to offset the influence of temperature. Corresponding to the detection circuit, this embodiment defines that when the temperature changes, the resistance value of the equivalent resistor of the first N-type transistor M1 remains the same as the resistance value of the first resistor R1, the resistance value of the equivalent resistor of the first P-type transistor M2 remains the same as the resistance value of the second resistor R2, and the resistance value of the equivalent resistor of the second P-type transistor M3 remains the same as the resistance value of the equivalent resistor of the second N-type transistor M4. At the same time, corresponding to the reference circuit, the resistance values ​​of the third resistor R3 and the fourth resistor R4 in this embodiment meet the following conditions: the difference between the first voltage signal of the first group of comparison signals and the second voltage signal of the first group of comparison signals determined according to the resistance value of the third resistor R3 and the resistance value of the fourth resistor R4 is greater than the threshold voltage of the first comparator 21; the resistance values ​​of the fifth resistor R5 and the sixth resistor R6 meet the following conditions: the difference between the first voltage signal of the second group of comparison signals and the second voltage signal of the second group of comparison signals determined according to the resistance value of the fifth resistor R5 and the resistance value of the sixth resistor R6 is greater than the threshold voltage of the second comparator 22; the resistance values ​​of the seventh resistor R7 and the eighth resistor R8 meet the following conditions: the difference between the first voltage signal of the third group of comparison signals and the second voltage signal of the third group of comparison signals determined according to the resistance value of the seventh resistor R7 and the resistance value of the eighth resistor R8 is greater than the threshold voltage of the third comparator 23.

[0026] Specifically, combined Figure 2 In the first detection circuit structure shown in FIG. 1 , the equivalent resistance of M1 is 1 / g m1 ,but:

[0027]

[0028] When the temperature changes, the change value of the equivalent resistance of M1 The resistance change ΔR1 of R1 is as follows:

[0029] ΔR1=R1(α1*ΔT+α2*ΔT 2 +·····+α n *ΔT n ) (3)

[0030]

[0031] By adjusting the size of R1 and the aspect ratio of M1, we can achieve:

[0032]

[0033] The values ​​of R3 and R4 must meet the following conditions:

[0034]

[0035] V 1p -V 1n >V th.com (7)

[0036] Based on the same derivation principle, the configuration basis of M2, M3, M4 and R5 to R8 can be obtained, which will not be repeated here.

[0037] Taking VDD as 3V and TT process corner type as an example, V 1p The output voltage changes as Figure 5 As shown, its minimum voltage is about 1.7446V, and the temperature drift coefficient is 11.08ppm, so V 1n The corresponding output voltage can be set to 1.7V, and according to V 1n The resistance values ​​of R3 and R4 are set accordingly. Similarly, the resistance values ​​of different resistors can be configured under different process angle types. Table 1 shows the voltage output of each port under different process angle states. When actually setting, you can refer to Table 1 for circuit design and implementation, or you can design it in combination with different requirements. This embodiment does not limit it.

[0038] Table 1

[0039]

[0040]

[0041] In some embodiments, the detection circuit may further include a compensation unit for compensating for the transistor to be trimmed whose electrical characteristics have changed in the chip to be tested according to the process angle type of the chip to be tested determined by the logic result output unit, so that the transconductance between the two ends of the transistor to be trimmed and the bias voltage is the same under different process angle states.

[0042] Specifically, the compensation unit includes at least an N-type transistor trimming array and a P-type transistor trimming array; wherein the N-type transistor trimming array is used to compensate the N-type transistor to be trimmed, and the P-type transistor trimming array is used to compensate the P-type transistor to be trimmed.

[0043] Figure 6 The circuit structure diagram of the N-type transistor trimming array is shown, which mainly includes the first switch to the tenth switch, the first N-type trimming transistor N1 to the tenth N-type trimming transistor N10, wherein one end of the first switch S1, the second switch S2, the third switch S3, the fourth switch S4 and the fifth switch S5 are simultaneously connected to the output end of the logic result output unit 30, the other end of the first switch S1 is connected to the drain of the first N-type trimming transistor N1, the other end of the second switch S2 is connected to the drain of the second N-type trimming transistor N2, the other end of the third switch S3 is connected to the drain of the third N-type trimming transistor N3, the other end of the fourth switch S4 is connected to the drain of the fourth N-type trimming transistor N4, the other end of the fifth switch S5 is connected to the drain of the fifth N-type trimming transistor N5, and one end of the sixth switch S6, the seventh switch S7, the eighth switch S8, the ninth switch S9 and the tenth switch S10 are simultaneously connected The other end of the sixth switch S6 is connected to the drain of the sixth N-type trimming transistor N6, the other end of the seventh switch S7 is connected to the drain of the seventh N-type trimming transistor N7, the other end of the eighth switch S8 is connected to the drain of the eighth N-type trimming transistor N8, the other end of the ninth switch S9 is connected to the drain of the ninth N-type trimming transistor N9, the other end of the tenth switch S10 is connected to the drain of the tenth N-type trimming transistor N10, the sources of the sixth N-type trimming transistor N6 to the tenth N-type trimming transistor N10 are simultaneously connected to the source of the N-type transistor to be trimmed N0, the sources of the first N-type trimming transistor N1 to the fifth N-type trimming transistor N5 are simultaneously connected to the drain of the N-type transistor to be trimmed N0, and the gates of all the N-type trimming transistors and the gates of the N-type transistor to be trimmed are connected to the bias voltage Vb.

[0044] Figure 7The circuit structure diagram of the P-type transistor trimming array is shown, which mainly includes the eleventh switch S11 to the twentieth switch S20, the first P-type trimming transistor P1 to the tenth P-type trimming transistor P10, wherein one end of the eleventh switch S11, the twelfth switch S12, the thirteenth switch S13, the fourteenth switch S14 and the fifteenth switch S15 are connected to the output end of the logic result output unit 30 at the same time, the other end of the eleventh switch S11 is connected to the drain of the first P-type trimming transistor P1, the other end of the twelfth switch S12 is connected to the drain of the second P-type trimming transistor P2, the other end of the thirteenth switch S13 is connected to the drain of the third P-type trimming transistor P3, the other end of the fourteenth switch S14 is connected to the drain of the fourth P-type trimming transistor P4, the other end of the fifteenth switch S15 is connected to the drain of the fifth P-type trimming transistor P5, the sixteenth switch S16, the seventeenth switch S17, the eighteenth switch S18, the nineteenth switch S19 and the fifteenth switch S20 are connected to the drain of the fifth P-type trimming transistor P5, and the sixteenth switch S16, the seventeenth switch S17, the eighteenth switch S18, the nineteenth switch S19 and the fifteenth switch S20 are connected to the drain of the fifth P-type trimming transistor P5. One end of the twentieth switch S20 is connected to the sources of the first P-type trimming transistor P1 to the fifth P-type trimming transistor P5 at the same time, the other end of the sixteenth switch S16 is connected to the drain of the sixth P-type trimming transistor P6, the other end of the seventeenth switch S17 is connected to the drain of the seventh P-type trimming transistor P7, the other end of the eighteenth switch S18 is connected to the drain of the eighth P-type trimming transistor P8, the other end of the nineteenth switch S19 is connected to the drain of the ninth P-type trimming transistor P9, the other end of the twentieth switch S20 is connected to the drain of the tenth P-type trimming transistor P10, the sources of the sixth P-type trimming transistor P6 to the tenth P-type trimming transistor P10 are connected to the source of the P-type transistor to be trimmed P0 at the same time, the sources of the first P-type trimming transistor P1 to the fifth P-type trimming transistor P5 are connected to the drain of the P-type transistor to be trimmed P0 at the same time, and the gates of all the P-type trimming transistors P and the gate of the P-type transistor to be trimmed P0 are connected to the bias voltage Vb.

[0045] Corresponding to the above-mentioned compensation unit, the first switch S1, the sixth switch S6, the eleventh switch S11 and the sixteenth switch S16 are closed when the logic result output unit outputs that the chip to be tested is a typical angle; the second switch S2, the seventh switch S7, the twelfth switch S12 and the seventeenth switch S17 are closed when the logic result output unit outputs that the chip to be tested is a slow N-type and a slow P-type; the third switch S3, the eighth switch S8, the thirteenth switch S13S and the eighteenth switch S18 are closed when the logic result output unit outputs that the chip to be tested is a fast N-type and a fast P-type; the fourth switch S4, the ninth switch S9, the fourteenth switch S14 and the nineteenth switch S19 are closed when the logic result output unit outputs that the chip to be tested is a fast N-type and a slow P-type; the fifth switch S5, the tenth switch S10, the fifteenth switch S15 and the twentieth switch S20 are closed when the logic result output unit outputs that the chip to be tested is a slow N-type and a fast P-type.

[0046] like Figure 6 and Figure 7 As shown, the compensation unit receives the voltage signals TT, SS, FF, FS, and SF output by the logic result output unit under different process conditions. When the corresponding voltage signal is high, the corresponding switch is closed, and then the size of each transistor is adjusted so that Gm ab,tt =Gm ab,ss =Gm ab,ff =Gm ab,sf =Gm ab,fs . Where Gm ab,tt Gm is the transconductance between AB and Vb voltage in TT process corner state. ab,ss Gm is the transconductance between AB and Vb voltage in SS process corner state. ab,ff Gm is the transconductance between AB and Vb voltage in FF process corner state. ab,fs Gm is the transconductance between AB and Vb voltage in FS process corner state, ab,sf It is the transconductance between AB and Vb voltage in SF process corner state.

[0047] by Figure 6 For example, the width-to-length ratio of the transistor N0 to be adjusted is set to W0 / L0, the width-to-length ratio of the sixth N-type adjustment transistor N6 connected in parallel is set to W6 / L6, and the width-to-length ratio of the first N-type adjustment transistor N1 connected in series is set to W1 / L1, satisfying L0=L6, W1=W0+W6. Figure 8 As shown, the equivalent transistor at both ends of AC is Neq, and its width-to-length ratio is (W0+W6) / L0, as shown in Fig. 9 As shown, the equivalent transistor at both ends of AB is N0tt, and its width-to-length ratio is (W0+W6) / (L0+L1).

[0048]

[0049] Among them, μ n,tt is the electron mobility under the TT process corner state, V gs,NOtt is the gate-source voltage difference of the equivalent transistor N0tt under the TT process corner state, V th,N0tt is the threshold voltage of the equivalent transistor N0tt in the TT process corner state, It is the width-to-length ratio of the equivalent transistor N0tt in the TT process corner state.

[0050] By analogy, we can get:

[0051]

[0052] Among them, μ n,tt is the electron mobility under the TT process corner state, V gs,NOttis the gate-source voltage difference of the equivalent transistor N0tt under the TT process corner state, V th,N0tt is the threshold voltage of the equivalent transistor N0tt in the TT process corner state. By adjusting the size of the equivalent transistor Make Gm ab,tt =Gm ab,ss =Gm ab,ff =Gm ab,sf =Gm ab,fs Established.

[0053] In this embodiment, the process angle detection circuit outputs a voltage that is independent of temperature but related to the process angle, and outputs a voltage that is independent of both temperature and process angle, and uses the comparison result of the two to reflect the process angle state, and finally outputs the logic operation results representing different process angle types through the logic result output unit, so as to achieve rapid and accurate detection of the process angle of the chip to be tested. The entire circuit structure is simple and easy to implement. At the same time, the compensation unit is used to compensate for the transistors in the chip with electrical characteristics changes, so that the chip performance is stable.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A chip process angle detection circuit, characterized in that: include: A process angle detection unit, used for collecting three groups of comparison signals in the chip to be tested, each group of the comparison signals includes a first voltage signal related to the process angle and independent of temperature, and a second voltage signal independent of both the process angle and temperature; a comparison unit, used to determine a comparison result between two voltage signals of each set of comparison signals; The logic result output unit is used to perform different preset types of logic operations on all the comparison results, and determine the process angle type of the chip to be tested according to the logic operation results.

2. The detection circuit according to claim 1, characterized in that: The process angle detection unit at least includes: a first detection circuit, a second detection circuit, a third detection circuit, a first reference circuit, a second reference circuit and a third reference circuit; wherein, The first detection circuit includes a first N-type transistor and a first resistor in the chip to be tested, the drain and gate of the first N-type transistor are connected to the working voltage, the source of the first N-type transistor is connected to the first end of the first resistor and leads to a first voltage signal of a first group of comparison signals, and the second end of the first resistor is grounded; The second detection circuit includes a first P-type transistor and a second resistor in the chip to be tested, the source and gate of the first P-type transistor are connected to the working voltage, the drain of the first P-type transistor is connected to the first end of the second resistor and leads to a first voltage signal of the second group of comparison signals, and the second end of the second resistor is grounded; The third detection circuit includes a second N-type transistor and a second P-type transistor in the chip to be tested, the source of the second P-type transistor is connected to the working voltage, the gate of the second P-type transistor is connected to the gate of the second N-type transistor, the drain of the second P-type transistor is connected to the drain of the second N-type transistor and leads to a first voltage signal of the third group of comparison signals, and the source of the second N-type transistor is grounded; The first reference circuit comprises a third resistor and a fourth resistor connected in series to a working voltage and a ground terminal, and a second voltage signal of the first group of comparison signals is drawn between the third resistor and the fourth resistor; The second reference circuit comprises a fifth resistor and a sixth resistor connected in series to the working voltage and the ground terminal, and a second voltage signal of the second group of comparison signals is drawn between the fifth resistor and the sixth resistor; The third reference circuit includes a seventh resistor and an eighth resistor connected in series to a working voltage and a ground terminal, and a second voltage signal of the third group of comparison signals is derived between the seventh resistor and the eighth resistor.

3. The detection circuit according to claim 2, characterized in that: The comparison unit at least includes: a first comparator, a second comparator and a third comparator; wherein, The non-inverting input terminal of the first comparator is connected to the first voltage signal of the first group of comparison signals, the inverting input terminal of the first comparator is connected to the second voltage signal of the first group of comparison signals, and the output terminal of the first comparator outputs a first comparison result; The non-inverting input terminal of the second comparator is connected to the first voltage signal of the second group of comparison signals, the inverting input terminal of the second comparator is connected to the second voltage signal of the second group of comparison signals, and the output terminal of the second comparator outputs a second comparison result; The non-inverting input terminal of the third comparator is connected to the first voltage signal of the third group of comparison signals, the inverting input terminal of the third comparator is connected to the second voltage signal of the third group of comparison signals, and the output terminal of the third comparator outputs a third comparison result.

4. The detection circuit according to claim 3, characterized in that: The logic result output unit at least includes a first logic operation circuit, a second logic operation circuit, a third logic operation circuit, a fourth logic operation circuit and a fifth logic operation circuit, and all logic operation circuits are three-input AND gates; wherein, The first input terminal of the first logic operation circuit is connected to the first comparison result, the second input terminal of the first logic operation circuit is connected to the inverted signal of the second comparison result, and the third input terminal of the first logic operation circuit is connected to the inverted signal of the third comparison result; The first input terminal of the second logic operation circuit is connected to the inverted signal of the first comparison result, the second input terminal of the second logic operation circuit is connected to the inverted signal of the second comparison result, and the third input terminal of the second logic operation circuit is connected to the inverted signal of the third comparison result; The first input terminal of the third logic operation circuit is connected to the first comparison result, the second input terminal of the third logic operation circuit is connected to the second comparison result, and the third input terminal of the third logic operation circuit is connected to the inverted signal of the third comparison result; The first comparison result is connected to the first input terminal of the fourth logic operation circuit, the inverted signal of the second comparison result is connected to the second input terminal of the fourth logic operation circuit, and the third comparison result is connected to the third input terminal of the fourth logic operation circuit; The first input terminal of the fifth logic operation circuit is connected to the inverted signal of the first comparison result, the second input terminal of the fifth logic operation circuit is connected to the second comparison result, and the third input terminal of the fifth logic operation circuit is connected to the inverted signal of the third comparison result.

5. The detection circuit according to claim 4, characterized in that: The process angle types include at least: typical angle, fast N-type slow P-type, slow N-type fast P-type, fast N-type fast P-type and slow N-type slow P-type; wherein, The output result of the first logic operation circuit is used to indicate whether the chip to be tested is a typical corner; The output result of the second logic operation circuit is used to indicate whether the chip to be tested is a slow N-type or slow P-type chip; The output result of the third logic operation circuit is used to indicate whether the chip to be tested is a fast N-type fast P-type; The output result of the fourth logic operation circuit is used to indicate whether the chip to be tested is a fast N-type and slow P-type chip; The output result of the fifth logic operation circuit is used to indicate whether the chip to be tested is a slow N-type and fast P-type chip.

6. The detection circuit according to claim 4, characterized in that: When the temperature changes, the resistance value of the equivalent resistor of the first N-type transistor remains the same as the resistance value of the first resistor, the resistance value of the equivalent resistor of the first P-type transistor remains the same as the resistance value of the second resistor, and the resistance value of the equivalent resistor of the second P-type transistor remains the same as the resistance value of the equivalent resistor of the second N-type transistor.

7. The detection circuit according to claim 4, characterized in that: The resistance values ​​of the third resistor and the fourth resistor satisfy the following condition: a difference between a first voltage signal of the first group of comparison signals and a second voltage signal of the first group of comparison signals determined according to the resistance values ​​of the third resistor and the fourth resistor is greater than a threshold voltage of the first comparator; The resistance values ​​of the fifth resistor and the sixth resistor satisfy the following condition: a difference between a first voltage signal of the second set of comparison signals and a second voltage signal of the second set of comparison signals determined according to the resistance values ​​of the fifth resistor and the sixth resistor is greater than a threshold voltage of the second comparator; The resistance values ​​of the seventh resistor and the eighth resistor satisfy the following condition: a difference between a first voltage signal of a third group of comparison signals and a second voltage signal of the third group of comparison signals determined according to the resistance values ​​of the seventh resistor and the eighth resistor is greater than a threshold voltage of the third comparator.

8. The detection circuit according to any one of claims 1 to 7, characterized in that: Also includes: The compensation unit is used to compensate the transistor to be adjusted whose electrical characteristics have changed in the chip to be tested according to the process angle type of the chip to be tested determined by the logic result output unit, so that the transconductance between the two ends of the transistor to be adjusted and the bias voltage is the same under different process angle states.

9. The detection circuit according to claim 8, characterized in that: The compensation unit at least includes: an N-type transistor trimming array and a P-type transistor trimming array; wherein, The N-type transistor trimming array is used to compensate the N-type transistor to be trimmed, and at least includes: a first switch to a tenth switch, a first N-type trimming transistor to a tenth N-type trimming transistor, wherein one end of the first switch, the second switch, the third switch, the fourth switch and the fifth switch are simultaneously connected to the output end of the logic result output unit, the other end of the first switch is connected to the drain of the first N-type trimming transistor, the other end of the second switch is connected to the drain of the second N-type trimming transistor, the other end of the third switch is connected to the drain of the third N-type trimming transistor, the other end of the fourth switch is connected to the drain of the fourth N-type trimming transistor, the other end of the fifth switch is connected to the drain of the fifth N-type trimming transistor, and one end of the sixth switch, the seventh switch, the eighth switch, the ninth switch and the tenth switch are simultaneously connected to the output end of the first N-type trimming transistor. a first N-type trimming transistor to the source of the fifth N-type trimming transistor, the other end of the sixth switch is connected to the drain of the sixth N-type trimming transistor, the other end of the seventh switch is connected to the drain of the seventh N-type trimming transistor, the other end of the eighth switch is connected to the drain of the eighth N-type trimming transistor, the other end of the ninth switch is connected to the drain of the ninth N-type trimming transistor, the other end of the tenth switch is connected to the drain of the tenth N-type trimming transistor, the source of the sixth N-type trimming transistor to the tenth N-type trimming transistor is simultaneously connected to the source of the N-type transistor to be trimmed, the source of the first N-type trimming transistor to the fifth N-type trimming transistor is simultaneously connected to the drain of the N-type transistor to be trimmed, and the gates of all the N-type trimming transistors and the gates of the N-type transistors to be trimmed are connected to a bias voltage; The P-type transistor trimming array is used to compensate for a P-type transistor to be trimmed, and at least includes: an eleventh switch to a twentieth switch, and a first P-type trimming transistor to a tenth P-type trimming transistor, wherein one end of the eleventh switch, the twelfth switch, the thirteenth switch, the fourteenth switch and the fifteenth switch are simultaneously connected to the output end of the logic result output unit, the other end of the eleventh switch is connected to the drain of the first P-type trimming transistor, the other end of the twelfth switch is connected to the drain of the second P-type trimming transistor, the other end of the thirteenth switch is connected to the drain of the third P-type trimming transistor, the other end of the fourteenth switch is connected to the drain of the fourth P-type trimming transistor, the other end of the fifteenth switch is connected to the drain of the fifth P-type trimming transistor, and one end of the sixteenth switch, the seventeenth switch, the eighteenth switch, the nineteenth switch and the twenty-first switch are simultaneously connected to the output end of the logic result output unit, and the other end of the eleventh switch is connected to the drain of the first P-type trimming transistor, the other end of the twelfth switch is connected to the drain of the second P-type trimming transistor, the other end of the thirteenth switch is connected to the drain of the third P-type trimming transistor, the other end of the fourteenth switch is connected to the drain of the fourth P-type trimming transistor, the other end of the fifteenth switch is connected to the drain of the fifth P-type trimming transistor, and one end of the sixteenth switch, the seventeenth switch, the eighteenth switch, the nineteenth switch and the twenty-first switch are simultaneously connected to the output end of the logic result output unit. The first P-type trimming transistor is connected to the source of the fifth P-type trimming transistor, the other end of the sixteenth switch is connected to the drain of the sixth P-type trimming transistor, the other end of the seventeenth switch is connected to the drain of the seventh P-type trimming transistor, the other end of the eighteenth switch is connected to the drain of the eighth P-type trimming transistor, the other end of the nineteenth switch is connected to the drain of the ninth P-type trimming transistor, the other end of the twentieth switch is connected to the drain of the tenth P-type trimming transistor, the source of the sixth P-type trimming transistor to the tenth P-type trimming transistor is simultaneously connected to the source of the P-type transistor to be trimmed, the source of the first P-type trimming transistor to the fifth P-type trimming transistor is simultaneously connected to the drain of the P-type transistor to be trimmed, and the gates of all the P-type trimming transistors and the gates of the P-type transistors to be trimmed are connected to the bias voltage.

10. The detection circuit according to claim 9, characterized in that: The first switch, the sixth switch, the eleventh switch and the sixteenth switch are closed when the logic result output unit outputs that the chip under test is a typical angle; The second switch, the seventh switch, the twelfth switch and the seventeenth switch are closed when the logic result output unit outputs that the chip under test is a slow N-type or slow P-type; The third switch, the eighth switch, the thirteenth switch and the eighteenth switch are closed when the logic result output unit outputs that the chip under test is a fast N-type fast P-type; The fourth switch, the ninth switch, the fourteenth switch, and the nineteenth switch are closed when the logic result output unit outputs that the chip under test is a fast N-type and a slow P-type; The fifth switch, the tenth switch, the fifteenth switch, and the twentieth switch are closed when the logic result output unit outputs that the chip under test is a slow N-type and a fast P-type.

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