Method and system for judging quality of test data of integrated chip package under non-normal distribution

Abstract

The application discloses a non-normal distribution integrated chip packaging test data quality judgment method and system, belongs to the integrated chip detection technical field, solves how to judge the integrated chip packaging quality under the non-normal distribution, and judges the integrated chip packaging quality by judging the integrated chip packaging test data distribution, selecting different methods to calculate the process capability index of the test data according to the test data distribution, and judging the integrated chip packaging quality grade according to the data concentration degree and process offset degree in the process capability index. When the integrated chip packaging test data is in the non-normal distribution, 1% significance level is used to filter out the interference data with too large offset and replace the process mean with the wave peak mean, so that the process capability index calculated by the integrated chip packaging test data under the non-normal distribution has stronger anti-interference capability, and the reliability of the integrated chip packaging quality judgment is higher.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated chip detection, and relates to a method and system for judging the quality of test data of an integrated chip under non-normal distribution. BACKGROUND

[0002] In today's rapidly developing information technology, integrated circuits, as the core and foundation of the modern information technology industry, are facing unprecedented challenges and opportunities. However, the traditional integrated circuit technology route has encountered the bottlenecks of "power wall", "storage wall" and "area wall", and it is difficult to meet the growing computing demand. In order to break through these limitations, a new technical solution-chiplet technology has emerged, which integrates several chiplets together to form a high-performance and function-rich integrated chip to meet the diverse application needs. Integrated chip technology opens up a new path for the development of China's integrated circuit industry. Through independent research and development and the driving of large-scale market demand, integrated chip technology not only effectively meets the current needs, but also drives the progress of the entire industry chain.

[0003] Integrated chip technology can break through the limitations of current chip manufacturing area, promote the continuous improvement of chip integration and computing power, and break through the bottlenecks of traditional packaging technology. Through chiplet pre-assembly, the chip design cycle is reduced, and each chiplet in the integrated chip is manufactured separately through different processes, which can break through the limitations of a single process. As the integrated circuit process enters below 5nm, size miniaturization approaches the physical limit and brings many problems such as chip yield and wafer utilization rate, and the slowing down of Moore's Law has become an important challenge for the development of integrated chips at home and abroad.

[0004] The existing integrated chip uses a new design paradigm of "decomposition-combination-integration". "Decomposition" is to abstract several chiplet pre-assemblies according to different characteristics, "combination" is to form a special chip and system according to the needs of the pre-assemblies, and "integration" is to obtain an integrated chip according to specific needs. Integrated chip packaging testing is the last testing link after integrated chip packaging, and the tested integrated chip will be delivered to the customer. Integrated chip packaging has a crucial impact on the entire production and manufacturing process and the final testing, so there is an urgent need for a method to study the quality of integrated chip packaging.

[0005] With the rapid development of modern economic system, product quality has become a key indicator to assess the competitiveness of enterprises. The gradual development and evolution of product quality management methods have significantly improved the performance of enterprises' products in the market, and the improvement of product quality has brought about the reduction of production cost and the enhancement of customer satisfaction and brand influence. Process capability index reflects whether the quality of products produced in the manufacturing process can be within the specified range, so as to meet the quality standards required by customers. How to calculate the process capability index and use it to evaluate the quality of products has been a problem that engineers have been trying to solve. The invention patent with the application publication number CN118034221A discloses a quality control system for multi-type microwave assembly mixed-line production, calculates the product parameter data, process parameter data and equipment parameter data, obtains the process capability index CPK and transmits it to the process control system, and controls the product production state according to the evaluation result corresponding to the process capability index CPK. However, in the field of integrated chip detection, when judging the packaging quality of integrated chips, researchers only use experience to make judgments, and have not proposed a related method for systematically judging the packaging quality of integrated chips using integrated chip packaging test data, especially when the test data is not normally distributed, there is no suitable method to calculate the process capability index of integrated chip packaging test data, therefore, it is urgent to design a method for judging the packaging quality of integrated chips under non-normal distribution based on process capability index. SUMMARY

[0006] The technical problem to be solved by the present application is how to judge the packaging quality of integrated chips under non-normal distribution.

[0007] The present application solves the above technical problems by the following technical solutions:

[0008] The method for judging the quality of integrated chip packaging test data under non-normal distribution comprises the following steps:

[0009] Step 1, selecting integrated chip packaging test data;

[0010] Step 2, using AD test to judge the distribution of integrated chip packaging test data;

[0011] Step 3, calculating the process capability index of integrated chip packaging test data under normal distribution;

[0012] Step 4, calculating the process capability index of integrated chip packaging test data under non-normal distribution;

[0013] Step 5, using the data concentration degree and the process overall deviation degree to jointly judge the quality classification of integrated chip packaging.

[0014] Further, the step 1 is specifically: obtaining corresponding test data obtained after the integrated chip package test, the test data type including any type of test data such as voltage, current or time, and randomly taking a group of n data as sample data set, wherein n≥50 and n is an integer.

[0015] Further, the step 2 is specifically: using AD test to judge whether the integrated chip package test data satisfies normal distribution, and giving AD normality test definition.

[0016] The step of using AD test to judge whether the integrated chip package test data satisfies normal distribution is specifically: calculating test statistic and critical value, if the test statistic is greater than the critical value, the original hypothesis is rejected, it is considered that the sample data does not conform to normal distribution, and step 4 is executed; if the test statistic is less than the critical value, the original hypothesis is not rejected, it is considered that the sample data is subject to normal distribution, and step 3 is executed.

[0017] The AD normality test definition includes:

[0018] The original hypothesis H0: the data is subject to normal distribution;

[0019] The alternative hypothesis H1: the data is subject to non-normal distribution.

[0020] Further, the step 3 includes the following steps:

[0021] Step 31, presetting process specification upper limit USL and process specification lower limit LSL;

[0022] Step 32, calculating process standard deviation σ and process mean μ of the normal distribution sample data set of the integrated chip package test data;

[0023] Step 33, calculating the data concentration, and the data concentration expression is as follows:

[0024]

[0025] In the formula, C p represents the data concentration, and d represents the process specification upper and lower limit distance.

[0026] Step 34, calculating the process overall offset degree, and executing step 5; the process overall offset degree is as follows:

[0027]

[0028] In the formula, C pk represents the process overall offset degree.

[0029] Further, the step 4 includes the following steps:

[0030] Step 41: Preset the upper limit of process specification (USL) and the lower limit of process specification (LSL);

[0031] Step 42: Calculate the degree of data centrality. The expression for the degree of data centrality is as follows:

[0032]

[0033] In the formula, C p F represents the degree of data centrality. 0.005 F represents the x-axis value of the area representing 0.5% of the span of the integrated chip package test data. 0.995 The x-axis value represents the 99.5% area span of the integrated chip package test data.

[0034] Step 43: Obtain the peak value X from the line graph of the integrated chip packaging test data. i The number of data points Y within the histogram boundary i Calculate the peak mean M m The peak mean M m The expression is as follows:

[0035]

[0036] Step 44: Calculate the overall process offset and proceed to step 5; the overall process offset is as follows:

[0037]

[0038] In the formula, C pk This indicates the overall degree of deviation in the process.

[0039] Furthermore, step 5 includes the following steps:

[0040] Step 51: Set the data concentration level C p Grade, according to C p The magnitude of the value is used to classify the degree of centralization of the integrated chip package test data;

[0041] Step 52: Set the overall offset degree C of the process. pk Grade, according to C pk The magnitude of the value is used to classify the overall deviation of the integrated chip packaging test data process;

[0042] Step 53: Set the integrated chip packaging quality level, classify the integrated chip packaging quality according to the judgment criteria, and implement the corresponding processing principles for the graded integrated chips.

[0043] Further, step 51 specifically includes:

[0044] When C pWhen the value is greater than 2.0, the data concentration degree is A level;

[0045] When C p When the value is greater than 1.5 and less than 2.0, the data concentration degree is B level;

[0046] When C p When the value is greater than 1.33 and less than 1.5, the data concentration degree is C level;

[0047] When C p When the value is greater than 1.0 and less than 1.33, the data concentration degree is D level;

[0048] When C p When the value is less than 1.0, the data concentration degree is E level.

[0049] Further, the step 52 is specifically:

[0050] When C pk When the value is greater than 2.0, the process overall deviation degree is A level;

[0051] When C pk When the value is greater than 1.5 and less than 2.0, the process overall deviation degree is B level;

[0052] When C pk When the value is greater than 1.33 and less than 1.5, the process overall deviation degree is C level;

[0053] When C pk When the value is greater than 1.0 and less than 1.33, the process overall deviation degree is D level;

[0054] When C pk When the value is less than 1.0, the process overall deviation degree is E level.

[0055] Further, the step 53 is specifically:

[0056] When the data concentration degree and the process overall deviation degree are both A level, the integrated chip packaging quality is I level, which means that the integrated chip packaging quality is very good, but the process quality related to the data concentration degree and the process overall deviation degree can be reduced to reduce the cost;

[0057] When one of the data concentration degree and the process overall deviation degree is A level and the other is B level, the integrated chip packaging quality is II level, which means that the integrated chip packaging quality is very good, and the process quality related to the data concentration degree and the process overall deviation degree can be appropriately reduced to reduce the cost;

[0058] When one of the data concentration degree and the process overall deviation degree is A level and the other is C level, the integrated chip packaging quality level is III level, indicating that the integrated chip packaging quality is very good, and the process quality related to A level can be appropriately reduced to reduce the cost;

[0059] When one of the data concentration degree and the process overall deviation degree is B level and the other is C level, the integrated chip packaging quality level is IV level, indicating that the integrated chip packaging quality is better and no improvement is needed;

[0060] When one of the data concentration degree and the process overall deviation degree is A level and the other is D level, the integrated chip packaging quality level is V level, indicating that the integrated chip packaging quality is acceptable, and the process quality related to A level can be appropriately reduced to reduce the cost, and the process quality related to D level needs to be appropriately improved for the products with strict process requirements;

[0061] When one of the data concentration degree and the process overall deviation degree is B level and the other is D level, the integrated chip packaging quality level is VI level, indicating that the integrated chip packaging quality is acceptable, but the process quality related to D level needs to be appropriately improved for the products with strict process requirements;

[0062] When one of the data concentration degree and the process overall deviation degree is C level and the other is D level, the integrated chip packaging quality level is VII level, indicating that the integrated chip packaging quality is acceptable, but all the process quality needs to be appropriately improved for the products with strict process requirements;

[0063] When one of the data concentration degree and the process overall deviation degree is E level, the integrated chip packaging quality level is VIII level, indicating that the integrated chip packaging quality is poor and needs to be immediately improved.

[0064] The integrated chip packaging test data quality judgment system under non-normal distribution includes a data selection module, a data distribution module, a normal distribution module, a non-normal distribution module, and a quality grading module.

[0065] The data selection module is used to select integrated chip packaging test data.

[0066] The data distribution module is used to determine the distribution of integrated chip packaging test data using AD test.

[0067] The normal distribution module is used to calculate the process capability index under the normal distribution of integrated chip packaging test data.

[0068] The non-normal distribution module is used to calculate the process capability index under the non-normal distribution of integrated chip packaging test data.

[0069] The quality grading module is used for jointly judging the quality grading of the integrated chip package by using the data concentration degree and the process overall offset degree.

[0070] The present application has the advantages of:

[0071] (1) The present application judges the integrated chip package test data distribution, selects different methods to calculate the process capability index of the test data according to the test data distribution, and judges the integrated chip package quality level according to the data concentration degree and the process offset degree in the process capability index; when the integrated chip package test data is non-normal distribution, 1% significance level is used to filter out the data with too large offset and replace the process mean with the peak mean, so that the process capability index calculated by the integrated chip package test data under non-normal distribution has stronger anti-interference ability, the reliability when judging the integrated chip package quality is higher, the integrated chip package quality can be accurately judged, compared with the traditional method, the integrated chip package quality can be obviously graded, and the advantages of easy simulation calculation and intuitive observation of chip package quality are achieved.

[0072] (2) The present application uses the process capability index to evaluate the integrated chip package quality, can detect the weak link in the integrated chip package process, detect whether there is potential package quality problem and process improvement space in the integrated chip package process, improve the overall quality of the integrated chip package, and is beneficial to avoid unqualified products flowing into the market to cause repair and recovery loss. BRIEF DESCRIPTION OF DRAWINGS

[0073] Figure 1 is a flow chart of the quality judgment method of the integrated chip package test data under non-normal distribution of the first embodiment of the present application;

[0074] Figure 2 is a probability density distribution graph of the integrated chip package test data under non-normal distribution of the first embodiment of the present application;

[0075] Figure 3 is a data line graph of the integrated chip package test data under non-normal distribution of the first embodiment of the present application. DETAILED DESCRIPTION

[0076] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and completely below in combination with the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0077] The technical solutions of the present application will be further described below in combination with the accompanying drawings and specific embodiments.

[0078] Embodiment one

[0079] As shown in the specific, disclosed is a method for judging the quality of integrated chip packaging test data under non-normal distribution, comprising the following steps: Figure 1

[0080] Step 1, selecting integrated chip packaging test data;

[0081] In this embodiment, first, the corresponding test data obtained after the integrated chip packaging test is acquired, the test data type includes voltage (V), current (A) or time (s) or any other type of test data, from which a group of n data is randomly taken as the sample data set of this embodiment, the sample data set can be randomly selected according to customer requirements, or it can be selected at will, wherein n≥50 and n is an integer.

[0082] Step 2, using AD test to judge the distribution of integrated chip packaging test data;

[0083] In this embodiment, AD test is used to judge whether the integrated chip packaging test data meets normal distribution, and the definition of AD normality test is given.

[0084] AD test is a statistical method for testing whether the sample data conforms to a specific distribution, AD test compares the difference between the distribution of sample data and the theoretical distribution (such as normal distribution) to determine whether the data conforms to the distribution, in this embodiment, AD test is used to judge whether the integrated chip packaging test data conforms to normal distribution, and the method for calculating the process capability index is determined according to the distribution of the tested integrated chip data.

[0085] Since the data distribution of integrated chip packaging test does not always conform to normal distribution, especially when the data is affected by non-ideal production conditions, test environment and other complex factors, therefore, AD test can help to judge the distribution characteristics of test data, so as to select the appropriate statistical analysis method

[0086] Further, the use of AD test to judge whether the integrated chip packaging test data meets normal distribution is specifically:

[0087] Calculate the test statistic and the critical value, if the test statistic is greater than the critical value, reject the original hypothesis, consider that the sample data does not conform to normal distribution, and execute step 4; if the test statistic is less than the critical value, do not reject the original hypothesis, consider that the sample data conforms to normal distribution, and execute step 3.

[0088] Further, the definition of AD normality test includes:

[0089] ​Original hypothesis H0: data is subject to normal distribution;

[0090] Alternative hypothesis H1: data is subject to non-normal distribution.

[0091] Step 3, calculate the process capability index of the integrated chip package test data under normal distribution;

[0092] In this embodiment, when calculating the process capability index of the integrated chip package test data under normal distribution, the upper and lower limits of the process specification need to be given, and the process standard deviation and the process mean are calculated.

[0093] Further, the step 3 includes the following specific steps:

[0094] Step 31, preset the upper limit USL and the lower limit LSL of the process specification;

[0095] Step 32, calculate the process standard deviation σ and the process mean μ of the normal distribution sample data set of the integrated chip package test data;

[0096] Step 33, calculate the data concentration, and the expression of the data concentration is as follows:

[0097]

[0098] In the formula, C p represents the data concentration, d represents the distance between the upper and lower limits of the process specification, and in this embodiment

[0099] Step 34, calculate the overall process offset degree, and execute step 5; the overall process offset degree is as follows:

[0100]

[0101] In the formula, C pk represents the overall process offset degree.

[0102] Step 4, calculate the process capability index of the integrated chip package test data under non-normal distribution;

[0103] Since the process capability index tests the concentration and offset of the test data, step 3 is only effective when the test data is subject to normal distribution; when the data is subject to non-normal distribution, the concentration and offset of the test data need to be recalculated after the data is processed.

[0104] In this embodiment, when calculating the process capability index of the integrated chip package test data under non-normal distribution, unlike the process capability index under normal distribution, this embodiment uses the horizontal coordinate corresponding to the area span in the probability density distribution diagram to replace the process standard deviationFigure 2 As shown, the mean of the peaks in the line chart is used to replace the process mean. Figure 3 As shown.

[0105] Furthermore, step 4 includes the following specific steps:

[0106] Step 41: Preset the upper limit of process specification (USL) and the lower limit of process specification (LSL);

[0107] Step 42: Calculate the x-axis value F of the area representing 0.5% of the span of the integrated chip package test data. 0.005 And the x-axis value F of the area spanning 99.5%. 0.995 , use F 0.995 -F 0.005 Instead of 6σ in step 3, the degree of data concentration is calculated, and the expression for the degree of data concentration is as follows:

[0108]

[0109] In the formula, F 0.005 F represents the x-axis value of the area representing 0.5% of the span of the integrated chip package test data. 0.995 The x-axis value represents the 99.5% area span of the integrated chip package test data.

[0110] Step 43: Obtain the peak value X in the line graph of the integrated chip packaging test data. i The number of data points Y within the histogram boundaries i Calculate the peak mean M m The peak mean M m The expression is as follows:

[0111]

[0112] Step 44: Calculate the overall process offset and proceed to step 5; the overall process offset is as follows:

[0113]

[0114] In this embodiment, the above-mentioned data centralization level C p And the overall offset degree of the process C pk The calculation is independent of the process standard deviation σ and the process mean μ. By using a 1% significance level to filter out interference data with excessive offset and replacing the process mean with the peak mean, the process capability index calculated from integrated chip packaging test data under non-normal distribution will have stronger anti-interference ability and higher reliability in judging the quality of integrated chip packaging.

[0115] The result calculated based on the traditional process capability index calculation method under the non-normal distribution is often high or low, and cannot clearly classify the integrated chip packaging quality. The traditional method is usually a mathematical calculation method, and it is not simple to intuitively process. The process capability index of the integrated chip packaging test data under the non-normal distribution is calculated based on step 4 of the embodiment, which has the advantages of easy simulation calculation and intuitive observation of chip packaging quality.

[0116] Further, the process capability index calculation method disclosed in step 4 of the embodiment can replace the process standard deviation and process mean in the process capability index calculation method, regardless of whether the integrated chip packaging test data conforms to the normal distribution or the non-normal distribution, to calculate the process capability index. When the integrated chip packaging test data conforms to the non-normal distribution, the calculated data is closer to the true value, so that the method disclosed in the embodiment has a wider range of application compared to other methods, and the judgment of the integrated chip packaging quality is more reliable.

[0117] Step 5, integrated chip packaging quality classification;

[0118] In the embodiment, the data concentration degree C p and the overall process deviation degree C pk are used together to judge the integrated chip packaging quality classification. First, the data concentration degree C p and the overall process deviation degree C pk are rated, and the integrated chip packaging quality level is determined by the two rating results.

[0119] Further, the step 5 includes the following specific steps:

[0120] Step 51, set the data concentration degree C p level, and classify the integrated chip packaging test data concentration degree according to the size of C p value, specifically:

[0121] When the C p value is greater than 2.0, the data concentration degree is A level;

[0122] When the C p value is greater than 1.5 and less than 2.0, the data concentration degree is B level;

[0123] When the C p value is greater than 1.33 and less than 1.5, the data concentration degree is C level;

[0124] When the C p value is greater than 1.0 and less than 1.33, the data concentration degree is D level;

[0125] When the Cp When the value is less than 1.0, the concentration level of the data is level E.

[0126] Step 52: Set the overall offset degree C of the process. pk Grade, according to C pk The magnitude of the value is used to classify the overall offset of the integrated chip packaging test data process, specifically as follows:

[0127] When C pk When the value is greater than 2.0, the overall process offset level is A.

[0128] When C pk When the value is greater than 1.5 and less than 2.0, the overall deviation level of the process is B.

[0129] When C pk When the value is greater than 1.33 and less than 1.5, the overall deviation level of the process is C.

[0130] When C pk When the value is greater than 1.0 and less than 1.33, the overall deviation level of the process is D.

[0131] When C pk When the value is less than 1.0, the overall process offset level is E.

[0132] Step 53: Set the integrated chip packaging quality level, classify the integrated chip packaging quality according to the judgment criteria, and implement the corresponding processing principles for the classified integrated chips, specifically:

[0133] When both the data centralization level and the overall process offset level are A, the integrated chip packaging quality level is I, indicating that the integrated chip packaging quality is very good, but the process quality related to the data centralization level and the overall process offset level can be reduced to reduce costs.

[0134] When either the data centralization level or the overall process offset level is A and the other is B, the integrated chip packaging quality level is II, which means that the integrated chip packaging quality is very good. The process quality related to the data centralization level and the overall process offset level can be appropriately reduced to reduce costs.

[0135] When either the data centralization level or the overall process offset level is A and the other is C, the integrated chip packaging quality level is III, indicating that the integrated chip packaging quality is very good. The process quality related to A can be appropriately reduced to lower costs. For example, if the data centralization level is A and the overall process offset level is C, the process quality related to the data centralization level can be appropriately reduced to lower costs.

[0136] When one of the data concentration degree and the process overall deviation degree is B and the other is C, the integrated chip packaging quality level is IV, indicating that the integrated chip packaging quality is good and no improvement is needed.

[0137] When one of the data concentration degree and the process overall deviation degree is A and the other is D, the integrated chip packaging quality level is V, indicating that the integrated chip packaging quality is acceptable, and the process quality related to A can be appropriately reduced to reduce costs, while the process quality related to D needs to be appropriately improved for products with strict process requirements.

[0138] When one of the data concentration degree and the process overall deviation degree is B and the other is D, the integrated chip packaging quality level is VI, indicating that the integrated chip packaging quality is acceptable, but the process quality related to D needs to be appropriately improved for products with strict process requirements.

[0139] When one of the data concentration degree and the process overall deviation degree is C and the other is D, the integrated chip packaging quality level is VII, indicating that the integrated chip packaging quality is acceptable, but the overall process quality needs to be appropriately improved for products with strict process requirements.

[0140] When one of the data concentration degree and the process overall deviation degree is E, the integrated chip packaging quality level is VIII, indicating that the integrated chip packaging quality is poor and needs to be immediately improved.

[0141] In this embodiment, the integrated chip packaging quality level, determination criteria and processing principles are shown in Table 1 as follows:

[0142] Table 1 Integrated chip packaging quality level, determination criteria and processing principles

[0143]

[0144]

[0145] As can be seen from the above, when the integrated chip packaging quality level is I, it indicates that the integrated chip packaging quality is the best, but the process quality can be reduced to reduce costs. Levels II to VII indicate that the integrated chip packaging process is acceptable, but the overall process quality needs to be appropriately improved for products with strict process requirements. Level VIII indicates that the integrated chip packaging process needs to be immediately improved. This embodiment uses process capability index to evaluate the integrated chip packaging quality, which can detect weak links in the integrated chip packaging process, detect whether there is a potential packaging quality problem and process improvement space in the integrated chip packaging process, improve the overall quality of the integrated chip packaging, and is conducive to avoiding unqualified products flowing into the market to cause repair and recovery losses.

[0146] The application further provides a system for judging quality of integrated chip package test data under non-normal distribution, comprising a data selection module, a data distribution module, a normal distribution module, a non-normal distribution module and a quality grading module.

[0147] The data selection module is used for selecting integrated chip package test data.

[0148] The data distribution module is used for judging distribution of integrated chip package test data by using AD test.

[0149] The normal distribution module is used for calculating process capability index of integrated chip package test data under normal distribution.

[0150] The non-normal distribution module is used for calculating process capability index of integrated chip package test data under non-normal distribution.

[0151] The quality grading module is used for judging quality grading of integrated chip package by using data concentration degree and process overall deviation degree.

[0152] The above examples are only used to illustrate the technical solutions of the application, but not limit the application; although the application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can be modified, or some technical features can be replaced equivalently; and the modification or replacement does not make the essence of the corresponding technical solution deviate from the spirit and scope of the technical solutions of the embodiments of the application.

Claims

1. A method for judging the quality of integrated circuit package test data under non-normal distribution, characterized in that, Includes the following steps: Step 1: Select integrated chip packaging test data; Step 2: Use AD verification to determine the distribution of integrated chip package test data; Step 3: Calculate the process capability index under the normal distribution of integrated chip packaging test data; Step 4: Calculate the process capability index under the non-normal distribution of integrated chip packaging test data; Step 4 includes the following steps: Step 41: Preset the upper limit of process specification (USL) and the lower limit of process specification (LSL); Step 42: Calculate the degree of data centrality. The expression for the degree of data centrality is as follows: In the formula, C p F represents the degree of data centrality. 0.005 F represents the x-axis value of the area representing 0.5% of the span of the integrated chip package test data. 0.995 The x-axis value represents the 99.5% area span of the integrated chip package test data. Step 43: Obtain the peak value X from the line graph of the integrated chip packaging test data. i The number of data points Y within the histogram boundaries i Calculate the peak mean M m The peak mean M m The expression is as follows: Step 44: Calculate the overall process offset and proceed to step 5; the overall process offset is as follows: In the formula, C pk Indicates the overall degree of deviation in the process; Step 5: Use the degree of data centralization and the degree of overall process offset to jointly determine the quality grade of integrated chip packaging.

2. The method for judging the quality of integrated chip packaging test data under non-normal distribution according to claim 1, characterized in that, Step 1 specifically involves: obtaining the corresponding test data after the integrated chip packaging test. The test data types include any type of test data such as voltage, current, or time. A set of n data points is randomly selected as a sample dataset, where n ≥ 50 and n is an integer.

3. The method for judging the quality of integrated chip packaging test data under non-normal distribution according to claim 1, characterized in that, Step 2 specifically involves: using the AD test to determine whether the integrated chip packaging test data meets the normal distribution, and providing the definition of the AD normality test; The process of using the A / D test to determine whether the integrated chip packaging test data conforms to a normal distribution is as follows: calculate the test statistic and the critical value. If the test statistic is greater than the critical value, reject the null hypothesis and consider that the sample data does not conform to a normal distribution, and proceed to step 4. If the test statistic is less than the critical value, the null hypothesis is not rejected, and the sample data is considered to follow a normal distribution. Then proceed to step 3. The definition of the AD normality test includes: Null hypothesis H0: The data follows a normal distribution; Alternative hypothesis H1: The data follows a non-normal distribution.

4. The method for judging the quality of integrated chip packaging test data under non-normal distribution according to claim 3, characterized in that, Step 3 includes the following steps: Step 31: Preset the upper limit of process specification (USL) and the lower limit of process specification (LSL); Step 32: Calculate the process standard deviation σ and process mean μ of the normally distributed sample dataset of integrated chip packaging test data; Step 33: Calculate the degree of data centrality. The expression for the degree of data centrality is as follows: In the formula, C p Indicates the degree of data centralization, where d represents the distance between the upper and lower limits of the process specification; Step 34: Calculate the overall process offset and proceed to step 5; the overall process offset is as follows: In the formula, C pk This indicates the overall degree of deviation in the process.

5. The method for judging the quality of integrated chip packaging test data under non-normal distribution according to claim 1, characterized in that, Step 5 includes the following steps: Step 51: Set the data concentration level C p Grade, according to C p The magnitude of the value is used to classify the degree of centralization of the integrated chip package test data; Step 52: Set the overall offset degree C of the process. pk Grade, according to C pk The magnitude of the value is used to classify the overall deviation of the integrated chip packaging test data process; Step 53: Set the integrated chip packaging quality level, classify the integrated chip packaging quality according to the judgment criteria, and implement the corresponding processing principles for the graded integrated chips.

6. The method for judging the quality of integrated chip packaging test data under non-normal distribution according to claim 5, characterized in that, Step 51 specifically involves: When C p When the value is greater than 2.0, the data concentration level is A. When C p When the value is greater than 1.5 and less than 2.0, the concentration level of the data is B. When C p When the value is greater than 1.33 and less than 1.5, the concentration level of the data is C. When C p When the value is greater than 1.0 and less than 1.33, the concentration level of the data is D. When C p When the value is less than 1.0, the concentration level of the data is level E.

7. The method for judging the quality of integrated chip packaging test data under non-normal distribution according to claim 5, characterized in that, Step 52 specifically involves: When C pk When the value is greater than 2.0, the overall process offset level is A. When C pk When the value is greater than 1.5 and less than 2.0, the overall deviation level of the process is B. When C pk When the value is greater than 1.33 and less than 1.5, the overall deviation level of the process is C. When C pk When the value is greater than 1.0 and less than 1.33, the overall deviation level of the process is D. When C pk When the value is less than 1.0, the overall process offset level is E.

8. The method for judging the quality of integrated chip packaging test data under non-normal distribution according to claim 5, characterized in that, Step 53 specifically involves: When both the data centralization level and the overall process offset level are A, the integrated chip packaging quality level is I, indicating that the integrated chip packaging quality is very good, but the process quality related to the data centralization level and the overall process offset level can be reduced to reduce costs. When either the data centralization level or the overall process offset level is A and the other is B, the integrated chip packaging quality level is II, which means that the integrated chip packaging quality is very good. The process quality related to the data centralization level and the overall process offset level can be appropriately reduced to reduce costs. When either the data centralization level or the overall process offset level is A and the other is C, the integrated chip packaging quality level is III, which means that the integrated chip packaging quality is very good. The process quality related to A level can be appropriately reduced to reduce costs. When either the data centralization level or the overall process offset level is B and the other is C, the integrated chip packaging quality level is IV, indicating that the integrated chip packaging quality is good and no improvement is needed. When either the data centralization level or the overall process offset level is A and the other is D, the integrated chip packaging quality level is V, which means that the integrated chip packaging quality is acceptable. Costs can be reduced by appropriately lowering the process quality related to A. At the same time, for products with strict process requirements, the process quality related to D needs to be appropriately improved. When either the data centralization level or the overall process offset level is B and the other is D, the integrated chip packaging quality level is VI, indicating that the integrated chip packaging quality is acceptable. However, for products with strict process requirements, appropriate improvements to the process quality related to level D are necessary. When either the data centralization level or the overall process offset level is C and the other is D, the integrated chip packaging quality level is VII, indicating that the integrated chip packaging quality is acceptable. However, for products with strict process requirements, appropriate improvements need to be made to the overall process quality. When either the data centralization level or the overall process offset level is level E, the integrated chip packaging quality level is level VIII, indicating poor integrated chip packaging quality and the need for immediate process improvement.

9. A system for judging the quality of integrated chip packaging test data under non-normal distribution, characterized in that, It includes a data selection module, a data distribution module, a normal distribution module, a non-normal distribution module, and a quality grading module; The data selection module is used to select integrated chip packaging test data; The data distribution module is used to determine the distribution of integrated chip packaging test data using AD verification. The normal distribution module is used to calculate the process capability index under the normal distribution of integrated chip packaging test data; The non-normal distribution module is used to calculate the process capability index under the non-normal distribution of integrated chip packaging test data; The quality grading module is used to determine the quality grading of integrated chip packaging by combining the degree of data centralization and the degree of overall process offset.

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