A photomask, a method for placing graphic elements, a device, and a medium

Abstract

The present invention provides a photomask, a method for placing graphic elements, a device and a medium. The photomask includes: a main chip graphic area, an inner scribing lane area, and an outer scribing lane area; multiple groups of first set of scribing mark graphic groups, which are respectively placed on the outer scribing lane area; multiple test element graphics, which are placed on the inner scribing lane area; multiple groups of alignment mark graphic groups, which are placed on the inner scribing lane area; multiple groups of second set of scribing mark graphic groups, which are placed on the inner scribing lane area; the first set of scribing mark graphic groups includes multiple scribing mark graphics, the second set of scribing mark graphic groups includes multiple scribing mark graphics, the alignment mark graphic groups includes multiple alignment mark graphics, and the types and quantities of the graphic units are set according to the requirements of the manufacturing process. Through a photomask, a method for placing graphic elements, a device and a medium provided by the present invention, it is possible to make full use of a relatively small space for effective mark arrangement and improve the space utilization rate of the entire design.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to a photomask, a method for arranging graphic elements, a device, and a medium. Background Art

[0002] In the process of integrated circuit manufacturing, with the increase in product complexity, multiple functional modules and components need to be formed on a wafer, which requires a high alignment accuracy and graphic overlay accuracy between multiple film layers (layers). For this purpose, during the design process of a photomask (Mask), alignment mark graphics and overlay mark graphics are usually arranged, as well as test element graphics (Testkey) for process monitoring.

[0003] In the current technology, if a certain platform product needs to share a process flow, designers usually form a common version mark on the photomask that includes all layers. As the number of required layers increases, the length of the common version mark continuously becomes longer. At the same time, its length and area requirements result in a large amount of space being occupied on the scribe line, making it lack flexibility during the arrangement process of the long common version mark, unable to make effective mark arrangements by fully utilizing a smaller space, and reducing the space utilization rate of the entire design. Therefore, there is room for improvement. Summary of the Invention

[0004] The purpose of the present invention is to provide a photomask, a method for arranging graphic elements, a device, and a medium, which can make effective mark arrangements by fully utilizing a smaller space and improve the space utilization rate of the entire design.

[0005] To solve the above technical problems, the present invention is implemented through the following technical solutions:

[0006] The present invention provides a photomask, including:

[0007] Multiple main chip graphic areas, with adjacent two of the main chip graphic areas being arranged in parallel;

[0008] An inner scribe line area, formed between adjacent two of the main chip graphic areas;

[0009] An outer scribe line area, formed on the periphery of the multiple main chip graphic areas, and the shape of the outer scribe line area is rectangular;

[0010] Multiple groups of first overlay mark graphic groups, respectively arranged on the outer scribe line area and located on the four sides of the rectangle;

[0011] Multiple test element graphics, arranged on the inner scribe line area;

[0012] Multiple groups of alignment mark graphic groups, arranged on the inner scribing lane area; and

[0013] Multiple groups of second set of scribing mark graphic groups, arranged on the inner scribing lane area;

[0014] Wherein, the first set of scribing mark graphic group includes multiple scribing mark graphics, the second set of scribing mark graphic group includes multiple scribing mark graphics, the alignment mark graphic group includes multiple alignment mark graphics, the scribing mark graphics, the alignment mark graphics, and the test element graphics are graphic units, and the type and quantity of the graphic units are set according to the requirements of the manufacturing process.

[0015] In an embodiment of the present invention, the first set of scribing mark graphic group is located on one side of the end of the rectangle; the two opposite outer scribing lane areas of the rectangle are divided into a first outer scribing lane area and a second outer scribing lane area, and the projection of the first set of scribing mark graphic group on the first outer scribing lane area on the second outer scribing lane area does not contact the first set of scribing mark graphic group on the second outer scribing lane area.

[0016] In an embodiment of the present invention, the inner scribing lane area is a single scribing lane area.

[0017] In an embodiment of the present invention, the inner scribing lane area includes:

[0018] A first inner scribing lane area for arranging the test element graphics; and

[0019] A second inner scribing lane area for arranging the alignment mark graphic group and the second set of scribing mark graphic groups;

[0020] Wherein, the priority of arranging graphic units in the first inner scribing lane area is greater than the priority of arranging graphic units in the second inner scribing lane area.

[0021] In an embodiment of the present invention, on the same first inner scribing lane area, multiple test element graphics are arranged in sequence, and the distance between two adjacent test element graphics is greater than or equal to 5um.

[0022] In an embodiment of the present invention, on the same second inner scribing lane area, multiple alignment mark graphic groups and / or the second set of scribing mark graphic groups are arranged in sequence.

[0023] In an embodiment of the present invention, when the remaining space in the second inner cutting channel area cannot accommodate the alignment mark graphic group or the second set of lithography mark graphic groups, part of the alignment mark graphic group or part of the second set of lithography mark graphic groups are placed in the remaining space in the second inner cutting channel area, and the other remaining alignment mark graphic groups or the other remaining second set of lithography mark graphic groups are placed in the remaining space in the first inner cutting channel area and / or between two adjacent test element graphics.

[0024] The present invention also discloses a method for placing graphic elements of a photomask, including:

[0025] Obtaining corresponding graphic units of different types and quantities according to the process requirements;

[0026] Combining the graphic units of different types and quantities to form multiple sets of first lithography mark graphic groups, multiple sets of second lithography mark graphic groups, multiple sets of alignment mark graphic groups, and multiple test element graphics, where the first lithography mark graphic group includes multiple lithography mark graphics, the second lithography mark graphic group includes multiple lithography mark graphics, and the alignment mark graphic group includes multiple alignment mark graphics;

[0027] Placing the multiple sets of the first lithography mark graphic groups on the outer cutting channel areas around multiple main chip graphic areas respectively, the shape of the outer cutting channel area is rectangular, and the multiple sets of the first lithography mark graphic groups are respectively located on the four sides of the rectangle;

[0028] Placing the multiple test element graphics, the multiple sets of the second lithography mark graphic groups, and the multiple sets of the alignment mark graphic groups on the inner cutting channel areas formed between two adjacent main chip graphic areas.

[0029] The present invention also discloses a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the method for placing graphic elements of a photomask are implemented.

[0030] The present invention also discloses a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of the method for placing graphic elements of a photomask are implemented.

[0031] As described above, the present invention provides a photomask, a method for placing graphic elements, a device, and a medium. By dividing the alignment mark graphics and the lithography mark graphics into independent units according to the process requirements and only combining the layers of the photomask required for the current process, the length of a single set of lithography mark graphic groups or alignment mark graphic groups is significantly reduced.

[0032] Of course, it is not necessary for any product implementing the present invention to achieve all the above advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0034] Figure 1 Schematic diagram of a photomask in an embodiment of the present invention;

[0035] Figure 2 Flowchart of the placement method of the graphic elements of the photomask in an embodiment of the present invention;

[0036] Figure 3 Schematic diagram of an electronic device in an embodiment of the present invention.

[0037] In the figure: 10, main chip graphic area; 20, inner scribe lane area; 30, outer scribe lane area; 40, test element graphic; 50, first set of alignment mark graphics group; 60, second set of alignment mark graphics group; 70, alignment mark graphics group; 1, electronic device; 12, memory; 13, processor. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0039] Please refer to Figure 1 , the present invention provides a photomask, which can re-place the graphic units, and improve the chip output by increasing the usable area of the chips on the wafer. The photomask may include a main chip graphic area 10, an inner scribe lane area 20, an outer scribe lane area 30, a test element graphic 40, a first set of alignment mark graphics group 50, a second set of alignment mark graphics group 60, and an alignment mark graphics group 70.

[0040] Please refer to Figure 1, in one embodiment, the main chip graphic area 10 refers to the area on the photomask specifically used to contain the chip design pattern. The main chip graphic area 10 contains the detailed layout of the circuit, including transistors, connection lines, components, etc., and is directly drawn according to the designed circuit. The specific shape of the main chip graphic area 10 is not limited. For example, in this embodiment, the shape of the main chip graphic area 10 is rectangular, and two adjacent main chip graphic areas 10 can be parallel to each other to optimize space utilization, enabling more chips to be formed on a limited wafer area.

[0041] Please refer to Figure 1 , in one embodiment, the inner scribe line area 20 can be formed between two adjacent main chip graphic areas 10. The inner scribe line area 20 refers to the slender area on the wafer used to cut a single main chip graphic area 10, enabling each main chip graphic area 10 to be finally independently separated. Among them, the inner scribe line area 20 can be a single scribe line, and the width of the single scribe line is generally controlled to the minimum to ensure effective separation without wasting space. In this embodiment, the inner scribe line area 20 is designed as a single scribe line. By reducing the width or number of scribe lines, more wafer space can be released for the production of actual chips, enabling more chips to be arranged on the same wafer area.

[0042] Please refer to Figure 1 , in one embodiment, the outer scribe line area 30 can be located at the periphery of the entire main chip graphic area 10 array. The outer scribe line area 30 can be used to cut the chips at the wafer boundary. The outer scribe line area 30 can ensure that there is no breakage or incompleteness in the cutting of the peripheral chips. Since the chip layout on the wafer presents a rectangular arrangement. Therefore, the overall shape of the outer scribe line area 30 can also be rectangular.

[0043] In one embodiment, during the semiconductor manufacturing process, the precise design of graphic units is crucial for ensuring the function and performance of the chip. The types of graphic units can include contact area graphics (Contact), active area graphics (ActiveArea), gate area graphics (Gate / Poly), metal layer graphics (Metal), via graphics (Via), and test element graphics (Test Key), etc.

[0044] Please refer to Figure 1 , in one embodiment, when placing graphic units on the inner scribe line area 20 and the outer scribe line area 30, the overlay mark can be preferentially placed on the outer scribe line area 30. The overlay mark can be used for marks to improve alignment accuracy. By precisely defining the position of one layer relative to another layer, the patterns can be accurately superimposed in different process steps to ensure accurate alignment. The overlay mark can be selected from the above-mentioned graphic units.

[0045] In one embodiment, for different manufacturing processes, different types, quantities, and arrangements of overlay mark patterns may be required. For example, high-precision nodes may require more complex mark configurations. For different manufacturing processes, the corresponding required overlay mark patterns can be selected and then combined and arranged. After selecting the overlay mark patterns, the overlay mark patterns can be arranged in sequence to form a first set of overlay mark pattern groups 50.

[0046] In one embodiment, the types, quantities, and arrangements of the overlay mark patterns included in the first set of overlay mark pattern groups 50 can be set according to different manufacturing processes. For example, the first set of overlay mark pattern groups 50 may include a first contact area pattern, a first active area pattern, a first gate area pattern, a metal layer pattern, a channel pattern, a second contact area pattern, a second active area pattern, etc. arranged in sequence. Another example is that the first set of overlay mark pattern groups 50 may include a first gate area pattern, a metal layer pattern, a channel pattern, a contact area pattern, an active area pattern, a second gate area pattern, etc. arranged in sequence.

[0047] In one embodiment, the number of the first set of overlay mark pattern groups 50 can be multiple groups, for example, four groups. Since the overall shape of the outer scribe lane area 30 is rectangular, at least one set of the first set of overlay mark pattern groups 50 can be placed on each side of the rectangle. By this placement method, multi-directional alignment references can be provided, effectively compensating for alignment errors caused by equipment deviations or wafer warping.

[0048] In one embodiment, the first set of overlay mark pattern groups 50 can be located on one side of the end of the rectangle. By preferentially placing the first set of overlay mark pattern groups 50 at the four ends of the rectangle, the positions at the ends help to form a comprehensive reference system, ensuring reliable alignment guidance during the overall exposure process. Specifically, precise alignment is required between different layers (such as the layer corresponding to the active area pattern). The first set of overlay mark pattern groups 50 can provide a reference, enabling the graphic elements of the upper and lower layers to form a complete structure.

[0049] In one embodiment, two opposite outer scribe lane regions of a rectangle can be distinguished as a first outer scribe lane region and a second outer scribe lane region. For example, in the length direction of the main chip pattern region 10, two opposite outer scribe lane regions of the rectangle can be distinguished as a first outer scribe lane region and a second outer scribe lane region. Also for example, in the width direction of the main chip pattern region 10, two opposite outer scribe lane regions of the rectangle can be distinguished as a first outer scribe lane region and a second outer scribe lane region. At this time, since the first set of engraved marking graphic groups 50 need to be placed on both the first outer scribe lane region and the second outer scribe lane region, in order to ensure the uniqueness and consistency of the positions of the first set of engraved marking graphic groups 50 and avoid interference and overlap between the marking groups, therefore, the projection of the first set of engraved marking graphic groups 50 on the first outer scribe lane region on the second outer scribe lane region and the first set of engraved marking graphic groups 50 on the second outer scribe lane region need to be set to not touch.

[0050] Please refer to Figure 1 , in one embodiment, the inner scribe lane region 20 can be divided into two parts, namely a first inner scribe lane region and a second inner scribe lane region, and each part has different uses and functions. Among them, the priority of placing graphic units in the first inner scribe lane region is higher than that of placing graphic units in the second inner scribe lane region.

[0051] In one embodiment, after placing the first set of engraved marking graphic groups 50 in the outer scribe lane region 30, the test element graphics 40 can be placed in the first inner scribe lane region. The test element graphics 40 can be used to test various electrical and physical characteristics during the production process to ensure that the manufactured chips meet the design requirements. The type and quantity of the test element graphics 40 can be set according to different process technology requirements.

[0052] In one embodiment, in the same first inner scribe lane region, multiple test element graphics 40 need to be placed in sequence. The spacing between two adjacent test element graphics 40 must be greater than or equal to 5 micrometers (um) to avoid interference between adjacent elements and ensure the accuracy of the test. In each first inner scribe lane region, the quantity of the test element graphics 40 to be placed can be unrestricted. For example, it can be 7 to 8, and the specific quantity can be set based on process design and test requirements. For all the first inner scribe lane regions, at least 40 test element graphics 40 need to be placed, that is, the design of the entire wafer requires the sum of all the test element graphics 40 distributed in multiple first inner scribe lane regions to reach at least 40 to ensure sufficient test coverage and data sampling to evaluate the production quality.

[0053] In one embodiment, after the test element pattern 40 is placed in the first inner dicing lane area, the alignment mark pattern group 70 and the second set of alignment mark patterns 60 can be placed in the second inner dicing lane area. Among them, the priority order of placing the alignment mark pattern group 70 and the second set of alignment mark patterns 60 can be unrestricted. Their priorities can be the same or different, which is not restricted here.

[0054] In one embodiment, the second set of alignment mark patterns 60 can be used as overlay marks for alignment and precision monitoring between layers in a multi-layer manufacturing process. The number of the second set of alignment mark patterns 60 can be multiple groups, for example, it can be four groups. The second set of alignment mark patterns 60 can include multiple alignment mark patterns. The alignment mark patterns can be selected from the above-mentioned graphic units. For different manufacturing processes, different types, numbers, and arrangements of alignment mark patterns may be required. For different manufacturing processes, the corresponding required alignment mark patterns can be selected and then combined and placed. After selecting the alignment mark patterns, the alignment mark patterns can be arranged in sequence to form a set of the second set of alignment mark patterns 60. Among them, the types, numbers, and arrangement orders of the alignment mark patterns included in the first set of alignment mark patterns 50 and the second set of alignment mark patterns 60 can be the same.

[0055] In one embodiment, the alignment mark pattern group 70 can be used for alignment in process steps to ensure precise alignment between different manufacturing steps. The alignment mark pattern group 70 can include multiple alignment mark patterns. The alignment mark patterns can be selected from the above-mentioned graphic units. For different manufacturing processes, different types, numbers, and arrangements of alignment mark patterns may be required. For different manufacturing processes, the corresponding required alignment mark patterns can be selected and then combined and placed. After selecting the alignment mark patterns, the alignment mark patterns can be arranged in sequence to form a set of alignment mark pattern group 70.

[0056] In one embodiment, the number of the alignment mark pattern group 70 is multiple groups, for example, it can be four groups. The number of the second set of alignment mark patterns 60 is at least 4 groups. In the same second inner dicing lane area, multiple alignment mark pattern groups 70 and / or multiple second set of alignment mark patterns 60 can be arranged in sequence or alternately to ensure the alignment accuracy of different layers during the production process.

[0057] In one embodiment, after the alignment mark pattern groups 70 and / or the second set of scribe mark pattern groups 60 are fully arranged on all the second inner scribe lane regions, for some of the second inner scribe lane regions, there is still some remaining space. However, due to space limitations, this remaining space is not sufficient to fully arrange the entire alignment mark pattern group 70 or the second set of scribe mark pattern groups 60. Therefore, when the space in the second inner scribe lane region is not sufficient to completely accommodate the entire alignment mark pattern group 70 or the second set of scribe mark pattern groups 60, a partial layout strategy can be adopted, that is: a part of the alignment mark pattern group 70 or a part of the second set of scribe mark pattern groups 60 can be placed in the above remaining space to make the best use of all available spaces in the second inner scribe lane region. For the remaining alignment mark pattern groups 70 or the second set of scribe mark pattern groups 60, they also need to be placed. At this time, the remaining alignment mark pattern groups 70 or the second set of scribe mark pattern groups 60 can be placed in the remaining space of the first inner scribe lane region and / or the space between two adjacent test element patterns 40. By dispersing the mark pattern groups in the alignment mark pattern group 70 and the second set of scribe mark pattern groups 60 in different regions and using the gaps between adjacent test element patterns 40, every available tiny space is maximally utilized.

[0058] It can be seen that in the above solution, an unexpected effect of the present invention is that by dividing the alignment marks and scribe marks into independent units according to the process requirements and only combining the layers of the photomasks required for the current process, the length of a single scribe mark pattern group or alignment mark pattern group is significantly reduced. Since the scribe mark pattern group or the alignment mark pattern group can be segmented and flexibly placed, this reduces the space waste caused by the inability to place due to the excessive length of the scribe mark pattern group or the alignment mark pattern group, allowing for more effective use of the area within the limited scribe lane space. By freely combining and arranging the scribe mark pattern group or the alignment mark pattern group, the area of the scribe lane is reduced, the effective chip area is increased, and thus the chip usage area on the wafer is improved. Without increasing the wafer size, by optimizing the layout of the scribe mark pattern group or the alignment mark pattern group, the chip area is increased and the number of chips per wafer is increased, the cost of a single chip is reduced, and the overall production efficiency is improved. Since products that originally required double scribe lanes or multiple scribe lanes can be processed using a single scribe lane, this further increases the effective utilization area of the wafer and improves the process simplicity and process flexibility.

[0059] Please refer to Figure 2 , the present invention also provides a method for placing graphic elements of a photomask. The placement method can be applied to the above photomask to place graphic units. The placement method may include the following steps:

[0060] Step S10: Obtain corresponding graphic units of different types and quantities according to the process requirements of the process;

[0061] Step S20: Combine graphic units of different types and quantities to form multiple groups of first set of alignment mark graphic groups, multiple groups of second set of alignment mark graphic groups, multiple groups of registration mark graphic groups, and multiple test element graphics. Among them, each first set of alignment mark graphic group includes multiple alignment mark graphics, each second set of alignment mark graphic group includes multiple alignment mark graphics, and each registration mark graphic group includes multiple registration mark graphics;

[0062] Step S30: Place the multiple groups of first set of alignment mark graphic groups on the outer scribing lanes outside the peripheries of multiple main chip graphics areas respectively. The shape of the outer scribing lane area is rectangular, and the multiple groups of first set of alignment mark graphic groups are respectively located on the four sides of the rectangle;

[0063] Step S40: Place the multiple test element graphics, multiple groups of second set of alignment mark graphic groups, and multiple groups of registration mark graphic groups on the inner scribing lane area formed between two adjacent main chip graphics areas.

[0064] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution. The order of execution of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0065] Please refer to Figure 3 , in one embodiment, the electronic device 1 may include a memory 12, a processor 13, and a bus, and may also include a computer program stored in the memory 12 and executable on the processor 13, such as a test program for the battery health status.

[0066] In one embodiment, the memory 12 includes at least one type of readable storage medium. The readable storage medium includes flash memory, mobile hard disk, multimedia card, card-type memory (such as SD or DX memory, etc.), magnetic memory, magnetic disk, optical disc, etc. The memory 12 may be an internal storage unit of the electronic device 1 in some embodiments, such as the mobile hard disk of the electronic device 1. The memory 12 may also be an external storage device of the electronic device 1 in other embodiments, such as a plug-in mobile hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. equipped on the electronic device 1. Further, the memory 12 may include both the internal storage unit and the external storage device of the electronic device 1. The memory 12 can be used not only to store application software installed in the electronic device 1 and various types of data, such as the code for the placement of graphic elements of a photomask, etc., but also to temporarily store data that has been output or will be output.

[0067] In one embodiment, the processor 13 may be composed of an integrated circuit in some embodiments. For example, it may be composed of a single packaged integrated circuit, or may be composed of multiple packaged integrated circuits with the same or different functions, including the combination of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips, etc. The processor 13 is the control core (Control Unit) of the electronic device 1, connecting various components of the entire electronic device 1 through various interfaces and circuits. By running or executing programs or modules stored in the memory 12 (such as the placement program of the graphic elements of the photomask, etc.), and by calling the data stored in the memory 12, it executes various functions of the electronic device 1 and processes data.

[0068] In one embodiment, the processor 13 executes the operating system of the electronic device 1 and various installed application programs. The processor 13 executes the application program to implement the steps in the above-mentioned method for placing the graphic elements of the photomask.

[0069] In one embodiment, a computer program may be divided into one or more modules. One or more modules are stored in the memory 12 and executed by the processor 13 to complete the present application. One or more modules may be a series of computer program instruction segments capable of performing specific functions, and these instruction segments are used to describe the execution process of the computer program in the electronic device 1.

[0070] The embodiments of the present invention disclosed above are only used to help explain the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principle and practical application of the present invention, so that those skilled in the art can understand and utilize the present invention well. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A photomask, characterized in that: include: A plurality of main chip graphic areas, two adjacent main chip graphic areas are arranged in parallel; An inner cutting road area is formed between two adjacent main chip pattern areas; An outer cutting road area is formed at the periphery of the plurality of main chip pattern areas, and the shape of the outer cutting road area is a rectangle; A plurality of first set of engraved mark pattern groups are respectively placed on the outer cutting road area and located on the four sides of the rectangle; A plurality of test element patterns are placed on the inner cutting track area; A plurality of alignment mark graphic groups are placed on the inner cutting track area; as well as A plurality of second sets of engraved marking graphic groups are placed on the inner cutting track area; The first overlay mark pattern group includes a plurality of overlay mark patterns, the second overlay mark pattern group includes a plurality of overlay mark patterns, the alignment mark pattern group includes a plurality of alignment mark patterns, the overlay mark patterns, the alignment mark patterns, and the test element patterns are pattern units, and the types and quantities of the pattern units are set according to process technology requirements; The inner cutting zone comprises: A first inner cutting track area is used to place the test element pattern; and The second inner cutting road area is used to place the alignment mark graphic group and the second overlay mark graphic group; wherein the priority of placing the graphic unit in the first inner cutting road area is greater than the priority of placing the graphic unit in the second inner cutting road area; On the same second inner cutting track area, a plurality of the alignment mark pattern groups and / or the second engraving mark pattern groups are placed in sequence; When the remaining space in the second inner cutting zone is insufficient to accommodate the alignment mark graphic group or the second engraving mark graphic group, part of the alignment mark graphic group or part of the second engraving mark graphic group is placed in the remaining space in the second inner cutting zone, and the other remaining alignment mark graphic group or other remaining second engraving mark graphic group is placed in the remaining space in the first inner cutting zone and / or between two adjacent test element graphics.

2. The photomask according to claim 1, wherein: The first set of engraved mark graphics group is located on one side of the end of the rectangle; the two opposite outer cutting lane areas of the rectangle are divided into a first outer cutting lane area and a second outer cutting lane area, and the projection of the first set of engraved mark graphics group on the first outer cutting lane area on the second outer cutting lane area does not contact the first set of engraved mark graphics group on the second outer cutting lane area.

3. The photomask according to claim 1, wherein: The inner cutting street area is a single cutting street area.

4. The photomask according to claim 1, wherein: On the same first inner cutting road area, a plurality of the test element patterns are placed in sequence, and a distance between two adjacent test element patterns is greater than or equal to 5 um.

5. A method for placing graphic elements of a mask, characterized in that: include: Obtain corresponding graphics units of different types and quantities according to process technology requirements; Combining the graphic units of different types and quantities to form a plurality of first overlay mark graphic groups, a plurality of second overlay mark graphic groups, a plurality of alignment mark graphic groups, and a plurality of test element graphics, wherein the first overlay mark graphic group includes a plurality of overlay mark graphics, the second overlay mark graphic group includes a plurality of overlay mark graphics, and the alignment mark graphic group includes a plurality of alignment mark graphics; Placing multiple sets of the first set of engraved mark pattern groups on the outer cutting road area outside the plurality of main chip pattern areas, wherein the outer cutting road area is in a rectangular shape, and the multiple sets of the first set of engraved mark pattern groups are respectively located on the four sides of the rectangle; Placing a plurality of the test element patterns, a plurality of the second overlay mark pattern groups, and a plurality of the alignment mark pattern groups on an inner cutting street area formed between two adjacent main chip pattern areas; the inner cutting street area includes a first inner cutting street area and a second inner cutting street area; the first inner cutting street area is used to place the test element patterns; the second inner cutting street area is used to place the alignment mark pattern group and the second overlay mark pattern group; the priority of placing the pattern unit in the first inner cutting street area is greater than the priority of placing the pattern unit in the second inner cutting street area; On the same second inner cutting track area, a plurality of the alignment mark pattern groups and / or the second engraving mark pattern groups are placed in sequence; When the remaining space in the second inner cutting zone is insufficient to accommodate the alignment mark graphic group or the second engraving mark graphic group, part of the alignment mark graphic group or part of the second engraving mark graphic group is placed in the remaining space in the second inner cutting zone, and the other remaining alignment mark graphic group or other remaining second engraving mark graphic group is placed in the remaining space in the first inner cutting zone and / or between two adjacent test element graphics.

6. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method for placing the graphic elements of the mask as claimed in claim 5 are implemented.

7. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method for placing graphic elements of a mask as claimed in claim 5 are implemented.

Images