Photomask, exposure method and manufacturing method of semiconductor device

Abstract

The invention provides a photomask, an exposure method and a manufacturing method of a semiconductor device.The photomask comprises a first exposure pattern and a second exposure pattern, the first exposure pattern and the second exposure pattern extend in the same direction and are different in size, the first exposure pattern comprises a first alignment mark, and the second exposure pattern comprises a second alignment mark. The first exposure pattern comprises a first alignment mark, the second exposure pattern comprises a second alignment mark, at least two rounds of exposure are performed on a target area by using the first exposure pattern and the second exposure pattern, and the first alignment mark and the second alignment mark are aligned in two adjacent rounds of exposure, so that a metal layer on the same layer as a welding pad can be removed by using the photomask. Therefore, the normal warping degree of the semiconductor substrate structure is ensured, the risk of sheet sliding is avoided, meanwhile, during the subsequent packaging process, the chip cutting is also facilitated, and the risk of cutter curling is avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a photomask, an exposure method and a method for manufacturing a semiconductor device. Background Art

[0002] With the rise of industries such as artificial intelligence, 5G, big data, and cloud computing, advanced packaged chips using interposers are becoming more and more common. Limited by the maximum exposure field of the lithography machine (for example, 26mm×33mm), that is, the maximum size of the mask (for example, 26mmx33mm), for scenarios where large-size chips need to be manufactured, splicing technology is required, that is, in the chip manufacturing process, the graphics involved are partitioned, exposed in sequence, and finally spliced ​​into a large-size chip area. At the same time, in order to allow the interposer to carry more chips, an overhang area is added to the interposer to expand the chip carrying area.

[0003] In the conventional chip manufacturing process, chip slippage is likely to occur after the aluminum pad is formed in the latter part of the process. In addition, chip rolling is also likely to occur when the chip is cut. Those skilled in the art have been seeking solutions to solve this problem. Summary of the invention

[0004] The purpose of the present invention is to provide a mask, an exposure method and a method for manufacturing a semiconductor device to solve the problem that in the existing chip manufacturing process, the chip slippage easily occurs after the bonding pad is formed in the later stage of the process, and the knife rolling is also very likely to occur when the chip is cut.

[0005] In order to solve the above technical problems, the present invention provides a photomask, which includes a substrate and a first exposure pattern and a second exposure pattern formed on the substrate, the first exposure pattern and the second exposure pattern extend in the same direction and have different sizes, the first exposure pattern includes a first alignment mark, the second exposure pattern includes a second alignment mark, and at least two rounds of exposure are performed on the target area using the first exposure pattern and the second exposure pattern, and the first alignment mark is aligned with the second alignment mark in two adjacent rounds of exposure.

[0006] Optionally, in the photomask, the first alignment mark and the second alignment mark both include a first direction mark line and a second direction mark line, and the first direction mark line and the second direction mark line are located on the boundary of the first exposure pattern or the second exposure pattern and intersect at a right angle.

[0007] Optionally, in the photomask, aligning the first alignment mark with the second alignment mark in two adjacent rounds of exposure includes:

[0008] The first direction mark of the first alignment mark and the first direction mark of the second alignment mark are on a straight line, and the second direction mark of the first alignment mark and the second direction mark of the second alignment mark overlap.

[0009] Optionally, in the photomask, two exposure areas formed by two adjacent rounds of exposure are adjacent to each other and extend in the same direction.

[0010] Optionally, in the mask, the target area is a suspended area on a semiconductor substrate structure, the semiconductor substrate structure also includes a chip area, the first alignment mark and / or the second alignment mark are also used to align with a third alignment mark, and the third alignment mark is used to form an exposure process for the chip area.

[0011] Optionally, in the photomask, the first alignment mark, the second alignment mark and the third alignment mark are combined into a cross-shaped alignment mark.

[0012] The present invention also provides an exposure method, the exposure method comprising:

[0013] providing a first photomask, and using the first photomask to expose a target to form a first exposure area on the target; and,

[0014] A second photomask is provided, wherein the second photomask includes a first exposure pattern and a second exposure pattern, wherein the first exposure pattern and the second exposure pattern extend in the same direction and have different sizes, wherein the first exposure pattern includes a first alignment mark, and the second exposure pattern includes a second alignment mark, and at least two rounds of exposure are performed on the target using the first exposure pattern and the second exposure pattern, wherein the first alignment mark is aligned with the second alignment mark in two adjacent rounds of exposure to form a second exposure area on the target.

[0015] Optionally, in the exposure method, using the first photomask to expose the target includes: there are at least two first photomasks, and at least two first photomasks are spliced ​​together to expose the target, wherein the size of the first photomask is less than or equal to the maximum exposure field of view of the lithography machine.

[0016] Optionally, in the exposure method, the target is a semiconductor substrate structure, the first exposure area is used to form a pad in a chip area of ​​the semiconductor substrate structure, and the second exposure area is used to remove a metal layer on the same layer as the pad on a suspended area of ​​the semiconductor substrate structure.

[0017] The present invention also provides a method for manufacturing a semiconductor device, the method comprising:

[0018] A semiconductor base structure is provided, wherein the semiconductor base structure comprises a semiconductor substrate and a metal layer formed on the semiconductor substrate, a mask layer is formed on the metal layer, and the semiconductor base structure comprises a chip area and a suspended area;

[0019] Using a first photomask to form a first patterned mask layer in the chip area, and using a second photomask to form a second patterned mask layer in the suspended area;

[0020] Using the first patterned mask layer as a mask to pattern the metal layer to form a pad in the chip area, and using the second patterned mask layer as a mask to remove the metal layer in the suspended area;

[0021] Among them, the second photomask includes a substrate and a first exposure pattern and a second exposure pattern formed on the substrate, the first exposure pattern and the second exposure pattern extend in the same direction and have different sizes, the first exposure pattern includes a first alignment mark, and the second exposure pattern includes a second alignment mark, and at least two rounds of exposure are performed on the suspended area using the first exposure pattern and the second exposure pattern, and the first alignment mark is aligned with the second alignment mark in two adjacent rounds of exposure.

[0022] Optionally, in the method for manufacturing the semiconductor device, using a first photomask to form a first patterned mask layer in the chip region includes: using at least two first photomasks to splice together to perform a first exposure process on the chip region.

[0023] Optionally, in the method for manufacturing the semiconductor device, the semiconductor base structure further includes a rewiring layer, the rewiring layer is formed on the semiconductor substrate, and the metal layer is formed on the rewiring layer.

[0024] Optionally, in the method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device further comprises:

[0025] The semiconductor substrate structure is cut along the suspended region.

[0026] Optionally, in the method for manufacturing the semiconductor device, the semiconductor substrate structure includes a plurality of the suspended regions, and each of the suspended regions extends along the same direction.

[0027] The inventors have found that in the existing chip manufacturing process, by adjusting the exposure step size of the photolithography process, a suspended area between the chip areas is formed on the semiconductor substrate structure, wherein the suspended area is not exposed. In the subsequent process of forming an aluminum pad, the aluminum metal that is not needed in the chip area is directly removed by photolithography and etching processes to form an aluminum pad. At this time, the suspended area is protected by a mask layer. Although the aluminum metal is not needed, it cannot be removed, which will cause abnormal wafer bow, thereby causing the risk of slipping in subsequent processes. In addition, during the subsequent packaging process, due to the presence of aluminum metal in the suspended area, chip cutting is very likely to cause the risk of knife rolling.

[0028] In the mask, exposure method and semiconductor device manufacturing method provided by the present invention, the mask includes a first exposure pattern and a second exposure pattern, the first exposure pattern and the second exposure pattern extend in the same direction and have different sizes, the first exposure pattern includes a first alignment mark, and the second exposure pattern includes a second alignment mark, and at least two rounds of exposure are performed on the target area using the first exposure pattern and the second exposure pattern. The first alignment mark is aligned with the second alignment mark in two adjacent rounds of exposure, so that the mask can be used to remove the metal layer on the same layer as the pad, ensuring that the warping of the semiconductor substrate structure is normal and avoiding the risk of slippage. At the same time, it is also convenient for chip cutting during the subsequent packaging process and avoiding the risk of knife rolling. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic structural diagram of a photomask provided by an embodiment of the present invention.

[0030] Figure 2 It is a schematic diagram of an exposure area formed by the exposure method provided in an embodiment of the present invention.

[0031] Figure 3 It is a cross-sectional schematic diagram of a semiconductor substrate structure provided by an embodiment of the present invention.

[0032] Figure 4 It is a schematic cross-sectional view of a device after a patterned mask layer is formed according to an embodiment of the present invention.

[0033] Figure 5 It is a schematic cross-sectional view of a device after a patterning process is performed on a metal layer according to an embodiment of the present invention.

[0034] Figure 6 It is a schematic cross-sectional view of a device after cutting a semiconductor substrate structure provided by an embodiment of the present invention.

[0035] The reference numerals are described as follows:

[0036] 10-mask; 11-substrate; 12A-first exposure pattern; 12B-second exposure pattern; 13A-first alignment mark; 13B-second alignment mark; 13C-third alignment mark; A1-first direction mark line; A2-second direction mark line; 20-first exposure area; 21-second exposure area.

[0037] 100 - semiconductor base structure; 101 - chip area; 102 - suspended area; 110 - semiconductor substrate; 120 - metal layer; 130 - redistribution layer; 131 - dielectric layer; 132 - conductive layer; 200 - mask layer; 210 - patterned mask layer; 210A - first patterned mask layer; 210B - second patterned mask layer; 300 - solder pad. DETAILED DESCRIPTION

[0038] In the existing chip manufacturing process, it is easy to slip after the aluminum pad is formed in the latter part of the process. In addition, it is also very easy to roll the chip when cutting. After the inventors conducted in-depth research on the prior art, they found that in the existing chip manufacturing process, by adjusting the exposure step length (step size) of the photolithography process, a suspended area between the chip area and the chip area is formed on the semiconductor substrate structure, wherein the suspended area is not exposed. In the subsequent process of forming the aluminum pad (Al pad), the aluminum metal that is not needed in the chip area is directly removed by photolithography and etching processes to form the aluminum pad. At this time, the suspended area is protected by a mask layer. Although the aluminum metal is not needed, it cannot be removed, which will cause abnormal wafer bow, thereby causing the risk of slipping in the subsequent process. In addition, when the subsequent packaging process is carried out, due to the presence of aluminum metal in the suspended area, chip cutting is very likely to have a roll risk.

[0039] Based on this, in the mask, exposure method and semiconductor device manufacturing method provided by the present invention, the mask includes a first exposure pattern and a second exposure pattern, the first exposure pattern and the second exposure pattern extend in the same direction and have different sizes, the first exposure pattern includes a first alignment mark, and the second exposure pattern includes a second alignment mark, and at least two rounds of exposure are performed on the target area using the first exposure pattern and the second exposure pattern, and the first alignment mark is aligned with the second alignment mark in two adjacent rounds of exposure, so that the mask can be used to remove the metal layer on the same layer as the pad, ensuring that the warping of the semiconductor substrate structure is normal and avoiding the risk of slippage. At the same time, it is also convenient for chip cutting during the subsequent packaging process and avoiding the risk of knife rolling.

[0040] The following is a further detailed description of the mask, exposure method and semiconductor device manufacturing method proposed in the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0041] The terms used in the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. Unless otherwise defined in the present application document, the technical terms or scientific terms used in the present invention should be the common meaning understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limit, but indicate that there is at least one. "Multiple" or "several" means two or more. Unless otherwise specified, words such as "upper / upper layer", "lower / lower layer" and the like are only for the convenience of explanation and are not limited to one position or one spatial orientation. Words such as "include" or "comprise" and the like mean that the elements or objects appearing in front of "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect. The singular forms "a", "said" and "the" used in the present specification and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0042] First, please refer to Figure 1 , which is a schematic diagram of the structure of the photomask provided by an embodiment of the present invention. Figure 1 As shown, in the embodiment of the present application, the mask 10 includes a substrate 11 and a first exposure pattern 12A and a second exposure pattern 12B formed on the substrate 11, the first exposure pattern 12A and the second exposure pattern 12B extend in the same direction and have different sizes, the first exposure pattern 12A includes a first alignment mark 13A, the second exposure pattern 12B includes a second alignment mark 13B, and at least two rounds of exposure are performed on the target area using the first exposure pattern 12A and the second exposure pattern 12B, and the first alignment mark 13A is aligned with the second alignment mark 13B in two adjacent rounds of exposure.

[0043] like Figure 1As shown, it is schematically shown here that three first exposure patterns 12A and three second exposure patterns 12B are formed on the substrate 11, and the three first exposure patterns 12A and the three second exposure patterns 12B can be divided into three exposure pattern groups. Usually, an exposure process is performed on a target area using the first exposure patterns 12A and the second exposure patterns 12B in the same exposure pattern group.

[0044] In the embodiment of the present application, the first exposure pattern 12A and the second exposure pattern 12B both extend in the horizontal direction. The first exposure pattern 12A and the second exposure pattern 12B in the same exposure pattern group have different sizes. The sizes in the present application include but are not limited to length, width, and shape, that is, the lengths are different here, so that they can be better used together to perform at least two rounds of exposure on the target area. Furthermore, the sizes of the three first exposure patterns 12A and the three second exposure patterns 12B on the substrate 11 are different, so that more exposure requirements can be met, the use efficiency of the mask 10 is improved, and the manufacturing cost is reduced.

[0045] Further, such as Figure 1 As shown, the first alignment mark 13A is located at the right end of the first exposure pattern 12A, specifically the upper right corner and the lower right corner, and the second alignment mark 13B is located at the left end of the second exposure pattern 12B, specifically the upper left corner and the lower left corner, so that in two adjacent exposure processes, the first alignment mark 13A and the second alignment mark 13B can be quickly and accurately aligned. The positions of the first alignment mark 13A and the second alignment mark 13B can be set as needed.

[0046] Here, the first alignment mark 13A and the second alignment mark 13B both include a first direction mark line A1 and a second direction mark line A2. The first direction mark line A1 and the second direction mark line A2 of the first alignment mark 13A are located on the boundary of the first exposure pattern 12A and intersect at a right angle. The first direction mark line A1 and the second direction mark line A2 of the second alignment mark 13B are located on the boundary of the second exposure pattern 12B and intersect at a right angle. In this way, the alignment of the front and rear wheel exposure processes can be conveniently and accurately achieved in the first direction and the second direction. Among them, the intersection of the first direction mark line A1 and the second direction mark line A2 can be in a "cross" shape; it can also be in a "T" shape; it can also be in a "vertical fold" shape or a "horizontal fold" shape, etc.

[0047] Specifically, the alignment of the first alignment mark 13A and the second alignment mark 13B in the adjacent two rounds of exposure includes: the first direction mark A1 of the first alignment mark 13A and the first direction mark A1 of the second alignment mark 13B are on the same straight line, and the second direction mark A2 of the first alignment mark 13A coincides with the second direction mark A2 of the second alignment mark 13B. Among them, the second direction mark A2 of the first alignment mark 13A and the second direction mark A2 of the second alignment mark 13B may also partially coincide, completely overlap, intersect, be parallel or be on the same straight line in the second direction. Specifically, reference can be made adaptively to Figure 2 .

[0048] Continue to refer to Figure 2 It can be seen that the two exposure regions formed by the adjacent two rounds of exposure performed on the target area using the first exposure pattern 12A and the second exposure pattern 12B are adjacent and extend in the same direction. Here, they both extend in the first direction, that is, along the X direction.

[0049] In the embodiment of the present application, the target of performing the exposure process may be a semiconductor substrate structure, and the target area is a suspended area on the semiconductor substrate structure. Among them, the semiconductor substrate structure further includes a chip area, and the first alignment mark 13A and / or the second alignment mark 13B are also used to align with a third alignment mark 13C, and the third alignment mark 13C is used for the exposure process of forming the chip area. As Figure 2 shown, after the exposure process, the first alignment mark 13A and / or the second alignment mark 13B in the adjacent two rounds of exposure also align with the third alignment mark 13C in the previous exposure process. In the embodiment of the present application, the first alignment mark 13A, the second alignment mark 13B and the third alignment mark 13C are combined into a cross-shaped alignment mark; in other embodiments of the present application, the first alignment mark 13A, the second alignment mark 13B and the third alignment mark 13C may also be combined into alignment marks of other shapes, such as a "rich" character shape, etc. The present application does not limit this.

[0050] Furthermore, the embodiment of the present application also provides an exposure method using the above-mentioned photomask 10, and reference can be made correspondingly to Figure 2 , the exposure method includes: providing a first photomask (not shown in the figure); using the first photomask to expose the target to form a first exposure area 20 on the target; and providing a second photomask, here it is the photomask 10, and reference can be made correspondingly to Figure 1, the mask 10 includes a first exposure pattern 12A and a second exposure pattern 12B, the first exposure pattern 12A and the second exposure pattern 12B extend in the same direction and have different sizes, the first exposure pattern 12A includes a first alignment mark 13A, the second exposure pattern 12B includes a second alignment mark 13B, at least two rounds of exposure are performed on the target using the first exposure pattern 12A and the second exposure pattern 12B, the first alignment mark 13A and the second alignment mark 13B are aligned in two adjacent rounds of exposure to form a second exposure area 21 on the target. Exposing the target using the first mask may include: the first mask is at least two sheets, and the at least two sheets of the first mask are spliced ​​to expose the target, wherein the size of the first mask may be less than or equal to the maximum exposure field of view of the lithography machine.

[0051] Among them, the first mask can be any existing mask used for splicing the photolithography process on the chip area, and the exposure pattern thereon can be determined according to the device structure to be formed. In the embodiment of the present application, specifically, the target is a semiconductor substrate structure, and the first mask is used to form a pad. The second mask is shown as the above-mentioned mask 10, and is used to remove the metal layer on the same layer as the pad on the suspended area. That is, the first exposure area 20 is used to form a pad in the chip area of ​​the semiconductor substrate structure, and the second exposure area 21 is used to remove the metal layer on the same layer as the pad on the suspended area of ​​the semiconductor substrate structure.

[0052] Please refer to Figure 1 and Figure 2 In the embodiment of the present application, the second exposure area 21 is formed by performing two rounds of exposure process by the first exposure pattern 12A and the second exposure pattern 12B, wherein the first round of exposure process uses the first exposure pattern 12A, and the second round of exposure process uses the second exposure pattern 12B. At the same time, the alignment between the second round of exposure and the first round of exposure is achieved by aligning the second alignment mark 13B with the first alignment mark 13A. Figure 2As shown, in the embodiment of the present application, the second direction mark line A2 of the first alignment mark 13A and the second direction mark line A2 of the second alignment mark 13B coincide with each other, and the first direction mark line A1 of the first alignment mark 13A and the first direction mark line A1 of the second alignment mark 13B are on the same straight line, thereby achieving alignment between the subsequent round of exposure and the previous round of exposure. Further, the second direction mark line A2 of the first alignment mark 13A and / or the second direction mark line A2 of the second alignment mark 13B are aligned with the third alignment mark 13C in the first mask (not shown in the figure), and the third alignment mark 13C is used to form the exposure process of the chip area, thereby achieving alignment between the second mask and the first mask, and here, alignment between the suspended area and the chip area is also achieved.

[0053] In the embodiment of the present application, a method for manufacturing a semiconductor device using the above-mentioned mask 10 is further provided. Figures 3 to 6 , which is a cross-sectional schematic diagram of a device structure formed by executing the method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0054] like Figure 3 As shown, a semiconductor base structure 100 is provided, and the semiconductor base structure 100 includes a semiconductor substrate 110 and a metal layer 120 formed on the semiconductor substrate 110. The semiconductor substrate 110 can be a silicon wafer, a silicon germanium wafer, a silicon carbide wafer, a gallium arsenide wafer, etc. The metal layer 120 can be an aluminum metal layer, a copper metal layer, a silver metal layer, a tungsten metal layer, etc. In the embodiment of the present application, the semiconductor base structure 100 also includes a rewiring layer 130, the rewiring layer 130 is formed on the semiconductor substrate 110, and the metal layer 120 is formed on the rewiring layer 130. Specifically, the rewiring layer 130 may include one or more dielectric layers 131 and one or more conductive layers 132 formed in the dielectric layer 131, wherein the conductive layer 132 may be connected to a conductive structure (not shown in the figure) in the semiconductor substrate 110.

[0055] like Figure 3 As shown, the semiconductor substrate structure 100 includes a chip area 101 and a suspended area 102, and the chip area 101 and the suspended area 102 are adjacent. In the embodiment of the present application, the semiconductor substrate structure 100 includes a plurality of chip areas 101 and a plurality of suspended areas 102, and each of the suspended areas 102 extends along the same direction, and can be referred to accordingly. Figure 2, each of the suspended regions 102 may also extend in different directions. Accordingly, the semiconductor substrate 110 includes the semiconductor substrate 110 of the chip region 101 and the semiconductor substrate 110 of the suspended region 102; the metal layer 120 includes the metal layer 120 of the chip region 101 and the metal layer 120 of the suspended region 102.

[0056] Furthermore, a mask layer 200 is formed on the metal layer 120, and the mask layer 200 covers the surface of the metal layer 120, including the metal layer 120 in the chip area 101 and the metal layer 120 in the suspended area 102. The mask layer 200 is, for example, a photoresist layer, and the mask layer 200 may also be other materials besides the photoresist layer.

[0057] Then, if Figure 4 As shown, a first photolithography process is performed on the chip area 101, and a second photolithography process is performed on the suspended area 102 to form a patterned mask layer 210, and the patterned mask layer 210 exposes the metal layer 120 of the suspended area 102 and part of the metal layer 120 of the chip area 101. Specifically, a first photomask is used to form a first patterned mask layer 210A in the chip area 101, and a second photomask is used to form a second patterned mask layer 210B in the suspended area 102. In the embodiment of the present application, the first patterned mask layer 210A exposes part of the metal layer 120 of the chip area 101, and at the same time, covers part of the metal layer 120 of the chip area 101 to form a pad; the second patterned mask layer 210B exposes the metal layer 120 of the suspended area 102, that is, the mask layer 200 of the suspended area 102 is removed by the second photolithography process.

[0058] Among them, a first exposure process can be performed on the mask layer 200 of the chip area 101, and a second exposure process can be performed on the mask layer 200 of the suspended area 102; then, a development process is performed on the mask layer 200 of the chip area 101 and the suspended area 102 at the same time, thereby completing the first photolithography process and the second photolithography process to form the patterned mask layer 210.

[0059] Specifically, multiple first masks may be spliced ​​to perform the first exposure process on the mask layer 200 of the chip area 101. Multiple rounds of the second exposure process are performed on the mask layer 200 of the suspended area 102 through a second mask. In one embodiment of the present application, the number of rounds of the second exposure process is the same as the number of the first masks.

[0060] In an embodiment of the present application, two first masks are used to perform a first photolithography process to form a pad in the chip area. The semiconductor substrate structure 100 includes a plurality of chip areas 101. The two first masks can perform an exposure process on the same or different chip areas 101 simultaneously or in steps to complete the exposure of all the chip areas 101.

[0061] In the embodiment of the present application, the semiconductor substrate structure 100 includes a plurality of the suspended areas 102. All the suspended areas 102 may be exposed by the first exposure pattern 12A on the mask 10, and then all the suspended areas 102 may be exposed by the second exposure pattern 12B, so as to complete the exposure of each suspended area 102. Alternatively, one suspended area 102 may be exposed by the first exposure pattern 12A on the mask 10, and then another suspended area 102 may be exposed by the second exposure pattern 12B, usually the same suspended area 102, so as to complete the exposure of the suspended area 102; then, the next suspended area 102 may be exposed by the first exposure pattern 12A, and the next suspended area 102 may be exposed by the second exposure pattern 12B, so as to complete the exposure of the next suspended area 102; and so on, so as to complete the exposure of the chip area 101. The specific exposure sequence is not limited in the present application.

[0062] Then, if Figure 5 As shown, the metal layer 120 is patterned using the first patterned mask layer 210A as a mask to form a pad 300 in the chip area 101, and the metal layer 120 in the suspended area 102 is removed using the second patterned mask layer 210B as a mask. That is, using the patterned mask layer 210 as a mask, the metal layer 120 is etched to form a pad 300 in the chip area 101, and the metal layer 120 in the suspended area 102 is removed. In the embodiment of the present application, the mask layer 200 in the suspended area 102 is removed using the second mask, i.e., the mask 10, to expose the metal layer 120 in the suspended area 102, so that when etching the metal layer 120, the metal layer 120 in the suspended area 102 can be removed. Thereby, the warping degree of the semiconductor substrate structure 100 can be ensured to be normal, and the risk of slipping can be avoided.

[0063] Please refer to Figure 6Furthermore, the method for manufacturing the semiconductor device may further include: cutting the semiconductor substrate structure 100 along the suspended area 102, that is, cutting the chip to form a single chip. In the embodiment of the present application, since the metal layer 120 of the suspended area 102 is removed, the suspended area 102 is convenient for performing a cutting process. When the semiconductor substrate structure 100 is cut along the suspended area 102, the risk of a cutting knife rolling is avoided, the process reliability is improved, and the manufacturing cost is reduced.

[0064] In summary, in the photomask, exposure method and semiconductor device manufacturing method provided in the present application, the photomask 10 includes a first exposure pattern 12A and a second exposure pattern 12B, the first exposure pattern 12A and the second exposure pattern 12B extend in the same direction and have different sizes, the first exposure pattern 12A includes a first alignment mark 13A, and the second exposure pattern 12B includes a second alignment mark 13B, and at least two rounds of exposure are performed on the target using the first exposure pattern 12A and the second exposure pattern 12B, and the first alignment mark 13A is aligned with the second alignment mark 13B in two adjacent rounds of exposure, so that the photomask can be used to remove the metal layer on the same layer as the pad, thereby ensuring that the warping of the semiconductor substrate structure is normal and avoiding the risk of slippage. At the same time, it is also convenient for chip cutting during the subsequent packaging process and avoiding the risk of knife rolling.

[0065] In the present application, references to "one embodiment" or "some embodiments" mean that features, structures, or characteristics described in conjunction with the embodiment are included in at least one embodiment, at least some embodiments, of the present application. Therefore, the appearance of the phrases "in one embodiment" or "in some embodiments" in various places of the present application does not necessarily refer to the same or the same embodiments. In addition, in one or more embodiments, features, structures, or characteristics may be combined in any suitable combination and / or sub-combination.

[0066] Although some specific embodiments of the present application have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present application. The various embodiments of the present application may be combined in any manner without departing from the spirit and scope of the present application. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.

Claims

1. A photomask, characterized in that: The photomask includes a substrate and a first exposure pattern and a second exposure pattern formed on the substrate, the first exposure pattern and the second exposure pattern extend in the same direction and have different sizes, the first exposure pattern includes a first alignment mark, the second exposure pattern includes a second alignment mark, and at least two rounds of exposure are performed on the target area using the first exposure pattern and the second exposure pattern, and the first alignment mark is aligned with the second alignment mark in two adjacent rounds of exposure.

2. The photomask according to claim 1, wherein: The first alignment mark and the second alignment mark both include a first direction mark line and a second direction mark line. The first direction mark line and the second direction mark line are located on the boundary of the first exposure pattern or the second exposure pattern and intersect at a right angle.

3. The photomask according to claim 2, wherein: The aligning of the first alignment mark with the second alignment mark in two adjacent rounds of exposure comprises: The first direction mark of the first alignment mark and the first direction mark of the second alignment mark are on a straight line, and the second direction mark of the first alignment mark and the second direction mark of the second alignment mark overlap.

4. The photomask according to claim 1, wherein: The two exposure areas formed by two adjacent rounds of exposure are adjacent to each other and extend in the same direction.

5. The photomask according to claim 1, wherein: The target area is a suspended area on a semiconductor substrate structure, and the semiconductor substrate structure also includes a chip area. The first alignment mark and / or the second alignment mark are also used to align with a third alignment mark, and the third alignment mark is used to form an exposure process for the chip area.

6. The photomask according to claim 5, wherein: The first alignment mark, the second alignment mark and the third alignment mark are combined into a cross-shaped alignment mark.

7. An exposure method, characterized in that: The exposure method comprises: providing a first photomask, and using the first photomask to expose a target to form a first exposure area on the target; and, A second photomask is provided, wherein the second photomask includes a first exposure pattern and a second exposure pattern, wherein the first exposure pattern and the second exposure pattern extend in the same direction and have different sizes, wherein the first exposure pattern includes a first alignment mark, and the second exposure pattern includes a second alignment mark, and at least two rounds of exposure are performed on the target using the first exposure pattern and the second exposure pattern, wherein the first alignment mark is aligned with the second alignment mark in two adjacent rounds of exposure to form a second exposure area on the target.

8. The exposure method according to claim 7, wherein: Using the first photomask to expose the target includes: there are at least two first photomasks, and at least two first photomasks are spliced ​​together to expose the target, wherein the size of the first photomask is less than or equal to the maximum exposure field of view of the lithography machine.

9. The exposure method according to claim 7, wherein: The target is a semiconductor substrate structure, the first exposure area is used to form a pad in a chip area of ​​the semiconductor substrate structure, and the second exposure area is used to remove a metal layer on the same layer as the pad on a suspended area of ​​the semiconductor substrate structure.

10. A method for manufacturing a semiconductor device, characterized in that: The method for manufacturing the semiconductor device comprises: A semiconductor base structure is provided, wherein the semiconductor base structure comprises a semiconductor substrate and a metal layer formed on the semiconductor substrate, a mask layer is formed on the metal layer, and the semiconductor base structure comprises a chip area and a suspended area; Using a first photomask to form a first patterned mask layer in the chip area, and using a second photomask to form a second patterned mask layer in the suspended area; Using the first patterned mask layer as a mask to pattern the metal layer to form a pad in the chip area, and using the second patterned mask layer as a mask to remove the metal layer in the suspended area; Among them, the second photomask includes a substrate and a first exposure pattern and a second exposure pattern formed on the substrate, the first exposure pattern and the second exposure pattern extend in the same direction and have different sizes, the first exposure pattern includes a first alignment mark, and the second exposure pattern includes a second alignment mark, and at least two rounds of exposure are performed on the suspended area using the first exposure pattern and the second exposure pattern, and the first alignment mark is aligned with the second alignment mark in two adjacent rounds of exposure.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: Using a first photomask to form a first patterned mask layer in the chip region includes: using at least two first photomasks to splice together to perform a first exposure process on the chip region.

12. The method for manufacturing a semiconductor device according to claim 10 or 11, wherein: The semiconductor base structure further includes a rewiring layer formed on the semiconductor substrate, and the metal layer is formed on the rewiring layer.

13. The method for manufacturing a semiconductor device according to claim 10 or 11, characterized in that: The method for manufacturing the semiconductor device further includes: The semiconductor substrate structure is cut along the suspended region.

14. The method for manufacturing a semiconductor device according to claim 10 or 11, wherein: The semiconductor substrate structure includes a plurality of suspended regions, and each of the suspended regions extends along the same direction.

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