A model predictive control optimization method, system, device and storage medium

Abstract

The present invention relates to the field of heterogeneous computing technology, and discloses a model predictive control optimization method, system, device and storage medium, comprising obtaining motion state data from a Kalman state observer; constructing a state transfer matrix according to the motion state data; obtaining MPC parameters from an ARM processor; constructing a state prediction matrix according to the MPC parameters and the state transfer matrix; calculating the state prediction matrix using a matrix acceleration calculator to obtain the state prediction matrix; constructing an optimization solution key matrix according to the state prediction matrix and the MPC parameters; calculating the optimization solution key matrix using a parallel optimization solver to obtain an MPC control rate; performing time-efficiency monitoring on the ARM processor, the matrix acceleration calculator and the parallel optimization solver to obtain the MPC control execution time, and effectively judging the MPC control execution time according to a preset threshold time to obtain a judgment result; and by constructing a heterogeneous computing architecture, high-speed acceleration of the MPC optimization solution is achieved, and the response speed and accuracy of the MPC control are improved.

Description

Technical Field

[0001] The present invention relates to the field of heterogeneous computing technology, and in particular to a model predictive control optimization method, system, device and storage medium. Background Art

[0002] Model predictive control (MPC) is a control strategy based on a system's dynamic model and is widely used in complex dynamic systems. The core of MPC is to optimize control inputs in real time to minimize a cost function while complying with constraints. However, MPC has high computational complexity, especially when dealing with high-dimensional states and control inputs. This can lead to extended computation time and increased resource consumption, impacting real-time response and system performance.

[0003] Traditional MPC implementations often rely on general-purpose processors (CPUs). When processing high-dimensional states and control inputs, the computation time may increase significantly, resulting in control delays. This delay is particularly noticeable in high-frequency control scenarios (such as industrial automation and robotic control), directly affecting the system's real-time response and control accuracy. Summary of the Invention

[0004] In order to overcome the shortcomings of the existing technology, the purpose of the present invention is to provide a model predictive control optimization method, which is based on a heterogeneous computing architecture and utilizes an ARM processor and multiple modules within an FPGA chip to work together to achieve parallel computing, thereby accelerating the optimization and solution of the MPC calculation process, thereby obtaining the MPC control rate at high speed and in real time, and realizing optimized control of the model predictive control.

[0005] The first aspect of the present invention provides a model predictive control optimization method, which is applied to a model predictive control optimization system, wherein the model predictive control optimization system includes: a control device and an ARM processor electrically connected to the control device, a Kalman state observer, a matrix accelerator calculator and a parallel optimization solver; the model predictive control optimization method includes the steps of: obtaining motion state data from the Kalman state observer; using the ARM processor to perform data processing on the motion state data to obtain a state transfer matrix; using the matrix accelerator calculator to calculate the state transfer matrix to obtain a state prediction matrix; using the ARM processor to perform data processing on the state prediction matrix to obtain an optimization solution key matrix; using the parallel optimization solver to calculate the optimization solution key matrix to obtain an MPC control rate; performing time-effectiveness monitoring on the ARM processor, the matrix accelerator calculator and the parallel optimization solver to obtain the MPC control execution time, and performing an effective judgment on the MPC control execution time according to a preset threshold time to obtain a judgment result; if the judgment result is valid, generating an MPC effective instruction according to the MPC control rate.

[0006] Optionally, in a first implementation method of the first aspect of the present invention, the model predictive control optimization system also includes a hardware accelerated computing state machine, which is electrically connected to the Kalman state observer; obtaining motion state data from the Kalman state observer includes: when the preset acquisition program execution conditions are met, obtaining data information of the controlled object from the hardware accelerated computing state machine; and using the Kalman state observer to observe the data information of the controlled object to obtain motion state data.

[0007] Optionally, in a second implementation of the first aspect of the present invention, the state transfer matrix is ​​calculated using a matrix accelerator calculator to obtain a state prediction matrix, including: performing sparsity feature analysis on the state transfer matrix to obtain a sparsity calculation strategy; and controlling the matrix accelerator calculator to perform parallel calculations on the state transfer matrix according to the sparsity calculation strategy to obtain a state prediction matrix.

[0008] Optionally, in a third implementation method of the first aspect of the present invention, constructing an optimization solution key matrix based on the state prediction matrix and MPC parameters includes: obtaining MPC parameters from an ARM processor; constructing an initial optimization solution key matrix based on the MPC parameters; and constructing an optimization solution key matrix based on the state prediction matrix and the initial optimization solution key matrix.

[0009] Optionally, in a fourth implementation method of the first aspect of the present invention, the use of a parallel optimization solver to calculate the optimization solution key matrix to obtain the MPC control rate includes: constructing a parallel optimization solver according to the IADMM algorithm; and using the parallel optimization solver to calculate the optimization solution key matrix to obtain the MPC control rate.

[0010] Optionally, in a fifth implementation of the first aspect of the present invention, the ARM processor, matrix acceleration calculator and parallel optimization solver are time-sensitively monitored to obtain the MPC control execution time, and the MPC control execution time is effectively judged according to a preset threshold time to obtain a judgment result, including: time-sensitive monitoring of the ARM processor, matrix acceleration calculator and parallel optimization solver to obtain the MPC control execution time; when the preset main control program execution condition is met, the MPC control execution time is effectively judged according to the preset threshold time to obtain a judgment result.

[0011] Optionally, in a sixth implementation of the first aspect of the present invention, the MPC control execution time is obtained, and a valid judgment is made on the MPC control execution time based on a preset threshold time, and after obtaining the judgment result, the method further includes: if the judgment result is invalid, an MPC invalid instruction is generated based on a preset error flag.

[0012] The second aspect of the present invention provides a model predictive control optimization system, which includes: a control device and an ARM processor electrically connected to the control device, a Kalman state observer, a matrix acceleration calculator and a parallel optimization solver; the control device is used to execute the model predictive control optimization method as described above.

[0013] The third aspect of the present invention provides a model predictive control optimization device, which includes: a memory and at least one processor, wherein the memory stores instructions; at least one processor calls the instructions in the memory to enable the model predictive control optimization device to execute each step of the model predictive control optimization method described above.

[0014] A fourth aspect of the present invention provides a computer-readable storage medium having instructions stored thereon, which, when executed by a processor, implement the various steps of any of the above-mentioned model predictive control optimization methods.

[0015] The model predictive control optimization method proposed in this invention forms a heterogeneous computing architecture by combining an ARM processor with the Kalman state observer, matrix acceleration calculator and parallel optimization solver in the FPGA chip, thereby accelerating the MPC solution. This enables accurate MPC control rate to be obtained in a short time and efficient MPC control to be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0017] Figure 1 A first flow chart of the model predictive control optimization method provided by an embodiment of the present invention;

[0018] Figure 2 A second flow chart of the model predictive control optimization method provided by an embodiment of the present invention;

[0019] Figure 3 A third flow chart of the model predictive control optimization method provided in an embodiment of the present invention;

[0020] Figure 4 A fourth flow chart of the model predictive control optimization method provided in an embodiment of the present invention;

[0021] Figure 5 A fifth flow chart of the model predictive control optimization method provided in an embodiment of the present invention;

[0022] Figure 6 A sixth flow chart of the model predictive control optimization method provided in an embodiment of the present invention;

[0023] Figure 7 A seventh flow chart of the model predictive control optimization method provided in an embodiment of the present invention;

[0024] Figure 8 A schematic diagram of the structure of a model predictive control optimization system provided by an embodiment of the present invention;

[0025] Figure 9 A schematic diagram of the structure of a model predictive control optimization device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The present invention provides a model predictive control optimization method, system, device and storage medium. Through the scheduling and coordination between an ARM processor, a Kalman state observer, a matrix acceleration calculator and a parallel optimization solver, a heterogeneous computing architecture is formed, which achieves high-speed acceleration of MPC optimization solution, thereby enabling accurate MPC control rate to be obtained in a short time.

[0027] The terms "first," "second," "third," "fourth," and the like (if any) in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" or "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0028] For ease of understanding, the specific process of the embodiment of the present invention is described below. Figure 1 , an embodiment of the model predictive control optimization method in an embodiment of the present invention includes: the model predictive control optimization system includes: a control device and an ARM processor electrically connected to the control device, a Kalman state observer, a matrix acceleration calculator and a parallel optimization solver;

[0029] In this embodiment, the ARM processor is used to connect to the host computer, receive instructions from the host computer and feed back the results of MPC control to the host computer; the ARM processor is also used to assist in constructing the state transfer matrix and optimizing the key matrix; the Kalman state observer, the matrix acceleration calculator and the parallel optimization solver are functional modules within the FPGA chip, among which the Kalman state observer is used to obtain the motion state of the controlled object, and the matrix acceleration calculator and the parallel optimization solver are used to parallelly calculate the state prediction matrix and optimize the key matrix, thereby optimizing the solution process; through the scheduling and coordination between the ARM processor, the Kalman state observer, the matrix acceleration calculator and the parallel optimization solver, the optimization of model predictive control (MPC) is achieved.

[0030] In one embodiment, the model predictive control optimization system further includes a DMA controller, a DMA state machine, a hardware accelerated computing state machine, a DDR memory, a FIFO memory, and a BRAM memory; the DMA controller is used to control data transmission, the DMA state machine and the hardware accelerated computing state machine are used for scheduling control, and the DDR memory, the FIFO memory, and the BRAM memory are used to store data. Specifically, data that needs to be called by the ARM processor is stored in the DDR memory, data that needs to be called by the Kalman state observer, the matrix accelerated calculator, and the parallel optimization solver is stored in the FIFO memory, and data output after processing by the Kalman state observer, the matrix accelerated calculator, and the parallel optimization solver is stored in the BRAM memory; the hardware accelerated computing state machine is used to schedule the Kalman state observer, the matrix accelerated calculator, and the parallel optimization solver to work, and the DMA state machine is used to schedule the DMA controller so that the DMA controller controls data transmission between the DDR memory, the FIFO memory, and the BRAM memory.

[0031] The model predictive control optimization method comprises the steps of:

[0032] 101. Obtain motion state data from the Kalman state observer;

[0033] In this embodiment, when the collection interval is met, the sensor is first used to collect data information of the controlled object. Then, the hardware accelerated computing state machine in the FPGA obtains the data information and schedules the Kalman state observer to work. The Kalman state observer observes the data information of the controlled object, thereby obtaining the motion state information of the controlled object and storing the motion state information in the BRAM memory. After the storage is completed, the hardware accelerated computing state machine sends a motion state storage instruction to the DMA state machine. After receiving the motion state storage instruction, the DMA state machine schedules the DMA controller to retrieve the motion state information from the BRAM memory and store the motion state information in the DDR memory so that the subsequent ARM processor can call the motion state information. After the motion state information is stored, the DMA state machine generates a storage completion signal and feeds it back to the hardware accelerated computing state machine. In this embodiment of the present invention, the hardware accelerated computing state machine in the FPGA periodically reads data information from the sensor and transmits it to the Kalman state observer to generate motion state information, ensuring that the system can obtain the motion state of the controlled object in real time and accurately, providing reliable basic data for subsequent prediction and control.

[0034] 102. Use the ARM processor to process the motion state data to obtain a state transfer matrix;

[0035] In this embodiment, MPC control is executed on a timed basis. When the interval for MPC control execution is met, the ARM processor reads the motion state information from the DDR memory and processes the motion state data to construct a state transfer matrix. The state transfer matrix is ​​then stored back in the DDR for subsequent calls. Because MPC calculations are sparse, the state transfer matrix can be stored as a sparse representation vector. The state transfer matrix describes how the system state naturally evolves over time in the absence of control input. In this embodiment of the present invention, the construction of the state transfer matrix marks the beginning of MPC control. Through the state transfer matrix, the system can simulate and predict the state changes of the controlled object over a period of time in the future, providing the necessary prediction information for MPC.

[0036] 103. Use a matrix acceleration calculator to calculate the state transfer matrix to obtain a state prediction matrix;

[0037] In this embodiment, after the state transfer matrix is ​​constructed, the ARM processor sends a state prediction matrix calculation instruction to the hardware acceleration calculator. The state prediction matrix calculation instruction is used to control the matrix acceleration calculator in the FGPA chip to perform parallel calculation on the state transfer matrix, thereby obtaining the state prediction matrix. Specifically, after receiving the state prediction matrix calculation instruction, the hardware acceleration calculation state machine first sends a matrix fetch instruction to the DMA state machine. The DMA state machine controls the DMA controller to fetch the state transfer matrix from the DDR memory and store it in the FIFO memory according to the matrix fetch instruction. After the storage is completed, the DMA state machine feeds back the storage result to the hardware acceleration calculation state machine. The hardware acceleration calculation state machine then issues a calculation instruction to the matrix acceleration calculator. The matrix acceleration calculator fetches the state transfer matrix from the FIFO memory and performs parallel calculation to obtain the state prediction matrix. After the state prediction matrix is ​​calculated, it will be stored in the BRAM memory. Subsequently, the hardware acceleration calculation state machine sends a matrix store instruction to the DMA state machine. The DMA state machine schedules the DMA controller to fetch the state prediction matrix from the BRAM memory and store it in the DDR memory for subsequent call. After the DMA state machine scheduling is completed, the execution result is fed back to the hardware acceleration calculation state machine, and the hardware calculation acceleration state machine then feeds back the execution result to the ARM controller. Through the scheduling and coordination of the ARM processor, hardware accelerated computing state machine, and DMA state machine, compared with the method of using only the CPU to complete matrix operations, the present invention better utilizes the scheduling advantages of the ARM processor, hardware accelerated computing state machine, and DMA state machine and the computing advantages of the PFGA internal matrix acceleration calculator, thereby better realizing MPC control.

[0038] 104. Use the ARM processor to process the state prediction matrix to obtain the key matrix for optimization solution;

[0039] In this embodiment, before constructing and executing the optimization solution key matrix, it is necessary to obtain MPC parameters from the ARM processor, initialize the MPC parameters, set the MPC prediction step size, control step size, weight matrix, etc., and obtain the MPC parameters; the ARM processor can construct the initial optimization solution key matrix based on the MPC parameters; then the ARM processor takes out the state prediction matrix from the DDR memory, calculates the optimization solution matrix based on the initial optimization solution key matrix and the state prediction matrix, and uses the sparsity of the optimization solution matrix to store it in the DDR memory as a sparse representation vector for subsequent call. In this embodiment, the ARM processor coordinates the construction of the optimization solution key matrix and dispatches it to the subsequent computing unit. Compared with the method of using only the CPU to complete matrix operations, the present invention better utilizes the scheduling advantages of the ARM processor and the computing advantages of the internal computing module of the PFGA, thereby better realizing MPC control.

[0040] 105. Use the parallel optimization solver to calculate the key matrix of the optimization solution and obtain the MPC control rate;

[0041] In this embodiment, when solving the optimization solution key matrix, the ARM processor sends an optimization solution instruction to the hardware acceleration calculator; the optimization solution instruction is used to control the parallel optimization solver in the FGPA chip to calculate the optimization solution key matrix, thereby obtaining the MPC control rate; specifically, after receiving the optimization solution instruction, the hardware acceleration calculation state machine first sends a matrix fetch instruction to the DMA state machine, and the DMA state machine controls the DMA controller to fetch the optimization solution key matrix from the DDR memory according to the matrix fetch instruction and stores it in the FIFO memory. After the storage is completed, the DMA state machine feeds back the storage result to the hardware acceleration calculation state machine, and the hardware acceleration calculation state machine immediately issues a calculation instruction to the parallel optimization solver, and the parallel optimization solver fetches the optimization solution key matrix from the FIFO memory and performs calculation to obtain the MP control rate. C control rate; after the MPC control rate is solved, it is stored in the BRAM memory. Subsequently, the hardware accelerated calculation state machine sends a matrix store instruction to the DMA state machine, so that the DMA state machine schedules the DMA controller to retrieve the MPC control rate from the BRAM memory and store it in the DDR memory; after the MPC control rate is stored, the hardware accelerated calculation state machine feeds back MPC calculation completion information to the ARM processor; in this embodiment of the present invention, the completion of the calculation of the MPC control rate marks the end of MPC control.

[0042] 106. Perform time-efficiency monitoring on the ARM processor, matrix acceleration calculator, and parallel optimization solver to obtain the MPC control execution time, and effectively judge the MPC control execution time according to the preset threshold time to obtain a judgment result;

[0043] In this embodiment, the ARM processor, matrix acceleration calculator and parallel optimization solver are monitored for timeliness, and the total time spent in cooperating to solve the MPC control rate is monitored to obtain the MPC control execution time; the ARM processor effectively judges the MPC control execution time based on the preset threshold time to obtain a judgment result. When the MPC control execution time is less than the threshold time, it is considered that the MPC control has been effectively optimized, and the judgment result is valid; when the MPC control execution time is greater than the threshold time, it is considered that the MPC control has not been effectively optimized, and the judgment result is invalid. By setting the threshold time, the system can determine whether the MPC control execution is completed within the specified time, ensure that the execution of the MPC control is effective, avoid outputting the wrong MPC control rate, and thus ensure the real-time and stability of the system.

[0044] 107. If the judgment result is valid, then generate an MPC valid instruction according to the MPC control rate;

[0045] In this embodiment, if the judgment result is valid, the ARM processor generates an MPC valid instruction. The MPC valid instruction is a valid flag that indicates that the current MPC control strategy should be executed. Based on the MPC valid instruction, the ARM processor outputs the MPC control rate to the controlled object. Subsequently, the ARM processor generates a reset signal to initialize the model predictive control system and prepare for the next MPC control implementation. When the MPC control execution time is valid, the system can generate valid control instructions based on the MPC control rate, achieving precise control of the controlled object.

[0046] In an embodiment of the present invention, an ARM processor and an FPGA are used to form a heterogeneous computing architecture to implement MPC optimization. The ARM processor independently executes a main control program, which is used to control the MPC optimization process. The ARM processor and the FPGA cooperate to implement MPC control, and the MPC control is based on using the ARM processor to deploy a matrix acceleration calculator and a parallel optimization solver within the FPGA chip to implement MPC matrix solution. The Kalman state observer within the FPGA chip is responsible for obtaining the motion state of the controlled object. Specifically, the Kalman state observer is first used to obtain the motion state information of the controlled object, and then MPC control is enabled. The motion state data is processed by the ARM processor to obtain a state transition matrix, and then the matrix acceleration calculator within the FPGA chip is used to calculate the state transition matrix to obtain a state prediction matrix. The ARM processor then constructs an optimization solution key matrix based on the state prediction matrix, and uses the parallel optimization solver to solve the optimization solution key matrix to obtain the MPC control rate, thereby completing the MPC control. The ARM processor periodically executes the main control program, obtains the MPC control execution time, and makes a valid judgment. If valid, an MPC valid instruction is generated and the MPC control rate is output.

[0047] The model predictive control optimization method proposed in this invention forms a heterogeneous computing architecture by combining an ARM processor with the Kalman state observer, matrix acceleration calculator and parallel optimization solver in the FPG A chip, thereby accelerating the MPC solution. This enables accurate MPC control rate to be obtained in a short time and efficient MPC control to be achieved.

[0048] See also Figure 2 The second embodiment of the model predictive control optimization method in the embodiment of the present invention includes:

[0049] The model predictive control optimization system further includes a hardware accelerated computing state machine, wherein the hardware accelerated computing state machine is electrically connected to the Kalman state observer;

[0050] In this embodiment, the hardware accelerated computing state machine is used to obtain data information of the controlled object from external sensors, and assist in scheduling and controlling the Kalman state observer, the matrix accelerated calculator, and the parallel optimization solver.

[0051] 201. When the preset acquisition program execution conditions are met, data information of the controlled object is obtained from the hardware accelerated computing state machine;

[0052] In this embodiment, when the preset acquisition program execution conditions are met, data information about the controlled object is acquired from the hardware-accelerated computing state machine. Specifically, the acquisition program execution condition is a timed trigger. A timer is provided within the FPGA to monitor the trigger time for the acquisition program execution. When the trigger time is reached, the acquisition program is executed. It should be noted that the hardware-accelerated computing state machine within the FPGA is typically electrically connected to external sensors, through which the data information about the controlled object is acquired.

[0053] 202. Using the Kalman state observer to observe the data information of the controlled object to obtain the motion state data;

[0054] In this embodiment, a Kalman state observer is built into the FPGA. Parameters such as the initial state estimate, state covariance matrix, observation noise covariance matrix, and process noise covariance matrix are set for the Kalman state observer. Before each data acquisition, the Kalman state observer predicts the current state estimate and state covariance matrix based on the previous state estimate and the system model. When new data arrives from the sensor, the Kalman state observer uses this data to update the state estimate and state covariance matrix. Ultimately, the Kalman state observer outputs the current state estimate, resulting in the motion state data for the controlled object. Furthermore, because the Kalman algorithm involves matrix and vector operations, the FPGA's internal BRAM memory is required to store intermediate results and parameters.

[0055] See also Figure 3 , a third embodiment of the model predictive control optimization method in the embodiment of the present invention includes:

[0056] 301. Perform sparsity feature analysis on the state transfer matrix to obtain a sparsity calculation strategy;

[0057] In this embodiment, the matrix computing accelerator obtains the state transfer matrix from the FIFO memory, performs sparsity feature analysis on the state transfer matrix, traverses each element in the state transfer matrix, counts the number of zero elements and the distribution of non-zero elements, analyzes the sparsity pattern of the state transfer matrix based on the statistical information of zero elements and non-zero elements, and then formulates a sparsity computing strategy based on its sparsity pattern; the sparsity computing strategy is used to accelerate the parallel computing of the state transfer matrix, and the sparsity computing strategy can be a block sparsity processing strategy or a band sparsity computing strategy.

[0058] 302. Controlling the matrix acceleration calculator to perform parallel calculations on the state transfer matrix according to the sparsity calculation strategy to obtain a state prediction matrix;

[0059] In this embodiment, according to the sparsity calculation strategy, the calculation tasks of the state transfer matrix are distributed, so that multiple cores of the matrix acceleration calculator can process different parts of the calculation respectively, reducing the calculation time, and finally obtaining the state prediction matrix, and storing the state prediction matrix in the BRAM memory for subsequent calls.

[0060] See also Figure 4 The fourth embodiment of the model predictive control optimization method in the embodiment of the present invention includes:

[0061] 401. Obtain MPC parameters from the ARM processor;

[0062] In this embodiment, before constructing the key matrix for executing the optimization solution, it is necessary to obtain MPC parameters from the ARM processor, initialize the MPC parameters, set the MPC prediction step size, control step size, weight matrix, etc., and obtain the MPC parameters; the ARM processor can construct the initial optimization solution key matrix based on the MPC parameters.

[0063] 402. Construct an initial optimization solution key matrix based on MPC parameters;

[0064] In this embodiment, it is first necessary to use the MPC parameters to determine the dimensional information required to construct the initial optimization solution key matrix; for example, the number of rows of the matrix is ​​determined according to the prediction step size and the number of system state variables, and the number of columns of the matrix is ​​determined according to the control step size and the number of control variables, thereby completing the construction of the initial optimization solution key matrix.

[0065] 403. Constructing an optimization solution key matrix based on the state prediction matrix and the initial optimization solution key matrix;

[0066] In this embodiment, the ARM processor retrieves the state prediction matrix from the DDR memory and, based on the initial optimization solution key matrix and the state prediction matrix, calculates the optimized solution matrix. The optimized solution matrix, taking advantage of its sparsity, is stored in the DDR memory as a sparse representation vector for subsequent access. Throughout this embodiment, the ARM processor fully utilizes its core role in coordination and scheduling, not only constructing the optimized solution key matrix but also meticulously assigning tasks to its computational flow. Compared to methods that solely utilize the CPU to perform matrix operations, this invention better leverages the scheduling advantages of the ARM processor and the computational advantages of the PFGA on-chip computing module, thereby better implementing MPC control.

[0067] See also Figure 5 The fifth embodiment of the model predictive control optimization method in the embodiment of the present invention includes:

[0068] 501. Construct a parallel optimization solver based on the IADMM algorithm;

[0069] In this example, the optimization problem in the MPC algorithm is first defined, including the objective function, constraints, variables, and parameters. This optimization problem is then matched with that of the IDMAA algorithm, thereby establishing a parallel processing framework. Based on this parallel processing framework, the specific steps of the IDMAA algorithm are implemented, completing the construction of a parallel optimization solver. Because IADMM approaches the optimal solution by alternating variable updates, the parallel optimization solver can achieve high-throughput floating-point solving using a QP solver, thereby accelerating the calculation of key matrices for the optimization solution.

[0070] 502. Calculate the key matrix of the optimization solution using a parallel optimization solver to obtain the MPC control rate;

[0071] In this embodiment, when solving the optimization key matrix, the ARM processor sends an optimization instruction to the hardware acceleration calculator. The optimization instruction is used to control the parallel optimization solver within the FGPA chip to calculate the optimization key matrix, thereby obtaining the MPC control rate. Specifically, after receiving the optimization instruction, the hardware acceleration calculation state machine first sends a matrix fetch instruction to the DMA state machine. The DMA state machine, based on the matrix fetch instruction, controls the DMA controller to retrieve the optimization key matrix from the DDR memory and store it in the FIFO memory. After storage is completed, the DMA state machine feeds the stored result back to the hardware acceleration calculation state machine. The hardware acceleration calculation state machine then issues a calculation instruction to the parallel optimization solver, which retrieves the optimization key matrix from the FIFO memory. The optimization key matrix is ​​used as input to the row optimization solver, which executes the IADMM algorithm to solve the MPC control rate. The MPC control rate is ultimately obtained and stored in the BRAM memory. The MPC control rate is used to guide the actual control input of the system over a period of time. In this embodiment of the present invention, the completion of the MPC control rate calculation marks the end of MPC control.

[0072] See also Figure 6 The sixth embodiment of the model predictive control optimization method in the embodiment of the present invention includes:

[0073] 601. Monitor the timing of the ARM processor, matrix acceleration calculator, and parallel optimization solver to obtain the MPC control execution time;

[0074] In this embodiment, the ARM processor, the matrix acceleration calculator, and the parallel optimization solver are monitored for their timeliness, and the total time taken for them to cooperate in solving the MPC control rate is monitored to obtain the MPC control execution time.

[0075] 602. When the preset main control program execution condition is met, the MPC control execution time is effectively judged according to the preset threshold time to obtain a judgment result;

[0076] When the preset main control program execution conditions are met, the ARM processor effectively judges the MPC control execution time based on the preset threshold time and obtains a judgment result; when the MPC control execution time is less than the threshold time, it is considered that the MPC control has been effectively optimized, and the judgment result is valid; when the MPC control execution time is greater than the threshold time, it is considered that the MPC control has not been effectively optimized, and the judgment result is invalid.

[0077] See also Figure 7 The seventh embodiment of the model predictive control optimization method in the embodiment of the present invention includes:

[0078] 701. If the judgment result is invalid, an MPC invalid instruction is generated according to a preset error flag;

[0079] In this embodiment, when the judgment result is invalid, the ARM processor generates an MPC invalid instruction based on a preset error flag. The MPC invalid instruction indicates that the current MPC control strategy should not be executed. The ARM processor then generates a reset signal to initialize the model predictive control system and prepare for the next MPC control execution. When the MPC control execution time is invalid, the system can generate an error instruction in a timely manner, avoiding system damage due to erroneous control, thereby improving system reliability and security.

[0080] The above describes the model predictive control optimization method in the embodiment of the present invention. The following describes the model predictive control optimization system in the embodiment of the present invention. Figure 8 In one embodiment of the present invention, a model predictive control optimization system includes:

[0081] The model predictive control optimization system includes: a control device 801 and an ARM processor 802 electrically connected to the control device 801, a Kalman state observer 8031, a matrix acceleration calculator 8032 and a parallel optimization solver 8033; the control device 801 is used to execute the model predictive control optimization method described above.

[0082] In one embodiment, the model predictive control optimization system further includes a DMA controller 804, a DMA state machine 805, a hardware accelerated computing state machine 806, a DDR memory 807, a FIFO memory 808, and a BRAM memory 809 electrically connected to the control device 801;

[0083] The ARM processor 802 is electrically connected to the DMA controller 804, the DMA state machine 805, the hardware accelerated computing state machine 806, and the DDR memory 807. The ARM processor 802 is used to issue instructions to the DMA controller 804, the DMA state machine 805, the hardware accelerated computing state machine 806, and the DDR memory 807.

[0084] The DMA controller 804 is electrically connected to the ARM processor 802, the DMA state machine 805, the DDR memory 807, the FIFO memory 808, and the BRAM memory 809. The DMA controller 804 receives instructions from the DMA state machine 805 and controls data transmission between the ARM processor 802, the DDR memory 807, the FIFO memory 808, and the BRAM memory 809.

[0085] The hardware accelerated computing state machine 806 is electrically connected to the ARM processor 802, the DMA state machine 805, the BRAM memory 809, the Kalman state observer 8031, the matrix accelerated calculator 8032, and the parallel optimization solver 8033; the hardware accelerated computing state machine 806 is used to receive instructions from the ARM processor 802 and send the instructions to the DMA state machine 805, the Kalman state observer 8031, the matrix accelerated calculator 8032, and the parallel optimization solver 8033;

[0086] The data that needs to be called by the ARM processor 802 is stored in the DDR memory 807, the data that needs to be called by the Kalman state observer 8031, the matrix acceleration calculator 8032 and the parallel optimization solver 8033 is stored in the FIFO memory 808, and the data output after processing by the Kalman state observer 8031, the matrix acceleration calculator 8032 and the parallel optimization solver 8033 is stored in the BRAM memory 809.

[0087] Figure 9is a schematic diagram of the structure of a model predictive control optimization device provided by an embodiment of the present invention. The model predictive control optimization device 900 may vary significantly due to different configurations or performances, and may include one or more processors (central processing units, CPUs) 910 (e.g., one or more processors) and a memory 920, and one or more storage media 930 (e.g., one or more mass storage devices) storing application programs 933 or data 932. The memory 920 and the storage medium 930 may be either short-term storage or persistent storage. The program stored in the storage medium 930 may include one or more modules (not shown), each of which may include a series of instruction operations in the model predictive control optimization device 900. Furthermore, the processor 910 may be configured to communicate with the storage medium 930, and execute a series of instruction operations in the storage medium 930 on the model predictive control optimization device 900 to implement the steps of the model predictive control optimization method provided by the above-mentioned method embodiments.

[0088] The model predictive control optimization device 900 may further include one or more power supplies 940, one or more wired or wireless network interfaces 950, one or more input and output interfaces 960, and / or one or more operating systems 931, such as Windows Server, Mac OS X, Unix, Linux, FreeBSD, etc. It will be understood by those skilled in the art that Figure 9 The illustrated structure of the model predictive control optimization device does not constitute a limitation on the model predictive control optimization device, and may include more or fewer components than illustrated, or a combination of certain components, or a different arrangement of components.

[0089] The present invention also provides a computer-readable storage medium, which may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. The computer-readable storage medium stores instructions, which, when executed on a computer, enable the computer to execute the steps of the model predictive control optimization method.

[0090] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, devices, and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0091] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc., various media that can store program code.

[0092] Finally, it should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art will be able to modify the technical solutions described in the aforementioned embodiments or substitute equivalents for some of the technical features. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A model predictive control optimization method, characterized in that: The invention is applied to a model predictive control optimization system, which includes: a control device and an ARM processor electrically connected to the control device, a Kalman state observer, a matrix acceleration calculator, and a parallel optimization solver; the model predictive control optimization method includes the following steps: Obtain motion state data from the Kalman state observer; The motion state data is processed using an ARM processor to obtain a state transfer matrix; the state transfer matrix is ​​calculated using a matrix acceleration calculator to obtain a state prediction matrix; the state prediction matrix is ​​processed using an ARM processor to obtain a key matrix for optimization solution; The parallel optimization solver is used to calculate the key matrix of the optimization solution to obtain the MPC control rate; the ARM processor, matrix acceleration calculator and parallel optimization solver are monitored for timeliness to obtain the MPC control execution time, and the MPC control execution time is effectively judged based on the preset threshold time to obtain the judgment result; If the judgment result is valid, an MPC valid instruction is generated according to the MPC control rate.

2. The model predictive control optimization method according to claim 1, characterized in that: The model predictive control optimization system further includes a hardware accelerated computing state machine, wherein the hardware accelerated computing state machine is electrically connected to the Kalman state observer; Acquiring motion state data from the Kalman state observer includes: When the preset acquisition program execution conditions are met, the data information of the controlled object is obtained from the hardware accelerated computing state machine; The Kalman state observer is used to observe the data information of the controlled object to obtain the motion state data.

3. The model predictive control optimization method according to claim 1, characterized in that: The state prediction matrix is ​​obtained by calculating the state transfer matrix using a matrix acceleration calculator, including: Perform sparsity feature analysis on the state transfer matrix to obtain the sparsity calculation strategy; According to the sparsity calculation strategy, the matrix acceleration calculator is controlled to perform parallel calculations on the state transfer matrix to obtain the state prediction matrix.

4. The model predictive control optimization method according to claim 1, characterized in that: The key matrix for optimizing and solving the problem is constructed based on the state prediction matrix and the MPC parameters, including: Get MPC parameters from the ARM processor; Construct the initial optimization solution key matrix based on MPC parameters; The optimization solution key matrix is ​​constructed according to the state prediction matrix and the initial optimization solution key matrix.

5. The model predictive control optimization method according to claim 1, characterized in that: The method of using a parallel optimization solver to calculate the optimization key matrix to obtain the MPC control rate includes: Construct a parallel optimization solver based on the IADMM algorithm; The parallel optimization solver is used to calculate the key matrix of the optimization solution and obtain the MPC control rate.

6. The model predictive control optimization method according to claim 1, characterized in that: The ARM processor, the matrix acceleration calculator, and the parallel optimization solver are monitored for time efficiency to obtain the MPC control execution time, and the MPC control execution time is effectively judged according to a preset threshold time to obtain a judgment result, including: Monitor the timing of the ARM processor, matrix acceleration calculator, and parallel optimization solver to obtain the MPC control execution time; When the preset main control program execution conditions are met, the MPC control execution time is effectively judged according to the preset threshold time to obtain a judgment result.

7. The model predictive control optimization method according to claim 1, characterized in that: The method of obtaining the MPC control execution time and effectively judging the MPC control execution time according to a preset threshold time, and obtaining the judgment result, includes: If the judgment result is invalid, an MPC invalid instruction is generated according to the preset error flag.

8. A model predictive control optimization system, characterized in that: The model predictive control optimization system includes: a control device and an ARM processor, a Kalman state observer, a matrix acceleration calculator and a parallel optimization solver electrically connected to the control device; the control device is used to execute the model predictive control optimization method as described in any one of claims 1 to 7.

9. A model predictive control optimization device, characterized in that: The model predictive control optimization device includes: a memory and at least one processor, wherein instructions are stored in the memory; at least one of the processors calls the instructions in the memory so that the model predictive control optimization device executes the various steps of the model predictive control optimization method as described in any one of claims 1 to 7.

10. A computer-readable storage medium having instructions stored thereon, characterized in that: When the instructions are executed by a processor, the various steps of the model predictive control optimization method according to any one of claims 1 to 7 are implemented.

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