Directed and looped graph-based instruction time sequence distribution method

Abstract

The invention relates to the technical field of programmable safety controllers, and particularly provides an instruction time sequence distribution method based on a directed and looped graph. The method comprises the following steps: constructing an initial directed and looped graph according to an instruction connection relationship; determining a starting point, performing sequential traversal on the initial directed and looped graph according to a path end constraint condition, searching an instruction path, and generating an instruction path set; removing repeated paths from the instruction path set, and sorting according to path lengths to obtain an action path list; establishing an instruction priority list, calculating the priority of the instruction according to the path sequence of the action path list, and updating the priority of the instruction in the instruction priority list; classifying and sorting the instruction priority list according to the updated instruction priorities to obtain an execution sequence of the instructions; according to the instruction execution sequence, the instruction set is loaded, the optimal instruction execution sequence is obtained through the method, the response speed of a machine is increased, the response time is shortened, and the output correctness is improved.

Description

Technical Field

[0001] The invention relates to the technical field of programmable safety controllers, and in particular to an instruction timing distribution method based on a directed cyclic graph. Background Art

[0002] A programmable safety controller is a programmable logic controller specially designed to meet high safety requirements. It is widely used in industrial automation fields such as logistics automation, safety protection and robot navigation.

[0003] Programmable safety controllers are programmed using function block diagrams. The function block diagram is edited on a dedicated host computer software, and the edited program is downloaded to the controller, which runs according to the configured program. For the controller, function blocks are equivalent to instructions, and the timing of instructions directly affects the response time of the machine and even the correctness of the output. However, the function block diagram program is large in scale and has complex branches. How to obtain the optimal instruction execution sequence is a problem that needs to be solved at present. Summary of the invention

[0004] In view of this, the present invention provides an instruction timing allocation method based on a directed cyclic graph to obtain the optimal instruction execution sequence, improve the response speed of the machine, reduce the response time, and improve the correctness of the output.

[0005] In a first aspect, the present invention provides an instruction timing allocation method based on a directed cyclic graph, the method comprising: Step 1: Construct an initial directed cyclic graph based on the instruction connection relationship; Step 2: Determine the starting point, traverse the initial directed cyclic graph in order according to the path end constraint, find the instruction path, and generate the instruction path set S; Step 3: Remove duplicate paths from the instruction path set S and sort them by path length to obtain the action path list S 1 ; Step 4: Create a command priority list , according to the action path list S 1 Calculate the priority of the instruction according to the path order, and update the priority of the instruction in the instruction priority list; Step 5: According to the updated instruction priority, the instruction priority list is classified and sorted to obtain the execution order of the instructions; Step 6: Load the instruction set according to the execution order of the instructions.

[0006] Optionally, step 1 includes: The connected instructions, inputs, and outputs are regarded as vertices on a directed cyclic graph, and the connection relationship between them is regarded as an edge of the directed cyclic graph, forming a graph G=(V,E), where V is a non-empty finite set of vertices and E is a set of edges.

[0007] Optionally, the basis for determining the starting point in step 2 is to take the vertex of the input type as the starting point until the traversal starting from the last starting point is completed, that is, the search for all feasible instruction paths is completed; The path ending constraint condition includes that if there is no subsequent vertex or the next output node is acyclic, the path ends; The sequential traversal is a depth-first search, which specifically starts from a vertex of the graph, visits vertices along a path until it is impossible to continue, then backtracks to the previous vertex and continues to explore other paths.

[0008] Optionally, the instruction path in step 2 is specifically as follows: Assume that from vertex V i Starting from the starting point, visit the vertices along the path Path until the vertex V j If you cannot continue, is an instruction path; then we get V i is all the paths of the starting point; similarly, all the paths of other starting points are obtained, and finally the instruction path set S is obtained.

[0009] Optionally, in step 3, duplicate paths are removed, specifically, the assumed paths , and Repeat all, or Included in Path j , then filter out ; The action path list S 1 After filtering for duplicate paths, sort the remaining set elements by path length to obtain the action path list S 1 .

[0010] Optionally, in step 4, a command priority list is established. ,in Indicates the vertex of the instruction type in graph G; express Priority; ; The priority calculation is specifically based on the assumption that the path , if exist The order in is higher than The current priority is updated Priority .

[0011] Optionally, in step 5, the classification and sorting are performed such that the instructions with the same priority are classified into one category, and the instruction priority list is sorted according to the priority.

[0012] Optionally, step 6 comprises loading the instructions according to the instruction order calculated in the instruction priority list.

[0013] In a second aspect, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored program, wherein when the program is running, the device where the computer-readable storage medium is located is controlled to execute the instruction timing allocation method based on a directed cyclic graph in the first aspect or any possible implementation of the first aspect.

[0014] In a third aspect, an embodiment of the present invention provides an electronic device, comprising: one or more processors; a memory; and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions, which, when executed by the device, enable the device to execute the instruction timing allocation method based on a directed cyclic graph in the first aspect or any possible implementation of the first aspect.

[0015] In the technical solution provided by the present invention, the method includes constructing an initial directed cyclic graph according to the instruction connection relationship; determining the starting point, sequentially traversing the initial directed cyclic graph according to the path end constraint condition, finding the instruction path, and generating an instruction path set S; removing duplicate paths from the instruction path set S, and sorting them according to the path length to obtain an action path list S 1 ; Establish a command priority list, according to the action path list S 1 The path order is calculated, the priority of the instruction is calculated, and the priority of the instruction is updated in the instruction priority list; according to the updated instruction priority, the instruction priority list is classified and sorted to obtain the execution order of the instruction; according to the execution order of the instruction, the instruction set is loaded. Through this method, the optimal instruction execution order is obtained, the response speed of the machine is improved, the response time is reduced, and the correctness of the output is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A flowchart of an instruction timing allocation method based on a directed cyclic graph provided by an embodiment of the present invention; Figure 2A schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] It should be clear that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention are also intended to include plural forms, unless the context clearly indicates other meanings.

[0021] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0022] The word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0023] Figure 1 A flowchart of a method for allocating instruction timing based on a directed cyclic graph provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the method includes: Step 1: Construct an initial directed cyclic graph based on the instruction connection relationship.

[0024] In the embodiment of the present invention, step 1 includes: The connected instructions, inputs, and outputs are regarded as vertices on a directed cyclic graph, and the connection relationship between them is regarded as an edge of the directed cyclic graph, forming a graph G=(V,E), where V is a non-empty finite set of vertices and E is a set of edges.

[0025] Step 2: Determine the starting point, traverse the initial directed cyclic graph sequentially according to the path end constraint, find the instruction path, and generate the instruction path set S.

[0026] In the embodiment of the present invention, the basis for determining the starting point in step 2 is to take the vertex of the input type as the starting point until the traversal starting from the last starting point is completed, that is, the search for all feasible instruction paths is completed; The path ending constraint condition includes that if there is no subsequent vertex or the next output node is acyclic, the path ends; The sequential traversal is a depth-first search, which specifically starts from a vertex of the graph, visits vertices along a path until it is impossible to continue, then backtracks to the previous vertex and continues to explore other paths.

[0027] In the embodiment of the present invention, the instruction path in step 2 is specifically as follows: Assume that from vertex V i Starting from the starting point, visit the vertices along the path Path until the vertex V j If you cannot continue, is an instruction path; then we get V i is all the paths of the starting point; similarly, all the paths of other starting points are obtained, and finally the instruction path set S is obtained.

[0028] Step 3: Remove duplicate paths from the instruction path set S and sort them by path length to obtain the action path list S 1 .

[0029] In the embodiment of the present invention, the duplicate paths are removed in step 3, specifically, the assumed paths , and Repeat all, or Included in Path j , then filter out ; The action path list S 1 After filtering for duplicate paths, sort the remaining set elements by path length to obtain the action path list S 1 .

[0030] Step 4: Create a command priority list , according to the action path list S 1 The path order is calculated, the priority of the instruction is calculated, and the priority of the instruction is updated in the instruction priority list.

[0031] In the embodiment of the present invention, in step 4, a command priority list is established. ,in Indicates the vertex of the instruction type in graph G; express Priority; ; The priority calculation is specifically based on the assumption that the path , if exist The order in is higher than The current priority is updated Priority .

[0032] Step 5: According to the updated instruction priority, the instruction priority list is classified and sorted to obtain the execution order of the instructions.

[0033] In the embodiment of the present invention, the classification and sorting in step 5 is that the instructions with the same priority are classified into one category, and the instruction priority list is sorted according to the priority.

[0034] Step 6: Load the instruction set according to the execution order of the instructions.

[0035] In an embodiment of the present invention, step 6 includes loading the instructions according to the instruction order calculated in the instruction priority list.

[0036] In the technical solution provided by the present invention, the method includes constructing an initial directed cyclic graph according to the instruction connection relationship; determining the starting point, sequentially traversing the initial directed cyclic graph according to the path end constraint condition, finding the instruction path, and generating an instruction path set S; removing duplicate paths from the instruction path set S, and sorting them according to the path length to obtain an action path list S 1 ; Establish a command priority list, according to the action path list S 1 The path order is calculated, the priority of the instruction is calculated, and the priority of the instruction is updated in the instruction priority list; according to the updated instruction priority, the instruction priority list is classified and sorted to obtain the execution order of the instruction; according to the execution order of the instruction, the instruction set is loaded. Through this method, the optimal instruction execution order is obtained, the response speed of the machine is improved, the response time is reduced, and the correctness of the output is improved.

[0037] Each step of the embodiment of the present invention may be performed by an electronic device, which includes but is not limited to a mobile phone, a tablet computer, a portable PC, a desktop computer, etc.

[0038] An embodiment of the present invention provides a computer-readable storage medium, which includes a stored program, wherein when the program is running, the electronic device where the computer-readable storage medium is located is controlled to execute the above-mentioned embodiment of the instruction timing allocation method based on a directed cyclic graph.

[0039] Figure 2 A schematic diagram of an electronic device provided by an embodiment of the present invention, such as Figure 2 As shown, the electronic device 21 includes: a processor 211, a memory 212, and a computer program 213 stored in the memory 212 and executable on the processor 211. When the computer program 213 is executed by the processor 211, the instruction timing allocation method based on the directed cyclic graph in the embodiment is implemented. To avoid repetition, they are not described one by one here.

[0040] The electronic device 21 includes, but is not limited to, a processor 211 and a memory 212. Those skilled in the art will appreciate that Figure 2 It is only an example of the electronic device 21 and does not constitute a limitation of the electronic device 21. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the electronic device may also include input and output devices, network access devices, buses, etc.

[0041] The processor 211 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0042] The memory 212 may be an internal storage unit of the electronic device 21, such as a hard disk or memory of the electronic device 21. The memory 212 may also be an external storage device of the electronic device 21, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card (FlashCard), etc. equipped on the electronic device 21. Further, the memory 212 may also include both an internal storage unit of the electronic device 21 and an external storage device. The memory 212 is used to store computer programs and other programs and data required by network devices. The memory 212 may also be used to temporarily store data that has been output or is to be output.

[0043] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0044] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for allocating instruction timing based on a directed cyclic graph, characterized in that: The method comprises: Step 1: Construct an initial directed cyclic graph based on the instruction connection relationship; Step 2: Determine the starting point, traverse the initial directed cyclic graph in order according to the path end constraint, find the instruction path, and generate the instruction path set S; Step 3: Remove duplicate paths from the instruction path set S and sort them by path length to obtain the action path list S 1 ; Step 4: Create a command priority list , according to the action path list S 1 Calculate the priority of the instruction according to the path order, and update the priority of the instruction in the instruction priority list; Step 5: According to the updated instruction priority, the instruction priority list is classified and sorted to obtain the execution order of the instructions; Step 6: Load the instruction set according to the execution order of the instructions.

2. The method according to claim 1, characterized in that The step 1 comprises: The connected instructions, inputs, and outputs are regarded as vertices on a directed cyclic graph, and the connection relationship between them is regarded as an edge of the directed cyclic graph, forming a graph G=(V,E), where V is a non-empty finite set of vertices and E is a set of edges.

3. The method according to claim 1, characterized in that The basis for determining the starting point in step 2 is to take the vertex of the input type as the starting point until the traversal starting from the last starting point is completed, that is, the search for all feasible instruction paths is completed; The path ending constraint condition includes that if there is no subsequent vertex or the next output node is acyclic, the path ends; The sequential traversal is a depth-first search, which specifically starts from a vertex of the graph, visits vertices along a path until it is impossible to continue, then backtracks to the previous vertex and continues to explore other paths.

4. The method according to claim 1, characterized in that: The specific instruction path in step 2 is: Assume that from vertex V i Starting from the starting point, visit the vertices along the path Path until the vertex V j If you cannot continue, is an instruction path; then we get V i is all the paths of the starting point; similarly, all the paths of other starting points are obtained, and finally the instruction path set S is obtained.

5. The method according to claim 1, characterized in that In step 3, duplicate paths are removed, specifically, the assumed paths , and Repeat all, or Included in Path j , then filter out ; The action path list S 1 After filtering for duplicate paths, sort the remaining set elements by path length to obtain the action path list S 1 .

6. The method according to claim 1, characterized in that In step 4, a command priority list is established. ,in Indicates the vertex of the instruction type in graph G; express Priority; ; The priority calculation is specifically based on the assumption that the path , if exist The order in is higher than The current priority is updated Priority .

7. The method according to claim 1, characterized in that In step 5, the instructions with the same priority are classified into one category, and the instruction priority list is sorted according to the priority.

8. The method according to claim 1, characterized in that: The step 6 comprises loading the instructions according to the instruction order calculated in the instruction priority list.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute the instruction timing allocation method based on a directed cyclic graph according to any one of claims 1 to 8.

10. An electronic device, characterized in that: include: one or more processors; Memory; And one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions, which, when executed by the device, enable the device to execute the instruction timing allocation method based on a directed cyclic graph as described in any one of claims 1 to 8.

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