Low dropout linear regulator (LDO) circuit, LDO chip, LDO and electronic device

Abstract

The application discloses a low dropout linear regulator (LDO) circuit, an LDO chip, an LDO and electronic equipment, and the circuit comprises a power device, a feedback unit adapted to generate a feedback voltage according to an output voltage of the LDO circuit, a comparison unit, a first input end of the comparison unit being adapted to be connected with a reference voltage, a second input end of the comparison unit being connected with an output end of the feedback unit, an output end of the comparison unit being connected with a control end of the power device, the comparison unit being adapted to compare the feedback voltage with the reference voltage, output a comparison signal, and the comparison signal being used for controlling the turn-on or turn-off of the power device, a load capacitor and a shunt control unit, the load capacitor and the shunt control unit being arranged respectively at an output end of the LDO circuit, and the shunt control unit being adapted to perform shunt control on the current passing through the load capacitor. The circuit performs shunt control on the current passing through the load capacitor, reduces the capacitance value requirement of the load capacitor under the premise of maintaining the performance of the LDO, and reduces the area of the LDO circuit.

Description

Technical Field

[0001] This invention relates to the field of electronic equipment technology, and in particular to a low dropout linear regulator (LDO) circuit, an LDO chip, an LDO, and an electronic device. Background Technology

[0002] In related technologies, for LDO designs without external capacitors, most of the area is occupied by the load capacitor. To maintain performance similar to external capacitors, a large internal load capacitor is typically used to meet performance requirements such as power supply ripple rejection ratio and load transient response. However, the use of a large internal load capacitor also increases the LDO module area. Summary of the Invention

[0003] This invention aims to at least partially solve one of the technical problems in related technologies. Therefore, the first objective of this invention is to provide a low-dropout linear regulator (LDO) circuit that shunts the current through the load capacitor using a shunt control unit, thereby reducing the capacitance requirement of the load capacitor while maintaining LDO performance, and thus reducing the application area of ​​the LDO circuit.

[0004] The second objective of this invention is to provide an LDO chip.

[0005] The third objective of this invention is to propose an LDO.

[0006] The fourth objective of this invention is to provide an electronic device.

[0007] To achieve the above objectives, a first aspect of the present invention provides a low-dropout linear regulator (LDO) circuit comprising: a power device, a first terminal of which is adapted to be connected to a first reference power supply, and a second terminal of which is adapted to be connected to the output terminal of the LDO circuit; a feedback unit, which is connected to the second terminal of the power device and is adapted to generate a feedback voltage based on the output voltage of the LDO circuit; a comparator unit, a first input terminal of which is adapted to be connected to the reference voltage, a second input terminal of which is connected to the output terminal of the feedback unit, and an output terminal of which is connected to the control terminal of the power device, adapted to compare the feedback voltage with the reference voltage and output a comparison signal, wherein the comparison signal is used to control the power device to turn on or off; a load capacitor and a shunt control unit, which are respectively provided corresponding to the output terminal of the LDO circuit, and the shunt control unit is adapted to shunt control the current passing through the load capacitor.

[0008] According to an embodiment of the present invention, a low-dropout linear regulator (LDO) circuit has a first terminal of a power device adapted to be connected to a first reference power supply, a second terminal of the power device adapted to be connected to the output terminal of the LDO circuit, a feedback unit connected to the second terminal of the power device, and the feedback unit generating a feedback voltage based on the output voltage of the LDO circuit. A first input terminal of a comparator unit adapted to be connected to the reference voltage, a second input terminal of the comparator unit connected to the output terminal of the feedback unit, and an output terminal of the comparator unit connected to the control terminal of the power device. The comparator unit compares the feedback voltage with the reference voltage and outputs a comparison signal, which is used to control the power device to turn on or off. A load capacitor and a shunt control unit are respectively configured corresponding to the output terminal of the LDO circuit, and the shunt control unit performs shunt control on the current passing through the load capacitor. Thus, this circuit reduces the capacitance requirement of the load capacitor while maintaining LDO performance, thereby reducing the application area of ​​the LDO circuit.

[0009] In addition, the low-dropout linear regulator (LDO) circuit according to the above embodiments of the present invention may also have the following additional technical features:

[0010] According to one embodiment of the present invention, the shunt control unit includes: a voltage divider resistor, one end of which is connected to the output terminal of the LDO circuit, and the other end of which is connected to one end of a load capacitor, the other end of which is grounded; a VI converter adapted to convert the voltage difference across the voltage divider resistor into a shunt current; and a current mirror adapted to mirror the shunt current to remove the shunt current.

[0011] According to one embodiment of the present invention, the current mirror ratio of the current mirror is adjustable.

[0012] According to one embodiment of the present invention, the VI converter includes: a first comparator, the negative input terminal of the first comparator being connected to one end of a voltage divider resistor, and the positive input terminal of the first comparator being connected to the other end of the voltage divider resistor; a pull-up resistor, one end of which is adapted to be connected to a second reference power supply; and a first switching transistor, the control terminal of which is connected to the output terminal of the first comparator, a first terminal of which is connected to the other end of the pull-up resistor, and a second terminal of which is adapted to provide a control current to a current mirror.

[0013] According to one embodiment of the present invention, the first switching transistor is a PMOS (P-Metal-Oxide-Semiconductor) transistor.

[0014] According to one embodiment of the present invention, the current mirror includes: a second switching transistor, the first end of which is connected to the other end of a voltage divider resistor, and the second end of which is grounded; and a third switching transistor, the control terminal of which is connected to the control terminal of the second switching transistor, the first end of which is connected to both the control terminal of the third switching transistor and the second end of the first switching transistor, and the second end of which is grounded.

[0015] According to one embodiment of the present invention, the number of second switching transistors is determined based on the current mirror ratio of the current mirror.

[0016] According to one embodiment of the present invention, the second switch and the third switch are NMOS (N-Metal-Oxide-Semiconductor) transistors.

[0017] According to one embodiment of the present invention, the power device is an NMOS transistor.

[0018] According to one embodiment of the present invention, the comparison unit includes a second comparator, the positive input terminal of the second comparator is adapted to be connected to a reference voltage, the negative input terminal of the second comparator is connected to the output terminal of the feedback unit, and the output terminal of the second comparator is connected to the control terminal of the power device.

[0019] According to one embodiment of the present invention, the feedback unit includes: a first resistor, one end of which is connected to a second terminal of the power device; a second resistor, one end of which is connected to the other end of the first resistor and has a first node, the other end of which is grounded, and the first node serves as the output terminal of the feedback unit.

[0020] To achieve the above objectives, a second aspect of the present invention provides an LDO chip, including the LDO circuit described above.

[0021] According to an embodiment of the present invention, the LDO chip, based on the above-described low dropout linear regulator (LDO) circuit, reduces the LDO chip area while maintaining the LDO chip performance.

[0022] To achieve the above objectives, a third aspect of the present invention provides an LDO, including the LDO chip described above.

[0023] According to the LDO of the present invention, based on the above-described LDO chip, the LDO area is reduced and the application cost is lowered while maintaining LDO performance.

[0024] To achieve the above objectives, a fourth aspect of the present invention provides an electronic device including the LDO described above.

[0025] According to embodiments of the present invention, the electronic device based on the above-described LDO reduces the area of ​​the electronic device and lowers the device cost while maintaining the performance of the electronic device.

[0026] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0027] Figure 1 This is a connection diagram of a low-dropout linear regulator (LDO) circuit according to an embodiment of the present invention.

[0028] Figure 2 This is a schematic diagram of a capacitor multiplier according to an embodiment of the present invention;

[0029] Figure 3 This is a circuit diagram of a low-dropout linear regulator (LDO) circuit in related technologies.

[0030] Figure 4 A circuit diagram of a low-dropout linear regulator (LDO) circuit according to a specific embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram of a startup simulation according to a specific embodiment of the present invention;

[0032] Figure 6 This is a simulation diagram of the power supply ripple rejection ratio according to a specific embodiment of the present invention;

[0033] Figure 7 This is a schematic diagram of a load transient response simulation according to a specific embodiment of the present invention;

[0034] Figure 8 A block diagram of an LDO chip according to an embodiment of the present invention;

[0035] Figure 9 This is a block diagram of an LDO according to an embodiment of the present invention;

[0036] Figure 10 This is a block diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0037] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0038] The following description, with reference to the accompanying drawings, describes the low-dropout linear regulator (LDO) circuit, LDO chip, LDO, and electronic device proposed in embodiments of the present invention.

[0039] Figure 1 This is a schematic diagram of the connection of a low-dropout linear regulator (LDO) circuit according to an embodiment of the present invention.

[0040] like Figure 1 As shown, the low dropout linear regulator (LDO) circuit of the real-time example of the present invention may include: a power device Q, a feedback unit 10, a comparator unit 20, a load capacitor C, and a shunt control unit 30.

[0041] In this circuit, the first terminal of the power device Q is adapted to be connected to the first reference power supply VCC1, and the second terminal of the power device Q is adapted to be connected to the output terminal of the LDO circuit. The feedback unit 10 is connected to the second terminal of the power device Q and is adapted to generate a feedback voltage V0 based on the output voltage Vout of the LDO circuit. The first input terminal of the comparison unit 20 is adapted to be connected to the reference voltage Vref, the second input terminal of the comparison unit 20 is connected to the output terminal of the feedback unit 10, and the output terminal of the comparison unit 20 is connected to the control terminal of the power device Q. The comparison unit 20 is adapted to compare the feedback voltage V0 with the reference voltage Vref and output a comparison signal, which is used to control the power device Q to turn on or off. The load capacitor C and the shunt control unit 30 are respectively set at the output terminals of the LDO circuit, and the shunt control unit 30 is adapted to shunt control the current passing through the load capacitor C.

[0042] Specifically, the feedback unit 10 acquires the output voltage Vout of the LDO circuit and generates a feedback voltage V0, which is then sent to the comparison unit 20. The comparison unit 20 compares the feedback voltage V0 with the reference voltage Vref, and generates a corresponding comparison signal based on the comparison result to control the power device Q to turn on or off. Assuming that when the feedback voltage V0 is greater than the reference voltage Vref, the comparison signal output by the comparison unit 20 can control the power device Q to turn on. The first reference power supply VCC1 is connected to the output of the LDO circuit through the turned-on power device Q. In this case, the output voltage Vout of the LDO circuit is the first reference power supply VCC1 minus the turn-on voltage of the power device Q.

[0043] When the power device Q is turned on, the output voltage Vout of the LDO circuit charges the load capacitor C, and simultaneously, the shunt control unit 30 controls the current flowing into the load capacitor C. (Refer to...) Figure 2 As shown, a resistor R is connected in series at the upper end of the load capacitor C. Here, the sink current refers to the current received by the resistor R, and the pump current refers to the portion of the current drawn from below the resistor R. The pump current does not flow through the load capacitor C and satisfies the following formula:

[0044] Q = CV = IT

[0045] C = IT / V

[0046] Where Q is the charge of the load capacitor, T is the charging and discharging time of the load capacitor, I is the current through the load capacitor, V is the voltage difference across the load capacitor, and C is the capacitance of the load capacitor.

[0047] As can be seen from the above formula, if the current through the load capacitor C decreases, the corresponding capacitance value will also decrease. Assuming the sink current is 5x and the pump current is 4x, then if the current through the load capacitor C is only x, the capacitance value of the load capacitor C can be reduced by a factor of 5. Meanwhile, since the sink current into the resistor R remains constant, the effective capacitance value corresponding to the output of the LDO circuit also remains unchanged.

[0048] Therefore, this application is based on Figure 2 The capacitor multiplier concept shown uses a shunt control unit 30 to shunt the current flowing into the load capacitor C, thereby reducing the current flowing into the load capacitor C. This reduces the capacitance requirement of the load capacitor C while maintaining the effective capacitance value corresponding to the LDO circuit output. In other words, while ensuring the operating performance of the LDO circuit, compared to... Figure 3 This application can use a load capacitor C with a smaller capacitance value to reduce the area of ​​the LDO circuit. Furthermore, if the same capacitance value of the load capacitor C is used, this application can improve the performance of the LDO circuit, such as the power supply ripple rejection ratio and the load transient response.

[0049] It should be noted that the power device Q described above can be used according to actual conditions. For example, in one embodiment of the present invention, the power device Q is an NMOS transistor. It is understood that the power device Q can also be a PMOS transistor, and this is not a limitation.

[0050] In addition, the feedback unit 10 generates a feedback voltage V0 based on the output voltage Vout. Specifically, a voltage divider circuit can be used to divide the received output voltage Vout in real time, and the resulting divided voltage can be used as the feedback voltage V0. Alternatively, the corresponding feedback voltage V0 can be output based on the output voltage Vout after the output voltage Vout exceeds or falls below the preset voltage threshold. There are no restrictions here.

[0051] The following example uses a power device, specifically an NMOS transistor, to illustrate the low-dropout linear regulator (LDO) circuit of this application.

[0052] Combination Figure 4As shown, in one embodiment of the present invention, the feedback unit 10 includes: a first resistor R1, one end of which is connected to the second end of the power device Q; a second resistor R2, one end of which is connected to the other end of the first resistor R1 and has a first node a, the other end of which is grounded, and the first node a serves as the output terminal of the feedback unit 10.

[0053] In other words, a voltage divider circuit is formed by the first resistor R1 and the second resistor R2 to divide the output voltage Vout, and the divided voltage is output as the feedback voltage V0 to the comparator unit 20 through the first node a. The feedback voltage V0 satisfies the formula... Where R1 is the resistance value of the first resistor R2, R2 is the resistance value of the second resistor R2, and Vout is the output voltage of the LDO circuit.

[0054] In one embodiment of the present invention, the comparison unit 20 includes a second comparator A2, the positive input terminal of the second comparator A2 is adapted to be connected to the reference voltage Vref, the negative input terminal of the second comparator A2 is connected to the output terminal of the feedback unit 10, and the output terminal of the second comparator A2 is connected to the control terminal of the power device Q.

[0055] When the power device Q is an NMOS transistor, the turn-on voltage is the voltage difference between the gate g and the drain d of the NMOS transistor.

[0056] Specifically, in the comparison unit 20, the feedback voltage V0 is compared with the reference voltage Vref, then amplified in the second comparator A2, and then a comparison signal is output to control the gate g of the NMOS transistor to control the NMOS transistor to turn on or off.

[0057] In one embodiment of the present invention, the shunt control unit 30 includes: a voltage divider resistor R3, a voltage-independent current converter (VI converter) 31, and a current mirror 32. One end of the voltage divider resistor R3 is connected to the output terminal of the LDO circuit, and the other end of the voltage divider resistor R3 is connected to one end of the load capacitor C, with the other end of the load capacitor C grounded. The VI converter 31 is adapted to convert the voltage difference across the voltage divider resistor R3 into a shunt current. The current mirror 32 is adapted to mirror the shunt current to remove it.

[0058] Specifically, in combination Figure 2 As shown, when the LDO circuit starts up, the load capacitor C is charged. Because a voltage difference is generated across the voltage divider resistor R3 when current flows through it, this voltage difference is converted into a shunt current by the VI converter 31. This shunt current is then mirrored by the current mirror 32, which removes a portion of the current, thus forming... Figure 2 The pumping current shown is used to reduce the current flowing through the load capacitor C.

[0059] In one embodiment of the invention, the current mirror ratio of the current mirror 32 is adjustable. For example, the current mirror 32 can be adjusted via a register to change the magnitude of the pumped current to accommodate load capacitance values ​​of different sizes.

[0060] In one embodiment of the present invention, the VI converter 31 includes: a first comparator A1, the negative input terminal of the first comparator A1 being connected to one end of a voltage divider resistor R3, and the positive input terminal of the first comparator A1 being connected to the other end of the voltage divider resistor R3; a pull-up resistor R4, one end of which is adapted to be connected to a second reference power supply VCC2; and a first switch Q1, the control terminal of the first switch Q1 being connected to the output terminal of the first comparator A1, the first terminal of the first switch Q1 being connected to the other end of the pull-up resistor R4, and the second terminal of the first switch Q1 being adapted to provide control current to the current mirror 32. The second reference power supply VCC2 can be set at the same potential as the first reference power supply VCC1, that is, the second reference power supply VCC2 and the first reference power supply VCC1 are the same reference power supply.

[0061] In one embodiment of the present invention, the first switching transistor Q1 is a PMOS transistor.

[0062] Specifically, when the LDO circuit starts working, the output voltage Vout of the LDO circuit is used to charge the load capacitor C through the voltage divider resistor R3. The voltage difference between the two terminals of the voltage divider resistor R3 is positive, that is, the voltage at the upper end of the voltage divider resistor R3 (the end away from the load capacitor C) is greater than the voltage at the lower end of the voltage divider resistor R3 (the end connected to the load capacitor C). In other words, the voltage at the positive input terminal of the first comparator A1 is less than the voltage at the negative input terminal. At this time, the first comparator A1 generates a comparison signal based on the comparison result and controls the PMOS transistor, i.e., the first switching transistor Q1, to turn on. The second reference power supply VCC2 and the pull-up resistor R4 are connected to the current mirror 32 through the turned-on first switching transistor Q1 to provide control current to the current mirror 32.

[0063] During the process of providing control current to the current mirror 32, if the voltage difference between the two poles of the voltage divider resistor R3 is large, that is, the current flowing through it is large, then the voltage difference between the positive input terminal and the negative input terminal of the first comparator A1 is large, the output signal of the first comparator A1 becomes stronger, the conduction voltage of the PMOS transistor, i.e., the voltage drop, becomes smaller, and the output control current increases.

[0064] In one embodiment of the present invention, the current mirror 32 includes: a second switch Q2, the first end of which is connected to the other end of the voltage divider resistor R3, and the second end of which is grounded; and a third switch Q3, the control terminal of which is connected to the control terminal of the second switch Q2, the first end of which is connected to both the control terminal of the third switch Q3 and the second end of the first switch Q2, and the second end of which is grounded.

[0065] In one embodiment of the present invention, the number of second switching transistors Q2 is determined according to the current mirror ratio of the current mirror 32. That is, the current extraction ratio is controlled by adjusting the current mirror ratio, for example, 4:5, 9:10, etc., thereby adjusting the current ratio flowing into the load capacitor and thus adjusting the required capacitance value of the load capacitor. Therefore, there is no limitation on the reduction of the LDO circuit area, which can be achieved by adjusting the current mirror ratio.

[0066] In one embodiment of the present invention, the second switch Q2 and the third switch Q3 are NMOS transistors.

[0067] Specifically, the control current output by the VI converter 31 flows into the second switch Q2 and is mirrored to the third switch Q3 through a mirroring effect. The current flowing through the third switch Q3 is the mirror current of the control current and changes with the control current. The current flowing through the third switch Q3 is the pumping current, thereby realizing the shunt control of the load capacitor C.

[0068] Furthermore, simulation results for three embodiments are provided below to illustrate the circuit performance of this application. In Embodiment 1, the LDO circuit is as follows: Figure 3 As shown, the load capacitor C has a capacitance of 50pF, and the large capacitor occupies about 70% of the total circuit area; in Embodiment 2, the LDO circuit is as follows. Figure 3 As shown, the load capacitor C has a capacitance of 10pF, resulting in the smallest circuit area; in Embodiment 3, the LDO circuit is as follows... Figure 4 As shown, the load capacitor C has a capacitance of 10pF. This circuit is designed based on a capacitor multiplier. The circuit area is slightly larger than that of Embodiment 2, but much smaller than that of Embodiment 1.

[0069] The effective capacitance value of a low-dropout linear regulator (LDO) circuit affects the transient current I during LDO circuit startup. For example... Figure 5 As shown, the simulated waveforms of the starting current in Example 1 and Example 3 are close to or even overlap. Compared with the simulated waveform of the starting current in Example 2, under the premise of the same starting voltage, the starting current in Example 1 and Example 3 is about 5 times larger than the starting current in Example 2.

[0070] The effective capacitance value of a low-dropout linear regulator (LDO) circuit affects the power supply ripple rejection ratio (PSRR) at high frequencies. A simulation comparison of the PSRR of the three embodiments is shown below. Figure 6 As shown, the simulation waveforms of Embodiment 1 and Embodiment 3 are similar or even overlap. Taking the power supply ripple suppression ratio at 10MHz as an example, Embodiments 1 and 3 are about 10dB lower than Embodiment 2. In addition, the effective capacitance values ​​of Embodiments 1 and 3 are also similar.

[0071] Figure 7 This is a comparative simulation diagram of the load transient response. When the load current output by the LDO circuit changes, the output voltage of the LDO circuit will have ripple. However, the larger the effective capacitance value, the smaller the ripple will be, and the better the output voltage quality of the LDO circuit will be. Figure 7 Taking the load current varying within the range of 0-12mA as an example, the simulation waveforms of Example 1 and Example 3 are close or even overlap. The ripple simulation results show that Example 1 and Example 3 fluctuate at 20mV, while Example 2 has a ripple of around 70mV due to its small effective capacitance value.

[0072] Therefore, through Figure 5 , Figure 6 and Figure 7 The simulation results from Embodiments 1 and 3 demonstrate that the low-dropout linear regulator (LDO) circuit provided in this application can reduce the load capacitor value and save circuit area while maintaining the effective capacitance value and performance. Simulation results from Embodiments 2 and 3 show that, while maintaining the same capacitance value, the LDO circuit proposed in this application achieves better LDO circuit performance, such as lower power supply ripple rejection ratio, better load transient response, and smaller ripple.

[0073] The low dropout linear regulator (LDO) circuit proposed in this application reduces the occupied area of ​​the load capacitor C and uses the shunt control unit 30 to shunt the current flowing into the load capacitor C, thus maintaining the characteristics of the same large capacitor and preserving the three important indicators of LDO without external capacitors: load stability, power supply ripple rejection ratio, and load transient response.

[0074] In summary, according to the embodiment of the low dropout linear regulator (LDO) circuit of the present invention, the first terminal of the power device is adapted to be connected to a first reference power supply, the second terminal of the power device is adapted to be connected to the output terminal of the LDO circuit, the feedback unit is connected to the second terminal of the power device, and the feedback unit generates a feedback voltage based on the output voltage of the LDO circuit. The first input terminal of the comparator unit is adapted to be connected to the reference voltage, the second input terminal of the comparator unit is connected to the output terminal of the feedback unit, and the output terminal of the comparator unit is connected to the control terminal of the power device. The comparator unit compares the feedback voltage with the reference voltage and outputs a comparison signal, wherein the comparison signal is used to control the power device to turn on or off. The load capacitor and the shunt control unit are respectively set corresponding to the output terminal of the LDO circuit, and the shunt control unit performs shunt control on the current passing through the load capacitor. Thus, this circuit shunts the current passing through the load capacitor through the shunt control unit, reducing the capacitance requirement of the load capacitor while maintaining LDO performance, thereby reducing the application area of ​​the LDO circuit. In addition, the technical solution proposed in this application can not only reduce the capacitor area, but also achieve better LDO performance, including power supply ripple rejection ratio and load transient response, while keeping the capacitor area unchanged.

[0075] Corresponding to the above embodiments, the present invention also proposes an LDO chip.

[0076] like Figure 8 As shown, the LDO chip 100 of this embodiment includes the LDO circuit 110 described above.

[0077] According to an embodiment of the present invention, the LDO chip, based on the above-described low dropout linear regulator (LDO) circuit, reduces the LDO chip area while maintaining the LDO chip performance.

[0078] Corresponding to the above embodiments, the present invention also proposes an LDO.

[0079] like Figure 9 As shown, the LDO200 of this embodiment includes the LDO chip 100 described above.

[0080] According to the LDO of the present invention, based on the above-described LDO chip, the LDO area is reduced and the application cost is lowered while maintaining LDO performance.

[0081] Corresponding to the above embodiments, the present invention also proposes an electronic device.

[0082] like Figure 10As shown, the electronic device 300 of this embodiment includes the LDO200 described above. The electronic device 300 is an electrical device, and the LDO200 is applicable to power consumption scenarios of digital circuits and low-voltage analog circuits in electrical devices. The specific circuit layout can be determined according to actual conditions, and no restrictions are imposed here.

[0083] According to embodiments of the present invention, the electronic device based on the above-described LDO reduces the area of ​​the electronic device and lowers the device cost while maintaining the performance of the electronic device.

[0084] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0085] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0086] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0087] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A low-dropout linear regulator (LDO) circuit, characterized in that, include: A power device, wherein a first terminal of the power device is adapted to be connected to a first reference power supply, and a second terminal of the power device is adapted to be connected to the output terminal of the LDO circuit; A feedback unit, which is connected to the second terminal of the power device, is adapted to generate a feedback voltage based on the output voltage of the LDO circuit; A comparison unit, wherein a first input terminal of the comparison unit is adapted to be connected to a reference voltage, a second input terminal of the comparison unit is connected to the output terminal of the feedback unit, and the output terminal of the comparison unit is connected to the control terminal of the power device, and is adapted to compare the feedback voltage with the reference voltage and output a comparison signal, wherein the comparison signal is used to control the power device to be turned on or off; A load capacitor and a shunt control unit are provided, wherein the load capacitor and the shunt control unit are respectively provided at the output terminal of the LDO circuit, and the shunt control unit is adapted to shunt control the current passing through the load capacitor; The diversion control unit includes: A voltage divider resistor, one end of which is connected to the output terminal of the LDO circuit, and the other end of which is connected to one end of the load capacitor, and the other end of the load capacitor is grounded; A VI converter is adapted to convert the voltage difference across the voltage divider resistor into a shunt current; A current mirror, adapted to mirror the shunt current in order to remove the shunt current; The VI converter includes: A first comparator, wherein the negative input terminal of the first comparator is connected to one end of the voltage divider resistor, and the positive input terminal of the first comparator is connected to the other end of the voltage divider resistor; A pull-up resistor, one end of which is adapted to be connected to a second reference power supply; A first switching transistor, the control terminal of the first switching transistor is connected to the output terminal of the first comparator, the first terminal of the first switching transistor is connected to the other terminal of the pull-up resistor, and the second terminal of the first switching transistor is adapted to provide control current to the current mirror. The current mirror includes: The second switching transistor has its first terminal connected to the other terminal of the voltage divider resistor and its second terminal grounded. The third switch has its control terminal connected to the control terminal of the second switch, and its first terminal is connected to both the control terminal of the third switch and the second terminal of the first switch. The second terminal of the third switch is grounded.

2. The LDO circuit according to claim 1, characterized in that, The current mirror ratio of the current mirror is adjustable.

3. The LDO circuit according to claim 1, characterized in that, The first switching transistor is a PMOS transistor.

4. The LDO circuit according to claim 1, characterized in that, The number of the second switching transistors is determined according to the current mirror ratio of the current mirror.

5. The LDO circuit according to claim 1, characterized in that, The second switch and the third switch are both NMOS transistors.

6. The LDO circuit according to any one of claims 1-5, characterized in that, The power device is an NMOS transistor.

7. The LDO circuit according to claim 6, characterized in that, The comparison unit includes a second comparator, the positive input terminal of which is adapted to be connected to the reference voltage, the negative input terminal of which is connected to the output terminal of the feedback unit, and the output terminal of which is connected to the control terminal of the power device.

8. The LDO circuit according to any one of claims 1-5, characterized in that, The feedback unit includes: A first resistor, one end of which is connected to the second end of the power device; The second resistor has one end connected to the other end of the first resistor and has a first node. The other end of the second resistor is grounded, and the first node serves as the output terminal of the feedback unit.

9. An LDO chip, characterized in that, Includes the LDO circuit according to any one of claims 1-8.

10. An electronic device, characterized in that, Includes the LDO chip according to claim 9.

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