Low-dropout linear regulator and radio frequency module

Abstract

The application relates to a low-dropout linear voltage regulator and a radio frequency module. The low-dropout linear voltage regulator comprises an output transistor, a detection transistor and a protection circuit. The second signal end of the output transistor is configured as an output end of the low-dropout linear voltage regulator, and is used for providing a stabilized output voltage of the low-dropout linear voltage regulator. The detection transistor is configured to copy the current flowing through the output transistor according to a set first proportion to obtain a detection current. The protection circuit is configured to generate and output a first-level current-limiting control signal to the control end of the output transistor under the joint control of the decrease of the stabilized output voltage and the increase of the detection current, so as to realize current-limiting control of the output transistor. The application improves the accuracy and stability of current-limiting detection.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronics, in particular to a low dropout regulator and a radio frequency module. BACKGROUND

[0002] A low dropout regulator (LDO) can convert a battery voltage provided by a power supply battery into a low-noise stable and accurate voltage to meet the needs of noise-sensitive analog modules and radio frequency modules in portable devices and the like. In addition, an LDO integrated with a CMOS process occupies a small chip area, and is also commonly used to power sub-modules in a SOC system to further meet the needs of anti-crosstalk and miniaturization.

[0003] However, the power tube in the LDO is a large-power load device with limited current capacity. When the LDO works under a large load current or an output short circuit, the gate-source voltage difference of the power tube is large, and the current flowing through the power tube is large, which is prone to avalanche breakdown and device burnout.

[0004] The current LDO current limiting circuit can separately control the LDO based on the LDO output voltage or separately control the LDO based on the LDO output current, which may trigger a false triggering operation of the current limiting protection. For example, Figure 7 The actual LDO output voltage waveform diagram is shown in the figure. As shown in the figure, at 100us and 150us, the LDO output voltage Vout changes, suddenly decreases, and automatically recovers in a very short time, while the output current may not change, which is a normal load adjustment when the LDO is in different working states, so the current limiting circuit does not need to work to implement current limiting control. However, if the current LDO current limiting circuit is used, the sudden decrease of Vout will prompt the current limiting circuit to work, resulting in a false operation.

[0005] Therefore, it is crucial to improve the accuracy and stability of LDO current limiting detection. SUMMARY

[0006] Therefore, the embodiments of the present application provide a low dropout regulator and a radio frequency module to solve at least one problem in the background art.

[0007] In a first aspect, the embodiments of the present application provide a low dropout regulator, which comprises an output transistor, a detection transistor and a protection circuit.

[0008] The second signal end of the output transistor is configured as an output end of the low dropout regulator, and is used to provide a regulated output voltage of the low dropout regulator.

[0009] The detection transistor is configured to copy the current flowing through the output transistor according to a first preset ratio to obtain a detection current;

[0010] The protection circuit is configured to generate and output a first level of current-limiting control signal to the control terminal of the output transistor under the joint control of the decrease of the regulated output voltage and the increase of the detection current, so as to realize current-limiting control of the output transistor.

[0011] With reference to the first aspect, in an optional implementation,

[0012] The protection circuit comprises a voltage and current comprehensive detection circuit and a first comparator;

[0013] The voltage and current comprehensive detection circuit is configured to determine an overcurrent voltage according to the difference between the detection current and the reference current when the detection current exceeds the reference current, to increase the detection voltage output by the voltage and current comprehensive detection circuit under the joint control of the increase of the overcurrent voltage and the decrease of the regulated output voltage, so that the detection voltage exceeds a second reference voltage; and when the detection voltage is increased only under any one of the increase of the overcurrent voltage and the decrease of the regulated output voltage, the detection voltage is lower than the second reference voltage.

[0014] The first comparator is configured to output a first level of current-limiting control signal when the detection voltage exceeds the second reference voltage.

[0015] With reference to the first aspect, in an optional implementation,

[0016] The voltage and current comprehensive detection circuit comprises a current subtraction circuit and a voltage generation circuit;

[0017] The current subtraction circuit is configured to perform current subtraction operation on the detection current and the reference current to generate a difference current of the detection current and the reference current when the detection current exceeds the reference current, and to copy the difference current according to a second preset ratio to obtain an overcurrent current, and further convert the overcurrent current to obtain the overcurrent voltage.

[0018] The voltage generation circuit is configured to increase a branch resistance value in an output branch for providing a detection voltage to a preset resistance threshold value when both the overcurrent voltage exceeds a fourth reference voltage and the regulated output voltage is lower than a third reference voltage, so that a detection voltage determined according to the preset resistance threshold value exceeds a second reference voltage; and determine the detection voltage according to the increased branch resistance value to be lower than the second reference voltage when only one of the overcurrent voltage exceeding the fourth reference voltage and the regulated output voltage being lower than the third reference voltage occurs.

[0019] With reference to the first aspect, in an optional implementation,

[0020] The voltage generation circuit comprises a second comparator and a third comparator.

[0021] The second comparator is configured to output a first switch signal of a first potential value for controlling the third resistance to be connected in series in the output branch when the regulated output voltage is lower than the third reference voltage, and output a first switch signal of a second potential value for controlling the third resistance to be shielded from being connected in series when the regulated output voltage exceeds the third reference voltage.

[0022] The third comparator is configured to output a second switch signal of a first potential value for controlling the fourth resistance to be connected in series in the output branch when the overcurrent voltage exceeds the fourth reference voltage, and output a second switch signal of a second potential value for controlling the fourth resistance to be shielded from being connected in series when the overcurrent voltage is lower than the fourth reference voltage.

[0023] When both the third resistance and the fourth resistance are connected in the output branch, the detection voltage exceeds the second reference voltage; and when only one of the third resistance and the fourth resistance is connected in the output branch, the detection voltage is lower than the second reference voltage.

[0024] With reference to the first aspect, in an optional implementation,

[0025] The output transistor is a PMOS transistor, and the detection transistor is a PMOS transistor.

[0026] The current subtraction circuit comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a seventh resistance and a first current source.

[0027] The gate end of the first NMOS tube is connected with the gate end of the fourth NMOS tube and the drain end of the fourth NMOS tube respectively; the drain end of the fourth NMOS tube is configured to obtain the first stable current provided by the first current source; the drain end of the first NMOS tube is configured to obtain the detection current and is connected with the drain end of the second NMOS tube, the gate end of the second NMOS tube and the gate end of the third NMOS tube respectively; the drain end of the third NMOS tube is connected with the first end of the seventh resistance; the second end of the seventh resistance is configured to provide the overcurrent voltage.

[0028] The source end of the first NMOS tube, the source end of the second NMOS tube, the source end of the third NMOS tube and the source end of the fourth NMOS tube are connected with the circuit ground end respectively.

[0029] In combination with the first aspect, in an optional implementation manner,

[0030] The voltage generating circuit comprises a second comparator, a third comparator, a fifth NMOS tube, a sixth NMOS tube, a third resistance, a fourth resistance, a fifth resistance, a sixth resistance and a second current source;

[0031] The first input end of the second comparator is configured to obtain the third reference voltage, the second input end of the second comparator is configured to obtain the stabilized output voltage, the output end of the second comparator is connected with the gate end of the fifth NMOS tube, the source end of the fifth NMOS tube is connected with the first end of the third resistance, and the drain end of the fifth NMOS tube is connected with the second end of the third resistance;

[0032] The first input end of the third comparator is configured to obtain the overcurrent voltage, the second input end of the third comparator is configured to obtain the fourth reference voltage, the output end of the third comparator is connected with the gate end of the sixth NMOS tube, the source end of the sixth NMOS tube is connected with the first end of the fourth resistance, and the drain end of the sixth NMOS tube is connected with the second end of the fourth resistance;

[0033] The fifth resistance, the sixth resistance, the third resistance and the fourth resistance are connected in series between the output end of the second current source and the circuit ground end in sequence; the connection node between the fifth resistance and the sixth resistance is configured to provide the detection voltage;

[0034] The detection voltage determined according to the output current of the second current source and the resistance values of the sixth resistance, the third resistance and the fourth resistance is higher than the second reference voltage; the detection voltage determined according to the output current of the second current source and the resistance values of the sixth resistance and the third resistance is lower than the second reference voltage; and the detection voltage determined according to the output current of the second current source and the resistance values of the sixth resistance and the fourth resistance is lower than the second reference voltage.

[0035] In combination with the first aspect, in an optional implementation manner,

[0036] At least one of the first comparator, the second comparator and the third comparator comprises a two-stage comparator;

[0037] The two-stage comparator comprises a seventh PMOS tube, an eighth PMOS tube, a ninth NMOS tube, a tenth PMOS tube, an eleventh NMOS tube, a twelfth NMOS tube and a thirteenth NMOS tube;

[0038] A gate end of the twelfth NMOS tube is configured as a first input end of the two-stage comparator, and a gate end of the thirteenth NMOS tube is configured as a second input end of the two-stage comparator;

[0039] A drain end of the twelfth NMOS tube is connected with a drain end of the seventh PMOS tube, a gate end of the seventh PMOS tube and a gate end of the eighth PMOS tube respectively, and a drain end of the thirteenth NMOS tube is connected with a drain end of the eighth PMOS tube and a gate end of the tenth PMOS tube respectively; a source end of the twelfth NMOS tube and a source end of the thirteenth NMOS tube are connected with a drain end of the ninth NMOS tube respectively, a gate end of the ninth NMOS tube and a gate end of the eleventh NMOS tube are configured to obtain a first low-bit bias voltage, and a drain end of the eleventh NMOS tube and a drain end of the tenth PMOS tube are connected and configured as an output end of the two-stage comparator;

[0040] A source end of the seventh PMOS tube, a source end of the eighth PMOS tube and a source end of the tenth PMOS tube are connected with a first power supply end respectively, and a source end of the ninth NMOS tube and a source end of the eleventh NMOS tube are connected with a second power supply end respectively.

[0041] With reference to the first aspect, in an optional implementation manner,

[0042] The low-dropout linear regulator further comprises an error amplifier and a feedback circuit;

[0043] A first input end of the error amplifier is configured to obtain a first reference voltage, a second input end of the error amplifier is connected with an output end of the feedback circuit, and an output end of the error amplifier is connected with a control end of the output transistor;

[0044] An input end of the feedback circuit is connected with an output end of the low-dropout linear regulator.

[0045] With reference to the first aspect, in an optional implementation manner,

[0046] The error amplifier comprises a twenty-first PMOS tube, a twenty-second PMOS tube, a twenty-third NMOS tube, a twenty-fourth NMOS tube, a twenty-fifth NMOS tube, a twenty-sixth NMOS tube, a twenty-seventh NMOS tube, a twenty-eighth NMOS tube, a twenty-ninth PMOS tube, a thirtieth PMOS tube and a thirty-first PMOS tube;

[0047] a gate terminal of the twenty-first PMOS is configured as a first input terminal of the error amplifier, and a gate terminal of the twenty-second PMOS is configured as a second input terminal of the error amplifier;

[0048] a drain terminal of the twenty-first PMOS is connected with a drain terminal of the twenty-third NMOS, a gate terminal of the twenty-third NMOS and a gate terminal of the twenty-fourth NMOS respectively, a drain terminal of the twenty-second PMOS is connected with a drain terminal of the twenty-fifth NMOS, a gate terminal of the twenty-fifth NMOS and a gate terminal of the twenty-sixth NMOS respectively; a drain terminal of the twenty-fourth NMOS is connected with a source terminal of the twenty-seventh NMOS, and a drain terminal of the twenty-sixth NMOS is connected with a source terminal of the twenty-eighth NMOS; a drain terminal of the twenty-seventh NMOS is connected with a drain terminal of the twenty-ninth PMOS, a gate terminal of the twenty-ninth PMOS and a gate terminal of the thirtieth PMOS respectively, and a drain terminal of the twenty-eighth NMOS is connected with a drain terminal of the thirtieth PMOS and configured as an output terminal of the error amplifier;

[0049] a source terminal of the twenty-first PMOS and a source terminal of the twenty-second PMOS are connected with a drain terminal of the thirty-first PMOS respectively; a source terminal of the thirty-first PMOS, a source terminal of the twenty-ninth PMOS and a source terminal of the thirtieth PMOS are connected with a first power supply terminal respectively; a source terminal of the twenty-third NMOS, a source terminal of the twenty-fourth NMOS, a source terminal of the twenty-fifth NMOS and a source terminal of the twenty-sixth NMOS are connected with a second power supply terminal respectively;

[0050] a gate terminal of the twenty-seventh NMOS and a gate terminal of the twenty-eighth NMOS are configured to obtain a second high-bit bias voltage, and a gate terminal of the thirty-first PMOS is configured to obtain a first high-bit bias voltage;

[0051] and / or, the feedback circuit comprises a first resistor and a second resistor;

[0052] the second input terminal of the error amplifier is connected with a second terminal of the first resistor and a first terminal of the second resistor respectively, a first terminal of the first resistor is connected with the output terminal of the low-dropout linear regulator; and a second terminal of the second resistor is connected with a circuit ground terminal.

[0053] In a second aspect, an embodiment of the present application provides a radio frequency module, which comprises the low-dropout linear regulator according to the first aspect.

[0054] The beneficial effects brought by the technical scheme provided by the embodiments of the present application include: through detecting the transistor and the protection circuit, current limiting control can be realized based on the voltage output and the detection current, so that the increase of the LDO current output and the decrease of the LDO voltage output when the LDO overcurrent phenomenon occurs can be detected at the same time, because when the LDO overcurrent phenomenon occurs, not only the current output of the LDO will increase, but also the voltage output of the LDO will decrease, thereby improving the accuracy and stability of the current limiting detection. And when the LDO overcurrent occurs, the protection circuit outputs the first level of current limiting control signal to the control end of the output transistor, which can control the output transistor to be disconnected, so that the LDO loop is disabled, and the LDO output is 0, thereby achieving the effect of current limiting.

[0055] Some of the aspects and advantages of the embodiments of the present application will be presented in the following description, some will become apparent from the following description, or will be understood by those skilled in the art through practice of the embodiments of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0056] The drawings described herein are used to provide further understanding of the present application, and form a part of the present application, wherein the drawings are not necessarily drawn to scale, and some local features can be enlarged or reduced to show the details of the local features more clearly. The illustrative embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation on the present application. In the drawings:

[0057] Figure 1 A circuit block diagram schematic diagram of a specific example of the low dropout linear voltage regulator in the embodiments of the present application;

[0058] Figure 2 A circuit block diagram schematic diagram of a specific example of the protection circuit in the embodiments of the present application;

[0059] Figure 3 A circuit block diagram schematic diagram of a specific example of the voltage and current comprehensive detection circuit in the embodiments of the present application;

[0060] Figure 4 A circuit schematic diagram of a specific example of the current subtraction circuit in the embodiments of the present application;

[0061] Figure 5 A circuit schematic diagram of a specific example of the two-stage comparator in the embodiments of the present application;

[0062] Figure 6 A circuit schematic diagram of a specific example of the error amplifier in the embodiments of the present application;

[0063] Figure 7 A waveform schematic diagram of a specific example of the LDO output voltage. DETAILED DESCRIPTION

[0064] In order to make the technical solutions and beneficial effects of the present application more obvious and easy to understand, the following will be described in detail by listing specific embodiments. The drawings are not necessarily drawn to scale, and local features can be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meaning as the technical and scientific terms in the technical field to which the present application belongs.

[0065] The embodiments of the present application are not exhaustive, but only illustrate some embodiments, and are not specific limitations on the protection scope of the present application. In the case of no contradiction, each step in an embodiment can be implemented as an independent embodiment, and the steps can be combined arbitrarily, for example, the scheme after removing some steps in an embodiment can also be implemented as an independent embodiment, and the order of the steps in an embodiment can be exchanged arbitrarily, in addition, the optional implementation manners in an embodiment can be combined arbitrarily; in addition, the embodiments can be combined arbitrarily, for example, the steps of different embodiments or part of the steps of different embodiments can be combined arbitrarily, an embodiment can be combined with the optional implementation manners of other embodiments arbitrarily.

[0066] In the embodiments of the present application, the terms and / or descriptions of the embodiments are consistent and can be referred to each other if there is no special description and logical conflict, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0067] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and not as a limitation on the present application.

[0068] In the embodiments of the present application, unless otherwise specified, the elements expressed in singular form, such as "one", "a", "the", "above", "said", "preceding", "this" and the like, can represent "one and only one", or "one or more", "at least one" and the like. For example, in the case of using articles such as "a", "an", "the" and the like in English, the noun after the article can be understood as singular expression, or can be understood as plural expression.

[0069] In the embodiments of the present application, "a plurality of" means two or more.

[0070] In some embodiments, the terms "at least one of", "one or more", "a plurality of", "multiple" and the like can be replaced with each other.

[0071] The prefix words, such as "first", "second" and the like, in the embodiments of the present application are merely used to distinguish different description objects, and do not constitute limitation on the position, sequence, priority, value or content of the description objects. The description objects are described in the claims or embodiments in the context of the description, and should not be construed as redundant limitation because of the use of the prefix words. For example, the value of the description object is not limited by the ordinal number, and can be one or more. For example, the value of "first device" can be one or more. In addition, the objects modified by different prefix words can be the same or different. For example, the description object is "device", and "first device" and "second device" can be the same device or different devices, and the types can be the same or different.

[0072] In some embodiments, the term "connection" can mean that there is mutual transmission of electrical signals or data between the connected end and the connected end, which can be understood as "electrical connection", "communication connection" and the like. The "connection" can be a direct connection between two components, or an indirect connection established through other components, or a communication within two components, or any other possible connection form.

[0073] In some embodiments, the terms "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not lower than", "above", "exceed" and the like can be replaced with each other, and the terms "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "not more than", "lower than", "lower than or equal to", "not higher than", "below" and the like can be replaced with each other.

[0074] In some embodiments, high voltage and low voltage, or high level and low level, or high voltage and low voltage, can be relative values, not limited to absolute values.

[0075] In some embodiments, the transistor can be a single transistor; or a series and / or parallel connection of multiple transistors, and has a functional terminal corresponding to each functional terminal of the single transistor respectively, and has the same working state as the single transistor, such as the on state and the off state. For example, the single transistor can be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor, abbreviated as MOS tube), and the functional terminals can include gate terminal G, source terminal S, drain terminal D and substrate terminal B. Therefore, the series and / or parallel connection of multiple transistors has gate terminal G, source terminal S, drain terminal D and substrate terminal B corresponding to gate terminal G, source terminal S, drain terminal D and substrate terminal B of the single transistor respectively, and the working state of the MOS tube. The MOS tube can include P-type MOS tube (abbreviated as PMOS tube) and N-type MOS tube (abbreviated as NMOS tube).

[0076] In some embodiments, the LDO circuit can be referred to by different names, such as LDO, low-dropout voltage regulator, low-dropout linear voltage regulator, low-dropout voltage regulator, low-dropout linear voltage regulator, etc., and the names are not limited herein.

[0077] The embodiment of the present application provides a low-dropout linear voltage regulator, Figure 1 A circuit block diagram of a specific example of the low-dropout linear voltage regulator in the embodiment of the present application is shown. As shown in the figure, the low-dropout linear voltage regulator includes an output transistor Mp, a detection transistor Ms and a protection circuit 10;

[0078] The second signal end of the output transistor Mp is configured as an output end of the low-dropout linear voltage regulator, and is used to provide a regulated output voltage Vout of the low-dropout linear voltage regulator;

[0079] The detection transistor Ms is configured to copy the current flowing through the output transistor Mp according to a set first proportion to obtain a detection current Isense;

[0080] The protection circuit 10 is configured to generate and output a first-level current-limiting control signal V G to the control end of the output transistor Mp to achieve current-limiting control of the output transistor Mp.

[0081] In this way, the embodiment of the present application can achieve current-limiting control based on the regulated output voltage and the detection current through the detection transistor and the protection circuit, so as to simultaneously detect the increase of the LDO current output and the decrease of the LDO voltage output when the LDO overflows, because when the LDO overflows, not only the current output of the LDO will increase, but also the voltage output of the LDO will decrease, thereby improving the accuracy and stability of current-limiting detection. And when the LDO overflows, the protection circuit outputs the first-level current-limiting control signal to the control end of the output transistor, which can control the output transistor to be disconnected, so that the loop of the LDO is invalid, and the LDO output is 0, thereby achieving the effect of current limiting.

[0082] In the embodiment of the present application, the protection circuit 10 is a peripheral circuit of the LDO, so it will not cause stability problems of the LDO.

[0083] In some possible implementation manners, the current copying ratio (the first ratio) can be set according to parameters of the output transistor Mp and the detection transistor Ms, such as a width-length ratio, and the like, according to actual requirements. For example, the ratio of Mp to Ms is K:1, and a current mirror is formed by using MOS tubes, and the mismatch effect is ignored. When the current flowing through Mp is Iout, the current flowing through Ms is Isense = Iout / K at this time. K can be greater than or much greater than 1.

[0084] The output transistor Mp and the detection transistor Ms can include at least one of the following: a MOSFET, a BJT (bipolar junction transistor, simply referred to as a triode), an IGBT (insulated gate bipolar transistor), a GTO (gate turn-off thyristor), an SCR (silicon controlled rectifier), an MCT (MOS controlled thyristor), an IGCT (integrated gate-commutated thyristor), and an IEGT (electron injection enhancement gate transistor). The output transistor Mp and the detection transistor Ms can include a control end, a first signal end, and a second signal end. The working principle is that the path between the first signal end and the second signal end is turned on or turned off under the control of the control signal input at the control end, so as to connect or block the signal transmission between the first signal end and the second signal end. For example, the first signal end can be a source end, and correspondingly, the second signal end can be a drain end; or conversely, the first signal end can be a drain end, and correspondingly, the second signal end can be a source end.

[0085] For example, the output transistor Mp can be a PMOS tube. Correspondingly, the detection transistor Ms can be a PMOS tube. Alternatively, the output transistor Mp can also be an NMOS tube. Correspondingly, the detection transistor Ms can be an NMOS tube.

[0086] In the embodiment of the application, the preset overcurrent condition can be set according to actual requirements, so that when the LDO overflows, the detection voltage Vsens satisfies the preset overcurrent condition, so that the circuit 10 can output the first level of the current limiting control signal V G , and the current limiting control of the output transistor Mp is realized.

[0087] In some possible implementation manners, the preset overcurrent condition can be determined at least according to the change form of the detection voltage Vsens with the decrease of the stabilized output voltage Vout and the increase of the detection current Isense, that is, according to whether the change form is increased or decreased to determine the preset overcurrent condition.

[0088] For example, if the detection voltage Vsens is determined to increase when the output voltage Vout decreases and the detection current Isense increases (overcurrent occurs), the preset overcurrent condition can be that the detection voltage Vsens exceeds a threshold voltage (e.g., the second reference voltage Vref2). For example, through voltage comparison between the detection voltage Vsens and the second reference voltage Vref2, it can be determined that the detection voltage Vsens exceeds the second reference voltage Vref2. In this case, the first-level current-limiting control signal V G .

[0089] Conversely, if the detection voltage Vsens is determined to decrease when the output voltage Vout decreases and the detection current Isense increases (overcurrent occurs), the preset overcurrent condition can be that the detection voltage Vsens is lower than a threshold voltage. In this case, the first-level current-limiting control signal V G .

[0090] In the embodiments of the present application, the manner of performing the above voltage comparison in the protection circuit 10 can be set according to actual needs, for example, at least one of the following can be included: using one or more voltage comparators; directly implementing the comparison circuit using different logic operations (AND, OR, NOT, etc.) of the gate circuit.

[0091] The first-level current-limiting control signal V G required to turn off the output transistor Mp can be a high level or a low level, which can be set according to actual needs. For example, it can be set according to the type of the output transistor Mp (e.g., PMOS transistor or NMOS transistor).

[0092] For example, if the output transistor Mp is a PMOS transistor, it is required to pull up the gate voltage of Mp when the LDO overcurrent occurs, that is, the first-level current-limiting control signal V G can be a high level. Conversely, if the output transistor Mp is an NMOS transistor, it is required to pull down the gate voltage of Mp when the LDO overcurrent occurs, that is, the first-level current-limiting control signal V G can be a low level.

[0093] The overall architecture of the low-dropout linear voltage regulator provided in the embodiments of the present application mainly includes two parts: an LDO main structure mainly composed of an error amplifier EA and an output transistor Mp; and a current-limiting structure mainly composed of a detection transistor Ms and a protection circuit 10.

[0094] The protection circuit 10 can detect the output current and the output voltage of the LDO simultaneously. For example, when overcurrent occurs, the detection voltage Vsens determined according to the stable output voltage Vout and the detection current Isense is a relatively high potential, so the first comparator com1 can be used and the comparator com1 outputs a high-level V G , and the output V G is connected to the gate of the output transistor Mp which can be a PMOS transistor, so that the loop of the LDO is disabled and the LDO output is 0, thereby achieving the effect of current limiting.

[0095] In a normal state, the detection voltage Vsens is a relatively low potential, so the first comparator com1 can output a low-level V G , i.e. a second-level current limiting control signal, and the LDO works normally. It should be understood herein that the second level is different from the first level, and is not limited to be low level, but can also be high level in some implementations. For details, refer to the above description, which will not be repeated here.

[0096] Figure 2 A circuit block diagram of a specific example of the protection circuit in the embodiment of the application is shown. As shown in the figure, in an optional implementation, the protection circuit 10 includes a voltage and current comprehensive detection circuit 101 and a first comparator com1;

[0097] The voltage and current comprehensive detection circuit 101 is configured to, when the detection current Isense exceeds a reference current I1, determine an overcurrent voltage V A according to the difference between the detection current Isense and the reference current I1, so as to increase the detection voltage Vsens output by the voltage and current comprehensive detection circuit 101 under the joint control of the increase of the overcurrent voltage V A and the decrease of the stable output voltage Vout, so that the detection voltage Vsens exceeds a second reference voltage Vref2; and when only one of the increase of the overcurrent voltage V A and the decrease of the stable output voltage Vout occurs to increase the detection voltage Vsens, the detection voltage Vsens is lower than the second reference voltage Vref2.

[0098] The first comparator com1 is configured to output a first-level current limiting control signal V G when the detection voltage Vsens exceeds the second reference voltage Vref2.

[0099] Therefore, the application improves the accuracy of overcurrent detection by accurately determining the difference between the detection current Isense and the reference current I1 in the detection circuit 101, and determines the overcurrent voltage V A , the overcurrent voltage V A and the stable output voltage Vout together determine the level of the detection voltage Vsens, and the first comparator determines the level of the current-limiting control signal V G according to the level of the detection voltage Vsens, thereby improving the accuracy of the protection circuit.

[0100] In the application, when the overcurrent voltage V A increases to a relatively high potential and the stable output voltage Vout decreases to a relatively low potential (overcurrent occurs), the detection voltage Vsens with the relatively high potential is obtained, which can make the detection voltage Vsens exceed the second reference voltage Vref2, and the current-limiting control signal V G with the first level is output, so that the loop of the LDO is disabled, thereby limiting the current. When only one of the overcurrent voltage V A increases to a relatively high potential and the stable output voltage Vout decreases to a relatively low potential (overcurrent occurs) occurs, or none of them occurs, the detection voltage Vsens cannot exceed the second reference voltage Vref2, and the circuit works normally.

[0101] In some possible implementation manners, the detection circuit 101 can use a subtraction circuit that can implement current / voltage addition and subtraction, or can be set according to actual needs to obtain the difference between the detection current Isense and the reference current I1.

[0102] In some possible implementation manners, the detection circuit 101 can use Ohm's law to increase the detection voltage Vsens under the joint action of the overcurrent voltage V A and the stable output voltage Vout, that is, the current or resistance in the branch is increased; or the voltage comparison can be directly used to achieve the increase of the detection voltage Vsens; or the increase of the detection voltage Vsens can be set according to actual needs.

[0103] Figure 3 FIG. 1 shows a circuit block diagram of a specific example of a voltage and current comprehensive detection circuit in the application. As shown in the figure, in an optional implementation manner, the protection circuit 10 can jointly adjust the detection voltage Vsens based on the decrease of the stable output voltage Vout and the increase of the detection current Isense, and output the current-limiting control signal V Gto the control end of the output transistor Mp to achieve current limiting control of the output transistor Mp when the decrease of the regulated output voltage Vout and the increase of the detection current Isense occur simultaneously.

[0104] In an optional embodiment, the voltage and current comprehensive detection circuit 101 comprises a current subtraction circuit 1011 and a voltage generation circuit 1012.

[0105] The current subtraction circuit 1011 is configured to perform current subtraction operation on the detection current Isense and the reference current I1 to generate a difference current I2 of the detection current Isense and the reference current I1 when the detection current Isense exceeds the reference current I1, and to copy the difference current I2 according to a set second proportion to obtain an overcurrent I3, and then to convert the overcurrent I3 to obtain the overcurrent voltage V A ;

[0106] The voltage generation circuit 1012 is configured to increase the branch resistance value in the output branch for providing the detection voltage Vsens to a preset resistance threshold value when both the overcurrent voltage V A exceeds the fourth reference voltage Vref4 and the regulated output voltage Vout is lower than the third reference voltage Vref3, so that the detection voltage Vsens determined according to the preset resistance threshold value exceeds the second reference voltage Vref2; and to determine the detection voltage Vsens according to the increased branch resistance value when only any one of the overcurrent voltage V A exceeds the fourth reference voltage Vref4 and the regulated output voltage Vout is lower than the third reference voltage Vref3, so that the detection voltage Vsens determined according to the increased branch resistance value is lower than the second reference voltage Vref2.

[0107] In this way, the current subtraction operation on the detection current Isense and the reference current I1 is performed to obtain the accurate current value (difference current I2) of the detection current Isense exceeding the reference current I1 when the detection current Isense exceeds the reference current I1, to realize the direct detection of the overcurrent occurrence based on the current value, to improve the overcurrent detection accuracy and timeliness, and to improve the accuracy and safety of the protection circuit. Under the common voltage comparison of the overcurrent voltage V A and the regulated output voltage Vout, the simultaneous detection of the increase of the output current and the decrease of the output voltage when the LDO overcurrent occurs is ensured, and the detection voltage Vsens with the expected voltage value can be obtained based on the controlled increased resistance value when the overcurrent voltage V A exceeds the fourth reference voltage Vref4 and the regulated output voltage Vout is lower than the third reference voltage Vref3.A When only one of the fourth reference voltage Vref4 and the steady output voltage Vout is lower than the third reference voltage Vref3, or none of them is lower than the third reference voltage Vref3, the current circuit cannot obtain the current, thereby improving the accuracy and safety of the current circuit to the current control.

[0108] In the embodiment, the reference current I1 can be copied from the first stable current Iref1 provided by the first current source, and has stable characteristics.

[0109] The copying ratio (the second ratio) between the difference current I2 and the overcurrent I3, and the preset resistance threshold can be set according to actual needs.

[0110] In some possible implementation manners, the overcurrent voltage V A The comparison of the two groups of voltages, the fourth reference voltage Vref4 and the steady output voltage Vout lower than the third reference voltage Vref3, can be realized by using independent or integrated voltage comparators, or directly realized by using different logic operations (AND, OR, NOT, etc.) of gate circuits, or can be set according to actual needs.

[0111] In an optional embodiment, the voltage generation circuit 1012 includes a second comparator com2 and a third comparator com3.

[0112] The second comparator com2 is configured to output a first switching signal of a first potential value for controlling the third resistance R3 to be connected in series in the output branch when the steady output voltage Vout is lower than the third reference voltage Vref3, and output a first switching signal of a second potential value for shielding the third resistance R3 from being connected in series when the steady output voltage Vout is higher than the third reference voltage Vref3.

[0113] The third comparator com3 is configured to output a second switching signal of a first potential value for controlling the fourth resistance R4 to be connected in series in the output branch when the overcurrent voltage V A output a second switching signal of a second potential value for shielding the fourth resistance R4 from being connected in series when the overcurrent voltage V A is lower than the fourth reference voltage Vref4.

[0114] When the third resistance R3 and the fourth resistance R4 are connected in the output branch at the same time, the detection voltage Vsens is higher than the second reference voltage Vref2; and when only one of the third resistance R3 and the fourth resistance R4 is connected in the output branch, the detection voltage Vsens is lower than the second reference voltage Vref2.

[0115] Thus, the embodiment of the present application realizes the voltage comparison of the stable output voltage Vout and the third reference voltage Vref3, and the overcurrent voltage V A and the fourth reference voltage Vref4, respectively, without affecting each other, thereby improving the overcurrent detection accuracy. When overcurrent occurs, the third resistor R3 and the fourth resistor R4 are connected in series based on the control of the first switch signal and the second switch signal, and are connected into the output branch for providing the detection voltage Vsens, so that the branch resistance value in the output branch is increased to a preset resistance threshold, thereby realizing the current limiting effect according to the detection voltage Vsens exceeding the second reference voltage Vref2. When only one of the third resistor R3 and the fourth resistor R4 is connected in series into the output branch, or none of them is connected, the detection voltage Vsens is lower than the second reference voltage Vref2, and the circuit works normally.

[0116] In the embodiment of the present application, the first potential value and the second potential value of the first switch signal and the second switch signal are different potentials, and can be set according to actual needs. For example, the first potential value can be a low level, and the second potential value can be a high level; or vice versa.

[0117] In some possible implementation manners, the manner of controlling the third resistor R3 and the fourth resistor R4 to be connected in series into the output branch and shielding the series connection can include at least one of the following: using a switching device to control the series connection or short-circuit removal of the resistor; or using a switching device to control the conduction or disconnection of the branch where the resistor is located; or other manners set according to actual needs.

[0118] Figure 4 A circuit schematic diagram of a specific example of the current subtraction circuit in the embodiment of the present application is shown. In the embodiment of the present application, the specific circuit structure of the current subtraction circuit can be set according to actual needs, and is not limited to the structure shown. Figure 4 As shown in FIGS. 1, Figure 1 , Figure 3 and Figure 4 In an optional implementation manner, the output transistor Mp is a PMOS tube, and the detection transistor Ms is a PMOS tube.

[0119] The current subtraction circuit 1011 includes a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a seventh resistor R7, and a first current source.

[0120] The gate end of the first NMOS transistor M1 is connected with the gate end of the fourth NMOS transistor M4 and the drain end of the fourth NMOS transistor M4 respectively; the drain end of the fourth NMOS transistor M4 is configured to obtain the first stable current Iref1 provided by the first current source; the drain end of the first NMOS transistor M1 is configured to obtain the detection current Isense and is connected with the drain end of the second NMOS transistor M2, the gate end of the second NMOS transistor M2 and the gate end of the third NMOS transistor M3 respectively; the drain end of the third NMOS transistor M3 is connected with the first end of the seventh resistor R7; the second end of the seventh resistor R7 is configured to provide the overcurrent voltage V A ;

[0121] The source end of the first NMOS transistor M1, the source end of the second NMOS transistor M2, the source end of the third NMOS transistor M3 and the source end of the fourth NMOS transistor M4 are connected with the circuit ground end respectively.

[0122] In the embodiment of the present application, the first NMOS transistor M1 and the second NMOS transistor M2 can constitute a current subtractor, and the fourth NMOS transistor M4 and the first NMOS transistor M1, and the second NMOS transistor M2 and the third NMOS transistor M3 can constitute a current mirror respectively. For example, the ratio of M4 and M1 can be 1:M, and the ratio of M2 and M3 can be 1:N, wherein M and N can be greater than or much greater than 1.

[0123] Then, through the current mirror, the reference current I1=M×Iref1 is copied from the first stable current Iref1, so the current value of the reference current I1 depends on the current value of the first stable current Iref1, and has a stable characteristic; and the detection current Isense entering the current subtractor is compared with the reference current I1 in current, so that the current of the detection current Isense exceeding the reference current I1 can be accurately determined, and the overcurrent detection accuracy and timeliness are improved.

[0124] In the case of overcurrent, the detection current Isense increases, and the difference current I2=Isense-I1 (because Isense>I1 at this time) flows through M2, and is copied to M3 through the current mirror of the mirror coefficient N to obtain the overcurrent I3=N×I2. At this time, the overcurrent I3 increases, which is reflected in the increase of the overcurrent voltage V A , so that the overcurrent voltage V A exceeds the fourth reference voltage Vref4.

[0125] In an optional embodiment, as shown in Figure 3 , the voltage generating circuit 1012 includes a second comparator com2, a third comparator com3, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a second current source;

[0126] The first input end of the second comparator com2 is configured to obtain the third reference voltage Vref3, the second input end of the second comparator com2 is configured to obtain the stabilized output voltage Vout, the output end of the second comparator com2 is connected with the gate end of the fifth NMOS tube M5, the source end of the fifth NMOS tube M5 is connected with the first end of the third resistor R3, and the drain end of the fifth NMOS tube M5 is connected with the second end of the third resistor R3;

[0127] The first input end of the third comparator com3 is configured to obtain the overcurrent voltage V A The second input end of the third comparator com3 is configured to obtain the fourth reference voltage Vref4, the output end of the third comparator com3 is connected with the gate end of the sixth NMOS tube M6, the source end of the sixth NMOS tube M6 is connected with the first end of the fourth resistor R4, and the drain end of the sixth NMOS tube M6 is connected with the second end of the fourth resistor R4;

[0128] The fifth resistor R5, the sixth resistor R6, the third resistor R3 and the fourth resistor R4 are connected in series between the output end of the second current source and the circuit ground end; the connection node between the fifth resistor R5 and the sixth resistor R6 is configured to provide the detection voltage Vsens;

[0129] Wherein, the detection voltage Vsens determined according to the second current source output current IB and the resistance values of the sixth resistor R6, the third resistor R3 and the fourth resistor R4 exceeds the second reference voltage Vref2; and the detection voltage Vsens determined according to the second current source output current IB and the resistance values of the sixth resistor R6 and the third resistor R3 is lower than the second reference voltage Vref2; and the detection voltage Vsens determined according to the second current source output current IB and the resistance values of the sixth resistor R6 and the fourth resistor R4 is lower than the second reference voltage Vref2.

[0130] In the embodiment of the application, the second current source can provide a second stable current IB with stable characteristics. The source end and the drain end of the fifth NMOS tube M5 are respectively connected across the two ends of the third resistor R3, and the source end and the drain end of the sixth NMOS tube M6 are respectively connected across the two ends of the fourth resistor R4. The control of the connection and shielding of the third resistor R3 and the fourth resistor R4 is realized by using the NMOS tube, the control speed is improved, and the timeliness of the current limiting control is ensured.

[0131] In the embodiment of the application, the first reference voltage Vref1 and the second reference voltage Vref2 can be provided by a bandgap reference circuit BGR. And R5=R6=R3=R4 can be designed.

[0132] For example, in the over-current state, the LDO's regulated output voltage Vout decreases, so that Vref3>Vout, the second comparator com2 can output a low level first switch signal, so as to control M5 to be off, and the third resistor R3 is connected in series into the circuit. Moreover, the over-current voltage V A increases, so that V A ref4, the third comparator com3 can output a low level second switch signal, so as to control M6 to be off, and the fourth resistor R4 is connected in series into the circuit. At this time, the output branch for providing the detection voltage Vsens can include the third resistor R3, the fourth resistor R4 and the sixth resistor R6, and the branch resistance value in the output branch increases to R6+R3+R4. At this time, IB*(R6+R3+R4)=Vsens>Vref2, IB*(R6+R3)<Vref2 and IB*(R6+R4)<Vref2 are guaranteed, and the first comparator com1 can output a high level current-limiting control signal V G , which can pull up the gate end voltage of Mp, so that the LDO loop is disabled and the output is 0.

[0133] The third reference voltage Vref3 and the fourth reference voltage Vref4 can be provided by other voltage stabilizing modules in the system.

[0134] In the normal state, Vref3 is slightly less than the LDO's regulated output voltage Vout, Vref3 A ref4, the third comparator com3 can output a high level second switch signal, so as to control M6 to be on, and the fourth resistor R4 is short-circuited and shielded. At this time, the output branch for providing the detection voltage Vsens can include the sixth resistor R6, and the branch resistance value in the output branch is a lower value compared with the branch resistance value (R6+R3+R4) in the output branch in the over-current state. Therefore, IB*R6=Vsens<Vref2, and the first comparator com1 can output a low level current-limiting control signal V G , so that the LDO normally works.

[0135] Figure 5 A circuit schematic diagram of a specific example of the two-stage comparator in the embodiment of the present application is shown. In the embodiment of the present application, the specific circuit structure of the first comparator com1, the second comparator com2 and the third comparator com3 can be set according to actual requirements, and is not limited to the specific circuit structure shown in the figure. Figure 5The two-stage comparator is shown. As shown, in an optional embodiment, at least one of the first comparator com1, the second comparator com2 and the third comparator com3 comprises a two-stage comparator.

[0136] The two-stage comparator comprises a seventh PMOS transistor M7, an eighth PMOS transistor M8, a ninth NMOS transistor M9, a tenth PMOS transistor M10, an eleventh NMOS transistor M11, a twelfth NMOS transistor M12 and a thirteenth NMOS transistor M13.

[0137] The gate terminal of the twelfth NMOS transistor M12 is configured as a first input terminal of the two-stage comparator, and the gate terminal of the thirteenth NMOS transistor M13 is configured as a second input terminal of the two-stage comparator.

[0138] The drain terminal of the twelfth NMOS transistor M12 is connected with the drain terminal of the seventh PMOS transistor M7, the gate terminal of the seventh PMOS transistor M7 and the gate terminal of the eighth PMOS transistor M8 respectively, and the drain terminal of the thirteenth NMOS transistor M13 is connected with the drain terminal of the eighth PMOS transistor M8 and the gate terminal of the tenth PMOS transistor M10 respectively; the source terminal of the twelfth NMOS transistor M12 and the source terminal of the thirteenth NMOS transistor M13 are connected with the drain terminal of the ninth NMOS transistor M9 respectively, and the gate terminal of the ninth NMOS transistor M9 and the gate terminal of the eleventh NMOS transistor M11 are configured to obtain a first low-bit bias voltage vbn1; the drain terminal of the eleventh NMOS transistor M11 and the drain terminal of the tenth PMOS transistor M10 are connected and configured as an output terminal of the two-stage comparator.

[0139] The source terminal of the seventh PMOS transistor M7, the source terminal of the eighth PMOS transistor M8 and the source terminal of the tenth PMOS transistor M10 are connected with a first power supply terminal vdda respectively, and the source terminal of the ninth NMOS transistor M9 and the source terminal of the eleventh NMOS transistor M11 are connected with a second power supply terminal vssa respectively.

[0140] In the embodiment, the first power supply terminal vdda can be used to provide a power supply signal, and the second power supply terminal vssa can be used to provide a ground signal (such as 0V).

[0141] The first input terminal V- of the two-stage comparator can be a negative input terminal, and the second input terminal V+ of the two-stage comparator can be a positive input terminal. M12 and M13 can be input pair transistors of the two-stage comparator. Through the two-stage comparator, the response speed can be improved, the timeliness of current limiting control can be ensured, and the safety of the LDO can be improved.

[0142] In an optional embodiment, as shown in Figure 1 The low-dropout linear voltage regulator further comprises an error amplifier EA and a feedback circuit.

[0143] The first input end of the error amplifier EA is configured to obtain a first reference voltage Vref1, the second input end of the error amplifier EA is connected with the output end of the feedback circuit, and the output end of the error amplifier EA is connected with the control end of the output transistor Mp.

[0144] The input end of the feedback circuit is connected with the output end of the low dropout linear regulator.

[0145] In the embodiment of the application, the source end of the output transistor Mp and the source end of the detection transistor Ms can be respectively connected with a circuit power supply end vin for inputting a power supply.

[0146] Figure 6 A circuit schematic diagram of a specific example of the error amplifier in the embodiment of the application is shown. In the embodiment of the application, the specific circuit structure of the error amplifier can be set according to actual needs, and is not limited to the structure shown. Figure 6 As shown in the figure, in an optional embodiment, the error amplifier EA includes a twenty-first PMOS transistor M21, a twenty-second PMOS transistor M22, a twenty-third NMOS transistor M23, a twenty-fourth NMOS transistor M24, a twenty-fifth NMOS transistor M25, a twenty-sixth NMOS transistor M26, a twenty-seventh NMOS transistor M27, a twenty-eighth NMOS transistor M28, a twenty-ninth PMOS transistor M29, a thirtieth PMOS transistor M30 and a thirty-first PMOS transistor M31.

[0147] The gate end of the twenty-first PMOS transistor M21 is configured as the first input end of the error amplifier EA, and the gate end of the twenty-second PMOS transistor M22 is configured as the second input end of the error amplifier EA.

[0148] The drain end of the twenty-first PMOS transistor M21 is respectively connected with the drain end of the twenty-third NMOS transistor M23, the gate end of the twenty-third NMOS transistor M23 and the gate end of the twenty-fourth NMOS transistor M24, and the drain end of the twenty-second PMOS transistor M22 is respectively connected with the drain end of the twenty-fifth NMOS transistor M25, the gate end of the twenty-fifth NMOS transistor M25 and the gate end of the twenty-sixth NMOS transistor M26; the drain end of the twenty-fourth NMOS transistor M24 is connected with the source end of the twenty-seventh NMOS transistor M27, and the drain end of the twenty-sixth NMOS transistor M26 is connected with the source end of the twenty-eighth NMOS transistor M28; the drain end of the twenty-seventh NMOS transistor M27 is respectively connected with the drain end of the twenty-ninth PMOS transistor M29, the gate end of the twenty-ninth PMOS transistor M29 and the gate end of the thirtieth PMOS transistor M30, and the drain end of the twenty-eighth NMOS transistor M28 is connected with the drain end of the thirtieth PMOS transistor M30 and is configured as the output end Vea of the error amplifier;

[0149] The source end of the twenty-first PMOS transistor M21 and the source end of the twenty-second PMOS transistor M22 are respectively connected with the drain end of the thirty-first PMOS transistor M31; the source end of the thirty-first PMOS transistor M31, the source end of the twenty-ninth PMOS transistor M29 and the source end of the thirtieth PMOS transistor M30 are respectively connected with the first power supply end vdda; the source end of the twenty-third NMOS transistor M23, the source end of the twenty-fourth NMOS transistor M24, the source end of the twenty-fifth NMOS transistor M25 and the source end of the twenty-sixth NMOS transistor M26 are respectively connected with the second power supply end vssa;

[0150] The gate end of the twenty-seventh NMOS transistor M27 and the gate end of the twenty-eighth NMOS transistor M28 are respectively configured to obtain the second low-bit bias voltage vbn2, and the gate end of the thirty-first PMOS transistor M31 is configured to obtain the first high-bit bias voltage vbp1.

[0151] And / or, the feedback circuit comprises a first resistor R1 and a second resistor R2.

[0152] The second input end of the error amplifier EA is respectively connected with the second end of the first resistor R1 and the first end of the second resistor R2, and the first end of the first resistor R1 is connected with the output end of the low-dropout linear regulator; and the second end of the second resistor R2 is connected with the circuit ground end.

[0153] In the embodiment of the application, the first input end of the error amplifier EA can be a negative input end, and the second input end of the error amplifier EA can be a positive input end. M21 and M22 can be input pair transistors of the error amplifier EA, the gate end of M21 can obtain the first reference voltage Vref1, and the gate end of M22 can obtain the feedback signal vfb, which can be connected to the connection node between the first resistor R1 and the second resistor R2. The gate end of the output transistor Mp and the gate end of the detection transistor Ms can be respectively connected to the drain end of M28 and the drain end of M30.

[0154] In the embodiment of the application, the specific circuit structure of the feedback circuit can be set according to actual needs, and is not limited to Figure 1 the structure shown in the figure.

[0155] The first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 can each be a single resistor, or a series and / or parallel connection of multiple resistors, and can also include a passive resistance network or an active resistance network of resistors, capacitors, inductors and the like.

[0156] The first reference voltage Vref1, the second reference voltage Vref2, the third reference voltage Vref3 and the fourth reference voltage Vref4 have stable characteristics to improve the comparison accuracy.

[0157] The first low voltage bias signal vbn1, the second low voltage bias signal vbn2 and the first high voltage bias signal vbp1 can be provided by external bias circuits, which can be controlled by a logic control circuit. These are not the inventive points of the application, and the bias circuits and the logic control circuit are prior art, which will not be described in detail.

[0158] The embodiments of the present application also provide a radio frequency module, which comprises the low dropout linear regulator as described in the above embodiments, so that the safety of the module can be improved under the improved LDO current limiting control accuracy.

[0159] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations included in the claims. Various modifications and changes can also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, any combination of the technical features of the above embodiments can also be made to form additional embodiments of the present application which can not have been explicitly described. Therefore, the above embodiments only express several implementation manners of the present application and do not limit the protection scope of the patent of the present application.

Claims

1. A low dropout linear regulator, characterized by, The low-dropout linear voltage regulator comprises an output transistor, a detection transistor and a protection circuit; a second signal terminal of the output transistor is configured as an output terminal of the low-dropout linear voltage regulator, for providing a regulated output voltage of the low-dropout linear voltage regulator; the detection transistor is configured to copy a current flowing through the output transistor according to a set first proportion to obtain a detection current; the protection circuit is configured to generate and output a first-level current-limiting control signal to a control terminal of the output transistor under the joint control of a decrease of the regulated output voltage and an increase of the detection current, so as to realize current-limiting control of the output transistor; the protection circuit comprises a voltage-current comprehensive detection circuit and a first comparator; the voltage-current comprehensive detection circuit is configured to determine an overcurrent voltage according to a difference between the detection current and a reference current when the detection current exceeds the reference current, to increase a detection voltage output by the voltage-current comprehensive detection circuit under the joint control of an increase of the overcurrent voltage and a decrease of the regulated output voltage, so that the detection voltage exceeds a second reference voltage, and to keep the detection voltage below the second reference voltage when the increase of the overcurrent voltage and the decrease of the regulated output voltage only one of them occurs. the first comparator is configured to output the first-level current-limiting control signal when the detection voltage exceeds the second reference voltage.

2. The low-dropout linear voltage regulator of claim 1, wherein the voltage-current comprehensive detection circuit comprises a current subtraction circuit and a voltage generation circuit; the current subtraction circuit is configured to perform a current subtraction operation on the detection current and the reference current to generate a difference current of the detection current and the reference current when the detection current exceeds the reference current, and to copy the difference current according to a set second proportion to obtain an overcurrent current, and then convert the overcurrent current to obtain the overcurrent voltage; the voltage generation circuit is configured to increase a branch resistance value in an output branch for providing the detection voltage to a preset resistance threshold value when both the overcurrent voltage exceeds a fourth reference voltage and the regulated output voltage is lower than a third reference voltage, so that the detection voltage determined according to the preset resistance threshold value exceeds the second reference voltage; and configured to keep the detection voltage below the second reference voltage when only one of the overcurrent voltage exceeding the fourth reference voltage and the regulated output voltage being lower than the third reference voltage occurs.

3. The low-dropout linear voltage regulator of claim 2, wherein the voltage generation circuit comprises a second comparator and a third comparator; the second comparator is configured to output a first switching signal of a first potential value when the regulated output voltage is lower than the third reference voltage, for controlling a third resistance to be connected in series in the output branch. ​ output a first switch signal of a second potential value for controlling the series connection of the third resistor to be shielded when the regulated output voltage exceeds a third reference voltage; the third comparator is configured to output a second switch signal of a first potential value for controlling the series connection of the fourth resistor into the output branch when the overcurrent voltage exceeds a fourth reference voltage; output a second switch signal of a second potential value for controlling the series connection of the fourth resistor to be shielded when the overcurrent voltage is lower than the fourth reference voltage; wherein the detection voltage exceeds the second reference voltage when both the third resistor and the fourth resistor are connected in series in the output branch; and the detection voltage is lower than the second reference voltage when only one of the third resistor and the fourth resistor is connected in series in the output branch. 4.The low-dropout linear regulator of claim 3, wherein the output transistor is a PMOS transistor, and the detection transistor is a PMOS transistor. The current subtraction circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a seventh resistor, and a first current source. The gate terminal of the first NMOS transistor is connected to the gate terminal of the fourth NMOS transistor and the drain terminal of the fourth NMOS transistor, respectively; the drain terminal of the fourth NMOS transistor is configured to obtain a first stable current provided by the first current source; the drain terminal of the first NMOS transistor is configured to obtain the detection current and is connected to the drain terminal of the second NMOS transistor, the gate terminal of the second NMOS transistor, and the gate terminal of the third NMOS transistor, respectively; the drain terminal of the third NMOS transistor is connected to the first terminal of the seventh resistor; the second terminal of the seventh resistor is configured to provide the overcurrent voltage. The source terminal of the first NMOS transistor, the source terminal of the second NMOS transistor, the source terminal of the third NMOS transistor, and the source terminal of the fourth NMOS transistor are connected to the circuit ground terminal, respectively. 5.The low-dropout linear regulator of claim 4, wherein the voltage generation circuit includes a second comparator, a third comparator, a fifth NMOS transistor, a sixth NMOS transistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a second current source. The first input terminal of the second comparator is configured to obtain the third reference voltage, and the second input terminal of the second comparator is configured to obtain the regulated output voltage; the output terminal of the second comparator is connected to the gate terminal of the fifth NMOS transistor; the source terminal of the fifth NMOS transistor is connected to the first terminal of the third resistor; and the drain terminal of the fifth NMOS transistor is connected to the second terminal of the third resistor. The first input terminal of the third comparator is configured to obtain the overcurrent voltage, and the second input terminal of the third comparator is configured to obtain the fourth reference voltage; the output terminal of the third comparator is connected to the gate terminal of the sixth NMOS transistor; the source terminal of the sixth NMOS transistor is connected to the first terminal of the fourth resistor; and the drain terminal of the sixth NMOS transistor is connected to the second terminal of the fourth resistor. The fifth resistor, the sixth resistor, the third resistor, and the fourth resistor are connected in series between the output terminal of the second current source and the circuit ground terminal; and the connection node between the fifth resistor and the sixth resistor is configured to provide the detection voltage. ​ ​ ​ wherein the detection voltage determined according to the output current of the second current source and the resistance values of the sixth resistor, the third resistor and the fourth resistor exceeds the second reference voltage; and the detection voltage determined according to the output current of the second current source and the resistance values of the sixth resistor and the third resistor is lower than the second reference voltage; and the detection voltage determined according to the output current of the second current source and the resistance values of the sixth resistor and the fourth resistor is lower than the second reference voltage. 6.The low dropout linear regulator of claim 5, wherein at least one of the first comparator, the second comparator and the third comparator comprises a two-stage comparator; the two-stage comparator comprises a seventh PMOS transistor, an eighth PMOS transistor, a ninth NMOS transistor, a tenth PMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor and a thirteenth NMOS transistor; a gate terminal of the twelfth NMOS transistor is configured as a first input terminal of the two-stage comparator, and a gate terminal of the thirteenth NMOS transistor is configured as a second input terminal of the two-stage comparator; a drain terminal of the twelfth NMOS transistor is connected with a drain terminal of the seventh PMOS transistor, a gate terminal of the seventh PMOS transistor and a gate terminal of the eighth PMOS transistor respectively, a drain terminal of the thirteenth NMOS transistor is connected with a drain terminal of the eighth PMOS transistor and a gate terminal of the tenth PMOS transistor respectively, a source terminal of the twelfth NMOS transistor and a source terminal of the thirteenth NMOS transistor are connected with a drain terminal of the ninth NMOS transistor respectively, a gate terminal of the ninth NMOS transistor and a gate terminal of the eleventh NMOS transistor are configured to obtain a first low bias voltage, a drain terminal of the eleventh NMOS transistor and a drain terminal of the tenth PMOS transistor are connected and configured as an output terminal of the two-stage comparator; a source terminal of the seventh PMOS transistor, a source terminal of the eighth PMOS transistor and a source terminal of the tenth PMOS transistor are connected with a first power supply terminal respectively, and a source terminal of the ninth NMOS transistor and a source terminal of the eleventh NMOS transistor are connected with a second power supply terminal respectively. 7.The low dropout linear regulator of any one of claims 1-6, wherein the low dropout linear regulator further comprises an error amplifier and a feedback circuit; a first input terminal of the error amplifier is configured to obtain a first reference voltage, a second input terminal of the error amplifier is connected with an output terminal of the feedback circuit, and an output terminal of the error amplifier is connected with a control terminal of the output transistor; an input terminal of the feedback circuit is connected with an output terminal of the low dropout linear regulator. 8.The low dropout linear regulator of claim 7, wherein the error amplifier comprises a twenty-first PMOS transistor, a twenty-second PMOS transistor, a twenty-third NMOS transistor, a twenty-fourth NMOS transistor, a twenty-fifth NMOS transistor, a twenty-sixth NMOS transistor, a twenty-seventh NMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth PMOS transistor, a thirtieth PMOS transistor and a thirty-first PMOS transistor; a gate terminal of the twenty-first PMOS transistor is configured as a first input terminal of the error amplifier, and a gate terminal of the twenty-second PMOS transistor is configured as a second input terminal of the error amplifier. The drain end of the twenty-first PMOS tube is connected with the drain end of the twenty-third NMOS tube, the gate end of the twenty-third NMOS tube and the gate end of the twenty-fourth NMOS tube respectively, the drain end of the twenty-second PMOS tube is connected with the drain end of the twenty-fifth NMOS tube, the gate end of the twenty-fifth NMOS tube and the gate end of the twenty-sixth NMOS tube respectively; the drain end of the twenty-fourth NMOS tube is connected with the source end of the twenty-seventh NMOS tube, and the drain end of the twenty-sixth NMOS tube is connected with the source end of the twenty-eighth NMOS tube; the drain end of the twenty-seventh NMOS tube is connected with the drain end of the twenty-ninth PMOS tube, the gate end of the twenty-ninth PMOS tube and the gate end of the thirtieth PMOS tube respectively, and the drain end of the twenty-eighth NMOS tube is connected with the drain end of the thirtieth PMOS tube and configured as the output end of the error amplifier; The source end of the twenty-first PMOS tube and the source end of the twenty-second PMOS tube are connected with the drain end of the thirty-first PMOS tube respectively; the source end of the thirty-first PMOS tube, the source end of the twenty-ninth PMOS tube and the source end of the thirtieth PMOS tube are connected with the first power supply end respectively; the source end of the twenty-third NMOS tube, the source end of the twenty-fourth NMOS tube, the source end of the twenty-fifth NMOS tube and the source end of the twenty-sixth NMOS tube are connected with the second power supply end respectively; The gate end of the twenty-seventh NMOS tube and the gate end of the twenty-eighth NMOS tube are configured to obtain the second low-level bias voltage, and the gate end of the thirty-first PMOS tube is configured to obtain the first high-level bias voltage; And / or, the feedback circuit comprises a first resistor and a second resistor; The second input end of the error amplifier is connected with the second end of the first resistor and the first end of the second resistor respectively, the first end of the first resistor is connected with the output end of the low-dropout linear voltage regulator; and the second end of the second resistor is connected with the circuit ground end.

9. A radio frequency module, characterized by The radio frequency module comprises the low-dropout linear voltage regulator according to any one of claims 1-8.

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