Flicker-noise-free band-gap reference voltage generator circuit

Abstract

The invention relates to a flicker-noise-free band-gap reference voltage generator circuit. The bandgap voltage generator circuit is formed using only bipolar transistors. The bandgap voltage generator circuit includes an output node at which a bandgap reference voltage is generated. A transconductance amplifier circuit in the current control feedback loop has a differential input that receives a base current. The compensation current sink circuit operates to sink, from the output node, a compensation current corresponding to a base current received at a differential input of the transconductance amplifier.

Description

Technical Field

[0001] The present disclosure relates generally to a bandgap type reference voltage generator circuit, and more particularly to a bandgap reference voltage generator circuit formed using only bipolar transistors to solve flicker noise problems and including a compensation circuit configured to compensate for bipolar base current effects. Background Art

[0002] refer to Figure 1A and Figure 1B , which shows a circuit diagram for a conventional current mode bandgap reference voltage generator circuit 10. The circuit 10 includes a current mirror circuit 12 and a bandgap core circuit 14.

[0003] The current mirror circuit 12 is formed by p-channel metal oxide semiconductor field effect transistor (MOSFET) devices M1, M2 and M3. The source terminals of transistors M1, M2 and M3 are coupled (preferably connected) to the power supply node Vdd. The gate terminals of transistors M1, M2 and M3 are coupled (preferably connected) to each other and biased by the voltage Vout to generate a mirror current. The drain terminal of transistor M1 outputs a first mirror current, the drain terminal of transistor M2 outputs a second mirror current, and the drain terminal of transistor M3 outputs a third mirror current. The third mirror current output from the drain terminal of transistor M3 is applied across resistor R3 to generate a bandgap reference voltage Vbg at the output node of circuit 10. Resistor R3 has a first terminal coupled (preferably connected) to the drain of transistor M3 at the output node, and a second terminal coupled (preferably connected) to the ground node Gnd.

[0004] The bandgap core circuit 14 includes a differential amplifier circuit 16, such as an operational amplifier (OP-AMP), configured in a current control feedback loop that generates a bias voltage Vout that controls the mirror current generated by transistors M1, M2, and M3. The non-inverting (+) input terminal of the differential amplifier circuit 16 receives the voltage V+ at the drain of transistor M1, while the inverting (-) input terminal of the differential amplifier circuit 16 receives the voltage V- at the drain of transistor M2. The bandgap core circuit 14 also includes PNP bipolar transistors Q1 and Q2. The collector terminals of the transistors Q1 and Q2 are coupled (preferably connected) to the ground node Gnd. The base terminals of the transistors Q1 and Q2 are coupled (preferably connected) to each other and to the ground node Gnd. Therefore, the transistors Q1 and Q2 of the bandgap core circuit 14 are each connected in a diode configuration. The emitter terminal of the transistor Q1 is coupled (preferably connected) to the intermediate node 18. The emitter terminal of transistor Q2 is coupled (preferably connected) to the drain of transistor M2 at the inverting (-) input of the differential amplifier circuit 16. Resistor R1 has a first terminal coupled (preferably connected) to the intermediate node 18, and a second terminal coupled (preferably connected) to the drain of transistor M1 at the non-inverting (+) input of the differential amplifier circuit 16. The first resistor R2 has a first terminal coupled (preferably connected) to the drain of transistor M1 at the non-inverting (+) input of the differential amplifier circuit 16, and a second terminal coupled (preferably connected) to the ground node Gnd. The second resistor R2 has a first terminal coupled (preferably connected) to the emitter of transistor Q2 at the inverting (-) input of the differential amplifier circuit 16, and a second terminal coupled (preferably connected) to the node Gnd.

[0005] As an example, the differential amplifier circuit 16 includes a differential pair 20 of input transistors M5, M6, which are coupled to a current mirror load circuit 22 formed by transistors M7, M8. The input transistors M5, M6 are n-channel MOSFETs. The load transistors M7, M8 are p-channel MOSFETs. The common source terminal of the transistors M5 and M6 is coupled (preferably connected) to a tail current source 20, which is connected to a ground node Gnd. The gate terminal of the input transistor M5 (at the non-inverting (+) input) receives the voltage V+ at the drain of the transistor M1, and the gate terminal of the input transistor M6 (at the inverting (-) input) receives the voltage V- at the drain of the transistor M2. The drain terminal of the input transistor M5 is coupled (preferably connected) to the drain and gate terminals of the load transistor M7. The drain terminal of the input transistor M6 is coupled (preferably connected) to the drain terminal of the load transistor M8 at the output of the amplifier. The gate terminals of the transistors M7, M8 are coupled (preferably connected) to each other. Transistor M7 is connected in a diode configuration. The output voltage Vout of the differential amplifier circuit 16 is generated at the common drain terminal of transistors M6, M8 and is a function of the difference between the voltages V+ and V-, and the magnitudes of the first, second and third mirror currents at the drains of transistors M1, M2 and M3 are functions of the voltage Vout.

[0006] The operating principle of circuit 10 is to generate a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) voltage and then add these voltages in a scaled ratio to achieve cancellation of positive and negative temperature coefficients.

[0007] The generation of the PTAT component uses the base-to-emitter voltage (V) between two forward bias voltages with different current densities (m) using transistors Q1 and Q2. BE ). Therefore, the voltage across resistor R1 is actually PTAT:

[0008]

[0009] The current flowing through resistor R2 is CTAT:

[0010]

[0011] The output bandgap voltage Vbg can be expressed as follows:

[0012]

[0013] Thus, the operating point of circuit 10 can be scaled by setting the resistance of resistors R2 and R3 , and the temperature coefficient can be adjusted by setting the resistance of resistors R1 and R2 .

[0014] There is a well-known problem with circuit 10. MOSFETs M5, M6, M7, and M8 introduce flicker (1 / f) noise that can interfere with the output voltage Vbg. This is a problem when the output voltage Vbg provides a reference voltage for noise-sensitive circuits such as an analog-to-digital converter (ADC).

[0015] To address the flicker noise problem, there are teachings in the art to use chopper technology. See, for example, U.S. Patent Application Publication No. 2010 / 0295529 and U.S. Patent No. 10,983,547 (both incorporated herein by reference). However, there are many disadvantages associated with the use of chopper technology, including the need for more complex circuitry and a stable (e.g., external) clock source to control the switching operation. Summary of the invention

[0016] In an embodiment, a circuit includes: a bandgap voltage generator circuit formed using only bipolar transistors, wherein the bandgap voltage generator circuit includes an output node at which a bandgap reference voltage is generated and a transconductance amplifier circuit located in a current control feedback loop, the transconductance amplifier circuit having a differential input terminal for receiving a base current; and a compensation current sink circuit configured to sink a compensation current corresponding to the base current at the differential input terminal of the transconductance amplifier from the output node.

[0017] In an embodiment, a circuit includes: a current mirror circuit including a first bipolar transistor, a second bipolar transistor, and a third bipolar transistor, wherein an output voltage is generated at an output node in response to a third mirror current output by the third bipolar transistor; a bandgap core circuit including: a fourth bipolar transistor and a fifth bipolar transistor, respectively coupled to the first bipolar transistor and the second bipolar transistor and configured to use a difference in base-to-emitter voltages of the fourth bipolar transistor and the fifth bipolar transistor according to the output voltages of the first bipolar transistor and the second bipolar transistor, respectively. a first mirror current and a second mirror current to generate a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) voltage; and a transconductance amplifier circuit having differential input terminals respectively coupled to the first bipolar transistor and the second bipolar transistor to receive base currents, and output terminals coupled to apply bias currents to base terminals of the first bipolar transistor, the second bipolar transistor, and the third bipolar transistor; and a current sink circuit configured to sink a compensation current corresponding to the base current at the differential input terminals of the transconductance amplifier circuit from an output node. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0019] Figure 1A and Figure 1B A circuit diagram for a conventional current mode bandgap reference voltage generator circuit is shown; and

[0020] Figure 2A and Figure 2B A circuit diagram for a flicker noise free current mode bandgap reference voltage generator circuit is shown. DETAILED DESCRIPTION

[0021] The same features in the various figures are indicated by the same reference numerals. In particular, common structural and / or functional features between multiple embodiments may have the same reference numerals and may be deployed with the same structure, dimensions and material properties.

[0022] Unless otherwise specified, when two elements are referred to as being connected together, this means a direct connection without any intermediate elements except conductors, and when two elements are referred to as being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0023] In the following description, when referring to terms defining absolute positions (such as "front", "back", "top", "bottom", "left", "right", etc.) or terms defining relative positions (such as "above", "below", "upper", "lower", etc.) or terms defining directions (such as "horizontal", "vertical", etc.), unless otherwise specified, reference is made to the orientation of the drawing.

[0024] Reference now Figure 2A and Figure 2B , these figures show a circuit diagram of a flicker-noise-free current-mode bandgap reference voltage generator circuit 110. The circuit 110 includes a current mirror circuit 112, a bandgap core circuit 114, and a compensation current sink circuit 115.

[0025] The current mirror circuit 112 is formed by PNP bipolar transistors QA, QB and QC. The emitter terminals of transistors QA, QB and QC are coupled (preferably connected) to the power supply node Vdd. The base terminals of transistors QA, QB and QC are coupled (preferably connected) to each other and biased by a bias current Ibias to generate a mirror current. The collector terminal of transistor QA outputs a first mirror current, the collector terminal of transistor QB outputs a second mirror current, and the collector terminal of transistor QC outputs a third mirror current. The third mirror current output from the collector terminal of transistor QC is applied across resistor R3 to generate a bandgap reference voltage Vbg at an output node 134 of circuit 110. Resistor R3 has a first terminal coupled (preferably connected) to the collector of transistor QC at the output node 134 and a second terminal coupled (preferably connected) to the ground node Gnd.

[0026] The bandgap core circuit 114 includes a differential operational transconductance amplifier (OTA) circuit 116 configured in a current control feedback loop, which generates an output current Iout, which controls transistors QA, QB and QC to generate a mirror current. The non-inverting (+) input terminal of the differential OTA circuit 116 receives the voltage V+ at the collector of transistor QA, and the inverting (-) input terminal of the differential OTA circuit 116 receives the voltage V- at the collector of transistor QB. The bandgap core circuit 114 also includes PNP bipolar transistors Q1 and Q2. The collector terminals of transistors Q1 and Q2 are coupled (preferably connected) to a virtual ground node 150. The base terminals of transistors Q1 and Q2 are coupled (preferably connected) to each other and the virtual ground node 150. Therefore, the transistors Q1 and Q2 of the bandgap core circuit 114 are each connected in a diode configuration. The emitter terminal of transistor Q1 is coupled (preferably connected) to an intermediate node 118. The emitter terminal of transistor Q2 is coupled (preferably connected) to the collector of transistor QB at the inverting (-) input of the differential OTA circuit 116. Resistor R1 has a first terminal coupled (preferably connected) to the intermediate node 118 and a second terminal coupled (preferably connected) to the collector of transistor QA at the non-inverting (+) input of the differential OTA circuit 116. The first resistor R2 has a first terminal coupled (preferably connected) to the collector of transistor QA at the non-inverting (+) input of the differential OTA circuit 116 and a second terminal coupled (preferably connected) to the virtual ground node 150. The second resistor R2 has a first terminal coupled (preferably connected) to the emitter of transistor Q2 at the inverting (-) input of the differential OTA circuit 116 and a second terminal coupled (preferably connected) to the virtual ground node 150.

[0027] The resistor Rshift has a first terminal coupled (preferably connected) to the virtual ground node 150 and a second terminal coupled (preferably connected) to the circuit ground node Gnd. Note that in an alternative embodiment, the resistor Rshift may be omitted, and the virtual ground node 150 and the ground node Gnd will be the same node. This alternative embodiment Figure 2A Indicated by the dotted double arrow connection 152.

[0028] The differential OTA circuit 116 includes a differential pair 120 of input transistors Q5, Q6, which are coupled to a current mirror load circuit 122 formed by transistors Q7, Q8. The input transistors Q5, Q6 are NPN bipolar transistors. The load transistors Q7, Q8 are PNP bipolar transistors. The common emitter terminal of transistors Q5 and Q6 is coupled (preferably connected) to a tail current source 124, which is connected to a ground node Gnd. The base terminal of the input transistor Q5 (at the non-inverting (+) input terminal) receives the voltage V+ (and base current Ib) at the collector of transistor QA, and the base terminal of the input transistor Q6 (at the inverting (-) input terminal) receives the voltage V- (and base current Ib) at the collector of transistor QB. The collector terminal of the input transistor Q5 is coupled (preferably connected) to the collector and base terminals of the load transistor Q7. The collector terminal of input transistor Q6 is coupled (preferably connected) to the collector terminal of load transistor Q8 at the output of the amplifier. The base terminals of transistors Q7, Q8 are coupled (preferably connected) to each other. Transistor Q7 is connected in a diode configuration. The output current Iout of the differential OTA circuit 116 generated at the common collector terminal of transistors Q6 and Q8 is a function of the difference between the voltages V+ and V-. The stabilizing capacitor Cs has a first terminal coupled (preferably connected) to the common collector terminal of transistors Q6 and Q8, and a second terminal coupled (preferably connected) to the ground node Gnd.

[0029] Using an OTA amplifier 116 formed of bipolar transistor devices (with Figure 1B The difference amplifier 16 formed by the MOSFET devices in the current mirror circuit 112 helps to solve the flicker (1 / f) noise problem. Flicker noise is also solved by using bipolar transistors QA, QB and QC (with Figure 1A The main disadvantage of using bipolar transistors for the differential pair 120 of input transistors Q5, Q6 is their base current Ib. It will be noted that the mirror current flowing through each of transistors QA, QB and QC has three components: a PTAT current Iptat across R1, a CTAT current Ictat across R2, and a base current Ib flowing into the base of the transistor pair 120. The base current Ib is undesirable and must be addressed by compensation. The effect of this base current Ib is compensated at the output node 134 where the reference voltage Vbg is generated. The compensation current sink circuit 115 operates to sink a compensation current Ib' from a third current flowing through transistor QC, wherein the compensation current Ib' corresponds to the base current Ib (i.e., is equal to or substantially equal to the base current Ib within the limits of circuit tolerances).

[0030] The current sink circuit 115 uses a bipolar PNP transistor QD (matched with transistor Q7), an NPN transistor QE (matched with transistor Q5), and a current source 140 (corresponding to the tail current source 124, but with a different current magnitude) to replicate half of the differential OTA circuit 116. The emitter terminal of transistor QD is coupled (preferably connected) to the supply node Vdd. The collector and base terminals of transistor QD are coupled (preferably connected) to each other at an intermediate node 142. Transistor QD is connected in a diode configuration. The collector terminal of transistor QE is coupled (preferably connected) to the intermediate node 142. The base terminal of transistor QE is coupled (preferably connected) to the output node 134 and is biased by a compensation current Ib', which corresponds to the base current Ib at the transistor pair 120 in the amplifier 116. The emitter terminal of transistor QE is coupled (preferably connected) to the current source 140, which is connected to the ground node Gnd. Because the current sink circuit 115 replicates only half of the differential OTA circuit 116 , the current source 140 sinks a current Is having a magnitude that is half the magnitude of the current 2Is sunk by the current source 124 .

[0031] Since amplifier 116 is of the OTA type, it cannot effectively drive a resistive load (i.e., it cannot sink a current of 3Ib from the connected bases of transistors QA, QB, and QC with current Iout) without introducing a significant offset to the amplifier input. To address this problem, bandgap core circuit 114 also includes current buffer circuit 130. Output current Iout is buffered by current buffer circuit 130 to generate bias current Ibias. The magnitude of the first, second, and third mirror currents at the collectors of transistors QA, QB, and QC is a function of bias current Ibias.

[0032] The current buffer circuit 130 includes a first follower circuit formed by a first transistor T1 having a control terminal coupled (preferably connected) to receive the amplifier output current Iout, a reference terminal coupled (preferably connected) to a ground node Gnd, and a follower terminal coupled (preferably connected) to receive a first source current Isrc generated by a first current source 150 coupled to a power supply node Vdd. The current buffer circuit 130 also includes a second follower circuit formed by a second transistor T2 having a control terminal coupled (preferably connected) to the follower terminal of the transistor T1, a reference terminal coupled (preferably connected) to the power supply node Vdd, and a follower terminal coupled (preferably connected) to receive a sink current Isnk generated by a second current source 152 coupled to the ground node Gnd. A bias current Ibias is generated at the follower terminal of the transistor T2.

[0033] exist Figure 2BIn the preferred embodiment shown in , the current buffer circuit 130 is implemented as a source follower circuit, wherein the first transistor T1 is a p-channel MOSFET device and the second transistor T2 is an n-channel MOSFET device. The drain of transistor T1 is connected to ground and the source of transistor T1 is connected to the first current source 150 and to the gate of transistor T2. The drain of transistor T2 is connected to the supply node Vdd and the source of transistor T2 is connected to the second current source 152 and provides the current Ibias. The embodiment shown using MOSFET devices for transistors T1, T2 is preferred because there is no current consumption at the gate terminal. It will be noted that any flicker noise introduced by using MOSFET devices for transistors T1, T2 is considered to be insignificant and can be ignored as a contribution to the overall noise in the output voltage Vbg.

[0034] The use of the first and second follower circuits in the current buffer circuit 130 allows approximately the same voltage to be maintained at the collector terminals of the transistors Q7 , Q8 to ensure linear operation of the transistor Q8 in generating the current Iout, thereby avoiding any early differential effect.

[0035] In an embodiment using resistor Rshift, the resistance of resistor Rshift is selected based on the mirrored first and second currents (in transistors QA and QB) and the base current Ib so that the voltage drop across the resistor is equal to or substantially equal to (within the designed tolerance) the voltage drop across the current source 124 in the amplifier 116.

[0036] Although the present invention has been illustrated and described in detail in the drawings and the above description, such illustration and description should be considered illustrative or exemplary rather than restrictive; the present invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention by studying the drawings, the disclosure, and the appended claims.

Claims

1. A circuit comprising: a bandgap voltage generator circuit formed using only bipolar transistors, wherein the bandgap voltage generator circuit includes an output node at which a bandgap reference voltage is generated and a transconductance amplifier circuit located in a current control feedback loop, the transconductance amplifier circuit having a differential input terminal receiving a base current; and The compensation current sink circuit is configured to sink a compensation current corresponding to a base current at a differential input terminal of the transconductance amplifier from an output node.

2. The circuit according to claim 1: wherein the transconductance amplifier circuit includes a first bipolar transistor in a diode-connected configuration, the first bipolar transistor being coupled to a second bipolar transistor having a base terminal receiving a base current; and The compensation current sink circuit includes a third bipolar transistor in a diode-connected configuration, the third bipolar transistor being coupled to a fourth bipolar transistor whose base terminal receives the compensation current.

3. The circuit of claim 2, wherein the first bipolar transistor and the third bipolar transistor are matched transistors.

4. The circuit of claim 2, wherein the second bipolar transistor and the fourth bipolar transistor are matched transistors.

5. The circuit according to claim 2: wherein the transconductance amplifier circuit further comprises a tail current source coupled to the second bipolar transistor; and wherein the current sink circuit further comprises an additional current source coupled to the fourth bipolar transistor; The current magnitude of the tail current source is twice the current magnitude of the additional current source.

6. The circuit of claim 5, further comprising: wherein the bandgap voltage generator circuit is coupled to a virtual ground; a shift resistor coupled between the virtual ground and the circuit ground; as well as Wherein the voltage drop across the shift resistor is equal to or substantially equal to the voltage drop across the tail current source.

7. The circuit of claim 1, further comprising a current buffer circuit configured to buffer an output current of the transconductance amplifier circuit to generate a bias current for a current control feedback loop.

8. The circuit of claim 7, wherein the current buffer circuit comprises: a first follower circuit having an input terminal coupled to receive an output current of the transconductance amplifier circuit; as well as The second follower circuit has an input coupled to receive the output of the first follower circuit and an output configured to generate a bias current.

9. A circuit as described in claim 8, wherein the first follower circuit includes a first follower transistor, which is coupled to a first current source at the output end of the first follower circuit, wherein the control terminal of the first follower transistor is configured to receive the output current of the transconductance amplifier circuit, and wherein the second follower circuit includes a second follower transistor, which is coupled to a second current source at the output end of the second follower circuit, wherein the control terminal of the second follower transistor is coupled to the output end of the first follower circuit.

10. The circuit of claim 9, wherein the first current source is configured to provide current to the first follower transistor, and wherein the second current source is configured to sink current from the second follower transistor.

11. A circuit comprising: a current mirror circuit including a first bipolar transistor, a second bipolar transistor, and a third bipolar transistor, wherein an output voltage is generated at an output node in response to a third mirror current output by the third bipolar transistor; Bandgap core circuit, including: a fourth bipolar transistor and a fifth bipolar transistor, respectively coupled to the first bipolar transistor and the second bipolar transistor and configured to use a difference in base-to-emitter voltages of the fourth bipolar transistor and the fifth bipolar transistor to generate a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) voltage from first and second mirror currents output by the first and second bipolar transistors, respectively; and a transconductance amplifier circuit having differential input terminals respectively coupled to the first bipolar transistor and the second bipolar transistor to receive base currents, and output terminals coupled to apply bias currents to base terminals of the first bipolar transistor, the second bipolar transistor, and the third bipolar transistor; and The current sink circuit is configured to sink a compensation current corresponding to a base current at a differential input terminal of the transconductance amplifier circuit from an output node.

12. The circuit according to claim 11: wherein the transconductance amplification circuit includes a sixth bipolar transistor in a diode-connected configuration, the sixth bipolar transistor being coupled to a seventh bipolar transistor having a base terminal receiving a base current; and The current sink circuit includes an eighth bipolar transistor in a diode-connected configuration, the eighth bipolar transistor being coupled to a ninth bipolar transistor having a base terminal receiving the compensation current.

13. The circuit of claim 12, wherein the sixth bipolar transistor and the eighth bipolar transistor are matched transistors.

14. The circuit of claim 12, wherein the seventh bipolar transistor and the ninth bipolar transistor are matched transistors.

15. The circuit of claim 12: The transconductance amplifier circuit further comprises a tail current source coupled to the seventh bipolar transistor; and wherein the current sink circuit further comprises an additional current source coupled to the ninth bipolar transistor; The current magnitude of the tail current source is twice the current magnitude of the additional current source.

16. The voltage generator circuit of claim 15, further comprising: wherein the fourth bipolar transistor and the fifth bipolar transistor are coupled to a virtual ground; a shift resistor coupled between the virtual ground and the circuit ground; as well as Wherein the voltage drop across the shift resistor is equal to or substantially equal to the voltage drop across the tail current source.

17. The voltage generator circuit of claim 11, wherein the transconductance amplification circuit comprises a transconductance amplifier and a current buffer, wherein the current buffer is configured to buffer an output current of the transconductance amplifier to generate a bias current applied to base terminals of the first bipolar transistor, the second bipolar transistor, and the third bipolar transistor.

18. The circuit of claim 17, wherein the current buffer comprises: a first follower circuit having an input terminal coupled to receive an output current of the transconductance amplifier; as well as The second follower circuit has an input coupled to receive the output of the first follower circuit and an output configured to generate a bias current.

19. A circuit as claimed in claim 18, wherein the first follower circuit includes a first follower transistor, which is coupled to a first current source at the output end of the first follower circuit, wherein the control terminal of the first follower transistor is configured to receive the output current of the transconductance amplifier, and wherein the second follower circuit includes a second follower transistor, which is coupled to a second current source at the output end of the second follower circuit, wherein the control terminal of the second follower transistor is coupled to the output end of the first follower circuit.

20. The voltage generator circuit of claim 19, wherein the first current source is configured to provide current to the first follower transistor, and wherein the second current source is configured to sink current from the second follower transistor.

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