Trimming high-order compensation band-gap reference circuit

Abstract

The high-order compensation band-gap reference circuit capable of being trimmed comprises PNP type triodes Q0-Q2, PMOS (P-channel Metal Oxide Semiconductor) transistors M1-M3, an NMOS (N-channel Metal Oxide Semiconductor) transistor M4, resistors R0-R3, a resistor RT (1) capable of being trimmed, a four-input operational amplifier A1 and a two-input operational amplifier A2, according to the reference voltage generated by the circuit provided by the invention, high-order compensation is completed by utilizing the four-input operational amplifier A1 on the basis of traditional first-order temperature compensation, and meanwhile, the trimming resistor circuit is added to ensure that the band-gap reference voltage is not influenced by temperature and process changes, so that the high-precision band-gap reference voltage is obtained; the band-gap reference has the advantages of high band-gap reference precision, simple compensation algorithm and good compensation stability.

Description

Technical Field

[0001] The invention relates to the technical field of bandgap reference voltage circuits, and in particular to an adjustable high-order compensated bandgap reference circuit. Technical Background

[0002] The bandgap reference voltage source is an indispensable part of analog integrated circuit design. It is widely used in analog and mixed digital circuits. It can provide other circuit modules with a clear and stable reference voltage that is insensitive to changes in power supply voltage and temperature. Its performance directly affects the performance of the overall circuit.

[0003] So far, there are many ways to implement high-precision CMOS bandgap references. The more common approach is to perform temperature compensation on the high-order terms of VBE based on first-order temperature compensation, including second-order temperature compensation and exponential temperature compensation. Due to the operational amplifier offset and resistor ratio offset caused by process deviation, it is usually necessary to adjust to obtain better temperature characteristics.

[0004] The conventional trimming method is to adjust the absolute value of the resistor and thus the temperature coefficient by opening and closing the NMOS switch. Although this method is simple to use, it has the following problems: first, the parallel connection of the NMOS switch and the resistor will introduce additional temperature effects, which will vary greatly with the process; second, the equivalent resistance of the NMOS switch will change with the power supply voltage, resulting in a poor power supply rejection ratio of the bandgap reference voltage; in addition, the step consistency of this trimming method is poor.

[0005] The patent application with publication number [CN109324655B] provides a high-precision exponential temperature compensated bandgap reference circuit. The main principle of the invention is to introduce a temperature compensation voltage containing a current gain β into ΔVBE, generate a current related to β, reduce the influence of β on the reference, and make the reference voltage achieve better temperature characteristics. The patent uses the process parameters of transistors for exponential temperature compensation, but the high-order compensation effect depends on the current gain β of the transistor. It is necessary to determine the most reasonable area of ​​the transistor emitter region to achieve the best effect, and the area of ​​the transistor emitter region cannot be fine-tuned, so it is difficult to achieve the best compensation effect; on the other hand, the algorithm for determining the value of the resistance value in this design is relatively complex, and various fitting approximation methods need to be used to obtain the optimal compensation effect, which also increases the intensity of the design work.

[0006] In summary, in view of the above technical problems, it is necessary to provide a high-order compensation method with a simple compensation algorithm, and at the same time optimize the adjustment method to achieve a better temperature-independent bandgap reference voltage. Summary of the invention

[0007] In order to overcome the shortcomings of the prior art, the purpose of the present invention is to provide an adjustable high-order compensated bandgap reference circuit, which optimizes the adjustment method, ensures that the bandgap reference voltage is not affected by temperature conditions, and solves the problems of the existing bandgap reference having insufficient accuracy, complex compensation algorithm and insufficient stability.

[0008] In order to achieve the above object, the present invention provides the following technical solutions:

[0009] A high-order compensated bandgap reference circuit that can be adjusted includes transistors Q0-Q2, PMOS transistors M1-M3, a first NMOS transistor M4, resistors R0-R3, and an adjustable resistor R T , four-input operational amplifier A1 and two-input operational amplifier A2;

[0010] The source of the first PMOS tube M1 is connected to the power supply, the gate thereof is connected to the output end of the four-input operational amplifier A1, and the drain of the first PMOS tube M1 is connected to the adjustable resistor R T The first end connection;

[0011] Adjustable resistance R T The end of the resistor is connected to the first end of the second resistor R1 and to the first end of the third resistor R2;

[0012] The end of the second resistor R1 is connected to the first positive input terminal of the four-input operational amplifier A1, and the end of the third resistor R2 is connected to the first negative input terminal of the four-input operational amplifier A1;

[0013] The emitter of the first transistor Q0 is connected to the end of the second resistor R1 through the first resistor R0, and the base and collector of the first transistor Q0 are grounded;

[0014] The emitter of the second transistor Q1 is connected to the first non-inverting input terminal of the four-input operational amplifier A1, and is connected to the second non-inverting input terminal of the four-input operational amplifier A1, and is connected to the non-inverting input terminal of the two-input operational amplifier A2, and the base and collector of the second transistor Q1 are grounded;

[0015] The emitter of the third transistor Q2 is connected to the second inverting input terminal of the four-input operational amplifier A1 and to the drain of the second PMOS transistor M2, and the base and collector of the third transistor Q2 are grounded;

[0016] The sources of the second PMOS tube M2 and the third PMOS tube M3 are both connected to the power supply, the second PMOS tube M2 and the third PMOS tube M3 share a gate, and the gates of the second PMOS tube M2 and the third PMOS tube M3 are connected to the drain of the third PMOS tube M3;

[0017] The drain of the first NMOS tube M4 is connected to the drain of the third PMOS tube M3, the gate of the first NMOS tube M4 is connected to the output end of the two-input operational amplifier A2, and the source of the first NMOS tube M4 is connected to the first end of the fourth resistor R3;

[0018] A first end of the fourth resistor R3 is connected to the inverting input terminal of the two-input operational amplifier A2, and a terminal of the fourth resistor R3 is grounded.

[0019] The second resistor R1 and the third resistor R2 have the same resistance value.

[0020] The emitter junction area ratio of the transistors Q0-Q2 is Q0:Q1:Q2=N:1:1, where N is an integer greater than 1.

[0021] The four-input operational amplifier A1 includes MOS tubes M5-M14, a zeroing resistor Rz and a Miller compensation capacitor Cc;

[0022] The MOS tubes M5 to M14 include: a fourth PMOS tube M5, a fifth PMOS tube M6, a sixth PMOS tube M7, a seventh PMOS tube M8, an eighth PMOS tube M11, a ninth PMOS tube M12 and a tenth PMOS tube M13; a second NMOS tube M9, a third NMOS tube M10 and a fourth NMOS tube M14;

[0023] Among them, the source of the eighth PMOS tube M11, the source of the ninth PMOS tube M12 and the source of the tenth PMOS tube M13 are all connected to the power supply VDD, and the gates of the eighth PMOS tube M11, the ninth PMOS tube M12 and the tenth PMOS tube M13 are all connected to the bias voltage VB;

[0024] The drain of the eighth PMOS tube M11 is connected to the source of the fourth PMOS tube M5 and the source of the fifth PMOS tube M6, and the drain of the ninth PMOS tube M12 is connected to the source of the sixth PMOS tube M7 and the source of the seventh PMOS tube M8;

[0025] The drain of the fourth PMOS tube M5 is connected to the drain of the sixth PMOS tube M7 and the drain of the second NMOS tube M9, and the drain of the fifth PMOS tube M6 is connected to the drain of the seventh PMOS tube M8 and the drain of the third NMOS tube M10;

[0026] The source of the second NMOS tube M9 and the source of the third NMOS tube M10 are both grounded, and the gate of the second NMOS tube M9 is connected to the gate of the third NMOS tube M10 and the drain of the second NMOS tube M9;

[0027] The drain of the third NMOS transistor M10 is connected to the gate of the fourth NMOS transistor M14, and the source of the fourth NMOS transistor M14 is grounded;

[0028] The zeroing resistor Rz and the Miller compensation capacitor Cc are connected in series and bridged between the gate and the drain of the fourth NMOS transistor M14;

[0029] The drain of the fourth NMOS tube M14 is connected to the drain of the tenth PMOS tube M13.

[0030] The fourth PMOS tube M5 and the fifth PMOS tube M6 serve as a first input pair of tubes of the four-input operational amplifier A1;

[0031] The sixth PMOS tube M7 and the seventh PMOS tube M8 serve as a second input pair of tubes of the four-input operational amplifier A1;

[0032] The gate of the fourth PMOS tube M5 serves as the first in-phase input terminal IP1 of the four-input operational amplifier A1;

[0033] The gate of the fifth PMOS tube M6 serves as the first inverting input terminal IN1 of the four-input operational amplifier A1;

[0034] The gate of the sixth PMOS tube M7 serves as the second non-inverting input terminal IP2 of the four-input operational amplifier A1;

[0035] The gate of the seventh PMOS tube M8 serves as the second inverting input terminal IN2 of the four-input operational amplifier A1;

[0036] The drain of the tenth PMOS transistor M13 and the drain of the fourth NMOS transistor M14 are connected to serve as the output terminal OUT of the four-input operational amplifier A1.

[0037] The adjustable resistance R T The first adjustable resistor R is connected in series T0 , the second adjustable resistor R T1 , the third adjustable resistor R T2 and the fourth adjustable resistor R T3 , the first adjustable resistor R T0 A first metal fuse RM1 is connected in parallel, and the second adjustable resistor R T1 A second metal fuse RM2 is connected in parallel, and the third adjustable resistor R T2 A third metal fuse RM3 is connected in parallel.

[0038] The trimming resistor R T The trimming can be achieved in the following manner: by blowing the first metal fuse RM1, the second metal fuse RM2 and the third metal fuse RM3, thereby adjusting the trimmable resistor R T The resistance value is used to adjust the temperature coefficient of the reference voltage VREF.

[0039] The adjustable resistance R TThe voltage at the end is used as the reference voltage VREF, and the expression of the reference voltage VREF is:

[0040]

[0041] Wherein, VBE1 is the BE junction voltage of the second transistor Q1;

[0042] V T is the thermal voltage;

[0043] N is the emitter junction area ratio of the first transistor Q0 and the second transistor Q1;

[0044] ΔV BE，Q1Q2 is the BE junction voltage difference between the second transistor Q1 and the third transistor Q2;

[0045] gm1 is the transconductance of the first input pair of the four-input operational amplifier A1;

[0046] gm2 is the transconductance of the second input pair of the four-input operational amplifier A1.

[0047] Compared with the prior art, the beneficial effects of the present invention are:

[0048] 1) The present invention further compensates on the basis of the traditional first-order bandgap reference voltage source circuit, completes the weighted addition of voltage through a four-input operational amplifier, eliminates the residual high-order temperature term, and generates a reference voltage with a low temperature coefficient at the output end of the operational amplifier, so that the temperature coefficient of the reference voltage VREF is reduced from tens of ppm of the traditional first-order compensation to less than 1ppm;

[0049] 2) The present invention provides an optimized trimming method, which divides the trimming resistor into a certain number of segmented resistors, and uses metal fuses to be connected in parallel with the segmented resistors respectively, and controls the connection or short-circuit of the segmented resistors by controlling whether the metal fuses are blown, thereby solving the technical problems of introducing additional temperature effects, poor power supply rejection ratio, and poor trimming step consistency in the existing MOS switch trimming circuit, ensuring the consistency of the bandgap reference voltage, ensuring that the bandgap reference voltage is not affected by temperature conditions, and obtaining a higher precision reference voltage;

[0050] 3) The present invention also has the advantage of a simple compensation algorithm. The compensation method provided by the present invention is to adjust the transconductance ratio of the first input pair of tubes and the second input pair of tubes of the four-input operational amplifier. Therefore, it is only necessary to adjust the parallel number of MOS tubes and the current size of the first input pair of tubes and the second input pair of tubes in equal proportion until the high-order temperature term is completely offset, so that the compensation of the high-order temperature term can be completed. Therefore, compared with the bandgap reference circuit with exponential temperature compensation having a more complex resistance value algorithm, the present invention greatly reduces the design difficulty. In addition, since the main error of the compensation method comes from the transconductance mismatch between the first input pair of tubes and the second input pair of tubes, it also has the advantages of stable compensation effect and small error.

[0051] In summary, the present invention makes further compensation on the basis of the traditional first-order bandgap reference voltage source circuit, completes the weighted addition of voltages through a four-input operational amplifier, and generates a reference voltage with a low temperature coefficient at the output end of the operational amplifier; at the same time, the present invention provides an optimized adjustment method, which solves the technical problems of introducing additional temperature effects, poor power supply rejection ratio and poor consistency of adjustment steps in the existing adjustment circuit, ensures the consistency of the bandgap reference voltage, ensures that the bandgap reference voltage is not affected by temperature conditions, and obtains a higher-precision reference voltage; in addition, the present invention also has the advantage of a simple compensation algorithm, and only needs to adjust the transconductance ratio of the first input pair of tubes and the second input pair of tubes of the four-input operational amplifier to complete the compensation of high-order terms. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 The schematic diagram of the adjustable high-order compensation bandgap reference circuit of the present invention is shown in FIG.

[0053] Figure 2 This is an internal circuit diagram of a four-input operational amplifier in an embodiment of the present invention.

[0054] Figure 3 It is a simulation waveform diagram of the reference voltage VREF of the bandgap reference circuit of the present invention.

[0055] Figure 4 A circuit schematic diagram of an adjustable resistor in an embodiment of the present invention. DETAILED DESCRIPTION

[0056] The structural principle and working principle of the present invention are described in detail below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0057] like Figure 1As shown, a high-order compensated bandgap reference circuit that can be adjusted includes PNP transistors Q0-Q2, PMOS transistors M1-M3, NMOS transistor M4, resistors R0-R3, and an adjustable resistor R T , four-input operational amplifier A1 and two-input operational amplifier A2;

[0058] The source of the first PMOS tube M1 is connected to the power supply, the gate thereof is connected to the output end of the four-input operational amplifier A1, and the drain of the first PMOS tube M1 is connected to the adjustable resistor R T The first end connection;

[0059] Adjustable resistance R T The end of the resistor is connected to the first end of the second resistor R1 and to the first end of the third resistor R2;

[0060] The end of the second resistor R1 is connected to the first positive input terminal of the four-input operational amplifier A1, and the end of the third resistor R2 is connected to the first negative input terminal of the four-input operational amplifier A1;

[0061] The emitter of the first transistor Q0 is connected to the end of the second resistor R1 through the first resistor R0, and the base and collector of the first transistor Q0 are grounded;

[0062] The emitter of the second transistor Q1 is connected to the first non-inverting input terminal of the four-input operational amplifier A1, and is connected to the second non-inverting input terminal of the four-input operational amplifier A1, and is connected to the non-inverting input terminal of the two-input operational amplifier A2, and the base and collector of the second transistor Q1 are grounded;

[0063] The emitter of the third transistor Q2 is connected to the second inverting input terminal of the four-input operational amplifier A1 and to the drain of the second PMOS transistor M2, and the base and collector of the third transistor Q2 are grounded;

[0064] The sources of the second PMOS tube M2 and the third PMOS tube M3 are both connected to the power supply, the second PMOS tube M2 and the third PMOS tube M3 share a gate, and the gates of the second PMOS tube M2 and the third PMOS tube M3 are connected to the drain of the third PMOS tube M3;

[0065] The drain of the first NMOS tube M4 is connected to the drain of the third PMOS tube M3, the gate of the first NMOS tube M4 is connected to the output end of the two-input operational amplifier A2, and the source of the first NMOS tube M4 is connected to the first end of the fourth resistor R3;

[0066] A first end of the fourth resistor R3 is connected to the inverting input terminal of the two-input operational amplifier A2, and a terminal of the fourth resistor R3 is grounded.

[0067] Furthermore, the resistance values ​​of the resistor R1 and the resistor R2 are the same.

[0068] Preferably, the emitter junction area ratio of the transistors Q0-Q2 is Q0:Q1:Q2=N:1:1=7:1:1, where N is an integer greater than 1, preferably 5-20.

[0069] like Figure 2 As shown, the internal circuit of the four-input operational amplifier A1 in the present invention is shown:

[0070] The four-input operational amplifier A1 includes MOS tubes M5-M14, a zeroing resistor Rz and a Miller compensation capacitor Cc;

[0071] The MOS tubes M5 to M14 include: a fourth PMOS tube M5, a fifth PMOS tube M6, a sixth PMOS tube M7, a seventh PMOS tube M8, an eighth PMOS tube M11, a ninth PMOS tube M12 and a tenth PMOS tube M13; a second NMOS tube M9, a third NMOS tube M10 and a fourth NMOS tube M14;

[0072] Among them, the source of the eighth PMOS tube M11, the source of the ninth PMOS tube M12 and the source of the tenth PMOS tube M13 are all connected to the power supply VDD, and the gates of the eighth PMOS tube M11, the ninth PMOS tube M12 and the tenth PMOS tube M13 are all connected to the bias voltage VB;

[0073] The drain of the eighth PMOS tube M11 is connected to the source of the fourth PMOS tube M5 and the source of the fifth PMOS tube M6, and the drain of the ninth PMOS tube M12 is connected to the source of the sixth PMOS tube M7 and the source of the seventh PMOS tube M8;

[0074] The drain of the fourth PMOS tube M5 is connected to the drain of the sixth PMOS tube M7 and the drain of the second NMOS tube M9, and the drain of the fifth PMOS tube M6 is connected to the drain of the seventh PMOS tube M8 and the drain of the third NMOS tube M10;

[0075] The source of the second NMOS tube M9 and the source of the third NMOS tube M10 are both grounded, and the gate of the second NMOS tube M9 is connected to the gate of the third NMOS tube M10 and the drain of the second NMOS tube M9;

[0076] The drain of the third NMOS transistor M10 is connected to the gate of the fourth NMOS transistor M14, and the source of the fourth NMOS transistor M14 is grounded;

[0077] The zeroing resistor Rz and the Miller compensation capacitor Cc are connected in series and bridged between the gate and the drain of the fourth NMOS transistor M14;

[0078] The drain of the fourth NMOS tube M14 is connected to the drain of the tenth PMOS tube M13.

[0079] The fourth PMOS tube M5 and the fifth PMOS tube M6 serve as a first input pair of tubes of the four-input operational amplifier A1;

[0080] The sixth PMOS tube M7 and the seventh PMOS tube M8 serve as a second input pair of tubes of the four-input operational amplifier A1;

[0081] The gate of the fourth PMOS tube M5 serves as the first in-phase input terminal IP1 of the four-input operational amplifier A1;

[0082] The gate of the fifth PMOS tube M6 serves as the first inverting input terminal IN1 of the four-input operational amplifier A1;

[0083] The gate of the sixth PMOS tube M7 serves as the second non-inverting input terminal IP2 of the four-input operational amplifier A1;

[0084] The gate of the seventh PMOS tube M8 serves as the second inverting input terminal IN2 of the four-input operational amplifier A1;

[0085] The drain of the tenth PMOS transistor M13 and the drain of the fourth NMOS transistor M14 are connected to serve as the output terminal OUT of the four-input operational amplifier A1.

[0086] like Figure 4 As shown, further, the resistor R T The first adjustable resistor R is connected in series T0 , the second adjustable resistor R T1 , the third adjustable resistor R T2 and the fourth adjustable resistor R T3 , the first adjustable resistor R T0 A first metal fuse RM1 is connected in parallel, and the second adjustable resistor R T1 A second metal fuse RM2 is connected in parallel, and the third adjustable resistor R T2 A third metal fuse RM3 is connected in parallel.

[0087] Furthermore, the adjustable resistor R T The trimming is achieved by: the first metal fuse RM1, the second metal fuse RM2 and the third metal fuse RM3 are blown, thereby adjusting the trimmable resistor R T The resistance value is used to adjust the temperature coefficient of the reference voltage VREF.

[0088] Furthermore, the adjustable resistor R T The voltage at the end is used as the reference voltage VREF, and the expression of the reference voltage VREF is:

[0089]

[0090] Wherein, VBE1 is the BE junction voltage of the second transistor Q1;

[0091] V T is the thermal voltage;

[0092] N is the emitter junction area ratio of the first transistor Q0 and the second transistor Q1;

[0093] ΔV BE，Q1Q2 is the BE junction voltage difference between the second transistor Q1 and the third transistor Q2;

[0094] gm1 is the transconductance of the first input pair of the four-input operational amplifier A1;

[0095] gm2 is the transconductance of the second input pair of the four-input operational amplifier A1.

[0096] In the embodiment of the present invention, the derivation process of the expression of the bandgap reference voltage of the circuit of the present invention is provided:

[0097] The traditional first-order compensated bandgap reference circuit can completely cancel the first-order temperature coefficient of the bandgap reference voltage, but the higher-order terms cannot be compensated. The higher-order temperature coefficient is mainly derived from the temperature characteristics of the base-emitter voltage VBE of the transistor. The expression of VBE is:

[0098] V BE =V G0 -(V G0 -V BE0 )(T / T 0 )-(η-α)V T ln(T / T 0 )--Formula (1)

[0099] Among them, V G0 is the bandgap voltage of silicon, V BE0 is at temperature T 0 V BE , η is a constant determined by the process and is approximately equal to 4, α is a constant that depends on the temperature characteristics of the transistor collector current. If the collector current in the transistor is positively correlated with the temperature, then α=1; if the current is negatively correlated with the temperature, then α=-1; if the current is independent of the temperature, then α=0.

[0100] It can be seen that in addition to the first-order linear part, there is also a high-order term related to TlnT in formula (1).

[0101] The main principle of the high-order compensation of the present invention is to use the second transistor Q1 and the third transistor Q2 with different collector current temperature characteristics to generate a voltage difference ΔV with a high-order temperature coefficient term. BE，Q1Q2 , the voltage difference is weighted and superimposed on the reference voltage VREF through the structure of a four-input operational amplifier to offset the high-order terms related to TlnT, and finally obtain a bandgap reference with a lower temperature drift coefficient.

[0102] The specific temperature compensation method is: Due to the virtual short characteristic of the two-input operational amplifier A2, V R3 =V BE1 , after being mirrored by the current mirror, the current flowing through the collector of the third transistor Q2 is The current is negatively correlated with the temperature, and the current flowing through the collector of the second transistor Q1 is The current is positively correlated with the temperature, so a current containing C is generated between the second transistor Q1 and the third transistor Q2. 1 ×TlnT term, and this voltage difference also includes the first-order temperature coefficient term C 2 ×T, the voltage difference can be expressed as:

[0103] ΔV BE，Q1Q2 =C 1 ×TlnT+C 2 ×T

[0104] Among them, constants C1 and C2 are determined by the resistance value, temperature coefficient and V of several transistors. BE Voltage control; in this circuit, C can be controlled by adjusting the resistor R3 1 and C 2 The value of .

[0105] Therefore, the output voltage VREF can be expressed as:

[0106]

[0107] Wherein gm1 and gm2 represent the transconductance of the first input pair and the transconductance of the second input pair of tubes of the four-input operational amplifier A1, respectively. In this embodiment, the ratio of gm1 and gm2 is determined by the width-to-length ratio of the two input pairs of tubes. Therefore, the high-order temperature term brought by the VBE1 component in VREF can be offset by adjusting the width-to-length ratio of the two input pairs of tubes in the four-input operational amplifier.

[0108] Figure 3The simulation results of the output voltage VREF of the bandgap reference circuit under the TT process angle are shown. It can be seen from the figure that within the temperature range of -40 to 125°C, the change of the reference voltage is about 0.19mV, which is equivalent to a temperature coefficient of 0.97ppm / °C. The output reference voltage of the traditional first-order compensated bandgap reference circuit generally has a temperature coefficient of tens of ppm. From the simulation results, it can be seen that the high-order compensation method provided by the present invention can effectively reduce the temperature coefficient of the output voltage and improve the temperature drift performance.

[0109] like Figure 4 In the circuit of this embodiment, a metal fuse is preferably used for adjustment. Under default conditions, the first adjustable resistor R T0 , the second adjustable resistor R T1 , the third adjustable resistor R T2 and the fourth adjustable resistor R T3 All short-circuited. When trimming is needed, just burn out the first metal fuse RM1 to the third metal fuse RM3. This method will not introduce additional temperature effects and power supply effects, and has the advantage of good step consistency. However, it should be noted that this trimming method is only applicable to unilateral trimming, so at the beginning of the design, the initial value needs to be unilaterally increased or decreased by half of the trimming range.

[0110] The present invention makes further compensation on the basis of the traditional first-order bandgap reference voltage source circuit, completes the weighted addition of voltages through a four-input operational amplifier, and generates a reference voltage with a low temperature coefficient at the output end of the operational amplifier; at the same time, the present invention provides an optimized adjustment method, which solves the technical problems of introducing additional temperature effects, poor power supply rejection ratio and poor consistency of adjustment steps in the existing adjustment circuit, ensures the consistency of the bandgap reference voltage, ensures that the bandgap reference voltage is not affected by temperature conditions, and obtains a reference voltage with higher accuracy.

[0111] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions or improvements made within the technical scope of the present invention should be included in the scope of protection of the present invention.

Claims

1. A high-order compensated bandgap reference circuit with adjustable characteristics, characterized in that: It includes three-stage tubes Q0-Q2, PMOS tubes M1-M3, the first NMOS tube M4, resistors R0-R3, and adjustable resistor R T , four-input operational amplifier A1 and two-input operational amplifier A2; The source of the first PMOS tube M1 is connected to the power supply, the gate thereof is connected to the output end of the four-input operational amplifier A1, and the drain of the first PMOS tube M1 is connected to the adjustable resistor R T The first end connection; Adjustable resistance R T The end of the resistor is connected to the first end of the second resistor R1 and to the first end of the third resistor R2; The end of the second resistor R1 is connected to the first positive input terminal of the four-input operational amplifier A1, and the end of the third resistor R2 is connected to the first negative input terminal of the four-input operational amplifier A1; The emitter of the first transistor Q0 is connected to the end of the second resistor R1 through the first resistor R0, and the base and collector of the first transistor Q0 are grounded; The emitter of the second transistor Q1 is connected to the first non-inverting input terminal of the four-input operational amplifier A1, and is connected to the second non-inverting input terminal of the four-input operational amplifier A1, and is connected to the non-inverting input terminal of the two-input operational amplifier A2, and the base and collector of the second transistor Q1 are grounded; The emitter of the third transistor Q2 is connected to the second inverting input terminal of the four-input operational amplifier A1 and to the drain of the second PMOS transistor M2, and the base and collector of the third transistor Q2 are grounded; The sources of the second PMOS tube M2 and the third PMOS tube M3 are both connected to the power supply, the second PMOS tube M2 and the third PMOS tube M3 share a gate, and the gates of the second PMOS tube M2 and the third PMOS tube M3 are connected to the drain of the third PMOS tube M3; The drain of the first NMOS tube M4 is connected to the drain of the third PMOS tube M3, the gate of the first NMOS tube M4 is connected to the output end of the two-input operational amplifier A2, and the source of the first NMOS tube M4 is connected to the first end of the fourth resistor R3; A first end of the fourth resistor R3 is connected to the inverting input terminal of the two-input operational amplifier A2, and a terminal of the fourth resistor R3 is grounded.

2. The adjustable high-order compensated bandgap reference circuit according to claim 1, characterized in that: The second resistor R1 and the third resistor R2 have the same resistance value.

3. The adjustable high-order compensated bandgap reference circuit according to claim 1, characterized in that: The emitter junction area ratio of the transistors Q0-Q2 is Q0:Q1:Q2=N:1:1, where N is an integer greater than 1.

4. The adjustable high-order compensated bandgap reference circuit according to claim 1, characterized in that: The four-input operational amplifier A1 includes MOS tubes M5-M14, a zeroing resistor Rz and a Miller compensation capacitor Cc; the MOS tubes M5-M14 include: a fourth PMOS tube M5, a fifth PMOS tube M6, a sixth PMOS tube M7, a seventh PMOS tube M8, an eighth PMOS tube M11, a ninth PMOS tube M12 and a tenth PMOS tube M13; a second NMOS tube M9, a third NMOS tube M10 and a fourth NMOS tube M14; Among them, the source of the eighth PMOS tube M11, the source of the ninth PMOS tube M12 and the source of the tenth PMOS tube M13 are all connected to the power supply VDD, and the gates of the eighth PMOS tube M11, the ninth PMOS tube M12 and the tenth PMOS tube M13 are all connected to the bias voltage VB; The drain of the eighth PMOS tube M11 is connected to the source of the fourth PMOS tube M5 and the source of the fifth PMOS tube M6, and the drain of the ninth PMOS tube M12 is connected to the source of the sixth PMOS tube M7 and the source of the seventh PMOS tube M8; The drain of the fourth PMOS tube M5 is connected to the drain of the sixth PMOS tube M7 and the drain of the second NMOS tube M9, and the drain of the fifth PMOS tube M6 is connected to the drain of the seventh PMOS tube M8 and the drain of the third NMOS tube M10; The source of the second NMOS tube M9 and the source of the third NMOS tube M10 are both grounded, and the gate of the second NMOS tube M9 is connected to the gate of the third NMOS tube M10 and the drain of the second NMOS tube M9; The drain of the third NMOS transistor M10 is connected to the gate of the fourth NMOS transistor M14, and the source of the fourth NMOS transistor M14 is grounded; The zeroing resistor Rz and the Miller compensation capacitor Cc are connected in series and bridged between the gate and the drain of the fourth NMOS transistor M14; The drain of the fourth NMOS tube M14 is connected to the drain of the tenth PMOS tube M13.

5. The adjustable high-order compensated bandgap reference circuit according to claim 4, characterized in that: The fourth PMOS tube M5 and the fifth PMOS tube M6 serve as a first input pair of tubes of the four-input operational amplifier A1; The sixth PMOS tube M7 and the seventh PMOS tube M8 serve as a second input pair of tubes of the four-input operational amplifier A1; The gate of the fourth PMOS tube M5 serves as the first in-phase input terminal IP1 of the four-input operational amplifier A1; The gate of the fifth PMOS tube M6 serves as the first inverting input terminal IN1 of the four-input operational amplifier A1; The gate of the sixth PMOS tube M7 serves as the second non-inverting input terminal IP2 of the four-input operational amplifier A1; The gate of the seventh PMOS tube M8 serves as the second inverting input terminal IN2 of the four-input operational amplifier A1; The drain of the tenth PMOS transistor M13 and the drain of the fourth NMOS transistor M14 are connected to serve as the output terminal OUT of the four-input operational amplifier A1.

6. The adjustable high-order compensated bandgap reference circuit according to claim 1, characterized in that: The adjustable resistance R T The first adjustable resistor R is connected in series T0 , the second adjustable resistor R T1 , the third adjustable resistor R T2 and the fourth adjustable resistor R T3 , the first adjustable resistor R T0 A first metal fuse RM1 is connected in parallel, and the second adjustable resistor R T1 A second metal fuse RM2 is connected in parallel, and the third adjustable resistor R T2 A third metal fuse RM3 is connected in parallel.

7. The adjustable high-order compensated bandgap reference circuit according to claim 6, characterized in that: The adjustable resistance R T The trimming is achieved by: the first metal fuse RM1, the second metal fuse RM2 and the third metal fuse RM3 are blown, thereby adjusting the trimmable resistor R T The resistance value is used to adjust the temperature coefficient of the reference voltage VREF.

8. The adjustable high-order compensated bandgap reference circuit according to claim 1, characterized in that: The adjustable resistance R T The voltage at the end is used as the reference voltage VREF, and the expression of the reference voltage VREF is: Wherein, VBE1 is the BE junction voltage of the second transistor Q1; V T is the thermal voltage; N is the emitter junction area ratio of the first transistor Q0 and the second transistor Q1; ΔV BE，Q1Q2 is the BE junction voltage difference between the second transistor Q1 and the third transistor Q2; gm1 is the transconductance of the first input pair of the four-input operational amplifier A1; gm2 is the transconductance of the second input pair of the four-input operational amplifier A1.

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