Band-gap reference circuit

Abstract

The invention provides a band-gap reference circuit, and relates to the technical field of integrated circuits, and the band-gap reference circuit comprises a core circuit, a negative temperature current extraction circuit, a high-order modulation processing circuit and an output circuit. The core circuit is used for generating an X-point voltage, a positive temperature coefficient PTAT current without a base current and a negative temperature coefficient CTAT current mixed with the base current. Wherein the X-point voltage is the base-emitter voltage of a triode through which the PTAT current flows in the core circuit. And the negative temperature current extraction circuit is used for extracting CTAT current without base current according to the X-point voltage. And the high-order modulation processing circuit is used for generating band-gap reference current which is subjected to high-order modulation and is subjected to base current influence elimination according to the X-point voltage and the PTAT current provided by the core circuit and the CTAT current provided by the negative temperature current extraction circuit. And the output circuit is used for converting the band-gap reference current into band-gap reference voltage and outputting the band-gap reference voltage.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a bandgap reference circuit. Background Art

[0002] Bandgap reference can provide stable reference voltage and bias current in the environment of temperature and power supply voltage change, so it is widely used in various analog integrated circuits. Its accuracy directly determines the accuracy of the whole system. The design indicators of bandgap reference source include small temperature coefficient, high power supply rejection ratio, small correlation with process angle and other parameters. Bandgap reference source with excellent performance is of great significance to the functional realization of many modules of the system.

[0003] Most of the bandgap reference circuits designed at present require amplifiers, which not only increase the chip area, but also affect the accuracy of the voltage reference due to its input offset voltage and noise. In addition, the current method of implementing high-order modulated bandgap reference is greatly affected by the base current, which is prone to errors and leads to a decrease in the accuracy of the bandgap reference.

[0004] Therefore, in order to obtain a high-precision bandgap reference, it is necessary to design a bandgap reference with a high-order modulation, a non-amplifier structure, and a low temperature coefficient that offsets most of the base current effects. Summary of the invention

[0005] The purpose of the present application is to provide a high-order modulated, amplifier-free bandgap reference circuit that offsets most of the base current influence and has a low temperature coefficient.

[0006] In order to achieve the above purpose, the technical solution adopted in this application is as follows:

[0007] The present application provides a bandgap reference circuit, comprising: a core circuit, a negative temperature current extraction circuit, a high-order modulation processing circuit and an output circuit;

[0008] The first port of the negative temperature current extraction circuit and the first port of the high-order modulation processing circuit are both connected to point X in the core circuit, the second port and the third port of the high-order modulation processing circuit are respectively connected to the second port of the negative temperature current extraction circuit and the first port of the core circuit, and the output end of the high-order modulation processing circuit is connected to the output circuit;

[0009] The core circuit is used to generate a point X voltage, a positive temperature coefficient PTAT current without a base current, and a negative temperature coefficient CTAT current mixed with a base current; wherein the point X voltage is the base-emitter voltage of the transistor in the core circuit through which the PTAT current flows;

[0010] The negative temperature current extraction circuit is used to extract the CTAT current without base current according to the X point voltage;

[0011] The high-order modulation processing circuit is used to generate a bandgap reference current that has undergone high-order modulation and eliminated the influence of the base current according to the X-point voltage and PTAT current provided by the core circuit and the CTAT current provided by the negative temperature current extraction circuit;

[0012] The output circuit is used for converting the bandgap reference current into a bandgap reference voltage and then outputting the converted voltage.

[0013] Further, the core circuit includes: Q0 tube, Q1 tube, Q2 tube, Q3 tube, Q4 tube, PM0 tube, PM1 tube, PM2 tube, PM3 tube, PM23 tube, PM24 tube, PM25 tube, NM4 tube, resistor R0, resistor R1 and a first cascade MOS tube;

[0014] Among them, Q0, Q1, Q2, Q3 and Q4 are all NPN transistors, and the parallel number of Q0 is greater than the parallel number of Q1; PM0, PM1, PM2, PM3, PM23, PM24 and PM25 are all PMOS tubes, and NM4 is an NMOS tube;

[0015] The sources of the PM0 tube, the PM1 tube, the PM2 tube, the PM3 tube and the first cascade MOS tube are all connected to the power supply, the sources of the PM25 tube, the PM24 tube and the PM23 tube are respectively connected to the drains of the PM3 tube, the PM0 tube and the PM2 tube, the gates of the PM25 tube, the PM24 tube and the PM23 tube are all connected to the gate of the first cascade MOS tube; the gate of the PM3 tube, the gate of the PM0 tube and the drain of the PM23 tube are all connected to the gate of the PM2 tube; wherein the gate of the PM2 tube serves as the first port of the core circuit;

[0016] The drain of PM25 is connected to the collector of Q3, the drain of PM24 is connected to the gate of PM1 and the collector of Q0, the drain of PM23 is also connected to the drain of NM4, the gate of NM4 is connected to the collector of Q3, the source of NM4 is connected to the base of Q3 and the collector of Q2, and the drain of the first cascade MOS is connected to the collector of Q4.

[0017] The emitters of Q0, Q1, Q2, Q3 and Q4 are all grounded, the bases of Q1, Q2 and Q4 are all connected to the point X, the collector of Q1 is respectively connected to the base of Q0 and one end of resistor R0, the other end of resistor R0 is respectively connected to the drain of PM1 and the point X, one end of resistor R1 is grounded, and the other end of resistor R1 is connected to the point X.

[0018] Further, the negative temperature current extraction circuit includes: a PM4 tube, a PM5 tube, a PM6 tube, a PM30 tube, a PM31 tube, a NM0 tube, a NM1 tube, a NM2 tube, a NM3 tube, a resistor R2, a resistor R3, a resistor R4 and a second cascade MOS tube;

[0019] Among them, PM4, PM5, PM6, PM30 and PM31 are all PMOS tubes, and NM0, NM1, NM2 and NM3 are all NMOS tubes;

[0020] The sources of the PM4 tube, the PM5 tube, the PM6 tube and the second cascade MOS tube are all connected to the power supply, the drains of the PM4 tube and the PM5 tube are respectively connected to the sources of the PM30 tube and the PM31 tube, and the gates of the PM30 tube and the PM31 tube are both connected to the gate of the second cascade MOS tube; the gate of the PM4 tube and the drain of the PM31 tube are both connected to the gate of the PM5 tube; wherein the gate of the PM5 tube serves as the second port of the negative temperature current extraction circuit;

[0021] The drain of the second cascade MOS tube is connected to the drain of the NM3 tube, the drain of the PM6 tube is connected to the drain of the NM0 tube and the gate of the NM0 tube respectively, the drain of the PM30 tube is connected to the gate of the PM6 tube and the drain of the NM1 tube respectively, and the drain of the PM31 tube is also connected to the drain of the NM2 tube;

[0022] The gates of NM3, NM1 and NM2 are all connected to the gate of NM0; the source of NM3 is grounded through resistor R4, the source of NM0 is grounded through resistor R3, the source of NM1 is grounded through resistor R2, and the source of NM2 is connected to the point X; wherein the source of NM2 serves as the first port of the negative temperature current extraction circuit.

[0023] Further, the first cascade MOS tubes include: PM32 tube, PM33 tube, PM34 tube and PM35 tube, and the second cascade MOS tubes include: PM26 tube, PM27 tube, PM28 tube and PM29 tube;

[0024] Among them, PM32, PM33, PM34, PM35, PM26, PM27, PM28 and PM29 are all PMOS tubes;

[0025] The source of the PM32 tube is connected to the power supply as the source of the first cascade MOS tube, the drain of the PM32 tube is connected to the source of the PM33 tube, the drain of the PM33 tube is connected to the source of the PM34 tube, and the drain of the PM34 tube is connected to the source of the PM35 tube; the gate of the PM32 tube, the gate of the PM33 tube, the gate of the PM34 tube, the gate of the PM35 tube and the drain of the PM35 tube are connected and serve as the gate of the first cascade MOS tube; the drain of the PM35 tube is also connected to the collector of the Q4 tube;

[0026] The source of the PM26 tube is connected to the power supply as the source of the second cascade MOS tube, the drain of the PM26 tube is connected to the source of the PM27 tube, the drain of the PM27 tube is connected to the source of the PM28 tube, and the drain of the PM28 tube is connected to the source of the PM29 tube; the gate of the PM26 tube, the gate of the PM27 tube, the gate of the PM28 tube, the gate of the PM29 tube and the drain of the PM29 tube are connected and serve as the gate of the second cascade MOS tube; the drain of the PM29 tube is also connected to the drain of the NM3 tube.

[0027] Furthermore, the high-order modulation processing circuit includes: a resistor R NL , a zero temperature current generating module, a first Wilson current mirror and a second Wilson current mirror;

[0028] The first input end of the zero temperature current generating module is connected to the second port of the negative temperature current extraction circuit, and the second input end of the zero temperature current generating module is connected to the first port of the core circuit; the first output end of the zero temperature current generating module is connected to the first port of the first Wilson current mirror, the second output end of the zero temperature current generating module is connected to the first port of the second Wilson current mirror, the third output end of the zero temperature current generating module is respectively connected to the second port of the first Wilson current mirror and the second port of the second Wilson current mirror, and the second port of the second Wilson current mirror is also connected to the output circuit; the resistor R NL One end of the resistor R is connected to the point X in the core circuit. NL The other end is connected to point Z in the first Wilson current mirror;

[0029] The zero temperature current generating module is used for providing a zero temperature coefficient ZTAT current to the first Wilson current mirror and the second Wilson current mirror according to the PTAT current and the CTAT current;

[0030] The resistor R NL Used to provide a high-order modulation current to the first Wilson current mirror according to the voltage at point X and the voltage at point Z; wherein the voltage at point Z is the base-emitter voltage of the transistor in the first Wilson current mirror through which the ZTAT current flows;

[0031] The first Wilson current mirror and the second Wilson current mirror are used to generate a bandgap reference current that has undergone high-order modulation and eliminates the influence of base current and the influence of transistor current gain reduction at low temperature according to the ZTAT current and the high-order modulation current.

[0032] Further, the zero-temperature current generating module includes: a PM7 tube, a PM8 tube, a PM9 tube, a PM10 tube, a PM11 tube, a PM12 tube, a PM17 tube, a PM18 tube, a PM19 tube, a PM20 tube, a PM21 tube and a PM22 tube;

[0033] Among them, PM7, PM8, PM9, PM10, PM11, PM12, PM17, PM18, PM19, PM20, PM21 and PM22 are all PMOS tubes;

[0034] The number of PM7 tubes in parallel = the number of PM22 tubes in parallel = the number of PM10 tubes in parallel = the number of PM20 tubes in parallel = the number of PM9 tubes in parallel = the number of PM17 tubes in parallel = the number of PM12 tubes in parallel = the number of PM18 tubes in parallel = a, the number of PM8 tubes in parallel = the number of PM21 tubes in parallel = the number of PM11 tubes in parallel = the number of PM19 tubes in parallel = b, a and b are both positive integers, and b>2a;

[0035] The sources of the PM7 tube, the PM8 tube, the PM9 tube, the PM10 tube, the PM11 tube and the PM12 tube are all connected to the power supply; the gates of the PM7 tube, the PM8 tube and the PM9 tube are all connected to the gate of the PM2 tube; the drains of the PM7 tube, the PM8 tube and the PM9 tube are respectively connected to the sources of the PM22 tube, the PM21 tube and the PM17 tube; the gates of the PM22 tube, the PM21 tube and the PM17 tube are all connected to the gate of the first cascade MOS tube;

[0036] The gates of the PM10 tube, the PM11 tube, and the PM12 tube are all connected to the gate of the PM5 tube, the drains of the PM10 tube, the PM11 tube, and the PM12 tube are respectively connected to the source of the PM20 tube, the PM19 tube, and the PM18 tube, and the gates of the PM20 tube, the PM19 tube, and the PM18 tube are all connected to the gate of the second cascade MOS tube;

[0037] The drain of the PM22 tube and the drain of the PM20 tube are connected as the first output end of the zero-temperature current generating module and are connected to the first port of the first Wilson current mirror. The drain of the PM17 tube and the drain of the PM18 tube are connected as the second output end of the zero-temperature current generating module and are connected to the first port of the second Wilson current mirror. The drain of the PM21 tube and the drain of the PM19 tube are connected as the third output end of the zero-temperature current generating module and are respectively connected to the second port of the first Wilson current mirror and the second port of the second Wilson current mirror.

[0038] Further, the first Wilson current mirror includes: NM5 tube, Q5 tube, Q6 tube, Q11 tube and Q12 tube, and the second Wilson current mirror includes: NM6 tube, Q7 tube, Q8 tube, Q9 tube and Q10 tube;

[0039] Among them, NM5 and NM6 are NMOS tubes, and Q5, Q6, Q7, Q8, Q9, Q10, Q11 and Q12 are NPN transistors;

[0040] The collector of Q12 is connected to the first output terminal of the zero-temperature current generating module and the gate of NM5, the drain of NM5 is connected to the third output terminal of the zero-temperature current generating module, the source of NM5 is connected to the collector of Q6, the base of Q6 and the base of Q12, the emitter of Q6 is connected to the collector of Q5; the emitter of Q12, the collector of Q11, the base of Q11, the base of Q5 and the resistor R NL One end of each is connected to point Z, and the emitters of Q11 and Q5 are grounded;

[0041] The drain of the NM6 tube is respectively connected to the third output end of the zero-temperature current generating module and the output circuit, and the source of the NM6 tube is connected to the collector of the Q7 tube; the collector of the Q10 tube is respectively connected to the second output end of the zero-temperature current generating module, the gate of the NM6 tube, the base of the Q10 tube and the base of the Q7 tube; the emitter of the Q10 tube is connected to the collector of the Q9 tube, and the emitter of the Q7 tube is respectively connected to the collector of the Q8 tube, the base of the Q8 tube and the base of the Q9 tube, and the emitters of the Q8 tube and the Q9 tube are both grounded.

[0042] Furthermore, the core circuit further includes a resistor Rs1, and the bandgap reference circuit further includes a startup circuit;

[0043] One end of the resistor Rs1 is connected to the point X, the other end of the resistor Rs1 is respectively connected to the drain of the PM1 tube and the first port of the startup circuit, the second port of the startup circuit is respectively connected to the gate of the PM6 tube, the drain of the PM30 tube and the drain of the NM1 tube, and the input end of the startup circuit is connected to the power supply.

[0044] Furthermore, the startup circuit includes: a Q13 tube, a NMs1 tube, a NMs2 tube, a resistor Rs2, a resistor Rs3 and a capacitor C1; wherein the Q13 tube is an NPN transistor, and the NMs1 tube and the NMs2 tube are both NMOS tubes;

[0045] One end of the resistor Rs3 is connected to the power supply, and the other end of the resistor Rs3 is respectively connected to the drain of the NMs1 tube, the gate of the NMs1 tube and the gate of the NMs2 tube; the source of the NMs1 tube is respectively connected to the collector of the Q13 tube and the base of the Q13 tube, and the emitter of the Q13 tube is grounded;

[0046] The source of NMs2 is connected to the drain of PM1 and one end of resistor Rs1 respectively, and the drain of NMs2 is connected to the gate of PM6, the drain of PM30 and the drain of NM1 respectively; the drain of NMs2 is also connected to one end of resistor Rs2, the other end of resistor Rs2 is connected to one end of capacitor C1, and the other end of capacitor C1 is grounded;

[0047] When the bandgap reference circuit outputs normally, the NMs2 tube is turned off and the startup circuit stops running.

[0048] Furthermore, the output circuit includes: a first current mirror, a second current mirror and a resistor R OUT ;

[0049] The first port of the first current mirror is connected to the output end of the high-order modulation processing circuit, the second port of the first current mirror is connected to the third port of the second current mirror, the third port and the fourth port of the first current mirror are both grounded, the first port and the second port of the second current mirror are both connected to the power supply, and the resistor R OUT One end of the resistor R OUT The other end is connected to the fourth port of the second current mirror as the output end of the bandgap reference circuit.

[0050] Compared with the prior art, this application has the following beneficial effects:

[0051] The present application provides a bandgap reference circuit, including: a core circuit, a negative temperature current extraction circuit, a high-order modulation processing circuit and an output circuit. The core circuit can generate a point X voltage (i.e., the base-emitter voltage of a transistor in the core circuit through which a positive temperature coefficient PTAT current flows), a positive temperature coefficient PTAT current without a base current, and a negative temperature coefficient CTAT current mixed with a base current. The negative temperature current extraction circuit extracts a CTAT current without a base current according to the point X voltage. The high-order modulation processing circuit generates a bandgap reference current after high-order modulation and elimination of the influence of the base current according to the point X voltage and PTAT current provided by the core circuit and the CTAT current provided by the negative temperature current extraction circuit. The output circuit converts the bandgap reference current into a bandgap reference voltage and outputs it. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0053] Figure 1 One of the structural schematic diagrams of a bandgap reference circuit provided in an embodiment of the present application;

[0054] Figure 2 A circuit diagram of a core circuit provided in an embodiment of the present application;

[0055] Figure 3 A circuit diagram including a core circuit and a negative temperature current extraction circuit provided in an embodiment of the present application;

[0056] Figure 4 A circuit diagram including a core circuit, a negative temperature current extraction circuit and a startup circuit provided in an embodiment of the present application;

[0057] Figure 5 A second structural schematic diagram of a bandgap reference circuit provided in an embodiment of the present application;

[0058] Figure 6 A circuit diagram of a high-order modulation processing circuit provided in an embodiment of the present application;

[0059] Figure 7 A circuit diagram of an output circuit provided in an embodiment of the present application;

[0060] Figure 8 A circuit diagram of a bandgap reference circuit provided in an embodiment of the present application.

[0061] Icons: 10-bandgap reference circuit; 100-core circuit; 110-first cascade MOS tube; 200-negative temperature current extraction circuit; 210-second cascade MOS tube; 300-high-order modulation processing circuit; 310-zero temperature current generation module; 320-first Wilson current mirror; 330-second Wilson current mirror; 400-output circuit; 410-first current mirror; 420-second current mirror; 500-start-up circuit. DETAILED DESCRIPTION

[0062] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0063] In the description of this application, it should be noted that relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The term "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.

[0064] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0065] As mentioned in the background technology, most existing bandgap reference circuits require amplifiers, which not only increase the chip area consumption, but also affect the accuracy of the voltage reference due to its input offset voltage and noise. In addition, the current method of implementing a high-order modulated bandgap reference is greatly affected by the base current and is prone to errors, resulting in a decrease in the accuracy of the bandgap reference.

[0066] In view of this, the present application provides a bandgap reference with a low temperature coefficient that is high-order modulated, has no amplifier structure, and offsets most of the base current influence. High-order modulation is performed based on the temperature characteristics of the base-emitter voltage of the transistor. The influence of the base current is eliminated through a negative temperature current extraction circuit and two Wilson current mirrors, eliminating the error caused by the reduction of the current gain β of the transistor at low temperatures, and finally generating a bandgap reference voltage with a low temperature coefficient.

[0067] See also Figure 1 An embodiment of the present application provides a bandgap reference circuit 10, including: a core circuit 100, a negative temperature current extraction circuit 200, a high-order modulation processing circuit 300 and an output circuit 400.

[0068] The first port of the negative temperature current extraction circuit 200 and the first port of the high-order modulation processing circuit 300 are both connected to point X in the core circuit 100. The second port and the third port of the high-order modulation processing circuit 300 are respectively connected to the second port of the negative temperature current extraction circuit 200 and the first port of the core circuit 100, and the output end of the high-order modulation processing circuit 300 is connected to the output circuit 400.

[0069] The core circuit 100 is used to generate a point X voltage, a positive temperature coefficient PTAT current without a base current, and a negative temperature coefficient CTAT current mixed with a base current. The point X voltage is the base-emitter voltage of the transistor in the core circuit 100 through which the PTAT current flows.

[0070] The negative temperature current extraction circuit 200 is used to extract a CTAT current without a base current according to the voltage at the point X.

[0071] The high-order modulation processing circuit 300 is used to generate a bandgap reference current I after high-order modulation and eliminating the influence of the base current and the decrease of the transistor β at low temperature according to the X-point voltage and PTAT current provided by the core circuit 100 and the CTAT current provided by the negative temperature current extraction circuit 200. ref .

[0072] The output circuit 400 is used to convert the bandgap reference current I ref Converted to bandgap reference voltage V ref After output.

[0073] Furthermore, in order to make the bandgap reference circuit 10 escape from the degenerate state of zero current, the bandgap reference circuit 10 also includes a startup circuit 500. The first port of the startup circuit 500 is connected to the core circuit 100, the second port of the startup circuit 500 is connected to the negative temperature current extraction circuit 200, and the input terminal of the startup circuit 500 is connected to the power supply VDD. The startup circuit 500 is used to start the core circuit 100 and the negative temperature current extraction circuit 200, and when the bandgap reference circuit 10 outputs normally, the startup circuit 500 stops running.

[0074] In order to better understand the technical solution of the present application, the specific structures and working principles of the core circuit 100, the negative temperature current extraction circuit 200, the startup circuit 500, the high-order modulation processing circuit 300 and the output circuit 400 will be described in turn below.

[0075] See also Figure 2 In the embodiment of the present application, the core circuit 100 includes: Q0 tube, Q1 tube, Q2 tube, Q3 tube, Q4 tube, PM0 tube, PM1 tube, PM2 tube, PM3 tube, PM23 tube, PM24 tube, PM25 tube, NM4 tube, resistor R0, resistor R1 and a first cascade MOS tube 110.

[0076] Among them, Q0, Q1, Q2, Q3 and Q4 are all NPN transistors, and the parallel number of Q0 is greater than the parallel number of Q1. Optionally, the parallel number m of Q0 is 8 times the parallel number m of Q1.

[0077] PM0, PM1, PM2, PM3, PM23, PM24 and PM25 are all PMOS tubes, and NM4 is an NMOS tube.

[0078] The connection relationship of each component of the core circuit 100 is as follows:

[0079] The sources of the PM0 transistor, the PM1 transistor, the PM2 transistor, the PM3 transistor and the first cascade MOS transistor 110 are all connected to the power supply VDD. The sources of the PM25 transistor, the PM24 transistor and the PM23 transistor are respectively connected to the drains of the PM3 transistor, the PM0 transistor and the PM2 transistor, and the gates of the PM25 transistor, the PM24 transistor and the PM23 transistor are all connected to the gate of the first cascade MOS transistor 110. The gate of the PM3 transistor, the gate of the PM0 transistor and the drain of the PM23 transistor are all connected to the gate of the PM2 transistor, wherein the gate of the PM2 transistor serves as the first port of the core circuit 100.

[0080] The drain of the PM25 tube is connected to the collector of the Q3 tube, the drain of the PM24 tube is connected to the gate of the PM1 tube and the collector of the Q0 tube respectively, the drain of the PM23 tube is also connected to the drain of the NM4 tube. The gate of the NM4 tube is connected to the collector of the Q3 tube, the source of the NM4 tube is connected to the base of the Q3 tube and the collector of the Q2 tube respectively, and the drain of the first cascade MOS tube 110 is connected to the collector of the Q4 tube.

[0081] The emitters of Q0, Q1, Q2, Q3 and Q4 are all grounded, and the bases of Q1, Q2 and Q4 are all connected to point X. The collector of Q1 is connected to the base of Q0 and one end of resistor R0 respectively, and the other end of resistor R0 is connected to the drain of PM1 and point X respectively. One end of resistor R1 is grounded, and the other end of resistor R1 is connected to point X.

[0082] Furthermore, the first cascade MOS tube 110 includes: a PM32 tube, a PM33 tube, a PM34 tube and a PM35 tube, wherein the PM32 tube, the PM33 tube, the PM34 tube and the PM35 tube are all PMOS tubes.

[0083] The source of the PM32 tube is connected to the power supply VDD as the source of the first cascade MOS tube 110, the drain of the PM32 tube is connected to the source of the PM33 tube, the drain of the PM33 tube is connected to the source of the PM34 tube, and the drain of the PM34 tube is connected to the source of the PM35 tube. The gate of the PM32 tube, the gate of the PM33 tube, the gate of the PM34 tube, the gate of the PM35 tube and the drain of the PM35 tube are connected to serve as the gate of the first cascade MOS tube 110. The drain of the PM35 tube is also connected to the collector of the Q4 tube.

[0084] The working principle of the core circuit 100 is as follows:

[0085] In the core circuit 100, Q1, Q2 and Q4 form a transistor current mirror, and PM3, PM0 and PM2 form a PMOS tube current mirror. When the base current of the transistor is ignored, the collector current and emitter current of the transistor are equal. At this time, the Q1, Q2, Q4 current mirror and the PM3, PM0, PM2 current mirror make the currents of Q0, Q1, Q2, Q3, Q4 equal. The parallel number of Q0 is 8 times that of Q1, and the voltage difference V across the resistor R0 is RO =Q0's base-emitter voltage V be0 and Q1’s base-emitter voltage V be1 The difference, V R0 =V be0 -V be1 =V T ln 8, so the current flowing through R0 Among them, V Tis the thermal voltage, and its value increases with the increase of temperature. It can be seen that the current flowing through R0 is the PTAT current. Q4 copies the PTAT current to PM32-PM35 to generate the bias voltage Vb1 required by the MOS tube current mirror.

[0086] The voltage at point X is unique when the currents of Q0 and Q1 are equal and not zero. Assuming that the voltage at point X is V1 at this time, analysis shows that: when the voltage at point X is greater than V1, the current of Q0 is less than the current of Q1; when the voltage at point X is less than V1, the current of Q0 is greater than the current of Q1.

[0087] It should be noted that the reason why the currents of Q0 and Q1 remain equal and the voltage at point X is maintained at V1 is because of the negative feedback path of PM1. If the voltage at point X is less than V1, the current of Q0 is greater than the currents of Q1 and Q2, the gate voltage of PM1 will drop, the current of PM1 will increase, and the voltage at point X will rise to V1. Conversely, when the voltage at point X is greater than V1, the voltage at point X will also be reduced to V1 through the negative feedback path of PM1.

[0088] Now consider the base current. Since Q0 draws a base current from the PTAT current flowing through R0, Q3 also draws the same base current from Q2 and makes the collector voltage of Q2 equal to that of Q1 to ensure accurate replication of the PTAT current. By setting NM4 to avoid direct connection between the base of Q3 and the gate of PM2, the gate voltage of PM2 can change only with the current of Q2 in a large range, providing freedom for the PM2 current mirror.

[0089] And, due to the transistor base-emitter voltage V be It is a negative temperature coefficient voltage, so a negative temperature coefficient current, i.e., CTAT current, can be obtained by connecting resistor R1 between point X and ground. At this time, PTAT current, CTAT current and four times base current (i.e., base current of Q0, Q1, Q2 and Q4) will converge at PM1.

[0090] In order to eliminate the influence of the base current, the present application strips off the base current through the negative temperature current extraction circuit 200, thereby providing a clean CTAT current (ie, a CTAT current without the base current) for the high-order modulation processing circuit 300.

[0091] The following will be combined Figure 3 The specific structure and working principle of the negative temperature current extraction circuit 200 are described.

[0092] like Figure 3 As shown, in the embodiment of the present application, the negative temperature current extraction circuit 200 includes: PM4 tube, PM5 tube, PM6 tube, PM30 tube, PM31 tube, NM0 tube, NM1 tube, NM2 tube, NM3 tube, resistor R2, resistor R3, resistor R4 and a second cascade MOS tube 210.

[0093] Among them, PM4, PM5, PM6, PM30 and PM31 are all PMOS tubes, and NM0, NM1, NM2 and NM3 are all NMOS tubes.

[0094] The sources of the PM4 tube, the PM5 tube, the PM6 tube and the second cascade MOS tube 210 are all connected to the power supply VDD. The drains of the PM4 tube and the PM5 tube are respectively connected to the sources of the PM30 tube and the PM31 tube, and the gates of the PM30 tube and the PM31 tube are both connected to the gate of the second cascade MOS tube 210. The gate of the PM4 tube and the drain of the PM31 tube are both connected to the gate of the PM5 tube. Among them, the gate of the PM5 tube serves as the second port of the negative temperature current extraction circuit 200.

[0095] The drain of the second cascade MOS tube 210 is connected to the drain of the NM3 tube, the drain of the PM6 tube is respectively connected to the drain of the NM0 tube and the gate of the NM0 tube, the drain of the PM30 tube is respectively connected to the gate of the PM6 tube and the drain of the NM1 tube, and the drain of the PM31 tube is also connected to the drain of the NM2 tube.

[0096] The gates of NM3, NM1 and NM2 are all connected to the gate of NM0. The source of NM3 is grounded through resistor R4, the source of NM0 is grounded through resistor R3, the source of NM1 is grounded through resistor R2, and the source of NM2 is connected to point X. The source of NM2 serves as the first port of the negative temperature current extraction circuit 200.

[0097] Furthermore, the second cascade MOS transistor 210 includes: a PM26 transistor, a PM27 transistor, a PM28 transistor and a PM29 transistor, wherein the PM26 transistor, the PM27 transistor, the PM28 transistor and the PM29 transistor are all PMOS transistors.

[0098] The source of the PM26 transistor is connected to the power supply VDD as the source of the second cascade MOS transistor 210, the drain of the PM26 transistor is connected to the source of the PM27 transistor, the drain of the PM27 transistor is connected to the source of the PM28 transistor, and the drain of the PM28 transistor is connected to the source of the PM29 transistor. The gate of the PM26 transistor, the gate of the PM27 transistor, the gate of the PM28 transistor, the gate of the PM29 transistor and the drain of the PM29 transistor are connected to serve as the gate of the second cascade MOS transistor 210. The drain of the PM29 transistor is also connected to the drain of the NM3 transistor.

[0099] Next, Figure 3Points L, N, J, Y, and K in FIG. The gate of PM6, the drain of PM30, and the drain of NM1 are all connected to point L. The gate of PM4, the gate of PM5, and the drain of PM31 are all connected to point N. The gate of NM3, the gate of NM0, the drain of NM0, the drain of PM6, the gate of NM1, and the gate of NM2 are all connected to point Y. Point J is the source of NM0, and point K is the source of NM1.

[0100] It should be noted that the types and resistance values ​​of resistors R1-R4 are the same. Assuming the resistance value is R C , that is, R1=R2=R3=R4=R C . Also, PM4-PM6 are equal in size, and NM0-NM3 are equal in size.

[0101] The negative temperature current extraction circuit 200 can copy the voltage at point X to point K and make the current flowing through PM5 fixed to V X / R C The current (i.e. CTAT current excluding base current) is analyzed as follows:

[0102] First assume that the current mirror currents are equal, that is, the current mirror can make the currents of NM2, PM5, PM4, and NM1 equal. Because the gate of NM1 is connected to the gate of NM2, the source voltage of NM1 = the source voltage of NM2 = the voltage at point X, so the current of NM1 = V X / R2=V X / R C , and the current of NM2 = V X / R C This requires that the voltage at point Y controlled by NM0 = V X +V gs (Wherein, V gs is the current V X / R C The gate-source voltage when flowing through NM1), that is, the voltage at point Y changes with the voltage at point X according to this equation. PM6 is to maintain this relationship. Considering the channel length modulation effect, the previous assumption that the currents of PM4 and PM5 are completely equal means that the voltage at point L is equal to the voltage at point N. Then the voltage at point L is used as the gate voltage of PM6, and the current of PM6 = the current of PM4, which can make the current of NM0 = the current of NM1 = the current of NM2 = V X / R C , the voltage at point J also copies the voltage at point X, so the voltage at point Y can always remain equal to V X +V gs Therefore, NM2 can extract V under the assumption that the current mirror current is equal. X / R C Current, that is, the CTAT current without the base current.

[0103] Now we no longer assume that the current mirror currents are equal. Assume that the voltage offset at point L makes the voltage at point L less than the voltage at point N, that is, at this time, the current mirror PM5 current is less than the current PM4 current. Then the current of PM6 will be greater than the current at the "assumed time" (that is, when the current mirror currents assumed to be equal), the voltage at point Y will rise relative to the "assumed time", and the current of NM2 will increase. If the gate voltage of PM1 does not change at this time, the current of PM1 will not change, and the voltage at point X will have to rise due to the increase in the voltage at point Y. Then the voltage at point X will exceed the voltage V1 (that is, the voltage at point X when the currents of Q0 and Q1 are equal and not zero), and the current of Q0 will be less than Q2, which will cause the gate voltage of PM1 to rise and the current of PM1 to decrease. As the voltage at point X rises, the currents of Q1 and R1 both increase, while the current of PM1 decreases, so the current flowing through NM2 will be greater than V at this time. X / R1, that is, greater than V X / R C The current of NM2 will be greater than the current of NM1, the reason is as follows:

[0104] Assumption: NMOS tube

[0105] Then the current I of NM2 is NM2 =K N (V Y -V X -V TH,N ) 2 >V X / R C ,

[0106] The current I of NM1 NM1 =K N (V Y -V K -V TH,N ) 2 =V K / R C ,

[0107] After finishing, we get:

[0108] That is V K >V X , that is to say, the gate-source voltage of NM1 is smaller than that of NM2, and the current flowing through NM2 will be larger than that of NM1, so the current of PM4 is smaller than that of PM5, PM4 enters the linear region, the voltage at point L rises, and negative feedback is established. On the contrary, the voltage at point L is larger than that at the "assumption time" and will be pulled back to be equal to the voltage at point N due to negative feedback, so that NM2 can extract V X / R C Electric current.

[0109] That is to say, even if the currents of the current mirrors (PM4-PM5, NM1-NM2) are temporarily unequal due to unknown interference, they will be equal due to negative feedback, and then the voltage at point K will be equal to the voltage at point X, so that NM2 can extract V X / R C Current, that is, the CTAT current without the base current.

[0110] NM3 copies the CTAT current to PM26-PM29, generating the bias voltage Vb required by the current mirror.

[0111] Combine the following Figure 4 The specific structure and working principle of the starting circuit 500 are described.

[0112] like Figure 4 As shown, in the embodiment of the present application, the core circuit 100 further includes a resistor Rs1. One end of the resistor Rs1 is connected to point X, and the other end of the resistor Rs1 is respectively connected to the drain of the PM1 transistor and the first port of the startup circuit 500. The second port of the startup circuit 500 is respectively connected to the gate of the PM6 transistor, the drain of the PM30 transistor, and the drain of the NM1 transistor, and the input end of the startup circuit 500 is connected to the power supply VDD.

[0113] Furthermore, the startup circuit 500 includes: a Q13 transistor, a NMs1 transistor, a NMs2 transistor, a resistor Rs2, a resistor Rs3 and a capacitor C1. Among them, the Q13 transistor is an NPN transistor, and the NMs1 transistor and the NMs2 transistor are both NMOS transistors.

[0114] One end of the resistor Rs3 is connected to the power supply VDD, and the other end of the resistor Rs3 is connected to the drain of the NMs1 tube, the gate of the NMs1 tube and the gate of the NMs2 tube respectively. The source of the NMs1 tube is connected to the collector of the Q13 tube and the base of the Q13 tube respectively, and the emitter of the Q13 tube is grounded.

[0115] The source of NMs2 is connected to the drain of PM1 and one end of resistor Rs1 respectively, and the drain of NMs2 is connected to the gate of PM6, the drain of PM30 and the drain of NM1 respectively. The drain of NMs2 is also connected to one end of resistor Rs2, the other end of resistor Rs2 is connected to one end of capacitor C1, and the other end of capacitor C1 is grounded.

[0116] The working principle of the start-up circuit 500 is as follows:

[0117] By adding resistor Rs1, the source of NMs2 obtains a voltage higher than V be (i.e., the base-emitter voltage of Q1 and Q2) r , to facilitate the final closing of the startup circuit 500.

[0118] When the power supply VDD is not 0 and the startup circuit 500 is not working, the entire bandgap reference circuit 10 has no current, the L point is high voltage, and C1 is charged by VDD. After adding the startup circuit 500, the gate voltage of NMs1 is increased by VDD, so that NMs2 has current flowing from L point to X point.

[0119] Since PM4 is not turned on yet, the current of NMs2 comes from capacitor C1. As the energy of C1 decreases, the potential of point L is pulled down. PM6 starts to have current, which makes the potential of point Y increase, and the bias circuit of Vb starts to work. At the same time, NM2 starts to flow current, and the current mirror from PM5 to PM4 works. The capacitor C1 gradually no longer needs to bear the current of NMs2. The negative temperature current extraction circuit 200 starts to work, and NM2 extracts V from point X. X / R C Electric current.

[0120] The current flowing from NM2 to point X causes the voltage at point X to rise. However, the voltage at point X is still lower than the stable value. Then, due to the advantage of 8 parallel connections, the current of Q0 will be greater than that of Q2. The gate voltage of PM1 will begin to decrease, and the current required by PM1 will increase. The current required by NM2 is also large, which forces the potential at point X to increase until it reaches the preset stable state. Before reaching the preset stable state, V r The potential also rises, and when it exceeds the start-up condition of NMs2, NMs2 is turned off, that is, the startup circuit 500 is turned off. The current requirements of PM1 and NM2 are still not met at this time, and the voltage at point X continues to increase until it reaches the preset stable state, and the bandgap reference circuit 10 is successfully started.

[0121] See also Figure 5 In the embodiment of the present application, the high-order modulation processing circuit 300 includes: a resistor R NL , a zero-temperature current generating module 310 , a first Wilson current mirror 320 , and a second Wilson current mirror 330 .

[0122] The first input terminal of the zero temperature current generating module 310 is connected to the second port of the negative temperature current extraction circuit 200, and the second input terminal of the zero temperature current generating module 310 is connected to the first port of the core circuit 100. The first output terminal of the zero temperature current generating module 310 is connected to the first port of the first Wilson current mirror 320, the second output terminal of the zero temperature current generating module 310 is connected to the first port of the second Wilson current mirror 330, the third output terminal of the zero temperature current generating module 310 is connected to the second port of the first Wilson current mirror 320 and the second port of the second Wilson current mirror 330, respectively, and the second port of the second Wilson current mirror 330 is also connected to the output circuit 400. The resistor R NL One end of the resistor R is connected to point X in the core circuit 100.NL The other end of is connected to point Z in the first Wilson current mirror 320 .

[0123] The zero temperature current generating module 310 is used to provide a zero temperature coefficient ZTAT current (i.e., I outputted from the first output terminal) to the first Wilson current mirror 320 and the second Wilson current mirror 330 according to the PTAT current and the CTAT current. ZTAT1 , the second output terminal outputs I ZTAT2 and the third output terminal outputs I ZTAT3 ).

[0124] Resistor R NL Provides a high-order modulation current I to the first Wilson current mirror 320 according to the voltage at point X and the voltage at point Z. NL Among them, I NL =(voltage at point X - voltage at point Z) / R NL , the voltage at point Z is the base-emitter voltage of the transistor in the first Wilson current mirror 320 through which the ZTAT current flows.

[0125] The first Wilson current mirror 320 and the second Wilson current mirror 330 are used to generate a bandgap reference current that has undergone high-order modulation and eliminates the influence of the base current and the reduction of the transistor current gain β at low temperature according to the ZTAT current and the high-order modulation current.

[0126] In order to better understand the principle of high-order modulation, the formula for the base-emitter voltage of the transistor is first introduced below.

[0127]

[0128] Among them, T r is the reference temperature, V bg (T r ) is T r The bandgap voltage at a certain temperature is considered to be a constant. η is a constant that is independent of temperature but is process-dependent. The coefficient x represents the temperature-dependent characteristics of the current flowing through the transistor. If it is a PTAT current, then x = 1. If it is a current that is independent of temperature (i.e., ZTAT current), then x = 0. It can be seen that the base-emitter voltage V be The first term of (T) is a constant term to be retained, the second term is a first-order term eliminated by the zero-temperature current generating module 310, and the third term is a high-order term that needs to be reduced by high-order modulation.

[0129] The high-order terms can be extracted by using the characteristic that the coefficient x changes due to the current characteristics. The difference between the emitter-base voltage of the transistor with PTAT current flowing (i.e., the voltage at point X) and the emitter-base voltage of the transistor with ZTAT current flowing (i.e., the voltage at point Z) is equal to The resistor RNL The current generated on the

[0130] For further information, see Figure 6 The zero-temperature current generating module 310 includes: a PM7 tube, a PM8 tube, a PM9 tube, a PM10 tube, a PM11 tube, a PM12 tube, a PM17 tube, a PM18 tube, a PM19 tube, a PM20 tube, a PM21 tube and a PM22 tube.

[0131] Among them, PM7 tube, PM8 tube, PM9 tube, PM10 tube, PM11 tube, PM12 tube, PM17 tube, PM18 tube, PM19 tube, PM20 tube, PM21 tube and PM22 tube are all PMOS tubes.

[0132] The number of PM7 tubes in parallel = the number of PM22 tubes in parallel = the number of PM10 tubes in parallel = the number of PM20 tubes in parallel = the number of PM9 tubes in parallel = the number of PM17 tubes in parallel = the number of PM12 tubes in parallel = the number of PM18 tubes in parallel = a. The number of PM8 tubes in parallel = the number of PM21 tubes in parallel = the number of PM11 tubes in parallel = the number of PM19 tubes in parallel = b. Wherein, a and b are both positive integers, and b>2a. Optionally, a=1, b=M, then M is a positive integer greater than 2.

[0133] The sources of the PM7 tube, the PM8 tube, the PM9 tube, the PM10 tube, the PM11 tube and the PM12 tube are all connected to the power supply VDD. The gates of the PM7 tube, the PM8 tube and the PM9 tube are all connected to the gate of the PM2 tube. The drains of the PM7 tube, the PM8 tube and the PM9 tube are respectively connected to the sources of the PM22 tube, the PM21 tube and the PM17 tube. The gates of the PM22 tube, the PM21 tube and the PM17 tube are all connected to the gate of the first cascade MOS tube 110.

[0134] The gates of the PM10, PM11 and PM12 tubes are all connected to the gate of the PM5 tube, the drains of the PM10, PM11 and PM12 tubes are respectively connected to the sources of the PM20, PM19 and PM18 tubes, and the gates of the PM20, PM19 and PM18 tubes are all connected to the gate of the second cascade MOS tube 210.

[0135] The drain of the PM22 tube and the drain of the PM20 tube are connected as the first output end of the zero-temperature current generating module 310 and are connected to the first port of the first Wilson current mirror 320. The drain of the PM17 tube and the drain of the PM18 tube are connected as the second output end of the zero-temperature current generating module 310 and are connected to the first port of the second Wilson current mirror 330. The drain of the PM21 tube and the drain of the PM19 tube are connected as the third output end of the zero-temperature current generating module 310 and are respectively connected to the second port of the first Wilson current mirror 320 and the second port of the second Wilson current mirror 330.

[0136] Further, the first Wilson current mirror 320 includes: NM5, Q5, Q6, Q11 and Q12. The second Wilson current mirror 330 includes: NM6, Q7, Q8, Q9 and Q10.

[0137] Among them, NM5 and NM6 are both NMOS tubes, and Q5, Q6, Q7, Q8, Q9, Q10, Q11 and Q12 are all NPN transistors.

[0138] The collector of Q12 is connected to the first output terminal of the zero temperature current generating module 310 and the gate of NM5, the drain of NM5 is connected to the third output terminal of the zero temperature current generating module 310, the source of NM5 is connected to the collector of Q6, the base of Q6 and the base of Q12, the emitter of Q6 is connected to the collector of Q5. The emitter of Q12, the collector of Q11, the base of Q11, the base of Q5 and the resistor R NL One end of each is connected to point Z, and the emitters of Q11 and Q5 are grounded.

[0139] The drain of NM6 is connected to the third output terminal of the zero temperature current generating module 310 and the output circuit 400, respectively, and the source of NM6 is connected to the collector of Q7. The collector of Q10 is connected to the second output terminal of the zero temperature current generating module 310, the gate of NM6, the base of Q10 and the base of Q7, respectively. The emitter of Q10 is connected to the collector of Q9, and the emitter of Q7 is connected to the collector of Q8, the base of Q8 and the base of Q9, respectively, and the emitters of Q8 and Q9 are both grounded.

[0140] The working principle of the high-order modulation processing circuit 300 is as follows:

[0141] Since PM7, PM8, PM9 form a current mirror with PM2, and PM10, PM11, PM12 form a current mirror with PM5, PM7, PM8, PM9 copy the PTAT current, and PM10, PM11, PM12 copy the CTAT current.

[0142] The PTAT current flowing through PM8 and the CTAT current flowing through PM11 merge at the third output terminal of the zero temperature current generating module 310 to form an M-fold ZTAT current, i.e., I ZTAT3 The PTAT current flowing through PM7 and the CTAT current flowing through PM10 merge at the first output terminal of the zero temperature current generating module 310 to form a ZTAT current, that is, I ZTAT1 Similarly, the second output terminal of the zero temperature current generating module 310 also outputs a ZTAT current, that is, I ZTAT2 Among them, I ZTAT3 =MI ZTAT1 =MI ZTAT2 Since PM7 and PM10 combine to form the ZTAT current (i.e., I ZTAT1 ) flows through Q11, so the voltage at point Z is the base-emitter voltage of Q11.

[0143] The Wilson current mirror used in this application can eliminate most of the base current compared to the ordinary current mirror, but there will still be errors. For example, in the first Wilson current mirror 320, I1 will be larger than I ZTAT1 many The reason is as follows (assuming there is no resistor R NL , and the following I Q are the collector currents of the transistors, I b1 is the base current of transistor Q11 or Q5, I b2 is the base current of transistor Q12 or Q6):

[0144] I Q11 =I Q5 =βI b1

[0145]

[0146] It can be seen that I1 is larger than I ZTAT1 More When β is large (β = 70 at room temperature), the error has almost no effect. However, at low temperatures, the value of β decreases. For example, at -40°C, β = 30, which will produce an error of 4 / 900, which is unacceptable for a bandgap reference.

[0147] In order to eliminate the error caused by the reduction of transistor β at low temperature, the embodiment of the present application adds a second Wilson current mirror 330 which is symmetrical to the first Wilson current mirror 320. Figure 6 This symmetrical circuit structure can offset the error. In addition, Q11 gets the ZTAT current plus the high-order current I NL , and the output requires ZTAT current minus INL , so a current subtraction is required. The specific analysis is as follows:

[0148] As mentioned earlier, in the absence of resistance R NL In case of:

[0149]

[0150] Then, after adding the resistor R NL In case of:

[0151]

[0152] If we ignore NM5 and NM6, the Q7Q8Q9Q10 structure is the same as the Q5Q6Q11Q12 structure, so:

[0153]

[0154] because and are approximately equal, and:

[0155] I ref =I ZTAT3 -I1-I2

[0156] I ZTAT3 =MI ZTAT1 =MI ZTAT2

[0157] so:

[0158] I ref =I ZTAT3 -I ZTAT1 -I ZTAT2 -I NL =(M-2)*ZTAT current-I NL

[0159] Wherein, M is a positive integer greater than 2. That is, the bandgap reference current I finally output by the high-order modulation processing circuit 300 is ref Equal to (M-2) times the ZTAT current minus the high-order modulation current I NL .in, Due to R NL The value of is related to the process constant η, R NL Without reducing I NL In the case of , it is usually designed to be large, and here the M value can reduce I NL The appropriate M value can reduce R NL design value to prevent the resistor from occupying too large a layout area.

[0160] Based on the above design, a bandgap reference current I is obtained after high-order modulation and elimination of the influence of base current and the reduction of transistor β at low temperature. ref At this time, it is also necessary to convert it into a bandgap reference voltage V through the output circuit 400 ref After output.

[0161] See also Figure 7 In the embodiment of the present application, the output circuit 400 includes: a first current mirror 410, a second current mirror 420 and a resistor R OUT .

[0162] The first port of the first current mirror 410 is connected to the output end of the high-order modulation processing circuit 300, the second port of the first current mirror 410 is connected to the third port of the second current mirror 420, the third port and the fourth port of the first current mirror 410 are both grounded, and the first port and the second port of the second current mirror 420 are both connected to the power supply VDD. OUT One end of the resistor R is grounded. OUT The other end of is connected to the fourth port of the second current mirror 420 as the output end of the bandgap reference circuit 10.

[0163] Further, the first current mirror 410 includes NM7, NM8, NM9 and NM10, and the second current mirror 420 includes PM13, PM14, PM15 and PM16. Among them, NM7, NM8, NM9 and NM10 are all NMOS transistors, and PM13, PM14, PM15 and PM16 are all PMOS transistors.

[0164] The drain of NM7 is connected to the output terminal of the high-order modulation processing circuit 300, the gate of NM7 and the gate of NM8 respectively. The source of NM7 is connected to the drain of NM9, the gate of NM9 and the gate of NM10 respectively, and the sources of NM9 and NM10 are both grounded. The source of NM8 is connected to the drain of NM10, and the drain of NM8 is connected to the drain of PM15, the gate of PM15 and the gate of PM16 respectively.

[0165] The source of PM15 is connected to the drain of PM13, the gate of PM13 and the gate of PM14 respectively. The source of PM13 and the source of PM14 are both connected to the power supply VDD. The drain of PM14 is connected to the source of PM16. OUT One end is grounded, R OUT The other end is connected to the drain of PM16 as the output end of the bandgap reference circuit 10.

[0166] The bandgap reference current I ref Accurately copy the resistor R OUT On, through ROUT I ref Converted to bandgap reference voltage V ref Output.

[0167] See also Figure 8 , Figure 8 The overall circuit diagram of the bandgap reference circuit 10 provided in the embodiment of the present application. It has been verified that the bandgap reference circuit of the above structure changes by 675uV when the output average voltage is 1.154V within -40 to 125 degrees Celsius, and the temperature coefficient is 3.4ppm / ℃. That is, the bandgap reference circuit 10 provided in the embodiment of the present application can generate a bandgap reference voltage with a low temperature coefficient after high-order modulation and eliminating the influence of base current and the reduction of transistor β at low temperature.

[0168] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0169] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A bandgap reference circuit, characterized in that: include: Core circuit, negative temperature current extraction circuit, high-order modulation processing circuit and output circuit; The first port of the negative temperature current extraction circuit and the first port of the high-order modulation processing circuit are both connected to point X in the core circuit, the second port and the third port of the high-order modulation processing circuit are respectively connected to the second port of the negative temperature current extraction circuit and the first port of the core circuit, and the output end of the high-order modulation processing circuit is connected to the output circuit; The core circuit is used to generate a point X voltage, a positive temperature coefficient PTAT current without a base current, and a negative temperature coefficient CTAT current mixed with a base current; wherein the point X voltage is the base-emitter voltage of the transistor in the core circuit through which the PTAT current flows; The negative temperature current extraction circuit is used to extract the CTAT current without the base current according to the X point voltage; The high-order modulation processing circuit is used to generate a bandgap reference current that has undergone high-order modulation and eliminated the influence of the base current according to the X-point voltage and PTAT current provided by the core circuit and the CTAT current provided by the negative temperature current extraction circuit; The output circuit is used for converting the bandgap reference current into a bandgap reference voltage and then outputting the converted voltage.

2. The bandgap reference circuit according to claim 1, characterized in that: The core circuit includes: Q0 tube, Q1 tube, Q2 tube, Q3 tube, Q4 tube, PM0 tube, PM1 tube, PM2 tube, PM3 tube, PM23 tube, PM24 tube, PM25 tube, NM4 tube, resistor R0, resistor R1 and a first cascade MOS tube; Among them, Q0, Q1, Q2, Q3 and Q4 are all NPN transistors, and the parallel number of Q0 is greater than the parallel number of Q1; PM0, PM1, PM2, PM3, PM23, PM24 and PM25 are all PMOS tubes, and NM4 is an NMOS tube; The sources of the PM0 tube, the PM1 tube, the PM2 tube, the PM3 tube and the first cascade MOS tube are all connected to the power supply, the sources of the PM25 tube, the PM24 tube and the PM23 tube are respectively connected to the drains of the PM3 tube, the PM0 tube and the PM2 tube, the gates of the PM25 tube, the PM24 tube and the PM23 tube are all connected to the gate of the first cascade MOS tube; the gate of the PM3 tube, the gate of the PM0 tube and the drain of the PM23 tube are all connected to the gate of the PM2 tube; wherein the gate of the PM2 tube serves as the first port of the core circuit; The drain of PM25 is connected to the collector of Q3, the drain of PM24 is connected to the gate of PM1 and the collector of Q0, the drain of PM23 is also connected to the drain of NM4, the gate of NM4 is connected to the collector of Q3, the source of NM4 is connected to the base of Q3 and the collector of Q2, and the drain of the first cascade MOS is connected to the collector of Q4. The emitters of Q0, Q1, Q2, Q3 and Q4 are all grounded, the bases of Q1, Q2 and Q4 are all connected to the point X, the collector of Q1 is respectively connected to the base of Q0 and one end of resistor R0, the other end of resistor R0 is respectively connected to the drain of PM1 and the point X, one end of resistor R1 is grounded, and the other end of resistor R1 is connected to the point X.

3. The bandgap reference circuit according to claim 2, characterized in that: The negative temperature current extraction circuit includes: a PM4 tube, a PM5 tube, a PM6 tube, a PM30 tube, a PM31 tube, a NM0 tube, a NM1 tube, a NM2 tube, a NM3 tube, a resistor R2, a resistor R3, a resistor R4 and a second cascade MOS tube; Among them, PM4, PM5, PM6, PM30 and PM31 are all PMOS tubes, and NM0, NM1, NM2 and NM3 are all NMOS tubes; The sources of the PM4 tube, the PM5 tube, the PM6 tube and the second cascade MOS tube are all connected to the power supply, the drains of the PM4 tube and the PM5 tube are respectively connected to the sources of the PM30 tube and the PM31 tube, and the gates of the PM30 tube and the PM31 tube are both connected to the gate of the second cascade MOS tube; the gate of the PM4 tube and the drain of the PM31 tube are both connected to the gate of the PM5 tube; wherein the gate of the PM5 tube serves as the second port of the negative temperature current extraction circuit; The drain of the second cascade MOS tube is connected to the drain of the NM3 tube, the drain of the PM6 tube is connected to the drain of the NM0 tube and the gate of the NM0 tube respectively, the drain of the PM30 tube is connected to the gate of the PM6 tube and the drain of the NM1 tube respectively, and the drain of the PM31 tube is also connected to the drain of the NM2 tube; The gates of NM3, NM1 and NM2 are all connected to the gate of NM0; the source of NM3 is grounded through resistor R4, the source of NM0 is grounded through resistor R3, the source of NM1 is grounded through resistor R2, and the source of NM2 is connected to the point X; wherein the source of NM2 serves as the first port of the negative temperature current extraction circuit.

4. The bandgap reference circuit according to claim 3, characterized in that: The first cascade MOS tubes include: PM32 tube, PM33 tube, PM34 tube and PM35 tube, and the second cascade MOS tubes include: PM26 tube, PM27 tube, PM28 tube and PM29 tube; Among them, PM32, PM33, PM34, PM35, PM26, PM27, PM28 and PM29 are all PMOS tubes; The source of the PM32 tube is connected to the power supply as the source of the first cascade MOS tube, the drain of the PM32 tube is connected to the source of the PM33 tube, the drain of the PM33 tube is connected to the source of the PM34 tube, and the drain of the PM34 tube is connected to the source of the PM35 tube; the gate of the PM32 tube, the gate of the PM33 tube, the gate of the PM34 tube, the gate of the PM35 tube and the drain of the PM35 tube are connected and serve as the gate of the first cascade MOS tube; the drain of the PM35 tube is also connected to the collector of the Q4 tube; The source of the PM26 tube is connected to the power supply as the source of the second cascade MOS tube, the drain of the PM26 tube is connected to the source of the PM27 tube, the drain of the PM27 tube is connected to the source of the PM28 tube, and the drain of the PM28 tube is connected to the source of the PM29 tube; the gate of the PM26 tube, the gate of the PM27 tube, the gate of the PM28 tube, the gate of the PM29 tube and the drain of the PM29 tube are connected and serve as the gate of the second cascade MOS tube; the drain of the PM29 tube is also connected to the drain of the NM3 tube.

5. The bandgap reference circuit according to claim 3, characterized in that: The high-order modulation processing circuit includes: a resistor R NL , a zero temperature current generating module, a first Wilson current mirror and a second Wilson current mirror; The first input end of the zero temperature current generating module is connected to the second port of the negative temperature current extraction circuit, and the second input end of the zero temperature current generating module is connected to the first port of the core circuit; the first output end of the zero temperature current generating module is connected to the first port of the first Wilson current mirror, the second output end of the zero temperature current generating module is connected to the first port of the second Wilson current mirror, the third output end of the zero temperature current generating module is respectively connected to the second port of the first Wilson current mirror and the second port of the second Wilson current mirror, and the second port of the second Wilson current mirror is also connected to the output circuit; the resistor R NL One end of the resistor R is connected to the point X in the core circuit. NL The other end is connected to point Z in the first Wilson current mirror; The zero temperature current generating module is used for providing a zero temperature coefficient ZTAT current to the first Wilson current mirror and the second Wilson current mirror according to the PTAT current and the CTAT current; The resistor R NL Used to provide a high-order modulation current to the first Wilson current mirror according to the voltage at point X and the voltage at point Z; wherein the voltage at point Z is the base-emitter voltage of the transistor in the first Wilson current mirror through which the ZTAT current flows; The first Wilson current mirror and the second Wilson current mirror are used to generate a bandgap reference current that has undergone high-order modulation and eliminates the influence of base current and the influence of transistor current gain reduction at low temperature according to the ZTAT current and the high-order modulation current.

6. The bandgap reference circuit according to claim 5, characterized in that: The zero-temperature current generating module includes: a PM7 tube, a PM8 tube, a PM9 tube, a PM10 tube, a PM11 tube, a PM12 tube, a PM17 tube, a PM18 tube, a PM19 tube, a PM20 tube, a PM21 tube and a PM22 tube; Among them, PM7, PM8, PM9, PM10, PM11, PM12, PM17, PM18, PM19, PM20, PM21 and PM22 are all PMOS tubes; The number of PM7 tubes in parallel = the number of PM22 tubes in parallel = the number of PM10 tubes in parallel = the number of PM20 tubes in parallel = the number of PM9 tubes in parallel = the number of PM17 tubes in parallel = the number of PM12 tubes in parallel = the number of PM18 tubes in parallel = a, the number of PM8 tubes in parallel = the number of PM21 tubes in parallel = the number of PM11 tubes in parallel = the number of PM19 tubes in parallel = b, a and b are both positive integers, and b>2a; The sources of the PM7 tube, the PM8 tube, the PM9 tube, the PM10 tube, the PM11 tube and the PM12 tube are all connected to the power supply; the gates of the PM7 tube, the PM8 tube and the PM9 tube are all connected to the gate of the PM2 tube; the drains of the PM7 tube, the PM8 tube and the PM9 tube are respectively connected to the sources of the PM22 tube, the PM21 tube and the PM17 tube; the gates of the PM22 tube, the PM21 tube and the PM17 tube are all connected to the gate of the first cascade MOS tube; The gates of the PM10 tube, the PM11 tube, and the PM12 tube are all connected to the gate of the PM5 tube, the drains of the PM10 tube, the PM11 tube, and the PM12 tube are respectively connected to the source of the PM20 tube, the PM19 tube, and the PM18 tube, and the gates of the PM20 tube, the PM19 tube, and the PM18 tube are all connected to the gate of the second cascade MOS tube; The drain of the PM22 tube and the drain of the PM20 tube are connected as the first output end of the zero-temperature current generating module and are connected to the first port of the first Wilson current mirror. The drain of the PM17 tube and the drain of the PM18 tube are connected as the second output end of the zero-temperature current generating module and are connected to the first port of the second Wilson current mirror. The drain of the PM21 tube and the drain of the PM19 tube are connected as the third output end of the zero-temperature current generating module and are respectively connected to the second port of the first Wilson current mirror and the second port of the second Wilson current mirror.

7. The bandgap reference circuit according to claim 5, characterized in that: The first Wilson current mirror includes: NM5, Q5, Q6, Q11 and Q12, and the second Wilson current mirror includes: NM6, Q7, Q8, Q9 and Q10; Among them, NM5 and NM6 are NMOS tubes, and Q5, Q6, Q7, Q8, Q9, Q10, Q11 and Q12 are NPN transistors; The collector of Q12 is connected to the first output terminal of the zero-temperature current generating module and the gate of NM5, the drain of NM5 is connected to the third output terminal of the zero-temperature current generating module, the source of NM5 is connected to the collector of Q6, the base of Q6 and the base of Q12, the emitter of Q6 is connected to the collector of Q5; the emitter of Q12, the collector of Q11, the base of Q11, the base of Q5 and the resistor R NL One end of each is connected to point Z, and the emitters of Q11 and Q5 are grounded; The drain of the NM6 tube is respectively connected to the third output end of the zero-temperature current generating module and the output circuit, and the source of the NM6 tube is connected to the collector of the Q7 tube; the collector of the Q10 tube is respectively connected to the second output end of the zero-temperature current generating module, the gate of the NM6 tube, the base of the Q10 tube and the base of the Q7 tube; the emitter of the Q10 tube is connected to the collector of the Q9 tube, and the emitter of the Q7 tube is respectively connected to the collector of the Q8 tube, the base of the Q8 tube and the base of the Q9 tube, and the emitters of the Q8 tube and the Q9 tube are both grounded.

8. The bandgap reference circuit according to claim 3, characterized in that: The core circuit further includes a resistor Rs1, and the bandgap reference circuit further includes a startup circuit; One end of the resistor Rs1 is connected to the point X, the other end of the resistor Rs1 is respectively connected to the drain of the PM1 tube and the first port of the startup circuit, the second port of the startup circuit is respectively connected to the gate of the PM6 tube, the drain of the PM30 tube and the drain of the NM1 tube, and the input end of the startup circuit is connected to the power supply.

9. The bandgap reference circuit according to claim 8, characterized in that: The startup circuit includes: Q13 tube, NMs1 tube, NMs2 tube, resistor Rs2, resistor Rs3 and capacitor C1; wherein Q13 tube is an NPN triode, and NMs1 tube and NMs2 tube are both NMOS tubes; One end of the resistor Rs3 is connected to the power supply, and the other end of the resistor Rs3 is respectively connected to the drain of the NMs1 tube, the gate of the NMs1 tube and the gate of the NMs2 tube; the source of the NMs1 tube is respectively connected to the collector of the Q13 tube and the base of the Q13 tube, and the emitter of the Q13 tube is grounded; The source of NMs2 is connected to the drain of PM1 and one end of resistor Rs1 respectively, and the drain of NMs2 is connected to the gate of PM6, the drain of PM30 and the drain of NM1 respectively; the drain of NMs2 is also connected to one end of resistor Rs2, the other end of resistor Rs2 is connected to one end of capacitor C1, and the other end of capacitor C1 is grounded; When the bandgap reference circuit outputs normally, the NMs2 tube is turned off and the startup circuit stops running.

10. The bandgap reference circuit according to claim 1, characterized in that: The output circuit includes: a first current mirror, a second current mirror and a resistor R OUT ; The first port of the first current mirror is connected to the output end of the high-order modulation processing circuit, the second port of the first current mirror is connected to the third port of the second current mirror, the third port and the fourth port of the first current mirror are both grounded, the first port and the second port of the second current mirror are both connected to the power supply, and the resistor R OUT One end of the resistor R OUT The other end is connected to the fourth port of the second current mirror as the output end of the bandgap reference circuit.

Images